195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 7035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3089d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 3195f25efeSWolfram Sang #include "sdhci-pltfm.h" 3295f25efeSWolfram Sang #include "sdhci-esdhc.h" 3395f25efeSWolfram Sang 34a215186dSHaibo Chen #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 3560bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 36fd44954eSHaibo Chen #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 3758ac8177SRichard Zhu /* VENDOR SPEC register */ 3860bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3960bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 400322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 41fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 4260bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 43cc17e129SDong Aisheng #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 4460bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 45de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 462a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 470322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 480322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 490b330e38SDong Aisheng #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 500322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 5128b07674SHaibo Chen #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 522a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 532a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 54d131a71cSDong Aisheng /* Tuning bits */ 55d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 5658ac8177SRichard Zhu 57602519b2SDong Aisheng /* dll control register */ 58602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 59602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 60602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 61602519b2SDong Aisheng 620322191eSDong Aisheng /* tune control register */ 630322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 640322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 650322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 660322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 670322191eSDong Aisheng 6828b07674SHaibo Chen /* strobe dll register */ 6928b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL 0x70 7028b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 7128b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 7228b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 7328b07674SHaibo Chen 7428b07674SHaibo Chen #define ESDHC_STROBE_DLL_STATUS 0x74 7528b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 7628b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 7728b07674SHaibo Chen 786e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 796e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 806e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 81d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 82d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_MASK 0xff 83260ecb3cSHaibo Chen #define ESDHC_TUNING_STEP_MASK 0x00070000 84d407e30bSHaibo Chen #define ESDHC_TUNING_STEP_SHIFT 16 856e9fd28eSDong Aisheng 86ad93220dSDong Aisheng /* pinctrl state */ 87ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 88ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 89ad93220dSDong Aisheng 9058ac8177SRichard Zhu /* 91af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 92af51079eSSascha Hauer */ 93af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 94af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 95af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 96af51079eSSascha Hauer 97af51079eSSascha Hauer /* 9897e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 9997e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 10097e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 10197e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 10297e4ba6aSRichard Zhu */ 10360bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 10497e4ba6aSRichard Zhu 10597e4ba6aSRichard Zhu /* 10658ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 10758ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 10858ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 10958ac8177SRichard Zhu * be generated. 11058ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 11158ac8177SRichard Zhu * operations automatically as required at the end of the 11258ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 11358ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 11458ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 11558ac8177SRichard Zhu */ 11631fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 11731fbb301SShawn Guo /* 11831fbb301SShawn Guo * The flag enables the workaround for ESDHC errata ENGcm07207 which 11931fbb301SShawn Guo * affects i.MX25 and i.MX35. 12031fbb301SShawn Guo */ 12131fbb301SShawn Guo #define ESDHC_FLAG_ENGCM07207 BIT(2) 1229d61c009SShawn Guo /* 1239d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1249d61c009SShawn Guo * integrated on the i.MX6 series. 1259d61c009SShawn Guo */ 1269d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1276e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1286e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1296e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1306e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1316e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1326e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 13318094430SDong Aisheng /* 13418094430SDong Aisheng * The IP has errata ERR004536 13518094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 13618094430SDong Aisheng * when reading data from the card 13718094430SDong Aisheng */ 13818094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 1394245afffSDong Aisheng /* The IP supports HS200 mode */ 1404245afffSDong Aisheng #define ESDHC_FLAG_HS200 BIT(8) 14128b07674SHaibo Chen /* The IP supports HS400 mode */ 14228b07674SHaibo Chen #define ESDHC_FLAG_HS400 BIT(9) 14328b07674SHaibo Chen 14428b07674SHaibo Chen /* A higher clock ferquency than this rate requires strobell dll control */ 14528b07674SHaibo Chen #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 146e149860dSRichard Zhu 147f47c4bbfSShawn Guo struct esdhc_soc_data { 148f47c4bbfSShawn Guo u32 flags; 149f47c4bbfSShawn Guo }; 150f47c4bbfSShawn Guo 151f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx25_data = { 152f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 153f47c4bbfSShawn Guo }; 154f47c4bbfSShawn Guo 155f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx35_data = { 156f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 157f47c4bbfSShawn Guo }; 158f47c4bbfSShawn Guo 159f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx51_data = { 160f47c4bbfSShawn Guo .flags = 0, 161f47c4bbfSShawn Guo }; 162f47c4bbfSShawn Guo 163f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx53_data = { 164f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 165f47c4bbfSShawn Guo }; 166f47c4bbfSShawn Guo 167f47c4bbfSShawn Guo static struct esdhc_soc_data usdhc_imx6q_data = { 1686e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1696e9fd28eSDong Aisheng }; 1706e9fd28eSDong Aisheng 1716e9fd28eSDong Aisheng static struct esdhc_soc_data usdhc_imx6sl_data = { 1726e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1734245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 1744245afffSDong Aisheng | ESDHC_FLAG_HS200, 17557ed3314SShawn Guo }; 17657ed3314SShawn Guo 177913d4951SDong Aisheng static struct esdhc_soc_data usdhc_imx6sx_data = { 178913d4951SDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1794245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 180913d4951SDong Aisheng }; 181913d4951SDong Aisheng 18228b07674SHaibo Chen static struct esdhc_soc_data usdhc_imx7d_data = { 18328b07674SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 18428b07674SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 18528b07674SHaibo Chen | ESDHC_FLAG_HS400, 18628b07674SHaibo Chen }; 18728b07674SHaibo Chen 188e149860dSRichard Zhu struct pltfm_imx_data { 189e149860dSRichard Zhu u32 scratchpad; 190e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 191ad93220dSDong Aisheng struct pinctrl_state *pins_default; 192ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 193ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 194f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 195842afc02SShawn Guo struct esdhc_platform_data boarddata; 19652dac615SSascha Hauer struct clk *clk_ipg; 19752dac615SSascha Hauer struct clk *clk_ahb; 19852dac615SSascha Hauer struct clk *clk_per; 199361b8482SLucas Stach enum { 200361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending*/ 201361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 202361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 203361b8482SLucas Stach } multiblock_status; 204de5bdbffSDong Aisheng u32 is_ddr; 205e149860dSRichard Zhu }; 206e149860dSRichard Zhu 207f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 20857ed3314SShawn Guo { 20957ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 210f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 21157ed3314SShawn Guo }, { 21257ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 213f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 21457ed3314SShawn Guo }, { 21557ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 216f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 21757ed3314SShawn Guo }, { 21857ed3314SShawn Guo /* sentinel */ 21957ed3314SShawn Guo } 22057ed3314SShawn Guo }; 22157ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 22257ed3314SShawn Guo 223abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 224f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 225f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 226f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 227f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 228913d4951SDong Aisheng { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 2296e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 230f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 23128b07674SHaibo Chen { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 232abfafc2dSShawn Guo { /* sentinel */ } 233abfafc2dSShawn Guo }; 234abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 235abfafc2dSShawn Guo 23657ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 23757ed3314SShawn Guo { 238f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 23957ed3314SShawn Guo } 24057ed3314SShawn Guo 24157ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 24257ed3314SShawn Guo { 243f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 24457ed3314SShawn Guo } 24557ed3314SShawn Guo 24695a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 24795a2482aSShawn Guo { 248f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 24995a2482aSShawn Guo } 25095a2482aSShawn Guo 2519d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2529d61c009SShawn Guo { 253f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2549d61c009SShawn Guo } 2559d61c009SShawn Guo 25695f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 25795f25efeSWolfram Sang { 25895f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 25995f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 26095f25efeSWolfram Sang 26195f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 26295f25efeSWolfram Sang } 26395f25efeSWolfram Sang 2647e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 2657e29c306SWolfram Sang { 266361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 267070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 268913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 269913413c3SShawn Guo 2700322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 2710322191eSDong Aisheng u32 fsl_prss = val; 2720322191eSDong Aisheng /* save the least 20 bits */ 2730322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 2740322191eSDong Aisheng /* move dat[0-3] bits */ 2750322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 2760322191eSDong Aisheng /* move cmd line bit */ 2770322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 2780322191eSDong Aisheng } 2790322191eSDong Aisheng 28097e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 2816b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 2826b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2836b4fb671SDong Aisheng val &= 0xffff0000; 2846b4fb671SDong Aisheng 28597e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 28697e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 28797e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 28897e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 28997e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 29097e4ba6aSRichard Zhu */ 29197e4ba6aSRichard Zhu 29297e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 29397e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 29497e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 29597e4ba6aSRichard Zhu } 29697e4ba6aSRichard Zhu } 29797e4ba6aSRichard Zhu 2986e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 2996e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 3006e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3016e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 3026e9fd28eSDong Aisheng else 3036e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 3040322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 305888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 306da0295ffSDong Aisheng | SDHCI_USE_SDR50_TUNING 307da0295ffSDong Aisheng | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); 30828b07674SHaibo Chen 30928b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 31028b07674SHaibo Chen val |= SDHCI_SUPPORT_HS400; 3116e9fd28eSDong Aisheng } 3126e9fd28eSDong Aisheng } 3130322191eSDong Aisheng 3149d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 3150322191eSDong Aisheng val = 0; 3160322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 3170322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 3180322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 3190322191eSDong Aisheng } 3200322191eSDong Aisheng 32197e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 32260bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 32360bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 32497e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 32597e4ba6aSRichard Zhu } 326361b8482SLucas Stach 327361b8482SLucas Stach /* 328361b8482SLucas Stach * mask off the interrupt we get in response to the manually 329361b8482SLucas Stach * sent CMD12 330361b8482SLucas Stach */ 331361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 332361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 333361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 334361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 335361b8482SLucas Stach SDHCI_INT_STATUS); 336361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 337361b8482SLucas Stach } 33897e4ba6aSRichard Zhu } 33997e4ba6aSRichard Zhu 3407e29c306SWolfram Sang return val; 3417e29c306SWolfram Sang } 3427e29c306SWolfram Sang 3437e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 3447e29c306SWolfram Sang { 345e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 346070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 3470d58864bSTony Lin u32 data; 348e149860dSRichard Zhu 34977da3da0SAaron Brice if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 35077da3da0SAaron Brice reg == SDHCI_INT_STATUS)) { 351b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 3520d58864bSTony Lin /* 3530d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 3540d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 3550d58864bSTony Lin * so we need to apply the following workaround: clear 3560d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 3570d58864bSTony Lin * interrupt. In case a card interrupt was lost, 3580d58864bSTony Lin * re-sample it by the following steps. 3590d58864bSTony Lin */ 3600d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 36160bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 3620d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 36360bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 3640d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 3650d58864bSTony Lin } 366915be485SDong Aisheng 367915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 368915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 369915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 370915be485SDong Aisheng } 3710d58864bSTony Lin } 3720d58864bSTony Lin 373f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 37458ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 37558ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 37658ac8177SRichard Zhu u32 v; 37760bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 37860bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 37960bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 380361b8482SLucas Stach 381361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 382361b8482SLucas Stach { 383361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 384361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 385361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 386361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 387361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 388361b8482SLucas Stach } 38958ac8177SRichard Zhu } 39058ac8177SRichard Zhu 3917e29c306SWolfram Sang writel(val, host->ioaddr + reg); 3927e29c306SWolfram Sang } 3937e29c306SWolfram Sang 39495f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 39595f25efeSWolfram Sang { 396ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 397070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 3980322191eSDong Aisheng u16 ret = 0; 3990322191eSDong Aisheng u32 val; 400ef4d0888SShawn Guo 40195a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 402ef4d0888SShawn Guo reg ^= 2; 4039d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 40495a2482aSShawn Guo /* 405ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 406ef4d0888SShawn Guo * Correct it here. 40795a2482aSShawn Guo */ 408ef4d0888SShawn Guo return SDHCI_SPEC_300; 409ef4d0888SShawn Guo } 41095a2482aSShawn Guo } 41195f25efeSWolfram Sang 4120322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 4130322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4140322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 4150322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 4160322191eSDong Aisheng 4179d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 4186e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 4190322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4206e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 4216e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 4226e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4236e9fd28eSDong Aisheng } 4246e9fd28eSDong Aisheng 4250322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 4260322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 4270322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 4280322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 4290322191eSDong Aisheng 4300322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 4310322191eSDong Aisheng 4320322191eSDong Aisheng return ret; 4330322191eSDong Aisheng } 4340322191eSDong Aisheng 4357dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 4367dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 4377dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4387dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 4397dd109efSDong Aisheng /* Swap AC23 bit */ 4407dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 4417dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 4427dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 4437dd109efSDong Aisheng } 4447dd109efSDong Aisheng } else { 4457dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 4467dd109efSDong Aisheng } 4477dd109efSDong Aisheng 4487dd109efSDong Aisheng return ret; 4497dd109efSDong Aisheng } 4507dd109efSDong Aisheng 45195f25efeSWolfram Sang return readw(host->ioaddr + reg); 45295f25efeSWolfram Sang } 45395f25efeSWolfram Sang 45495f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 45595f25efeSWolfram Sang { 45695f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 457070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 4580322191eSDong Aisheng u32 new_val = 0; 45995f25efeSWolfram Sang 46095f25efeSWolfram Sang switch (reg) { 4610322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 4620322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4630322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 4640322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4650322191eSDong Aisheng else 4660322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4670322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4680322191eSDong Aisheng return; 4690322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 4700322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4710322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 4720322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 4730322191eSDong Aisheng else 4740322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 4750322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4766e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 4770322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 478da0295ffSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4790322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 480da0295ffSDong Aisheng new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 481da0295ffSDong Aisheng } else { 4820322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 483da0295ffSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 484da0295ffSDong Aisheng } 4850322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 4866e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 4876e9fd28eSDong Aisheng u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4886e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4898b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4908b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4916e9fd28eSDong Aisheng } else { 4928b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4936e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 4940b330e38SDong Aisheng m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 4956e9fd28eSDong Aisheng } 4966e9fd28eSDong Aisheng 4978b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 4988b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 4998b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 5000b330e38SDong Aisheng m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 5018b2bb0adSDong Aisheng } else { 5028b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 5038b2bb0adSDong Aisheng } 5046e9fd28eSDong Aisheng 5056e9fd28eSDong Aisheng writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 5066e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5076e9fd28eSDong Aisheng } 5080322191eSDong Aisheng return; 50995f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 510f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 51158ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 51258ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 51358ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 51458ac8177SRichard Zhu u32 v; 51560bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 51660bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 51760bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 51858ac8177SRichard Zhu } 51969f54698SShawn Guo 5209d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 52169f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5222a15f981SShawn Guo /* Swap AC23 bit */ 5232a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 5242a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 5252a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 5262a15f981SShawn Guo } 5272a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 52869f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 52969f54698SShawn Guo } else { 53069f54698SShawn Guo /* 53169f54698SShawn Guo * Postpone this write, we must do it together with a 53269f54698SShawn Guo * command write that is down below. 53369f54698SShawn Guo */ 534e149860dSRichard Zhu imx_data->scratchpad = val; 53569f54698SShawn Guo } 53695f25efeSWolfram Sang return; 53795f25efeSWolfram Sang case SDHCI_COMMAND: 538361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 53958ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 54095a2482aSShawn Guo 541361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 542f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 543361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 544361b8482SLucas Stach 5459d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 54695a2482aSShawn Guo writel(val << 16, 54795a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 54869f54698SShawn Guo else 549e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 55095f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 55195f25efeSWolfram Sang return; 55295f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 55395f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 55495f25efeSWolfram Sang break; 55595f25efeSWolfram Sang } 55695f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 55795f25efeSWolfram Sang } 55895f25efeSWolfram Sang 55977da3da0SAaron Brice static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 56077da3da0SAaron Brice { 56177da3da0SAaron Brice u8 ret; 56277da3da0SAaron Brice u32 val; 56377da3da0SAaron Brice 56477da3da0SAaron Brice switch (reg) { 56577da3da0SAaron Brice case SDHCI_HOST_CONTROL: 56677da3da0SAaron Brice val = readl(host->ioaddr + reg); 56777da3da0SAaron Brice 56877da3da0SAaron Brice ret = val & SDHCI_CTRL_LED; 56977da3da0SAaron Brice ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 57077da3da0SAaron Brice ret |= (val & ESDHC_CTRL_4BITBUS); 57177da3da0SAaron Brice ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 57277da3da0SAaron Brice return ret; 57377da3da0SAaron Brice } 57477da3da0SAaron Brice 57577da3da0SAaron Brice return readb(host->ioaddr + reg); 57677da3da0SAaron Brice } 57777da3da0SAaron Brice 57895f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 57995f25efeSWolfram Sang { 5809a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 581070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 58295f25efeSWolfram Sang u32 new_val; 583af51079eSSascha Hauer u32 mask; 58495f25efeSWolfram Sang 58595f25efeSWolfram Sang switch (reg) { 58695f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 58795f25efeSWolfram Sang /* 58895f25efeSWolfram Sang * FSL put some DMA bits here 58995f25efeSWolfram Sang * If your board has a regulator, code should be here 59095f25efeSWolfram Sang */ 59195f25efeSWolfram Sang return; 59295f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 5936b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 594af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 5957122bbb0SMasanari Iida /* ensure the endianness */ 59695f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 5979a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 5989a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 59995f25efeSWolfram Sang /* DMA mode bits are shifted */ 60095f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 6019a0985b7SWilson Callan } 60295f25efeSWolfram Sang 603af51079eSSascha Hauer /* 604af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 605af51079eSSascha Hauer * esdhc_pltfm_bus_width. 606f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 607f6825748SMartin Fuzzey * SDIO interrupt errata workaround. 608af51079eSSascha Hauer */ 609f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 610af51079eSSascha Hauer 611af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 61295f25efeSWolfram Sang return; 61395f25efeSWolfram Sang } 61495f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 615913413c3SShawn Guo 616913413c3SShawn Guo /* 617913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 618913413c3SShawn Guo * that software reset should not affect card detection circuit. 619913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 620913413c3SShawn Guo * software reset. This will stop those clocks that card detection 621913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 622913413c3SShawn Guo * to keep card detection circuit functional. 623913413c3SShawn Guo */ 62458c8c4fbSShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 625913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 62658c8c4fbSShawn Guo /* 62758c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 62858c8c4fbSShawn Guo * Do it manually here. 62958c8c4fbSShawn Guo */ 630de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 631d131a71cSDong Aisheng /* the tuning bits should be kept during reset */ 632d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 633d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 634d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 635de5bdbffSDong Aisheng imx_data->is_ddr = 0; 636de5bdbffSDong Aisheng } 63758c8c4fbSShawn Guo } 63895f25efeSWolfram Sang } 63995f25efeSWolfram Sang 6400ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 6410ddf03c9SLucas Stach { 6420ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 6430ddf03c9SLucas Stach 644a974862fSDong Aisheng return pltfm_host->clock; 6450ddf03c9SLucas Stach } 6460ddf03c9SLucas Stach 64795f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 64895f25efeSWolfram Sang { 64995f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 65095f25efeSWolfram Sang 651a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 65295f25efeSWolfram Sang } 65395f25efeSWolfram Sang 6548ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 6558ba9580aSLucas Stach unsigned int clock) 6568ba9580aSLucas Stach { 6578ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 658070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 659a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 660d31fc00aSDong Aisheng int pre_div = 2; 661d31fc00aSDong Aisheng int div = 1; 662fed2f6e2SDong Aisheng u32 temp, val; 6638ba9580aSLucas Stach 664fed2f6e2SDong Aisheng if (clock == 0) { 6651650d0c7SRussell King host->mmc->actual_clock = 0; 6661650d0c7SRussell King 6679d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 668fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 669fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 670fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 671fed2f6e2SDong Aisheng } 672373073efSRussell King return; 673fed2f6e2SDong Aisheng } 674d31fc00aSDong Aisheng 675de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) 6765f7886c5SDong Aisheng pre_div = 1; 6775f7886c5SDong Aisheng 678d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 679d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 680d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 681d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 682d31fc00aSDong Aisheng 683d31fc00aSDong Aisheng while (host_clock / pre_div / 16 > clock && pre_div < 256) 684d31fc00aSDong Aisheng pre_div *= 2; 685d31fc00aSDong Aisheng 686d31fc00aSDong Aisheng while (host_clock / pre_div / div > clock && div < 16) 687d31fc00aSDong Aisheng div++; 688d31fc00aSDong Aisheng 689e76b8559SDong Aisheng host->mmc->actual_clock = host_clock / pre_div / div; 690d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 691e76b8559SDong Aisheng clock, host->mmc->actual_clock); 692d31fc00aSDong Aisheng 693de5bdbffSDong Aisheng if (imx_data->is_ddr) 694de5bdbffSDong Aisheng pre_div >>= 2; 695de5bdbffSDong Aisheng else 696d31fc00aSDong Aisheng pre_div >>= 1; 697d31fc00aSDong Aisheng div--; 698d31fc00aSDong Aisheng 699d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 700d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 701d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 702d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 703d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 704fed2f6e2SDong Aisheng 7059d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 706fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 707fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 708fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 709fed2f6e2SDong Aisheng } 710fed2f6e2SDong Aisheng 711d31fc00aSDong Aisheng mdelay(1); 7128ba9580aSLucas Stach } 7138ba9580aSLucas Stach 714913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 715913413c3SShawn Guo { 716842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 717070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 718842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 719913413c3SShawn Guo 720913413c3SShawn Guo switch (boarddata->wp_type) { 721913413c3SShawn Guo case ESDHC_WP_GPIO: 722fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 723913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 724913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 725913413c3SShawn Guo SDHCI_WRITE_PROTECT); 726913413c3SShawn Guo case ESDHC_WP_NONE: 727913413c3SShawn Guo break; 728913413c3SShawn Guo } 729913413c3SShawn Guo 730913413c3SShawn Guo return -ENOSYS; 731913413c3SShawn Guo } 732913413c3SShawn Guo 7332317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 734af51079eSSascha Hauer { 735af51079eSSascha Hauer u32 ctrl; 736af51079eSSascha Hauer 737af51079eSSascha Hauer switch (width) { 738af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 739af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 740af51079eSSascha Hauer break; 741af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 742af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 743af51079eSSascha Hauer break; 744af51079eSSascha Hauer default: 745af51079eSSascha Hauer ctrl = 0; 746af51079eSSascha Hauer break; 747af51079eSSascha Hauer } 748af51079eSSascha Hauer 749af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 750af51079eSSascha Hauer SDHCI_HOST_CONTROL); 751af51079eSSascha Hauer } 752af51079eSSascha Hauer 7530322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 7540322191eSDong Aisheng { 7550322191eSDong Aisheng u32 reg; 7560322191eSDong Aisheng 7570322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 7580322191eSDong Aisheng mdelay(1); 7590322191eSDong Aisheng 7600322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7610322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 7620322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 7630322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7640322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 7650322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 7660322191eSDong Aisheng "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 7670322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 7680322191eSDong Aisheng } 7690322191eSDong Aisheng 7700322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 7710322191eSDong Aisheng { 7720322191eSDong Aisheng u32 reg; 7730322191eSDong Aisheng 7740322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7750322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 776da0295ffSDong Aisheng reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 7770322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7780322191eSDong Aisheng } 7790322191eSDong Aisheng 7800322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 7810322191eSDong Aisheng { 7820322191eSDong Aisheng int min, max, avg, ret; 7830322191eSDong Aisheng 7840322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 7850322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 7860322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 7870322191eSDong Aisheng esdhc_prepare_tuning(host, min); 7889979dbe5SChaotian Jing if (!mmc_send_tuning(host->mmc, opcode, NULL)) 7890322191eSDong Aisheng break; 7900322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 7910322191eSDong Aisheng } 7920322191eSDong Aisheng 7930322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 7940322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 7950322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 7960322191eSDong Aisheng esdhc_prepare_tuning(host, max); 7979979dbe5SChaotian Jing if (mmc_send_tuning(host->mmc, opcode, NULL)) { 7980322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 7990322191eSDong Aisheng break; 8000322191eSDong Aisheng } 8010322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 8020322191eSDong Aisheng } 8030322191eSDong Aisheng 8040322191eSDong Aisheng /* use average delay to get the best timing */ 8050322191eSDong Aisheng avg = (min + max) / 2; 8060322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 8079979dbe5SChaotian Jing ret = mmc_send_tuning(host->mmc, opcode, NULL); 8080322191eSDong Aisheng esdhc_post_tuning(host); 8090322191eSDong Aisheng 8100322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 8110322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 8120322191eSDong Aisheng 8130322191eSDong Aisheng return ret; 8140322191eSDong Aisheng } 8150322191eSDong Aisheng 816ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 817ad93220dSDong Aisheng unsigned int uhs) 818ad93220dSDong Aisheng { 819ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 820070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 821ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 822ad93220dSDong Aisheng 823ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 824ad93220dSDong Aisheng 825ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 826ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 827ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 828ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 829ad93220dSDong Aisheng return -EINVAL; 830ad93220dSDong Aisheng 831ad93220dSDong Aisheng switch (uhs) { 832ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 8339f327845SHaibo Chen case MMC_TIMING_UHS_DDR50: 834ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 835ad93220dSDong Aisheng break; 836ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 837429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 83828b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 839ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 840ad93220dSDong Aisheng break; 841ad93220dSDong Aisheng default: 842ad93220dSDong Aisheng /* back to default state for other legacy timing */ 843ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 844ad93220dSDong Aisheng } 845ad93220dSDong Aisheng 846ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 847ad93220dSDong Aisheng } 848ad93220dSDong Aisheng 84928b07674SHaibo Chen /* 85028b07674SHaibo Chen * For HS400 eMMC, there is a data_strobe line, this signal is generated 85128b07674SHaibo Chen * by the device and used for data output and CRC status response output 85228b07674SHaibo Chen * in HS400 mode. The frequency of this signal follows the frequency of 85328b07674SHaibo Chen * CLK generated by host. Host receive the data which is aligned to the 85428b07674SHaibo Chen * edge of data_strobe line. Due to the time delay between CLK line and 85528b07674SHaibo Chen * data_strobe line, if the delay time is larger than one clock cycle, 85628b07674SHaibo Chen * then CLK and data_strobe line will misaligned, read error shows up. 85728b07674SHaibo Chen * So when the CLK is higher than 100MHz, each clock cycle is short enough, 85828b07674SHaibo Chen * host should config the delay target. 85928b07674SHaibo Chen */ 86028b07674SHaibo Chen static void esdhc_set_strobe_dll(struct sdhci_host *host) 86128b07674SHaibo Chen { 86228b07674SHaibo Chen u32 v; 86328b07674SHaibo Chen 86428b07674SHaibo Chen if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { 8657ac6da26SDong Aisheng /* disable clock before enabling strobe dll */ 8667ac6da26SDong Aisheng writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 8677ac6da26SDong Aisheng ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 8687ac6da26SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 8697ac6da26SDong Aisheng 87028b07674SHaibo Chen /* force a reset on strobe dll */ 87128b07674SHaibo Chen writel(ESDHC_STROBE_DLL_CTRL_RESET, 87228b07674SHaibo Chen host->ioaddr + ESDHC_STROBE_DLL_CTRL); 87328b07674SHaibo Chen /* 87428b07674SHaibo Chen * enable strobe dll ctrl and adjust the delay target 87528b07674SHaibo Chen * for the uSDHC loopback read clock 87628b07674SHaibo Chen */ 87728b07674SHaibo Chen v = ESDHC_STROBE_DLL_CTRL_ENABLE | 87828b07674SHaibo Chen (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 87928b07674SHaibo Chen writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 88028b07674SHaibo Chen /* wait 1us to make sure strobe dll status register stable */ 88128b07674SHaibo Chen udelay(1); 88228b07674SHaibo Chen v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); 88328b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) 88428b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 88528b07674SHaibo Chen "warning! HS400 strobe DLL status REF not lock!\n"); 88628b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 88728b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 88828b07674SHaibo Chen "warning! HS400 strobe DLL status SLV not lock!\n"); 88928b07674SHaibo Chen } 89028b07674SHaibo Chen } 89128b07674SHaibo Chen 892d9370424SHaibo Chen static void esdhc_reset_tuning(struct sdhci_host *host) 893d9370424SHaibo Chen { 894d9370424SHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 895d9370424SHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 896d9370424SHaibo Chen u32 ctrl; 897d9370424SHaibo Chen 898d9370424SHaibo Chen /* Rest the tuning circurt */ 899d9370424SHaibo Chen if (esdhc_is_usdhc(imx_data)) { 900d9370424SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 901d9370424SHaibo Chen ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 902d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 903d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 904d9370424SHaibo Chen writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 905d9370424SHaibo Chen writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 906d9370424SHaibo Chen } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 907d9370424SHaibo Chen ctrl = readl(host->ioaddr + SDHCI_ACMD12_ERR); 908d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 909d9370424SHaibo Chen writel(ctrl, host->ioaddr + SDHCI_ACMD12_ERR); 910d9370424SHaibo Chen } 911d9370424SHaibo Chen } 912d9370424SHaibo Chen } 913d9370424SHaibo Chen 914850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 915ad93220dSDong Aisheng { 91628b07674SHaibo Chen u32 m; 917ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 918070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 919602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 920ad93220dSDong Aisheng 92128b07674SHaibo Chen /* disable ddr mode and disable HS400 mode */ 92228b07674SHaibo Chen m = readl(host->ioaddr + ESDHC_MIX_CTRL); 92328b07674SHaibo Chen m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 92428b07674SHaibo Chen imx_data->is_ddr = 0; 92528b07674SHaibo Chen 926850a29b8SRussell King switch (timing) { 927ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 928ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 929ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 930ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 931429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 93228b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 933ad93220dSDong Aisheng break; 934ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 93569f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 93628b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN; 93728b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 938de5bdbffSDong Aisheng imx_data->is_ddr = 1; 939602519b2SDong Aisheng if (boarddata->delay_line) { 940602519b2SDong Aisheng u32 v; 941602519b2SDong Aisheng v = boarddata->delay_line << 942602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 943602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 944602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 945602519b2SDong Aisheng v <<= 1; 946602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 947602519b2SDong Aisheng } 948ad93220dSDong Aisheng break; 94928b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 95028b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 95128b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 95228b07674SHaibo Chen imx_data->is_ddr = 1; 9537ac6da26SDong Aisheng /* update clock after enable DDR for strobe DLL lock */ 9547ac6da26SDong Aisheng host->ops->set_clock(host, host->clock); 95528b07674SHaibo Chen esdhc_set_strobe_dll(host); 95628b07674SHaibo Chen break; 957d9370424SHaibo Chen case MMC_TIMING_LEGACY: 958d9370424SHaibo Chen default: 959d9370424SHaibo Chen esdhc_reset_tuning(host); 960d9370424SHaibo Chen break; 961ad93220dSDong Aisheng } 962ad93220dSDong Aisheng 963850a29b8SRussell King esdhc_change_pinstate(host, timing); 964ad93220dSDong Aisheng } 965ad93220dSDong Aisheng 9660718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 9670718e59aSRussell King { 9680718e59aSRussell King sdhci_reset(host, mask); 9690718e59aSRussell King 9700718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 9710718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 9720718e59aSRussell King } 9730718e59aSRussell King 97410fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 97510fd0ad9SAisheng Dong { 97610fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 977070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 97810fd0ad9SAisheng Dong 9792fb0b02bSHaibo Chen /* Doc Errata: the uSDHC actual maximum timeout count is 1 << 29 */ 9802fb0b02bSHaibo Chen return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 98110fd0ad9SAisheng Dong } 98210fd0ad9SAisheng Dong 983e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 984e33eb8e2SAisheng Dong { 985e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 986070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 987e33eb8e2SAisheng Dong 988e33eb8e2SAisheng Dong /* use maximum timeout counter */ 989a215186dSHaibo Chen esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 990a215186dSHaibo Chen esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 991e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 992e33eb8e2SAisheng Dong } 993e33eb8e2SAisheng Dong 9946e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 995e149860dSRichard Zhu .read_l = esdhc_readl_le, 9960c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 99777da3da0SAaron Brice .read_b = esdhc_readb_le, 998e149860dSRichard Zhu .write_l = esdhc_writel_le, 9990c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 10000c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 10018ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 10020ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 10030c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 100410fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 1005913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 1006e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 10072317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 1008ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 10090718e59aSRussell King .reset = esdhc_reset, 10100c6d49ceSWolfram Sang }; 10110c6d49ceSWolfram Sang 10121db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 101397e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 101497e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 101597e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 101685d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 101785d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 101885d6509dSShawn Guo }; 101985d6509dSShawn Guo 1020f3f5cf3dSDong Aisheng static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1021f3f5cf3dSDong Aisheng { 1022f3f5cf3dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1023f3f5cf3dSDong Aisheng struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 10242b16cf32SDong Aisheng int tmp; 1025f3f5cf3dSDong Aisheng 1026f3f5cf3dSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 1027f3f5cf3dSDong Aisheng /* 1028f3f5cf3dSDong Aisheng * The imx6q ROM code will change the default watermark 1029f3f5cf3dSDong Aisheng * level setting to something insane. Change it back here. 1030f3f5cf3dSDong Aisheng */ 1031f3f5cf3dSDong Aisheng writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1032f3f5cf3dSDong Aisheng 1033f3f5cf3dSDong Aisheng /* 1034f3f5cf3dSDong Aisheng * ROM code will change the bit burst_length_enable setting 1035f3f5cf3dSDong Aisheng * to zero if this usdhc is choosed to boot system. Change 1036f3f5cf3dSDong Aisheng * it back here, otherwise it will impact the performance a 1037f3f5cf3dSDong Aisheng * lot. This bit is used to enable/disable the burst length 1038f3f5cf3dSDong Aisheng * for the external AHB2AXI bridge, it's usefully especially 1039f3f5cf3dSDong Aisheng * for INCR transfer because without burst length indicator, 1040f3f5cf3dSDong Aisheng * the AHB2AXI bridge does not know the burst length in 1041f3f5cf3dSDong Aisheng * advance. And without burst length indicator, AHB INCR 1042f3f5cf3dSDong Aisheng * transfer can only be converted to singles on the AXI side. 1043f3f5cf3dSDong Aisheng */ 1044f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1045f3f5cf3dSDong Aisheng | ESDHC_BURST_LEN_EN_INCR, 1046f3f5cf3dSDong Aisheng host->ioaddr + SDHCI_HOST_CONTROL); 1047f3f5cf3dSDong Aisheng /* 1048f3f5cf3dSDong Aisheng * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1049f3f5cf3dSDong Aisheng * TO1.1, it's harmless for MX6SL 1050f3f5cf3dSDong Aisheng */ 1051f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + 0x6c) | BIT(7), 1052f3f5cf3dSDong Aisheng host->ioaddr + 0x6c); 1053f3f5cf3dSDong Aisheng 1054f3f5cf3dSDong Aisheng /* disable DLL_CTRL delay line settings */ 1055f3f5cf3dSDong Aisheng writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 10562b16cf32SDong Aisheng 10572b16cf32SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 10582b16cf32SDong Aisheng tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 10592b16cf32SDong Aisheng tmp |= ESDHC_STD_TUNING_EN | 10602b16cf32SDong Aisheng ESDHC_TUNING_START_TAP_DEFAULT; 10612b16cf32SDong Aisheng if (imx_data->boarddata.tuning_start_tap) { 10622b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_START_TAP_MASK; 10632b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_start_tap; 10642b16cf32SDong Aisheng } 10652b16cf32SDong Aisheng 10662b16cf32SDong Aisheng if (imx_data->boarddata.tuning_step) { 10672b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_STEP_MASK; 10682b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_step 10692b16cf32SDong Aisheng << ESDHC_TUNING_STEP_SHIFT; 10702b16cf32SDong Aisheng } 10712b16cf32SDong Aisheng writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 10722b16cf32SDong Aisheng } 1073f3f5cf3dSDong Aisheng } 1074f3f5cf3dSDong Aisheng } 1075f3f5cf3dSDong Aisheng 1076abfafc2dSShawn Guo #ifdef CONFIG_OF 1077c3be1efdSBill Pemberton static int 1078abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 107907bf2b54SSascha Hauer struct sdhci_host *host, 108091fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1081abfafc2dSShawn Guo { 1082abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 108391fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 10844800e87aSDong Aisheng int ret; 1085abfafc2dSShawn Guo 1086abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 1087abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 1088abfafc2dSShawn Guo 1089abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1090abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 1091abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 1092abfafc2dSShawn Guo 1093d407e30bSHaibo Chen of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1094d87fc966SDong Aisheng of_property_read_u32(np, "fsl,tuning-start-tap", 1095d87fc966SDong Aisheng &boarddata->tuning_start_tap); 1096d407e30bSHaibo Chen 1097ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 1098ad93220dSDong Aisheng boarddata->support_vsel = false; 1099ad93220dSDong Aisheng else 1100ad93220dSDong Aisheng boarddata->support_vsel = true; 1101ad93220dSDong Aisheng 1102602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1103602519b2SDong Aisheng boarddata->delay_line = 0; 1104602519b2SDong Aisheng 110507bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 110607bf2b54SSascha Hauer 110791fa4252SDong Aisheng /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 110891fa4252SDong Aisheng if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && 110991fa4252SDong Aisheng !IS_ERR(imx_data->pins_default)) { 111091fa4252SDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 111191fa4252SDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 111291fa4252SDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 111391fa4252SDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 111491fa4252SDong Aisheng if (IS_ERR(imx_data->pins_100mhz) || 111591fa4252SDong Aisheng IS_ERR(imx_data->pins_200mhz)) { 111691fa4252SDong Aisheng dev_warn(mmc_dev(host->mmc), 111791fa4252SDong Aisheng "could not get ultra high speed state, work on normal mode\n"); 111891fa4252SDong Aisheng /* 111991fa4252SDong Aisheng * fall back to not support uhs by specify no 1.8v quirk 112091fa4252SDong Aisheng */ 112191fa4252SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 112291fa4252SDong Aisheng } 112391fa4252SDong Aisheng } else { 112491fa4252SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 112591fa4252SDong Aisheng } 112691fa4252SDong Aisheng 112715064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 11284800e87aSDong Aisheng ret = mmc_of_parse(host->mmc); 11294800e87aSDong Aisheng if (ret) 11304800e87aSDong Aisheng return ret; 11314800e87aSDong Aisheng 1132287980e4SArnd Bergmann if (mmc_gpio_get_cd(host->mmc) >= 0) 11334800e87aSDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 11344800e87aSDong Aisheng 11354800e87aSDong Aisheng return 0; 1136abfafc2dSShawn Guo } 1137abfafc2dSShawn Guo #else 1138abfafc2dSShawn Guo static inline int 1139abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 114007bf2b54SSascha Hauer struct sdhci_host *host, 114191fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1142abfafc2dSShawn Guo { 1143abfafc2dSShawn Guo return -ENODEV; 1144abfafc2dSShawn Guo } 1145abfafc2dSShawn Guo #endif 1146abfafc2dSShawn Guo 114791fa4252SDong Aisheng static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 114891fa4252SDong Aisheng struct sdhci_host *host, 114991fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 115091fa4252SDong Aisheng { 115191fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 115291fa4252SDong Aisheng int err; 115391fa4252SDong Aisheng 115491fa4252SDong Aisheng if (!host->mmc->parent->platform_data) { 115591fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), "no board data!\n"); 115691fa4252SDong Aisheng return -EINVAL; 115791fa4252SDong Aisheng } 115891fa4252SDong Aisheng 115991fa4252SDong Aisheng imx_data->boarddata = *((struct esdhc_platform_data *) 116091fa4252SDong Aisheng host->mmc->parent->platform_data); 116191fa4252SDong Aisheng /* write_protect */ 116291fa4252SDong Aisheng if (boarddata->wp_type == ESDHC_WP_GPIO) { 116391fa4252SDong Aisheng err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 116491fa4252SDong Aisheng if (err) { 116591fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 116691fa4252SDong Aisheng "failed to request write-protect gpio!\n"); 116791fa4252SDong Aisheng return err; 116891fa4252SDong Aisheng } 116991fa4252SDong Aisheng host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 117091fa4252SDong Aisheng } 117191fa4252SDong Aisheng 117291fa4252SDong Aisheng /* card_detect */ 117391fa4252SDong Aisheng switch (boarddata->cd_type) { 117491fa4252SDong Aisheng case ESDHC_CD_GPIO: 117591fa4252SDong Aisheng err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 117691fa4252SDong Aisheng if (err) { 117791fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 117891fa4252SDong Aisheng "failed to request card-detect gpio!\n"); 117991fa4252SDong Aisheng return err; 118091fa4252SDong Aisheng } 118191fa4252SDong Aisheng /* fall through */ 118291fa4252SDong Aisheng 118391fa4252SDong Aisheng case ESDHC_CD_CONTROLLER: 118491fa4252SDong Aisheng /* we have a working card_detect back */ 118591fa4252SDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 118691fa4252SDong Aisheng break; 118791fa4252SDong Aisheng 118891fa4252SDong Aisheng case ESDHC_CD_PERMANENT: 118991fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 119091fa4252SDong Aisheng break; 119191fa4252SDong Aisheng 119291fa4252SDong Aisheng case ESDHC_CD_NONE: 119391fa4252SDong Aisheng break; 119491fa4252SDong Aisheng } 119591fa4252SDong Aisheng 119691fa4252SDong Aisheng switch (boarddata->max_bus_width) { 119791fa4252SDong Aisheng case 8: 119891fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 119991fa4252SDong Aisheng break; 120091fa4252SDong Aisheng case 4: 120191fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_4_BIT_DATA; 120291fa4252SDong Aisheng break; 120391fa4252SDong Aisheng case 1: 120491fa4252SDong Aisheng default: 120591fa4252SDong Aisheng host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 120691fa4252SDong Aisheng break; 120791fa4252SDong Aisheng } 120891fa4252SDong Aisheng 120991fa4252SDong Aisheng return 0; 121091fa4252SDong Aisheng } 121191fa4252SDong Aisheng 1212c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 121395f25efeSWolfram Sang { 1214abfafc2dSShawn Guo const struct of_device_id *of_id = 1215abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 121685d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 121785d6509dSShawn Guo struct sdhci_host *host; 12180c6d49ceSWolfram Sang int err; 1219e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 122095f25efeSWolfram Sang 1221070e6d3fSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1222070e6d3fSJisheng Zhang sizeof(*imx_data)); 122385d6509dSShawn Guo if (IS_ERR(host)) 122485d6509dSShawn Guo return PTR_ERR(host); 122585d6509dSShawn Guo 122685d6509dSShawn Guo pltfm_host = sdhci_priv(host); 122785d6509dSShawn Guo 1228070e6d3fSJisheng Zhang imx_data = sdhci_pltfm_priv(pltfm_host); 122957ed3314SShawn Guo 1230f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 12313770ee8fSShawn Guo pdev->id_entry->driver_data; 123285d6509dSShawn Guo 123352dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 123452dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 123552dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 1236e3af31c6SShawn Guo goto free_sdhci; 123795f25efeSWolfram Sang } 123852dac615SSascha Hauer 123952dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 124052dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 124152dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 1242e3af31c6SShawn Guo goto free_sdhci; 124352dac615SSascha Hauer } 124452dac615SSascha Hauer 124552dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 124652dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 124752dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 1248e3af31c6SShawn Guo goto free_sdhci; 124952dac615SSascha Hauer } 125052dac615SSascha Hauer 125152dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 1252a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 125352dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 125452dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 125552dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 125695f25efeSWolfram Sang 1257ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1258e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1259e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 1260e3af31c6SShawn Guo goto disable_clk; 1261e62d8b8fSDong Aisheng } 1262e62d8b8fSDong Aisheng 1263ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 1264ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 1265cd529af7SDirk Behme if (IS_ERR(imx_data->pins_default)) 1266cd529af7SDirk Behme dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 1267ad93220dSDong Aisheng 1268f47c4bbfSShawn Guo if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 12690c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 127097e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 127197e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 12720c6d49ceSWolfram Sang 127369ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 127469ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1275e2997c94SDong Aisheng host->mmc->caps |= MMC_CAP_1_8V_DDR; 12764245afffSDong Aisheng if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 12774245afffSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1278a75dcbf4SDong Aisheng 1279a75dcbf4SDong Aisheng /* clear tuning bits in case ROM has set it already */ 1280a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1281a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR); 1282a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 128369ed60e0SDong Aisheng } 1284f750ba9bSShawn Guo 12856e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 12866e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 12876e9fd28eSDong Aisheng esdhc_executing_tuning; 12888b2bb0adSDong Aisheng 128918094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 129018094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 129118094430SDong Aisheng 129228b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 129328b07674SHaibo Chen host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 129428b07674SHaibo Chen 129591fa4252SDong Aisheng if (of_id) 129691fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 129791fa4252SDong Aisheng else 129891fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 129991fa4252SDong Aisheng if (err) 1300e3af31c6SShawn Guo goto disable_clk; 1301ad93220dSDong Aisheng 1302f3f5cf3dSDong Aisheng sdhci_esdhc_imx_hwinit(host); 1303f3f5cf3dSDong Aisheng 130485d6509dSShawn Guo err = sdhci_add_host(host); 130585d6509dSShawn Guo if (err) 1306e3af31c6SShawn Guo goto disable_clk; 130785d6509dSShawn Guo 130889d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 130989d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 131089d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 131189d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 131277903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 131389d7e5c1SDong Aisheng 13147e29c306SWolfram Sang return 0; 13157e29c306SWolfram Sang 1316e3af31c6SShawn Guo disable_clk: 131752dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 131852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 131952dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 1320e3af31c6SShawn Guo free_sdhci: 132185d6509dSShawn Guo sdhci_pltfm_free(pdev); 132285d6509dSShawn Guo return err; 132395f25efeSWolfram Sang } 132495f25efeSWolfram Sang 13256e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 132695f25efeSWolfram Sang { 132785d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 132895f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1329070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 133085d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 133185d6509dSShawn Guo 13320b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 13330b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 13340b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 13350b414368SUlf Hansson 133685d6509dSShawn Guo sdhci_remove_host(host, dead); 13370c6d49ceSWolfram Sang 133852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 133952dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 134052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 134152dac615SSascha Hauer 134285d6509dSShawn Guo sdhci_pltfm_free(pdev); 134385d6509dSShawn Guo 134485d6509dSShawn Guo return 0; 134595f25efeSWolfram Sang } 134695f25efeSWolfram Sang 13472788ed42SUlf Hansson #ifdef CONFIG_PM_SLEEP 134804143fbaSDong Aisheng static int sdhci_esdhc_suspend(struct device *dev) 134904143fbaSDong Aisheng { 13503e3274abSUlf Hansson struct sdhci_host *host = dev_get_drvdata(dev); 13513e3274abSUlf Hansson 1352d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1353d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1354d38dcad4SAdrian Hunter 13553e3274abSUlf Hansson return sdhci_suspend_host(host); 135604143fbaSDong Aisheng } 135704143fbaSDong Aisheng 135804143fbaSDong Aisheng static int sdhci_esdhc_resume(struct device *dev) 135904143fbaSDong Aisheng { 1360cc17e129SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 1361cc17e129SDong Aisheng 136219dbfdd3SDong Aisheng /* re-initialize hw state in case it's lost in low power mode */ 136319dbfdd3SDong Aisheng sdhci_esdhc_imx_hwinit(host); 1364cc17e129SDong Aisheng 13653e3274abSUlf Hansson return sdhci_resume_host(host); 136604143fbaSDong Aisheng } 13672788ed42SUlf Hansson #endif 136804143fbaSDong Aisheng 13692788ed42SUlf Hansson #ifdef CONFIG_PM 137089d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 137189d7e5c1SDong Aisheng { 137289d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 137389d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1374070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 137589d7e5c1SDong Aisheng int ret; 137689d7e5c1SDong Aisheng 137789d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 137889d7e5c1SDong Aisheng 1379d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1380d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1381d38dcad4SAdrian Hunter 1382be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 138389d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 138489d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 1385be138554SRussell King } 138689d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 138789d7e5c1SDong Aisheng 138889d7e5c1SDong Aisheng return ret; 138989d7e5c1SDong Aisheng } 139089d7e5c1SDong Aisheng 139189d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 139289d7e5c1SDong Aisheng { 139389d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 139489d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1395070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 139689d7e5c1SDong Aisheng 1397be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 139889d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_per); 139989d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ipg); 1400be138554SRussell King } 140189d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ahb); 140289d7e5c1SDong Aisheng 140389d7e5c1SDong Aisheng return sdhci_runtime_resume_host(host); 140489d7e5c1SDong Aisheng } 140589d7e5c1SDong Aisheng #endif 140689d7e5c1SDong Aisheng 140789d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 140804143fbaSDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 140989d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 141089d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 141189d7e5c1SDong Aisheng }; 141289d7e5c1SDong Aisheng 141385d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 141485d6509dSShawn Guo .driver = { 141585d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1416abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 141789d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 141885d6509dSShawn Guo }, 141957ed3314SShawn Guo .id_table = imx_esdhc_devtype, 142085d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 14210433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 142295f25efeSWolfram Sang }; 142385d6509dSShawn Guo 1424d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 142585d6509dSShawn Guo 142685d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1427035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 142885d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1429