195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 7035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3089d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 3195f25efeSWolfram Sang #include "sdhci-pltfm.h" 3295f25efeSWolfram Sang #include "sdhci-esdhc.h" 3395f25efeSWolfram Sang 3460bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 3558ac8177SRichard Zhu /* VENDOR SPEC register */ 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3760bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 380322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 39fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 4060bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 4160bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 42de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 432a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 440322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 450322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 460322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 472a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 482a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 49d131a71cSDong Aisheng /* Tuning bits */ 50d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 5158ac8177SRichard Zhu 52602519b2SDong Aisheng /* dll control register */ 53602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 54602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 55602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 56602519b2SDong Aisheng 570322191eSDong Aisheng /* tune control register */ 580322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 590322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 600322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 610322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 620322191eSDong Aisheng 636e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 646e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 656e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 666e9fd28eSDong Aisheng #define ESDHC_TUNING_START_TAP 0x1 676e9fd28eSDong Aisheng 68ad93220dSDong Aisheng /* pinctrl state */ 69ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 70ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 71ad93220dSDong Aisheng 7258ac8177SRichard Zhu /* 73af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 74af51079eSSascha Hauer */ 75af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 76af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 77af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 78af51079eSSascha Hauer 79af51079eSSascha Hauer /* 8097e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 8197e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 8297e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 8397e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 8497e4ba6aSRichard Zhu */ 8560bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 8697e4ba6aSRichard Zhu 8797e4ba6aSRichard Zhu /* 8858ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 8958ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 9058ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 9158ac8177SRichard Zhu * be generated. 9258ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 9358ac8177SRichard Zhu * operations automatically as required at the end of the 9458ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 9558ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 9658ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 9758ac8177SRichard Zhu */ 9831fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 9931fbb301SShawn Guo /* 10031fbb301SShawn Guo * The flag enables the workaround for ESDHC errata ENGcm07207 which 10131fbb301SShawn Guo * affects i.MX25 and i.MX35. 10231fbb301SShawn Guo */ 10331fbb301SShawn Guo #define ESDHC_FLAG_ENGCM07207 BIT(2) 1049d61c009SShawn Guo /* 1059d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1069d61c009SShawn Guo * integrated on the i.MX6 series. 1079d61c009SShawn Guo */ 1089d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1096e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1106e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1116e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1126e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1136e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1146e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 11518094430SDong Aisheng /* 11618094430SDong Aisheng * The IP has errata ERR004536 11718094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 11818094430SDong Aisheng * when reading data from the card 11918094430SDong Aisheng */ 12018094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 1214245afffSDong Aisheng /* The IP supports HS200 mode */ 1224245afffSDong Aisheng #define ESDHC_FLAG_HS200 BIT(8) 123e149860dSRichard Zhu 124f47c4bbfSShawn Guo struct esdhc_soc_data { 125f47c4bbfSShawn Guo u32 flags; 126f47c4bbfSShawn Guo }; 127f47c4bbfSShawn Guo 128f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx25_data = { 129f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 130f47c4bbfSShawn Guo }; 131f47c4bbfSShawn Guo 132f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx35_data = { 133f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 134f47c4bbfSShawn Guo }; 135f47c4bbfSShawn Guo 136f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx51_data = { 137f47c4bbfSShawn Guo .flags = 0, 138f47c4bbfSShawn Guo }; 139f47c4bbfSShawn Guo 140f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx53_data = { 141f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 142f47c4bbfSShawn Guo }; 143f47c4bbfSShawn Guo 144f47c4bbfSShawn Guo static struct esdhc_soc_data usdhc_imx6q_data = { 1456e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1466e9fd28eSDong Aisheng }; 1476e9fd28eSDong Aisheng 1486e9fd28eSDong Aisheng static struct esdhc_soc_data usdhc_imx6sl_data = { 1496e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1504245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 1514245afffSDong Aisheng | ESDHC_FLAG_HS200, 15257ed3314SShawn Guo }; 15357ed3314SShawn Guo 154913d4951SDong Aisheng static struct esdhc_soc_data usdhc_imx6sx_data = { 155913d4951SDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1564245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 157913d4951SDong Aisheng }; 158913d4951SDong Aisheng 159e149860dSRichard Zhu struct pltfm_imx_data { 160e149860dSRichard Zhu u32 scratchpad; 161e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 162ad93220dSDong Aisheng struct pinctrl_state *pins_default; 163ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 164ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 165f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 166842afc02SShawn Guo struct esdhc_platform_data boarddata; 16752dac615SSascha Hauer struct clk *clk_ipg; 16852dac615SSascha Hauer struct clk *clk_ahb; 16952dac615SSascha Hauer struct clk *clk_per; 170361b8482SLucas Stach enum { 171361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending*/ 172361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 173361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 174361b8482SLucas Stach } multiblock_status; 175de5bdbffSDong Aisheng u32 is_ddr; 176e149860dSRichard Zhu }; 177e149860dSRichard Zhu 178f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 17957ed3314SShawn Guo { 18057ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 181f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 18257ed3314SShawn Guo }, { 18357ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 184f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 18557ed3314SShawn Guo }, { 18657ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 187f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 18857ed3314SShawn Guo }, { 18957ed3314SShawn Guo /* sentinel */ 19057ed3314SShawn Guo } 19157ed3314SShawn Guo }; 19257ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 19357ed3314SShawn Guo 194abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 195f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 196f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 197f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 198f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 199913d4951SDong Aisheng { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 2006e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 201f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 202abfafc2dSShawn Guo { /* sentinel */ } 203abfafc2dSShawn Guo }; 204abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 205abfafc2dSShawn Guo 20657ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 20757ed3314SShawn Guo { 208f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 20957ed3314SShawn Guo } 21057ed3314SShawn Guo 21157ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 21257ed3314SShawn Guo { 213f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 21457ed3314SShawn Guo } 21557ed3314SShawn Guo 21695a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 21795a2482aSShawn Guo { 218f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 21995a2482aSShawn Guo } 22095a2482aSShawn Guo 2219d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2229d61c009SShawn Guo { 223f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2249d61c009SShawn Guo } 2259d61c009SShawn Guo 22695f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 22795f25efeSWolfram Sang { 22895f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 22995f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 23095f25efeSWolfram Sang 23195f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 23295f25efeSWolfram Sang } 23395f25efeSWolfram Sang 2347e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 2357e29c306SWolfram Sang { 236361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 237361b8482SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 238913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 239913413c3SShawn Guo 2400322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 2410322191eSDong Aisheng u32 fsl_prss = val; 2420322191eSDong Aisheng /* save the least 20 bits */ 2430322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 2440322191eSDong Aisheng /* move dat[0-3] bits */ 2450322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 2460322191eSDong Aisheng /* move cmd line bit */ 2470322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 2480322191eSDong Aisheng } 2490322191eSDong Aisheng 25097e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 2516b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 2526b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2536b4fb671SDong Aisheng val &= 0xffff0000; 2546b4fb671SDong Aisheng 25597e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 25697e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 25797e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 25897e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 25997e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 26097e4ba6aSRichard Zhu */ 26197e4ba6aSRichard Zhu 26297e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 26397e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 26497e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 26597e4ba6aSRichard Zhu } 26697e4ba6aSRichard Zhu } 26797e4ba6aSRichard Zhu 2686e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 2696e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 2706e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2716e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 2726e9fd28eSDong Aisheng else 2736e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 2740322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 275888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 276888824bbSDong Aisheng | SDHCI_USE_SDR50_TUNING; 2776e9fd28eSDong Aisheng } 2786e9fd28eSDong Aisheng } 2790322191eSDong Aisheng 2809d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 2810322191eSDong Aisheng val = 0; 2820322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 2830322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 2840322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 2850322191eSDong Aisheng } 2860322191eSDong Aisheng 28797e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 28860bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 28960bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 29097e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 29197e4ba6aSRichard Zhu } 292361b8482SLucas Stach 293361b8482SLucas Stach /* 294361b8482SLucas Stach * mask off the interrupt we get in response to the manually 295361b8482SLucas Stach * sent CMD12 296361b8482SLucas Stach */ 297361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 298361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 299361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 300361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 301361b8482SLucas Stach SDHCI_INT_STATUS); 302361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 303361b8482SLucas Stach } 30497e4ba6aSRichard Zhu } 30597e4ba6aSRichard Zhu 3067e29c306SWolfram Sang return val; 3077e29c306SWolfram Sang } 3087e29c306SWolfram Sang 3097e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 3107e29c306SWolfram Sang { 311e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 312e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 3130d58864bSTony Lin u32 data; 314e149860dSRichard Zhu 3150d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 316b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 3170d58864bSTony Lin /* 3180d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 3190d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 3200d58864bSTony Lin * so we need to apply the following workaround: clear 3210d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 3220d58864bSTony Lin * interrupt. In case a card interrupt was lost, 3230d58864bSTony Lin * re-sample it by the following steps. 3240d58864bSTony Lin */ 3250d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 32660bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 3270d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 32860bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 3290d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 3300d58864bSTony Lin } 331915be485SDong Aisheng 332915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 333915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 334915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 335915be485SDong Aisheng } 3360d58864bSTony Lin } 3370d58864bSTony Lin 338f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 33958ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 34058ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 34158ac8177SRichard Zhu u32 v; 34260bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 34360bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 34460bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 345361b8482SLucas Stach 346361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 347361b8482SLucas Stach { 348361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 349361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 350361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 351361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 352361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 353361b8482SLucas Stach } 35458ac8177SRichard Zhu } 35558ac8177SRichard Zhu 3567e29c306SWolfram Sang writel(val, host->ioaddr + reg); 3577e29c306SWolfram Sang } 3587e29c306SWolfram Sang 35995f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 36095f25efeSWolfram Sang { 361ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 362ef4d0888SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 3630322191eSDong Aisheng u16 ret = 0; 3640322191eSDong Aisheng u32 val; 365ef4d0888SShawn Guo 36695a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 367ef4d0888SShawn Guo reg ^= 2; 3689d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 36995a2482aSShawn Guo /* 370ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 371ef4d0888SShawn Guo * Correct it here. 37295a2482aSShawn Guo */ 373ef4d0888SShawn Guo return SDHCI_SPEC_300; 374ef4d0888SShawn Guo } 37595a2482aSShawn Guo } 37695f25efeSWolfram Sang 3770322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 3780322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 3790322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 3800322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 3810322191eSDong Aisheng 3829d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 3836e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 3840322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 3856e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 3866e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 3876e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 3886e9fd28eSDong Aisheng } 3896e9fd28eSDong Aisheng 3900322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 3910322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 3920322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 3930322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 3940322191eSDong Aisheng 3950322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 3960322191eSDong Aisheng 3970322191eSDong Aisheng return ret; 3980322191eSDong Aisheng } 3990322191eSDong Aisheng 4007dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 4017dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 4027dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4037dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 4047dd109efSDong Aisheng /* Swap AC23 bit */ 4057dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 4067dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 4077dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 4087dd109efSDong Aisheng } 4097dd109efSDong Aisheng } else { 4107dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 4117dd109efSDong Aisheng } 4127dd109efSDong Aisheng 4137dd109efSDong Aisheng return ret; 4147dd109efSDong Aisheng } 4157dd109efSDong Aisheng 41695f25efeSWolfram Sang return readw(host->ioaddr + reg); 41795f25efeSWolfram Sang } 41895f25efeSWolfram Sang 41995f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 42095f25efeSWolfram Sang { 42195f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 422e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 4230322191eSDong Aisheng u32 new_val = 0; 42495f25efeSWolfram Sang 42595f25efeSWolfram Sang switch (reg) { 4260322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 4270322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4280322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 4290322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4300322191eSDong Aisheng else 4310322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4320322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4330322191eSDong Aisheng return; 4340322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 4350322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4360322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 4370322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 4380322191eSDong Aisheng else 4390322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 4400322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4416e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 4420322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4430322191eSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) 4440322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4450322191eSDong Aisheng else 4460322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4470322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 4486e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 4496e9fd28eSDong Aisheng u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4506e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4518b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4528b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4536e9fd28eSDong Aisheng } else { 4548b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4556e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 4566e9fd28eSDong Aisheng } 4576e9fd28eSDong Aisheng 4588b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 4598b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 4608b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 4618b2bb0adSDong Aisheng } else { 4628b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 4638b2bb0adSDong Aisheng } 4646e9fd28eSDong Aisheng 4656e9fd28eSDong Aisheng writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 4666e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 4676e9fd28eSDong Aisheng } 4680322191eSDong Aisheng return; 46995f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 470f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 47158ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 47258ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 47358ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 47458ac8177SRichard Zhu u32 v; 47560bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 47660bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 47760bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 47858ac8177SRichard Zhu } 47969f54698SShawn Guo 4809d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 48169f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4822a15f981SShawn Guo /* Swap AC23 bit */ 4832a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 4842a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 4852a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 4862a15f981SShawn Guo } 4872a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 48869f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 48969f54698SShawn Guo } else { 49069f54698SShawn Guo /* 49169f54698SShawn Guo * Postpone this write, we must do it together with a 49269f54698SShawn Guo * command write that is down below. 49369f54698SShawn Guo */ 494e149860dSRichard Zhu imx_data->scratchpad = val; 49569f54698SShawn Guo } 49695f25efeSWolfram Sang return; 49795f25efeSWolfram Sang case SDHCI_COMMAND: 498361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 49958ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 50095a2482aSShawn Guo 501361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 502f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 503361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 504361b8482SLucas Stach 5059d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 50695a2482aSShawn Guo writel(val << 16, 50795a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 50869f54698SShawn Guo else 509e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 51095f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 51195f25efeSWolfram Sang return; 51295f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 51395f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 51495f25efeSWolfram Sang break; 51595f25efeSWolfram Sang } 51695f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 51795f25efeSWolfram Sang } 51895f25efeSWolfram Sang 51995f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 52095f25efeSWolfram Sang { 5219a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5229a0985b7SWilson Callan struct pltfm_imx_data *imx_data = pltfm_host->priv; 52395f25efeSWolfram Sang u32 new_val; 524af51079eSSascha Hauer u32 mask; 52595f25efeSWolfram Sang 52695f25efeSWolfram Sang switch (reg) { 52795f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 52895f25efeSWolfram Sang /* 52995f25efeSWolfram Sang * FSL put some DMA bits here 53095f25efeSWolfram Sang * If your board has a regulator, code should be here 53195f25efeSWolfram Sang */ 53295f25efeSWolfram Sang return; 53395f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 5346b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 535af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 5367122bbb0SMasanari Iida /* ensure the endianness */ 53795f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 5389a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 5399a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 54095f25efeSWolfram Sang /* DMA mode bits are shifted */ 54195f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 5429a0985b7SWilson Callan } 54395f25efeSWolfram Sang 544af51079eSSascha Hauer /* 545af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 546af51079eSSascha Hauer * esdhc_pltfm_bus_width. 547f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 548f6825748SMartin Fuzzey * SDIO interrupt errata workaround. 549af51079eSSascha Hauer */ 550f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 551af51079eSSascha Hauer 552af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 55395f25efeSWolfram Sang return; 55495f25efeSWolfram Sang } 55595f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 556913413c3SShawn Guo 557913413c3SShawn Guo /* 558913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 559913413c3SShawn Guo * that software reset should not affect card detection circuit. 560913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 561913413c3SShawn Guo * software reset. This will stop those clocks that card detection 562913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 563913413c3SShawn Guo * to keep card detection circuit functional. 564913413c3SShawn Guo */ 56558c8c4fbSShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 566913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 56758c8c4fbSShawn Guo /* 56858c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 56958c8c4fbSShawn Guo * Do it manually here. 57058c8c4fbSShawn Guo */ 571de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 572d131a71cSDong Aisheng /* the tuning bits should be kept during reset */ 573d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 574d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 575d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 576de5bdbffSDong Aisheng imx_data->is_ddr = 0; 577de5bdbffSDong Aisheng } 57858c8c4fbSShawn Guo } 57995f25efeSWolfram Sang } 58095f25efeSWolfram Sang 5810ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 5820ddf03c9SLucas Stach { 5830ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5840ddf03c9SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 5850ddf03c9SLucas Stach struct esdhc_platform_data *boarddata = &imx_data->boarddata; 5860ddf03c9SLucas Stach 587a974862fSDong Aisheng if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock)) 5880ddf03c9SLucas Stach return boarddata->f_max; 5890ddf03c9SLucas Stach else 590a974862fSDong Aisheng return pltfm_host->clock; 5910ddf03c9SLucas Stach } 5920ddf03c9SLucas Stach 59395f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 59495f25efeSWolfram Sang { 59595f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 59695f25efeSWolfram Sang 597a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 59895f25efeSWolfram Sang } 59995f25efeSWolfram Sang 6008ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 6018ba9580aSLucas Stach unsigned int clock) 6028ba9580aSLucas Stach { 6038ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 604fed2f6e2SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 605a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 606d31fc00aSDong Aisheng int pre_div = 2; 607d31fc00aSDong Aisheng int div = 1; 608fed2f6e2SDong Aisheng u32 temp, val; 6098ba9580aSLucas Stach 610fed2f6e2SDong Aisheng if (clock == 0) { 6111650d0c7SRussell King host->mmc->actual_clock = 0; 6121650d0c7SRussell King 6139d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 614fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 615fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 616fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 617fed2f6e2SDong Aisheng } 618373073efSRussell King return; 619fed2f6e2SDong Aisheng } 620d31fc00aSDong Aisheng 621de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) 6225f7886c5SDong Aisheng pre_div = 1; 6235f7886c5SDong Aisheng 624d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 625d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 626d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 627d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 628d31fc00aSDong Aisheng 629d31fc00aSDong Aisheng while (host_clock / pre_div / 16 > clock && pre_div < 256) 630d31fc00aSDong Aisheng pre_div *= 2; 631d31fc00aSDong Aisheng 632d31fc00aSDong Aisheng while (host_clock / pre_div / div > clock && div < 16) 633d31fc00aSDong Aisheng div++; 634d31fc00aSDong Aisheng 635e76b8559SDong Aisheng host->mmc->actual_clock = host_clock / pre_div / div; 636d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 637e76b8559SDong Aisheng clock, host->mmc->actual_clock); 638d31fc00aSDong Aisheng 639de5bdbffSDong Aisheng if (imx_data->is_ddr) 640de5bdbffSDong Aisheng pre_div >>= 2; 641de5bdbffSDong Aisheng else 642d31fc00aSDong Aisheng pre_div >>= 1; 643d31fc00aSDong Aisheng div--; 644d31fc00aSDong Aisheng 645d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 646d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 647d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 648d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 649d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 650fed2f6e2SDong Aisheng 6519d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 652fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 653fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 654fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 655fed2f6e2SDong Aisheng } 656fed2f6e2SDong Aisheng 657d31fc00aSDong Aisheng mdelay(1); 6588ba9580aSLucas Stach } 6598ba9580aSLucas Stach 660913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 661913413c3SShawn Guo { 662842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 663842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 664842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 665913413c3SShawn Guo 666913413c3SShawn Guo switch (boarddata->wp_type) { 667913413c3SShawn Guo case ESDHC_WP_GPIO: 668fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 669913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 670913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 671913413c3SShawn Guo SDHCI_WRITE_PROTECT); 672913413c3SShawn Guo case ESDHC_WP_NONE: 673913413c3SShawn Guo break; 674913413c3SShawn Guo } 675913413c3SShawn Guo 676913413c3SShawn Guo return -ENOSYS; 677913413c3SShawn Guo } 678913413c3SShawn Guo 6792317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 680af51079eSSascha Hauer { 681af51079eSSascha Hauer u32 ctrl; 682af51079eSSascha Hauer 683af51079eSSascha Hauer switch (width) { 684af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 685af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 686af51079eSSascha Hauer break; 687af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 688af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 689af51079eSSascha Hauer break; 690af51079eSSascha Hauer default: 691af51079eSSascha Hauer ctrl = 0; 692af51079eSSascha Hauer break; 693af51079eSSascha Hauer } 694af51079eSSascha Hauer 695af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 696af51079eSSascha Hauer SDHCI_HOST_CONTROL); 697af51079eSSascha Hauer } 698af51079eSSascha Hauer 6990322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 7000322191eSDong Aisheng { 7010322191eSDong Aisheng u32 reg; 7020322191eSDong Aisheng 7030322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 7040322191eSDong Aisheng mdelay(1); 7050322191eSDong Aisheng 7060322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7070322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 7080322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 7090322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7100322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 7110322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 7120322191eSDong Aisheng "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 7130322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 7140322191eSDong Aisheng } 7150322191eSDong Aisheng 7160322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 7170322191eSDong Aisheng { 7180322191eSDong Aisheng u32 reg; 7190322191eSDong Aisheng 7200322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7210322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 7220322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7230322191eSDong Aisheng } 7240322191eSDong Aisheng 7250322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 7260322191eSDong Aisheng { 7270322191eSDong Aisheng int min, max, avg, ret; 7280322191eSDong Aisheng 7290322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 7300322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 7310322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 7320322191eSDong Aisheng esdhc_prepare_tuning(host, min); 733d1785326SUlf Hansson if (!mmc_send_tuning(host->mmc)) 7340322191eSDong Aisheng break; 7350322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 7360322191eSDong Aisheng } 7370322191eSDong Aisheng 7380322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 7390322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 7400322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 7410322191eSDong Aisheng esdhc_prepare_tuning(host, max); 742d1785326SUlf Hansson if (mmc_send_tuning(host->mmc)) { 7430322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 7440322191eSDong Aisheng break; 7450322191eSDong Aisheng } 7460322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 7470322191eSDong Aisheng } 7480322191eSDong Aisheng 7490322191eSDong Aisheng /* use average delay to get the best timing */ 7500322191eSDong Aisheng avg = (min + max) / 2; 7510322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 752d1785326SUlf Hansson ret = mmc_send_tuning(host->mmc); 7530322191eSDong Aisheng esdhc_post_tuning(host); 7540322191eSDong Aisheng 7550322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 7560322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 7570322191eSDong Aisheng 7580322191eSDong Aisheng return ret; 7590322191eSDong Aisheng } 7600322191eSDong Aisheng 761ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 762ad93220dSDong Aisheng unsigned int uhs) 763ad93220dSDong Aisheng { 764ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 765ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 766ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 767ad93220dSDong Aisheng 768ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 769ad93220dSDong Aisheng 770ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 771ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 772ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 773ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 774ad93220dSDong Aisheng return -EINVAL; 775ad93220dSDong Aisheng 776ad93220dSDong Aisheng switch (uhs) { 777ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 778ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 779ad93220dSDong Aisheng break; 780ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 781429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 782ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 783ad93220dSDong Aisheng break; 784ad93220dSDong Aisheng default: 785ad93220dSDong Aisheng /* back to default state for other legacy timing */ 786ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 787ad93220dSDong Aisheng } 788ad93220dSDong Aisheng 789ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 790ad93220dSDong Aisheng } 791ad93220dSDong Aisheng 792850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 793ad93220dSDong Aisheng { 794ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 795ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 796602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 797ad93220dSDong Aisheng 798850a29b8SRussell King switch (timing) { 799ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 800ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 801ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 802ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 803429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 804ad93220dSDong Aisheng break; 805ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 80669f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 807de5bdbffSDong Aisheng writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | 808de5bdbffSDong Aisheng ESDHC_MIX_CTRL_DDREN, 809de5bdbffSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 810de5bdbffSDong Aisheng imx_data->is_ddr = 1; 811602519b2SDong Aisheng if (boarddata->delay_line) { 812602519b2SDong Aisheng u32 v; 813602519b2SDong Aisheng v = boarddata->delay_line << 814602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 815602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 816602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 817602519b2SDong Aisheng v <<= 1; 818602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 819602519b2SDong Aisheng } 820ad93220dSDong Aisheng break; 821ad93220dSDong Aisheng } 822ad93220dSDong Aisheng 823850a29b8SRussell King esdhc_change_pinstate(host, timing); 824ad93220dSDong Aisheng } 825ad93220dSDong Aisheng 8260718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 8270718e59aSRussell King { 8280718e59aSRussell King sdhci_reset(host, mask); 8290718e59aSRussell King 8300718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 8310718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 8320718e59aSRussell King } 8330718e59aSRussell King 83410fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 83510fd0ad9SAisheng Dong { 83610fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 83710fd0ad9SAisheng Dong struct pltfm_imx_data *imx_data = pltfm_host->priv; 83810fd0ad9SAisheng Dong 83910fd0ad9SAisheng Dong return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; 84010fd0ad9SAisheng Dong } 84110fd0ad9SAisheng Dong 842e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 843e33eb8e2SAisheng Dong { 844e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 845e33eb8e2SAisheng Dong struct pltfm_imx_data *imx_data = pltfm_host->priv; 846e33eb8e2SAisheng Dong 847e33eb8e2SAisheng Dong /* use maximum timeout counter */ 848e33eb8e2SAisheng Dong sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 849e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 850e33eb8e2SAisheng Dong } 851e33eb8e2SAisheng Dong 8526e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 853e149860dSRichard Zhu .read_l = esdhc_readl_le, 8540c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 855e149860dSRichard Zhu .write_l = esdhc_writel_le, 8560c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 8570c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 8588ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 8590ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 8600c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 86110fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 862913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 863e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 8642317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 865ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 8660718e59aSRussell King .reset = esdhc_reset, 8670c6d49ceSWolfram Sang }; 8680c6d49ceSWolfram Sang 8691db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 87097e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 87197e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 87297e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 87385d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 87485d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 87585d6509dSShawn Guo }; 87685d6509dSShawn Guo 877abfafc2dSShawn Guo #ifdef CONFIG_OF 878c3be1efdSBill Pemberton static int 879abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 88007bf2b54SSascha Hauer struct sdhci_host *host, 88191fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 882abfafc2dSShawn Guo { 883abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 88491fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 8854800e87aSDong Aisheng int ret; 886abfafc2dSShawn Guo 8877f217794SArnd Bergmann if (of_get_property(np, "non-removable", NULL)) 888abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_PERMANENT; 889abfafc2dSShawn Guo 890abfafc2dSShawn Guo if (of_get_property(np, "fsl,cd-controller", NULL)) 891abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_CONTROLLER; 892abfafc2dSShawn Guo 893abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 894abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 895abfafc2dSShawn Guo 896abfafc2dSShawn Guo boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 897abfafc2dSShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 898abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_GPIO; 899abfafc2dSShawn Guo 900abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 901abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 902abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 903abfafc2dSShawn Guo 904af51079eSSascha Hauer of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); 905af51079eSSascha Hauer 9060ddf03c9SLucas Stach of_property_read_u32(np, "max-frequency", &boarddata->f_max); 9070ddf03c9SLucas Stach 908ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 909ad93220dSDong Aisheng boarddata->support_vsel = false; 910ad93220dSDong Aisheng else 911ad93220dSDong Aisheng boarddata->support_vsel = true; 912ad93220dSDong Aisheng 913602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 914602519b2SDong Aisheng boarddata->delay_line = 0; 915602519b2SDong Aisheng 91607bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 91707bf2b54SSascha Hauer 91891fa4252SDong Aisheng /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 91991fa4252SDong Aisheng if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && 92091fa4252SDong Aisheng !IS_ERR(imx_data->pins_default)) { 92191fa4252SDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 92291fa4252SDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 92391fa4252SDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 92491fa4252SDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 92591fa4252SDong Aisheng if (IS_ERR(imx_data->pins_100mhz) || 92691fa4252SDong Aisheng IS_ERR(imx_data->pins_200mhz)) { 92791fa4252SDong Aisheng dev_warn(mmc_dev(host->mmc), 92891fa4252SDong Aisheng "could not get ultra high speed state, work on normal mode\n"); 92991fa4252SDong Aisheng /* 93091fa4252SDong Aisheng * fall back to not support uhs by specify no 1.8v quirk 93191fa4252SDong Aisheng */ 93291fa4252SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 93391fa4252SDong Aisheng } 93491fa4252SDong Aisheng } else { 93591fa4252SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 93691fa4252SDong Aisheng } 93791fa4252SDong Aisheng 93815064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 9394800e87aSDong Aisheng ret = mmc_of_parse(host->mmc); 9404800e87aSDong Aisheng if (ret) 9414800e87aSDong Aisheng return ret; 9424800e87aSDong Aisheng 9434800e87aSDong Aisheng if (!IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc))) 9444800e87aSDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 9454800e87aSDong Aisheng 9464800e87aSDong Aisheng return 0; 947abfafc2dSShawn Guo } 948abfafc2dSShawn Guo #else 949abfafc2dSShawn Guo static inline int 950abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 95107bf2b54SSascha Hauer struct sdhci_host *host, 95291fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 953abfafc2dSShawn Guo { 954abfafc2dSShawn Guo return -ENODEV; 955abfafc2dSShawn Guo } 956abfafc2dSShawn Guo #endif 957abfafc2dSShawn Guo 95891fa4252SDong Aisheng static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 95991fa4252SDong Aisheng struct sdhci_host *host, 96091fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 96191fa4252SDong Aisheng { 96291fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 96391fa4252SDong Aisheng int err; 96491fa4252SDong Aisheng 96591fa4252SDong Aisheng if (!host->mmc->parent->platform_data) { 96691fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), "no board data!\n"); 96791fa4252SDong Aisheng return -EINVAL; 96891fa4252SDong Aisheng } 96991fa4252SDong Aisheng 97091fa4252SDong Aisheng imx_data->boarddata = *((struct esdhc_platform_data *) 97191fa4252SDong Aisheng host->mmc->parent->platform_data); 97291fa4252SDong Aisheng /* write_protect */ 97391fa4252SDong Aisheng if (boarddata->wp_type == ESDHC_WP_GPIO) { 97491fa4252SDong Aisheng err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 97591fa4252SDong Aisheng if (err) { 97691fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 97791fa4252SDong Aisheng "failed to request write-protect gpio!\n"); 97891fa4252SDong Aisheng return err; 97991fa4252SDong Aisheng } 98091fa4252SDong Aisheng host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 98191fa4252SDong Aisheng } 98291fa4252SDong Aisheng 98391fa4252SDong Aisheng /* card_detect */ 98491fa4252SDong Aisheng switch (boarddata->cd_type) { 98591fa4252SDong Aisheng case ESDHC_CD_GPIO: 98691fa4252SDong Aisheng err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 98791fa4252SDong Aisheng if (err) { 98891fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 98991fa4252SDong Aisheng "failed to request card-detect gpio!\n"); 99091fa4252SDong Aisheng return err; 99191fa4252SDong Aisheng } 99291fa4252SDong Aisheng /* fall through */ 99391fa4252SDong Aisheng 99491fa4252SDong Aisheng case ESDHC_CD_CONTROLLER: 99591fa4252SDong Aisheng /* we have a working card_detect back */ 99691fa4252SDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 99791fa4252SDong Aisheng break; 99891fa4252SDong Aisheng 99991fa4252SDong Aisheng case ESDHC_CD_PERMANENT: 100091fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 100191fa4252SDong Aisheng break; 100291fa4252SDong Aisheng 100391fa4252SDong Aisheng case ESDHC_CD_NONE: 100491fa4252SDong Aisheng break; 100591fa4252SDong Aisheng } 100691fa4252SDong Aisheng 100791fa4252SDong Aisheng switch (boarddata->max_bus_width) { 100891fa4252SDong Aisheng case 8: 100991fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 101091fa4252SDong Aisheng break; 101191fa4252SDong Aisheng case 4: 101291fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_4_BIT_DATA; 101391fa4252SDong Aisheng break; 101491fa4252SDong Aisheng case 1: 101591fa4252SDong Aisheng default: 101691fa4252SDong Aisheng host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 101791fa4252SDong Aisheng break; 101891fa4252SDong Aisheng } 101991fa4252SDong Aisheng 102091fa4252SDong Aisheng return 0; 102191fa4252SDong Aisheng } 102291fa4252SDong Aisheng 1023c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 102495f25efeSWolfram Sang { 1025abfafc2dSShawn Guo const struct of_device_id *of_id = 1026abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 102785d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 102885d6509dSShawn Guo struct sdhci_host *host; 10290c6d49ceSWolfram Sang int err; 1030e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 103195f25efeSWolfram Sang 10320e748234SChristian Daudt host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); 103385d6509dSShawn Guo if (IS_ERR(host)) 103485d6509dSShawn Guo return PTR_ERR(host); 103585d6509dSShawn Guo 103685d6509dSShawn Guo pltfm_host = sdhci_priv(host); 103785d6509dSShawn Guo 1038e3af31c6SShawn Guo imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 1039abfafc2dSShawn Guo if (!imx_data) { 1040abfafc2dSShawn Guo err = -ENOMEM; 1041e3af31c6SShawn Guo goto free_sdhci; 1042abfafc2dSShawn Guo } 104357ed3314SShawn Guo 1044f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 10453770ee8fSShawn Guo pdev->id_entry->driver_data; 104685d6509dSShawn Guo pltfm_host->priv = imx_data; 104785d6509dSShawn Guo 104852dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 104952dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 105052dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 1051e3af31c6SShawn Guo goto free_sdhci; 105295f25efeSWolfram Sang } 105352dac615SSascha Hauer 105452dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 105552dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 105652dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 1057e3af31c6SShawn Guo goto free_sdhci; 105852dac615SSascha Hauer } 105952dac615SSascha Hauer 106052dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 106152dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 106252dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 1063e3af31c6SShawn Guo goto free_sdhci; 106452dac615SSascha Hauer } 106552dac615SSascha Hauer 106652dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 1067a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 106852dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 106952dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 107052dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 107195f25efeSWolfram Sang 1072ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1073e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1074e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 1075e3af31c6SShawn Guo goto disable_clk; 1076e62d8b8fSDong Aisheng } 1077e62d8b8fSDong Aisheng 1078ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 1079ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 1080cd529af7SDirk Behme if (IS_ERR(imx_data->pins_default)) 1081cd529af7SDirk Behme dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 1082ad93220dSDong Aisheng 108337865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 108437865fe9SEric Bénard 1085f47c4bbfSShawn Guo if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 10860c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 108797e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 108897e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 10890c6d49ceSWolfram Sang 1090f750ba9bSShawn Guo /* 1091f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 1092f750ba9bSShawn Guo * to something insane. Change it back here. 1093f750ba9bSShawn Guo */ 109469ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 109560bf6396SShawn Guo writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 109669ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1097e2997c94SDong Aisheng host->mmc->caps |= MMC_CAP_1_8V_DDR; 109818094430SDong Aisheng 10994245afffSDong Aisheng if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 11004245afffSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 11014245afffSDong Aisheng 110218094430SDong Aisheng /* 110318094430SDong Aisheng * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 110418094430SDong Aisheng * TO1.1, it's harmless for MX6SL 110518094430SDong Aisheng */ 110618094430SDong Aisheng writel(readl(host->ioaddr + 0x6c) | BIT(7), 110718094430SDong Aisheng host->ioaddr + 0x6c); 110869ed60e0SDong Aisheng } 1109f750ba9bSShawn Guo 11106e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 11116e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 11126e9fd28eSDong Aisheng esdhc_executing_tuning; 11138b2bb0adSDong Aisheng 11148b2bb0adSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 11158b2bb0adSDong Aisheng writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | 11168b2bb0adSDong Aisheng ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, 11178b2bb0adSDong Aisheng host->ioaddr + ESDHC_TUNING_CTRL); 11188b2bb0adSDong Aisheng 111918094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 112018094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 112118094430SDong Aisheng 112291fa4252SDong Aisheng if (of_id) 112391fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 112491fa4252SDong Aisheng else 112591fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 112691fa4252SDong Aisheng if (err) 1127e3af31c6SShawn Guo goto disable_clk; 1128ad93220dSDong Aisheng 112985d6509dSShawn Guo err = sdhci_add_host(host); 113085d6509dSShawn Guo if (err) 1131e3af31c6SShawn Guo goto disable_clk; 113285d6509dSShawn Guo 113389d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 113489d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 113589d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 113689d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 113777903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 113889d7e5c1SDong Aisheng 11397e29c306SWolfram Sang return 0; 11407e29c306SWolfram Sang 1141e3af31c6SShawn Guo disable_clk: 114252dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 114352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 114452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 1145e3af31c6SShawn Guo free_sdhci: 114685d6509dSShawn Guo sdhci_pltfm_free(pdev); 114785d6509dSShawn Guo return err; 114895f25efeSWolfram Sang } 114995f25efeSWolfram Sang 11506e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 115195f25efeSWolfram Sang { 115285d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 115395f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1154e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 115585d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 115685d6509dSShawn Guo 11570b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 11580b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 11590b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 11600b414368SUlf Hansson 116185d6509dSShawn Guo sdhci_remove_host(host, dead); 11620c6d49ceSWolfram Sang 116352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 116452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 116552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 116652dac615SSascha Hauer 116785d6509dSShawn Guo sdhci_pltfm_free(pdev); 116885d6509dSShawn Guo 116985d6509dSShawn Guo return 0; 117095f25efeSWolfram Sang } 117195f25efeSWolfram Sang 1172162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 117389d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 117489d7e5c1SDong Aisheng { 117589d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 117689d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 117789d7e5c1SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 117889d7e5c1SDong Aisheng int ret; 117989d7e5c1SDong Aisheng 118089d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 118189d7e5c1SDong Aisheng 1182be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 118389d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 118489d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 1185be138554SRussell King } 118689d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 118789d7e5c1SDong Aisheng 118889d7e5c1SDong Aisheng return ret; 118989d7e5c1SDong Aisheng } 119089d7e5c1SDong Aisheng 119189d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 119289d7e5c1SDong Aisheng { 119389d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 119489d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 119589d7e5c1SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 119689d7e5c1SDong Aisheng 1197be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 119889d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_per); 119989d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ipg); 1200be138554SRussell King } 120189d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ahb); 120289d7e5c1SDong Aisheng 120389d7e5c1SDong Aisheng return sdhci_runtime_resume_host(host); 120489d7e5c1SDong Aisheng } 120589d7e5c1SDong Aisheng #endif 120689d7e5c1SDong Aisheng 120789d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 120889d7e5c1SDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) 120989d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 121089d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 121189d7e5c1SDong Aisheng }; 121289d7e5c1SDong Aisheng 121385d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 121485d6509dSShawn Guo .driver = { 121585d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1216abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 121789d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 121885d6509dSShawn Guo }, 121957ed3314SShawn Guo .id_table = imx_esdhc_devtype, 122085d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 12210433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 122295f25efeSWolfram Sang }; 122385d6509dSShawn Guo 1224d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 122585d6509dSShawn Guo 122685d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1227035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 122885d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1229