1a6e7e407SFabio Estevam // SPDX-License-Identifier: GPL-2.0 295f25efeSWolfram Sang /* 395f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 495f25efeSWolfram Sang * 595f25efeSWolfram Sang * derived from the OF-version. 695f25efeSWolfram Sang * 795f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 8035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 995f25efeSWolfram Sang */ 1095f25efeSWolfram Sang 1195f25efeSWolfram Sang #include <linux/io.h> 1295f25efeSWolfram Sang #include <linux/delay.h> 1395f25efeSWolfram Sang #include <linux/err.h> 1495f25efeSWolfram Sang #include <linux/clk.h> 1566506f76SShawn Guo #include <linux/module.h> 16e149860dSRichard Zhu #include <linux/slab.h> 171c4989b0SBOUGH CHEN #include <linux/pm_qos.h> 1895f25efeSWolfram Sang #include <linux/mmc/host.h> 1958ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2058ac8177SRichard Zhu #include <linux/mmc/sdio.h> 21fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 22abfafc2dSShawn Guo #include <linux/of.h> 23abfafc2dSShawn Guo #include <linux/of_device.h> 24e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2582906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 2689d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 2795f25efeSWolfram Sang #include "sdhci-pltfm.h" 2895f25efeSWolfram Sang #include "sdhci-esdhc.h" 29bb6e3581SBOUGH CHEN #include "cqhci.h" 3095f25efeSWolfram Sang 31a215186dSHaibo Chen #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 3260bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 33fd44954eSHaibo Chen #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 3458ac8177SRichard Zhu /* VENDOR SPEC register */ 3560bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 370322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 38fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 3960bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 40cc17e129SDong Aisheng #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 413fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 423fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 433fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 443fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 453fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 463fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 4760bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 48de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 492a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 500322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 510322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 520b330e38SDong Aisheng #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 530322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 5428b07674SHaibo Chen #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 55029e2476SBOUGH CHEN #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27) 562a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 572a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 58d131a71cSDong Aisheng /* Tuning bits */ 59d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 6058ac8177SRichard Zhu 61602519b2SDong Aisheng /* dll control register */ 62602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 63602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 64602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 65602519b2SDong Aisheng 660322191eSDong Aisheng /* tune control register */ 670322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 680322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 690322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 700322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 710322191eSDong Aisheng 7228b07674SHaibo Chen /* strobe dll register */ 7328b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL 0x70 7428b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 7528b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 7628b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 772eaf5a53SBOUGH CHEN #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) 7828b07674SHaibo Chen 7928b07674SHaibo Chen #define ESDHC_STROBE_DLL_STATUS 0x74 8028b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 8128b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 8228b07674SHaibo Chen 83bcdb5301SBOUGH CHEN #define ESDHC_VEND_SPEC2 0xc8 84bcdb5301SBOUGH CHEN #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8) 85bcdb5301SBOUGH CHEN 866e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 876e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 886e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 89d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 90d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_MASK 0xff 91260ecb3cSHaibo Chen #define ESDHC_TUNING_STEP_MASK 0x00070000 92d407e30bSHaibo Chen #define ESDHC_TUNING_STEP_SHIFT 16 936e9fd28eSDong Aisheng 94ad93220dSDong Aisheng /* pinctrl state */ 95ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 96ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 97ad93220dSDong Aisheng 9858ac8177SRichard Zhu /* 99af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 100af51079eSSascha Hauer */ 101af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 102af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 103af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 104af51079eSSascha Hauer 105af51079eSSascha Hauer /* 106d04f8d5bSBenoît Thébaudeau * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 10797e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 10897e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 10997e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 11097e4ba6aSRichard Zhu */ 11160bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 11297e4ba6aSRichard Zhu 113bb6e3581SBOUGH CHEN /* the address offset of CQHCI */ 114bb6e3581SBOUGH CHEN #define ESDHC_CQHCI_ADDR_OFFSET 0x100 115bb6e3581SBOUGH CHEN 11697e4ba6aSRichard Zhu /* 11758ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 11858ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 11958ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 12058ac8177SRichard Zhu * be generated. 12158ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 12258ac8177SRichard Zhu * operations automatically as required at the end of the 12358ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 12458ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 125d04f8d5bSBenoît Thébaudeau * exception. Bit1 of Vendor Spec register is used to fix it. 12658ac8177SRichard Zhu */ 12731fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 12831fbb301SShawn Guo /* 1299d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1309d61c009SShawn Guo * integrated on the i.MX6 series. 1319d61c009SShawn Guo */ 1329d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1336e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1346e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1356e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1366e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1376e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1386e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 13918094430SDong Aisheng /* 140d04f8d5bSBenoît Thébaudeau * The IP has erratum ERR004536 14118094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 14218094430SDong Aisheng * when reading data from the card 143667123f6SBenoît Thébaudeau * This flag is also set for i.MX25 and i.MX35 in order to get 144667123f6SBenoît Thébaudeau * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 14518094430SDong Aisheng */ 14618094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 1474245afffSDong Aisheng /* The IP supports HS200 mode */ 1484245afffSDong Aisheng #define ESDHC_FLAG_HS200 BIT(8) 14928b07674SHaibo Chen /* The IP supports HS400 mode */ 15028b07674SHaibo Chen #define ESDHC_FLAG_HS400 BIT(9) 151af6a50d4SBOUGH CHEN /* 152af6a50d4SBOUGH CHEN * The IP has errata ERR010450 153af6a50d4SBOUGH CHEN * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't 154af6a50d4SBOUGH CHEN * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. 155af6a50d4SBOUGH CHEN */ 156af6a50d4SBOUGH CHEN #define ESDHC_FLAG_ERR010450 BIT(10) 157029e2476SBOUGH CHEN /* The IP supports HS400ES mode */ 158029e2476SBOUGH CHEN #define ESDHC_FLAG_HS400_ES BIT(11) 159bb6e3581SBOUGH CHEN /* The IP has Host Controller Interface for Command Queuing */ 160bb6e3581SBOUGH CHEN #define ESDHC_FLAG_CQHCI BIT(12) 1611c4989b0SBOUGH CHEN /* need request pmqos during low power */ 1621c4989b0SBOUGH CHEN #define ESDHC_FLAG_PMQOS BIT(13) 163e149860dSRichard Zhu 164f47c4bbfSShawn Guo struct esdhc_soc_data { 165f47c4bbfSShawn Guo u32 flags; 166f47c4bbfSShawn Guo }; 167f47c4bbfSShawn Guo 1684f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx25_data = { 169667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 170f47c4bbfSShawn Guo }; 171f47c4bbfSShawn Guo 1724f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx35_data = { 173667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 174f47c4bbfSShawn Guo }; 175f47c4bbfSShawn Guo 1764f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx51_data = { 177f47c4bbfSShawn Guo .flags = 0, 178f47c4bbfSShawn Guo }; 179f47c4bbfSShawn Guo 1804f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx53_data = { 181f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 182f47c4bbfSShawn Guo }; 183f47c4bbfSShawn Guo 1844f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6q_data = { 1856e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1866e9fd28eSDong Aisheng }; 1876e9fd28eSDong Aisheng 1884f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sl_data = { 1896e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1904245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 1914245afffSDong Aisheng | ESDHC_FLAG_HS200, 19257ed3314SShawn Guo }; 19357ed3314SShawn Guo 1944f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sx_data = { 195913d4951SDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1964245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 197913d4951SDong Aisheng }; 198913d4951SDong Aisheng 199af6a50d4SBOUGH CHEN static const struct esdhc_soc_data usdhc_imx6ull_data = { 200af6a50d4SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 201af6a50d4SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 202af6a50d4SBOUGH CHEN | ESDHC_FLAG_ERR010450, 203af6a50d4SBOUGH CHEN }; 204af6a50d4SBOUGH CHEN 2054f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx7d_data = { 20628b07674SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 20728b07674SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 20828b07674SHaibo Chen | ESDHC_FLAG_HS400, 20928b07674SHaibo Chen }; 21028b07674SHaibo Chen 2111c4989b0SBOUGH CHEN static struct esdhc_soc_data usdhc_imx7ulp_data = { 2121c4989b0SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 2131c4989b0SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 2142eaf5a53SBOUGH CHEN | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400, 2151c4989b0SBOUGH CHEN }; 2161c4989b0SBOUGH CHEN 217029e2476SBOUGH CHEN static struct esdhc_soc_data usdhc_imx8qxp_data = { 218029e2476SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 219029e2476SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 220bb6e3581SBOUGH CHEN | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 221bb6e3581SBOUGH CHEN | ESDHC_FLAG_CQHCI, 222029e2476SBOUGH CHEN }; 223029e2476SBOUGH CHEN 224e149860dSRichard Zhu struct pltfm_imx_data { 225e149860dSRichard Zhu u32 scratchpad; 226e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 227ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 228ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 229f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 230842afc02SShawn Guo struct esdhc_platform_data boarddata; 23152dac615SSascha Hauer struct clk *clk_ipg; 23252dac615SSascha Hauer struct clk *clk_ahb; 23352dac615SSascha Hauer struct clk *clk_per; 2343602785bSMichael Trimarchi unsigned int actual_clock; 235361b8482SLucas Stach enum { 236361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending */ 237361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 238361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 239361b8482SLucas Stach } multiblock_status; 240de5bdbffSDong Aisheng u32 is_ddr; 2411c4989b0SBOUGH CHEN struct pm_qos_request pm_qos_req; 242e149860dSRichard Zhu }; 243e149860dSRichard Zhu 244f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 24557ed3314SShawn Guo { 24657ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 247f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 24857ed3314SShawn Guo }, { 24957ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 250f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 25157ed3314SShawn Guo }, { 25257ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 253f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 25457ed3314SShawn Guo }, { 25557ed3314SShawn Guo /* sentinel */ 25657ed3314SShawn Guo } 25757ed3314SShawn Guo }; 25857ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 25957ed3314SShawn Guo 260abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 261f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 262f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 263f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 264f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 265913d4951SDong Aisheng { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 2666e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 267f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 268af6a50d4SBOUGH CHEN { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, 26928b07674SHaibo Chen { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 2701c4989b0SBOUGH CHEN { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, }, 271029e2476SBOUGH CHEN { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, }, 272abfafc2dSShawn Guo { /* sentinel */ } 273abfafc2dSShawn Guo }; 274abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 275abfafc2dSShawn Guo 27657ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 27757ed3314SShawn Guo { 278f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 27957ed3314SShawn Guo } 28057ed3314SShawn Guo 28157ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 28257ed3314SShawn Guo { 283f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 28457ed3314SShawn Guo } 28557ed3314SShawn Guo 28695a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 28795a2482aSShawn Guo { 288f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 28995a2482aSShawn Guo } 29095a2482aSShawn Guo 2919d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2929d61c009SShawn Guo { 293f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2949d61c009SShawn Guo } 2959d61c009SShawn Guo 29695f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 29795f25efeSWolfram Sang { 29895f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 29995f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 30095f25efeSWolfram Sang 30195f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 30295f25efeSWolfram Sang } 30395f25efeSWolfram Sang 3047e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 3057e29c306SWolfram Sang { 306361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 307070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 308913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 309913413c3SShawn Guo 3100322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 3110322191eSDong Aisheng u32 fsl_prss = val; 3120322191eSDong Aisheng /* save the least 20 bits */ 3130322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 3140322191eSDong Aisheng /* move dat[0-3] bits */ 3150322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 3160322191eSDong Aisheng /* move cmd line bit */ 3170322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 3180322191eSDong Aisheng } 3190322191eSDong Aisheng 32097e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 3216b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 3226b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3236b4fb671SDong Aisheng val &= 0xffff0000; 3246b4fb671SDong Aisheng 32597e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 32697e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 32797e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 32897e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 329d04f8d5bSBenoît Thébaudeau * quirk on MX25/35 platforms. 33097e4ba6aSRichard Zhu */ 33197e4ba6aSRichard Zhu 33297e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 33397e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 33497e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 33597e4ba6aSRichard Zhu } 33697e4ba6aSRichard Zhu } 33797e4ba6aSRichard Zhu 3386e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 3396e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 3406e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3416e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 3426e9fd28eSDong Aisheng else 3436e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 3440322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 345888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 346da0295ffSDong Aisheng | SDHCI_USE_SDR50_TUNING 347da0295ffSDong Aisheng | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); 34828b07674SHaibo Chen 34928b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 35028b07674SHaibo Chen val |= SDHCI_SUPPORT_HS400; 35192748beaSStefan Agner 35292748beaSStefan Agner /* 35392748beaSStefan Agner * Do not advertise faster UHS modes if there are no 35492748beaSStefan Agner * pinctrl states for 100MHz/200MHz. 35592748beaSStefan Agner */ 35692748beaSStefan Agner if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || 35792748beaSStefan Agner IS_ERR_OR_NULL(imx_data->pins_200mhz)) 35892748beaSStefan Agner val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50 35992748beaSStefan Agner | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 3606e9fd28eSDong Aisheng } 3616e9fd28eSDong Aisheng } 3620322191eSDong Aisheng 3639d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 3640322191eSDong Aisheng val = 0; 3650322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 3660322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 3670322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 3680322191eSDong Aisheng } 3690322191eSDong Aisheng 37097e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 37160bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 37260bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 37397e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 37497e4ba6aSRichard Zhu } 375361b8482SLucas Stach 376361b8482SLucas Stach /* 377361b8482SLucas Stach * mask off the interrupt we get in response to the manually 378361b8482SLucas Stach * sent CMD12 379361b8482SLucas Stach */ 380361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 381361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 382361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 383361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 384361b8482SLucas Stach SDHCI_INT_STATUS); 385361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 386361b8482SLucas Stach } 38797e4ba6aSRichard Zhu } 38897e4ba6aSRichard Zhu 3897e29c306SWolfram Sang return val; 3907e29c306SWolfram Sang } 3917e29c306SWolfram Sang 3927e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 3937e29c306SWolfram Sang { 394e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 395070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 3960d58864bSTony Lin u32 data; 397e149860dSRichard Zhu 39877da3da0SAaron Brice if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 39977da3da0SAaron Brice reg == SDHCI_INT_STATUS)) { 400b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 4010d58864bSTony Lin /* 4020d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 403d04f8d5bSBenoît Thébaudeau * card interrupt. This is an eSDHC controller problem 4040d58864bSTony Lin * so we need to apply the following workaround: clear 4050d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 4060d58864bSTony Lin * interrupt. In case a card interrupt was lost, 4070d58864bSTony Lin * re-sample it by the following steps. 4080d58864bSTony Lin */ 4090d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 41060bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 4110d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 41260bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 4130d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 4140d58864bSTony Lin } 415915be485SDong Aisheng 416915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 417915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 418915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 419915be485SDong Aisheng } 4200d58864bSTony Lin } 4210d58864bSTony Lin 422f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 42358ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 42458ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 42558ac8177SRichard Zhu u32 v; 42660bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 42760bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 42860bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 429361b8482SLucas Stach 430361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 431361b8482SLucas Stach { 432361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 433361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 434361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 435361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 436361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 437361b8482SLucas Stach } 43858ac8177SRichard Zhu } 43958ac8177SRichard Zhu 4407e29c306SWolfram Sang writel(val, host->ioaddr + reg); 4417e29c306SWolfram Sang } 4427e29c306SWolfram Sang 44395f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 44495f25efeSWolfram Sang { 445ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 446070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 4470322191eSDong Aisheng u16 ret = 0; 4480322191eSDong Aisheng u32 val; 449ef4d0888SShawn Guo 45095a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 451ef4d0888SShawn Guo reg ^= 2; 4529d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 45395a2482aSShawn Guo /* 454ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 455ef4d0888SShawn Guo * Correct it here. 45695a2482aSShawn Guo */ 457ef4d0888SShawn Guo return SDHCI_SPEC_300; 458ef4d0888SShawn Guo } 45995a2482aSShawn Guo } 46095f25efeSWolfram Sang 4610322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 4620322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4630322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 4640322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 4650322191eSDong Aisheng 4669d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 4676e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 4680322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4696e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 4706e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 471869f8a69SAdrian Hunter val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 4726e9fd28eSDong Aisheng } 4736e9fd28eSDong Aisheng 4740322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 4750322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 4760322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 4770322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 4780322191eSDong Aisheng 4790322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 4800322191eSDong Aisheng 4810322191eSDong Aisheng return ret; 4820322191eSDong Aisheng } 4830322191eSDong Aisheng 4847dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 4857dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 4867dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4877dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 4887dd109efSDong Aisheng /* Swap AC23 bit */ 4897dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 4907dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 4917dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 4927dd109efSDong Aisheng } 4937dd109efSDong Aisheng } else { 4947dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 4957dd109efSDong Aisheng } 4967dd109efSDong Aisheng 4977dd109efSDong Aisheng return ret; 4987dd109efSDong Aisheng } 4997dd109efSDong Aisheng 50095f25efeSWolfram Sang return readw(host->ioaddr + reg); 50195f25efeSWolfram Sang } 50295f25efeSWolfram Sang 50395f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 50495f25efeSWolfram Sang { 50595f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 506070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 5070322191eSDong Aisheng u32 new_val = 0; 50895f25efeSWolfram Sang 50995f25efeSWolfram Sang switch (reg) { 5100322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 5110322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5120322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 5130322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 5140322191eSDong Aisheng else 5150322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 5160322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 5170322191eSDong Aisheng return; 5180322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 5190322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5200322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 5210322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 5220322191eSDong Aisheng else 5230322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 5240322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 5256e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 5260322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 527da0295ffSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 5280322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 529da0295ffSDong Aisheng new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 530da0295ffSDong Aisheng } else { 5310322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 532da0295ffSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 533da0295ffSDong Aisheng } 5340322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 5356e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 536869f8a69SAdrian Hunter u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 5376e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5388b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 5398b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 5406e9fd28eSDong Aisheng } else { 5418b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 5426e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 5430b330e38SDong Aisheng m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 5446e9fd28eSDong Aisheng } 5456e9fd28eSDong Aisheng 5468b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 5478b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 5488b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 5490b330e38SDong Aisheng m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 5508b2bb0adSDong Aisheng } else { 5518b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 5528b2bb0adSDong Aisheng } 5536e9fd28eSDong Aisheng 554869f8a69SAdrian Hunter writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 5556e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5566e9fd28eSDong Aisheng } 5570322191eSDong Aisheng return; 55895f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 559f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 56058ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 56158ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 56258ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 56358ac8177SRichard Zhu u32 v; 56460bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 56560bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 56660bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 56758ac8177SRichard Zhu } 56869f54698SShawn Guo 5699d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 5703fbd4322SAndrew Gabbasov u32 wml; 57169f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5722a15f981SShawn Guo /* Swap AC23 bit */ 5732a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 5742a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 5752a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 5762a15f981SShawn Guo } 5772a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 57869f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5793fbd4322SAndrew Gabbasov 5803fbd4322SAndrew Gabbasov /* Set watermark levels for PIO access to maximum value 5813fbd4322SAndrew Gabbasov * (128 words) to accommodate full 512 bytes buffer. 5823fbd4322SAndrew Gabbasov * For DMA access restore the levels to default value. 5833fbd4322SAndrew Gabbasov */ 5843fbd4322SAndrew Gabbasov m = readl(host->ioaddr + ESDHC_WTMK_LVL); 5853fbd4322SAndrew Gabbasov if (val & SDHCI_TRNS_DMA) 5863fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 5873fbd4322SAndrew Gabbasov else 5883fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 5893fbd4322SAndrew Gabbasov m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 5903fbd4322SAndrew Gabbasov ESDHC_WTMK_LVL_WR_WML_MASK); 5913fbd4322SAndrew Gabbasov m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 5923fbd4322SAndrew Gabbasov (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 5933fbd4322SAndrew Gabbasov writel(m, host->ioaddr + ESDHC_WTMK_LVL); 59469f54698SShawn Guo } else { 59569f54698SShawn Guo /* 59669f54698SShawn Guo * Postpone this write, we must do it together with a 59769f54698SShawn Guo * command write that is down below. 59869f54698SShawn Guo */ 599e149860dSRichard Zhu imx_data->scratchpad = val; 60069f54698SShawn Guo } 60195f25efeSWolfram Sang return; 60295f25efeSWolfram Sang case SDHCI_COMMAND: 603361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 60458ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 60595a2482aSShawn Guo 606361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 607f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 608361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 609361b8482SLucas Stach 6109d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 61195a2482aSShawn Guo writel(val << 16, 61295a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 61369f54698SShawn Guo else 614e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 61595f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 61695f25efeSWolfram Sang return; 61795f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 61895f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 61995f25efeSWolfram Sang break; 62095f25efeSWolfram Sang } 62195f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 62295f25efeSWolfram Sang } 62395f25efeSWolfram Sang 62477da3da0SAaron Brice static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 62577da3da0SAaron Brice { 62677da3da0SAaron Brice u8 ret; 62777da3da0SAaron Brice u32 val; 62877da3da0SAaron Brice 62977da3da0SAaron Brice switch (reg) { 63077da3da0SAaron Brice case SDHCI_HOST_CONTROL: 63177da3da0SAaron Brice val = readl(host->ioaddr + reg); 63277da3da0SAaron Brice 63377da3da0SAaron Brice ret = val & SDHCI_CTRL_LED; 63477da3da0SAaron Brice ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 63577da3da0SAaron Brice ret |= (val & ESDHC_CTRL_4BITBUS); 63677da3da0SAaron Brice ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 63777da3da0SAaron Brice return ret; 63877da3da0SAaron Brice } 63977da3da0SAaron Brice 64077da3da0SAaron Brice return readb(host->ioaddr + reg); 64177da3da0SAaron Brice } 64277da3da0SAaron Brice 64395f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 64495f25efeSWolfram Sang { 6459a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 646070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 64781a0a8bcSBenoît Thébaudeau u32 new_val = 0; 648af51079eSSascha Hauer u32 mask; 64995f25efeSWolfram Sang 65095f25efeSWolfram Sang switch (reg) { 65195f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 65295f25efeSWolfram Sang /* 65395f25efeSWolfram Sang * FSL put some DMA bits here 65495f25efeSWolfram Sang * If your board has a regulator, code should be here 65595f25efeSWolfram Sang */ 65695f25efeSWolfram Sang return; 65795f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 6586b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 659af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 6607122bbb0SMasanari Iida /* ensure the endianness */ 66195f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 6629a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 6639a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 66495f25efeSWolfram Sang /* DMA mode bits are shifted */ 66595f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 6669a0985b7SWilson Callan } 66795f25efeSWolfram Sang 668af51079eSSascha Hauer /* 669af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 670af51079eSSascha Hauer * esdhc_pltfm_bus_width. 671f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 672d04f8d5bSBenoît Thébaudeau * SDIO interrupt erratum workaround. 673af51079eSSascha Hauer */ 674f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 675af51079eSSascha Hauer 676af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 67795f25efeSWolfram Sang return; 67881a0a8bcSBenoît Thébaudeau case SDHCI_SOFTWARE_RESET: 67981a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_DATA) 68081a0a8bcSBenoît Thébaudeau new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 68181a0a8bcSBenoît Thébaudeau break; 68295f25efeSWolfram Sang } 68395f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 684913413c3SShawn Guo 68581a0a8bcSBenoît Thébaudeau if (reg == SDHCI_SOFTWARE_RESET) { 68681a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_ALL) { 687913413c3SShawn Guo /* 68881a0a8bcSBenoît Thébaudeau * The esdhc has a design violation to SDHC spec which 68981a0a8bcSBenoît Thébaudeau * tells that software reset should not affect card 69081a0a8bcSBenoît Thébaudeau * detection circuit. But esdhc clears its SYSCTL 69181a0a8bcSBenoît Thébaudeau * register bits [0..2] during the software reset. This 69281a0a8bcSBenoît Thébaudeau * will stop those clocks that card detection circuit 69381a0a8bcSBenoît Thébaudeau * relies on. To work around it, we turn the clocks on 69481a0a8bcSBenoît Thébaudeau * back to keep card detection circuit functional. 695913413c3SShawn Guo */ 696913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 69758c8c4fbSShawn Guo /* 69858c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 69958c8c4fbSShawn Guo * Do it manually here. 70058c8c4fbSShawn Guo */ 701de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 70281a0a8bcSBenoît Thébaudeau /* 70381a0a8bcSBenoît Thébaudeau * the tuning bits should be kept during reset 70481a0a8bcSBenoît Thébaudeau */ 705d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 706d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 707d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 708de5bdbffSDong Aisheng imx_data->is_ddr = 0; 709de5bdbffSDong Aisheng } 71081a0a8bcSBenoît Thébaudeau } else if (val & SDHCI_RESET_DATA) { 71181a0a8bcSBenoît Thébaudeau /* 71281a0a8bcSBenoît Thébaudeau * The eSDHC DAT line software reset clears at least the 71381a0a8bcSBenoît Thébaudeau * data transfer width on i.MX25, so make sure that the 71481a0a8bcSBenoît Thébaudeau * Host Control register is unaffected. 71581a0a8bcSBenoît Thébaudeau */ 71681a0a8bcSBenoît Thébaudeau esdhc_clrset_le(host, 0xff, new_val, 71781a0a8bcSBenoît Thébaudeau SDHCI_HOST_CONTROL); 71881a0a8bcSBenoît Thébaudeau } 71958c8c4fbSShawn Guo } 72095f25efeSWolfram Sang } 72195f25efeSWolfram Sang 7220ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 7230ddf03c9SLucas Stach { 7240ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 7250ddf03c9SLucas Stach 726a974862fSDong Aisheng return pltfm_host->clock; 7270ddf03c9SLucas Stach } 7280ddf03c9SLucas Stach 72995f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 73095f25efeSWolfram Sang { 73195f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 73295f25efeSWolfram Sang 733a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 73495f25efeSWolfram Sang } 73595f25efeSWolfram Sang 7368ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 7378ba9580aSLucas Stach unsigned int clock) 7388ba9580aSLucas Stach { 7398ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 740070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 741a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 7425143c953SBenoît Thébaudeau int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 7435143c953SBenoît Thébaudeau int pre_div = 1; 744d31fc00aSDong Aisheng int div = 1; 745fed2f6e2SDong Aisheng u32 temp, val; 7468ba9580aSLucas Stach 7479d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 748fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 749fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 750fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 751fed2f6e2SDong Aisheng } 75273e736f8SStefan Agner 75373e736f8SStefan Agner if (clock == 0) { 75473e736f8SStefan Agner host->mmc->actual_clock = 0; 755373073efSRussell King return; 756fed2f6e2SDong Aisheng } 757d31fc00aSDong Aisheng 758499ed50fSBenoît Thébaudeau /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 759499ed50fSBenoît Thébaudeau if (is_imx53_esdhc(imx_data)) { 760499ed50fSBenoît Thébaudeau /* 761499ed50fSBenoît Thébaudeau * According to the i.MX53 reference manual, if DLLCTRL[10] can 762499ed50fSBenoît Thébaudeau * be set, then the controller is eSDHCv3, else it is eSDHCv2. 763499ed50fSBenoît Thébaudeau */ 764499ed50fSBenoît Thébaudeau val = readl(host->ioaddr + ESDHC_DLL_CTRL); 765499ed50fSBenoît Thébaudeau writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 766499ed50fSBenoît Thébaudeau temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 767499ed50fSBenoît Thébaudeau writel(val, host->ioaddr + ESDHC_DLL_CTRL); 768499ed50fSBenoît Thébaudeau if (temp & BIT(10)) 769499ed50fSBenoît Thébaudeau pre_div = 2; 770499ed50fSBenoît Thébaudeau } 771499ed50fSBenoît Thébaudeau 772d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 773d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 774d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 775d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 776d31fc00aSDong Aisheng 777af6a50d4SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { 778af6a50d4SBOUGH CHEN unsigned int max_clock; 779af6a50d4SBOUGH CHEN 780af6a50d4SBOUGH CHEN max_clock = imx_data->is_ddr ? 45000000 : 150000000; 781af6a50d4SBOUGH CHEN 782af6a50d4SBOUGH CHEN clock = min(clock, max_clock); 783af6a50d4SBOUGH CHEN } 784af6a50d4SBOUGH CHEN 7855143c953SBenoît Thébaudeau while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 7865143c953SBenoît Thébaudeau pre_div < 256) 787d31fc00aSDong Aisheng pre_div *= 2; 788d31fc00aSDong Aisheng 7895143c953SBenoît Thébaudeau while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 790d31fc00aSDong Aisheng div++; 791d31fc00aSDong Aisheng 7925143c953SBenoît Thébaudeau host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 793d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 794e76b8559SDong Aisheng clock, host->mmc->actual_clock); 795d31fc00aSDong Aisheng 796d31fc00aSDong Aisheng pre_div >>= 1; 797d31fc00aSDong Aisheng div--; 798d31fc00aSDong Aisheng 799d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 800d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 801d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 802d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 803d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 804fed2f6e2SDong Aisheng 8059d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 806fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 807fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 808fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 809fed2f6e2SDong Aisheng } 810fed2f6e2SDong Aisheng 811d31fc00aSDong Aisheng mdelay(1); 8128ba9580aSLucas Stach } 8138ba9580aSLucas Stach 814913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 815913413c3SShawn Guo { 816842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 817070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 818842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 819913413c3SShawn Guo 820913413c3SShawn Guo switch (boarddata->wp_type) { 821913413c3SShawn Guo case ESDHC_WP_GPIO: 822fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 823913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 824913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 825913413c3SShawn Guo SDHCI_WRITE_PROTECT); 826913413c3SShawn Guo case ESDHC_WP_NONE: 827913413c3SShawn Guo break; 828913413c3SShawn Guo } 829913413c3SShawn Guo 830913413c3SShawn Guo return -ENOSYS; 831913413c3SShawn Guo } 832913413c3SShawn Guo 8332317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 834af51079eSSascha Hauer { 835af51079eSSascha Hauer u32 ctrl; 836af51079eSSascha Hauer 837af51079eSSascha Hauer switch (width) { 838af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 839af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 840af51079eSSascha Hauer break; 841af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 842af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 843af51079eSSascha Hauer break; 844af51079eSSascha Hauer default: 845af51079eSSascha Hauer ctrl = 0; 846af51079eSSascha Hauer break; 847af51079eSSascha Hauer } 848af51079eSSascha Hauer 849af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 850af51079eSSascha Hauer SDHCI_HOST_CONTROL); 851af51079eSSascha Hauer } 852af51079eSSascha Hauer 853de3e1dd0SBOUGH CHEN static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 854de3e1dd0SBOUGH CHEN { 855de3e1dd0SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 856de3e1dd0SBOUGH CHEN 857de3e1dd0SBOUGH CHEN /* 858de3e1dd0SBOUGH CHEN * i.MX uSDHC internally already uses a fixed optimized timing for 859de3e1dd0SBOUGH CHEN * DDR50, normally does not require tuning for DDR50 mode. 860de3e1dd0SBOUGH CHEN */ 861de3e1dd0SBOUGH CHEN if (host->timing == MMC_TIMING_UHS_DDR50) 862de3e1dd0SBOUGH CHEN return 0; 863de3e1dd0SBOUGH CHEN 864de3e1dd0SBOUGH CHEN return sdhci_execute_tuning(mmc, opcode); 865de3e1dd0SBOUGH CHEN } 866de3e1dd0SBOUGH CHEN 8670322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 8680322191eSDong Aisheng { 8690322191eSDong Aisheng u32 reg; 8700322191eSDong Aisheng 8710322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 8720322191eSDong Aisheng mdelay(1); 8730322191eSDong Aisheng 8740322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 8750322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 8760322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 8770322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 8780322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 8790322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 880d04f8d5bSBenoît Thébaudeau "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 8810322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 8820322191eSDong Aisheng } 8830322191eSDong Aisheng 8840322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 8850322191eSDong Aisheng { 8860322191eSDong Aisheng u32 reg; 8870322191eSDong Aisheng 8880322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 8890322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 890da0295ffSDong Aisheng reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 8910322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 8920322191eSDong Aisheng } 8930322191eSDong Aisheng 8940322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 8950322191eSDong Aisheng { 8960322191eSDong Aisheng int min, max, avg, ret; 8970322191eSDong Aisheng 8980322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 8990322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 9000322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 9010322191eSDong Aisheng esdhc_prepare_tuning(host, min); 9029979dbe5SChaotian Jing if (!mmc_send_tuning(host->mmc, opcode, NULL)) 9030322191eSDong Aisheng break; 9040322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 9050322191eSDong Aisheng } 9060322191eSDong Aisheng 9070322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 9080322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 9090322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 9100322191eSDong Aisheng esdhc_prepare_tuning(host, max); 9119979dbe5SChaotian Jing if (mmc_send_tuning(host->mmc, opcode, NULL)) { 9120322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 9130322191eSDong Aisheng break; 9140322191eSDong Aisheng } 9150322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 9160322191eSDong Aisheng } 9170322191eSDong Aisheng 9180322191eSDong Aisheng /* use average delay to get the best timing */ 9190322191eSDong Aisheng avg = (min + max) / 2; 9200322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 9219979dbe5SChaotian Jing ret = mmc_send_tuning(host->mmc, opcode, NULL); 9220322191eSDong Aisheng esdhc_post_tuning(host); 9230322191eSDong Aisheng 924d04f8d5bSBenoît Thébaudeau dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 9250322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 9260322191eSDong Aisheng 9270322191eSDong Aisheng return ret; 9280322191eSDong Aisheng } 9290322191eSDong Aisheng 930029e2476SBOUGH CHEN static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) 931029e2476SBOUGH CHEN { 932029e2476SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 933029e2476SBOUGH CHEN u32 m; 934029e2476SBOUGH CHEN 935029e2476SBOUGH CHEN m = readl(host->ioaddr + ESDHC_MIX_CTRL); 936029e2476SBOUGH CHEN if (ios->enhanced_strobe) 937029e2476SBOUGH CHEN m |= ESDHC_MIX_CTRL_HS400_ES_EN; 938029e2476SBOUGH CHEN else 939029e2476SBOUGH CHEN m &= ~ESDHC_MIX_CTRL_HS400_ES_EN; 940029e2476SBOUGH CHEN writel(m, host->ioaddr + ESDHC_MIX_CTRL); 941029e2476SBOUGH CHEN } 942029e2476SBOUGH CHEN 943ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 944ad93220dSDong Aisheng unsigned int uhs) 945ad93220dSDong Aisheng { 946ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 947070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 948ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 949ad93220dSDong Aisheng 950ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 951ad93220dSDong Aisheng 952ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 953ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 954ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 955ad93220dSDong Aisheng return -EINVAL; 956ad93220dSDong Aisheng 957ad93220dSDong Aisheng switch (uhs) { 958ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 9599f327845SHaibo Chen case MMC_TIMING_UHS_DDR50: 960ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 961ad93220dSDong Aisheng break; 962ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 963429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 96428b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 965ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 966ad93220dSDong Aisheng break; 967ad93220dSDong Aisheng default: 968ad93220dSDong Aisheng /* back to default state for other legacy timing */ 9692480b720SUlf Hansson return pinctrl_select_default_state(mmc_dev(host->mmc)); 970ad93220dSDong Aisheng } 971ad93220dSDong Aisheng 972ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 973ad93220dSDong Aisheng } 974ad93220dSDong Aisheng 97528b07674SHaibo Chen /* 976d04f8d5bSBenoît Thébaudeau * For HS400 eMMC, there is a data_strobe line. This signal is generated 97728b07674SHaibo Chen * by the device and used for data output and CRC status response output 97828b07674SHaibo Chen * in HS400 mode. The frequency of this signal follows the frequency of 979d04f8d5bSBenoît Thébaudeau * CLK generated by host. The host receives the data which is aligned to the 98028b07674SHaibo Chen * edge of data_strobe line. Due to the time delay between CLK line and 98128b07674SHaibo Chen * data_strobe line, if the delay time is larger than one clock cycle, 982d04f8d5bSBenoît Thébaudeau * then CLK and data_strobe line will be misaligned, read error shows up. 98328b07674SHaibo Chen */ 98428b07674SHaibo Chen static void esdhc_set_strobe_dll(struct sdhci_host *host) 98528b07674SHaibo Chen { 98628b07674SHaibo Chen u32 v; 98728b07674SHaibo Chen 9887ac6da26SDong Aisheng /* disable clock before enabling strobe dll */ 9897ac6da26SDong Aisheng writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 9907ac6da26SDong Aisheng ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 9917ac6da26SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 9927ac6da26SDong Aisheng 99328b07674SHaibo Chen /* force a reset on strobe dll */ 99428b07674SHaibo Chen writel(ESDHC_STROBE_DLL_CTRL_RESET, 99528b07674SHaibo Chen host->ioaddr + ESDHC_STROBE_DLL_CTRL); 9962eaf5a53SBOUGH CHEN /* clear the reset bit on strobe dll before any setting */ 9972eaf5a53SBOUGH CHEN writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 9982eaf5a53SBOUGH CHEN 99928b07674SHaibo Chen /* 100028b07674SHaibo Chen * enable strobe dll ctrl and adjust the delay target 100128b07674SHaibo Chen * for the uSDHC loopback read clock 100228b07674SHaibo Chen */ 100328b07674SHaibo Chen v = ESDHC_STROBE_DLL_CTRL_ENABLE | 10042eaf5a53SBOUGH CHEN ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | 100528b07674SHaibo Chen (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 100628b07674SHaibo Chen writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 10072eaf5a53SBOUGH CHEN /* wait 5us to make sure strobe dll status register stable */ 10082eaf5a53SBOUGH CHEN udelay(5); 100928b07674SHaibo Chen v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); 101028b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) 101128b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 101228b07674SHaibo Chen "warning! HS400 strobe DLL status REF not lock!\n"); 101328b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 101428b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 101528b07674SHaibo Chen "warning! HS400 strobe DLL status SLV not lock!\n"); 101628b07674SHaibo Chen } 101728b07674SHaibo Chen 1018d9370424SHaibo Chen static void esdhc_reset_tuning(struct sdhci_host *host) 1019d9370424SHaibo Chen { 1020d9370424SHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1021d9370424SHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1022d9370424SHaibo Chen u32 ctrl; 1023d9370424SHaibo Chen 1024d04f8d5bSBenoît Thébaudeau /* Reset the tuning circuit */ 1025d9370424SHaibo Chen if (esdhc_is_usdhc(imx_data)) { 1026d9370424SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1027d9370424SHaibo Chen ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1028d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1029d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1030d9370424SHaibo Chen writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1031d9370424SHaibo Chen writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1032d9370424SHaibo Chen } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1033869f8a69SAdrian Hunter ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1034d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1035869f8a69SAdrian Hunter writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1036d9370424SHaibo Chen } 1037d9370424SHaibo Chen } 1038d9370424SHaibo Chen } 1039d9370424SHaibo Chen 1040850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1041ad93220dSDong Aisheng { 104228b07674SHaibo Chen u32 m; 1043ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1044070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1045602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1046ad93220dSDong Aisheng 104728b07674SHaibo Chen /* disable ddr mode and disable HS400 mode */ 104828b07674SHaibo Chen m = readl(host->ioaddr + ESDHC_MIX_CTRL); 104928b07674SHaibo Chen m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 105028b07674SHaibo Chen imx_data->is_ddr = 0; 105128b07674SHaibo Chen 1052850a29b8SRussell King switch (timing) { 1053ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 1054ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 1055ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 1056ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 1057de0a0decSBOUGH CHEN case MMC_TIMING_MMC_HS: 1058429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 105928b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1060ad93220dSDong Aisheng break; 1061ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 106269f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 106328b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN; 106428b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1065de5bdbffSDong Aisheng imx_data->is_ddr = 1; 1066602519b2SDong Aisheng if (boarddata->delay_line) { 1067602519b2SDong Aisheng u32 v; 1068602519b2SDong Aisheng v = boarddata->delay_line << 1069602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 1070602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 1071602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 1072602519b2SDong Aisheng v <<= 1; 1073602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 1074602519b2SDong Aisheng } 1075ad93220dSDong Aisheng break; 107628b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 107728b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 107828b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 107928b07674SHaibo Chen imx_data->is_ddr = 1; 10807ac6da26SDong Aisheng /* update clock after enable DDR for strobe DLL lock */ 10817ac6da26SDong Aisheng host->ops->set_clock(host, host->clock); 108228b07674SHaibo Chen esdhc_set_strobe_dll(host); 108328b07674SHaibo Chen break; 1084d9370424SHaibo Chen case MMC_TIMING_LEGACY: 1085d9370424SHaibo Chen default: 1086d9370424SHaibo Chen esdhc_reset_tuning(host); 1087d9370424SHaibo Chen break; 1088ad93220dSDong Aisheng } 1089ad93220dSDong Aisheng 1090850a29b8SRussell King esdhc_change_pinstate(host, timing); 1091ad93220dSDong Aisheng } 1092ad93220dSDong Aisheng 10930718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 10940718e59aSRussell King { 10950718e59aSRussell King sdhci_reset(host, mask); 10960718e59aSRussell King 10970718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 10980718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 10990718e59aSRussell King } 11000718e59aSRussell King 110110fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 110210fd0ad9SAisheng Dong { 110310fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1104070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 110510fd0ad9SAisheng Dong 1106d04f8d5bSBenoît Thébaudeau /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 11072fb0b02bSHaibo Chen return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 110810fd0ad9SAisheng Dong } 110910fd0ad9SAisheng Dong 1110e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1111e33eb8e2SAisheng Dong { 1112e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1113070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1114e33eb8e2SAisheng Dong 1115e33eb8e2SAisheng Dong /* use maximum timeout counter */ 1116a215186dSHaibo Chen esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1117a215186dSHaibo Chen esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1118e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 1119e33eb8e2SAisheng Dong } 1120e33eb8e2SAisheng Dong 1121bb6e3581SBOUGH CHEN static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) 1122bb6e3581SBOUGH CHEN { 1123bb6e3581SBOUGH CHEN int cmd_error = 0; 1124bb6e3581SBOUGH CHEN int data_error = 0; 1125bb6e3581SBOUGH CHEN 1126bb6e3581SBOUGH CHEN if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1127bb6e3581SBOUGH CHEN return intmask; 1128bb6e3581SBOUGH CHEN 1129bb6e3581SBOUGH CHEN cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1130bb6e3581SBOUGH CHEN 1131bb6e3581SBOUGH CHEN return 0; 1132bb6e3581SBOUGH CHEN } 1133bb6e3581SBOUGH CHEN 11346e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 1135e149860dSRichard Zhu .read_l = esdhc_readl_le, 11360c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 113777da3da0SAaron Brice .read_b = esdhc_readb_le, 1138e149860dSRichard Zhu .write_l = esdhc_writel_le, 11390c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 11400c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 11418ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 11420ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 11430c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 114410fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 1145913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 1146e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 11472317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 1148ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 11490718e59aSRussell King .reset = esdhc_reset, 1150bb6e3581SBOUGH CHEN .irq = esdhc_cqhci_irq, 11510c6d49ceSWolfram Sang }; 11520c6d49ceSWolfram Sang 11531db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 115497e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 115597e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 115697e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 115785d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 115885d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 115985d6509dSShawn Guo }; 116085d6509dSShawn Guo 1161f3f5cf3dSDong Aisheng static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1162f3f5cf3dSDong Aisheng { 1163f3f5cf3dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1164f3f5cf3dSDong Aisheng struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 11652b16cf32SDong Aisheng int tmp; 1166f3f5cf3dSDong Aisheng 1167f3f5cf3dSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 1168f3f5cf3dSDong Aisheng /* 1169f3f5cf3dSDong Aisheng * The imx6q ROM code will change the default watermark 1170f3f5cf3dSDong Aisheng * level setting to something insane. Change it back here. 1171f3f5cf3dSDong Aisheng */ 1172f3f5cf3dSDong Aisheng writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1173f3f5cf3dSDong Aisheng 1174f3f5cf3dSDong Aisheng /* 1175f3f5cf3dSDong Aisheng * ROM code will change the bit burst_length_enable setting 1176d04f8d5bSBenoît Thébaudeau * to zero if this usdhc is chosen to boot system. Change 1177f3f5cf3dSDong Aisheng * it back here, otherwise it will impact the performance a 1178f3f5cf3dSDong Aisheng * lot. This bit is used to enable/disable the burst length 1179d04f8d5bSBenoît Thébaudeau * for the external AHB2AXI bridge. It's useful especially 1180f3f5cf3dSDong Aisheng * for INCR transfer because without burst length indicator, 1181f3f5cf3dSDong Aisheng * the AHB2AXI bridge does not know the burst length in 1182f3f5cf3dSDong Aisheng * advance. And without burst length indicator, AHB INCR 1183f3f5cf3dSDong Aisheng * transfer can only be converted to singles on the AXI side. 1184f3f5cf3dSDong Aisheng */ 1185f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1186f3f5cf3dSDong Aisheng | ESDHC_BURST_LEN_EN_INCR, 1187f3f5cf3dSDong Aisheng host->ioaddr + SDHCI_HOST_CONTROL); 1188e30be063SBOUGH CHEN 1189f3f5cf3dSDong Aisheng /* 1190d04f8d5bSBenoît Thébaudeau * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1191f3f5cf3dSDong Aisheng * TO1.1, it's harmless for MX6SL 1192f3f5cf3dSDong Aisheng */ 1193e30be063SBOUGH CHEN writel(readl(host->ioaddr + 0x6c) & ~BIT(7), 1194f3f5cf3dSDong Aisheng host->ioaddr + 0x6c); 1195f3f5cf3dSDong Aisheng 1196f3f5cf3dSDong Aisheng /* disable DLL_CTRL delay line settings */ 1197f3f5cf3dSDong Aisheng writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 11982b16cf32SDong Aisheng 1199bcdb5301SBOUGH CHEN /* 1200bcdb5301SBOUGH CHEN * For the case of command with busy, if set the bit 1201bcdb5301SBOUGH CHEN * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a 1202bcdb5301SBOUGH CHEN * transfer complete interrupt when busy is deasserted. 1203bcdb5301SBOUGH CHEN * When CQHCI use DCMD to send a CMD need R1b respons, 1204bcdb5301SBOUGH CHEN * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ, 1205bcdb5301SBOUGH CHEN * otherwise DCMD will always meet timeout waiting for 1206bcdb5301SBOUGH CHEN * hardware interrupt issue. 1207bcdb5301SBOUGH CHEN */ 1208bcdb5301SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1209bcdb5301SBOUGH CHEN tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); 1210bcdb5301SBOUGH CHEN tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ; 1211bcdb5301SBOUGH CHEN writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); 1212bcdb5301SBOUGH CHEN 1213bcdb5301SBOUGH CHEN host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1214bcdb5301SBOUGH CHEN } 1215bcdb5301SBOUGH CHEN 12162b16cf32SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 12172b16cf32SDong Aisheng tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 12182b16cf32SDong Aisheng tmp |= ESDHC_STD_TUNING_EN | 12192b16cf32SDong Aisheng ESDHC_TUNING_START_TAP_DEFAULT; 12202b16cf32SDong Aisheng if (imx_data->boarddata.tuning_start_tap) { 12212b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_START_TAP_MASK; 12222b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_start_tap; 12232b16cf32SDong Aisheng } 12242b16cf32SDong Aisheng 12252b16cf32SDong Aisheng if (imx_data->boarddata.tuning_step) { 12262b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_STEP_MASK; 12272b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_step 12282b16cf32SDong Aisheng << ESDHC_TUNING_STEP_SHIFT; 12292b16cf32SDong Aisheng } 12302b16cf32SDong Aisheng writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1231a98c557eSBOUGH CHEN } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1232a98c557eSBOUGH CHEN /* 1233a98c557eSBOUGH CHEN * ESDHC_STD_TUNING_EN may be configed in bootloader 1234a98c557eSBOUGH CHEN * or ROM code, so clear this bit here to make sure 1235a98c557eSBOUGH CHEN * the manual tuning can work. 1236a98c557eSBOUGH CHEN */ 1237a98c557eSBOUGH CHEN tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1238a98c557eSBOUGH CHEN tmp &= ~ESDHC_STD_TUNING_EN; 1239a98c557eSBOUGH CHEN writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 12402b16cf32SDong Aisheng } 1241f3f5cf3dSDong Aisheng } 1242f3f5cf3dSDong Aisheng } 1243f3f5cf3dSDong Aisheng 1244bb6e3581SBOUGH CHEN static void esdhc_cqe_enable(struct mmc_host *mmc) 1245bb6e3581SBOUGH CHEN { 1246bb6e3581SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 124785236d2bSBOUGH CHEN struct cqhci_host *cq_host = mmc->cqe_private; 1248bb6e3581SBOUGH CHEN u32 reg; 1249bb6e3581SBOUGH CHEN u16 mode; 1250bb6e3581SBOUGH CHEN int count = 10; 1251bb6e3581SBOUGH CHEN 1252bb6e3581SBOUGH CHEN /* 1253bb6e3581SBOUGH CHEN * CQE gets stuck if it sees Buffer Read Enable bit set, which can be 1254bb6e3581SBOUGH CHEN * the case after tuning, so ensure the buffer is drained. 1255bb6e3581SBOUGH CHEN */ 1256bb6e3581SBOUGH CHEN reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1257bb6e3581SBOUGH CHEN while (reg & SDHCI_DATA_AVAILABLE) { 1258bb6e3581SBOUGH CHEN sdhci_readl(host, SDHCI_BUFFER); 1259bb6e3581SBOUGH CHEN reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1260bb6e3581SBOUGH CHEN if (count-- == 0) { 1261bb6e3581SBOUGH CHEN dev_warn(mmc_dev(host->mmc), 1262bb6e3581SBOUGH CHEN "CQE may get stuck because the Buffer Read Enable bit is set\n"); 1263bb6e3581SBOUGH CHEN break; 1264bb6e3581SBOUGH CHEN } 1265bb6e3581SBOUGH CHEN mdelay(1); 1266bb6e3581SBOUGH CHEN } 1267bb6e3581SBOUGH CHEN 1268bb6e3581SBOUGH CHEN /* 1269bb6e3581SBOUGH CHEN * Runtime resume will reset the entire host controller, which 1270bb6e3581SBOUGH CHEN * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL. 1271bb6e3581SBOUGH CHEN * Here set DMAEN and BCEN when enable CMDQ. 1272bb6e3581SBOUGH CHEN */ 1273bb6e3581SBOUGH CHEN mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 1274bb6e3581SBOUGH CHEN if (host->flags & SDHCI_REQ_USE_DMA) 1275bb6e3581SBOUGH CHEN mode |= SDHCI_TRNS_DMA; 1276bb6e3581SBOUGH CHEN if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 1277bb6e3581SBOUGH CHEN mode |= SDHCI_TRNS_BLK_CNT_EN; 1278bb6e3581SBOUGH CHEN sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 1279bb6e3581SBOUGH CHEN 128085236d2bSBOUGH CHEN /* 128185236d2bSBOUGH CHEN * Though Runtime resume reset the entire host controller, 128285236d2bSBOUGH CHEN * but do not impact the CQHCI side, need to clear the 128385236d2bSBOUGH CHEN * HALT bit, avoid CQHCI stuck in the first request when 128485236d2bSBOUGH CHEN * system resume back. 128585236d2bSBOUGH CHEN */ 128685236d2bSBOUGH CHEN cqhci_writel(cq_host, 0, CQHCI_CTL); 128785236d2bSBOUGH CHEN if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT) 128885236d2bSBOUGH CHEN dev_err(mmc_dev(host->mmc), 128985236d2bSBOUGH CHEN "failed to exit halt state when enable CQE\n"); 129085236d2bSBOUGH CHEN 129185236d2bSBOUGH CHEN 1292bb6e3581SBOUGH CHEN sdhci_cqe_enable(mmc); 1293bb6e3581SBOUGH CHEN } 1294bb6e3581SBOUGH CHEN 1295bb6e3581SBOUGH CHEN static void esdhc_sdhci_dumpregs(struct mmc_host *mmc) 1296bb6e3581SBOUGH CHEN { 1297bb6e3581SBOUGH CHEN sdhci_dumpregs(mmc_priv(mmc)); 1298bb6e3581SBOUGH CHEN } 1299bb6e3581SBOUGH CHEN 1300bb6e3581SBOUGH CHEN static const struct cqhci_host_ops esdhc_cqhci_ops = { 1301bb6e3581SBOUGH CHEN .enable = esdhc_cqe_enable, 1302bb6e3581SBOUGH CHEN .disable = sdhci_cqe_disable, 1303bb6e3581SBOUGH CHEN .dumpregs = esdhc_sdhci_dumpregs, 1304bb6e3581SBOUGH CHEN }; 1305bb6e3581SBOUGH CHEN 1306abfafc2dSShawn Guo #ifdef CONFIG_OF 1307c3be1efdSBill Pemberton static int 1308abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 130907bf2b54SSascha Hauer struct sdhci_host *host, 131091fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1311abfafc2dSShawn Guo { 1312abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 131391fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 13144800e87aSDong Aisheng int ret; 1315abfafc2dSShawn Guo 1316abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 1317abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 1318abfafc2dSShawn Guo 131974ff81e1SLinus Walleij /* 132074ff81e1SLinus Walleij * If we have this property, then activate WP check. 132174ff81e1SLinus Walleij * Retrieveing and requesting the actual WP GPIO will happen 132274ff81e1SLinus Walleij * in the call to mmc_of_parse(). 132374ff81e1SLinus Walleij */ 132474ff81e1SLinus Walleij if (of_property_read_bool(np, "wp-gpios")) 1325abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 1326abfafc2dSShawn Guo 1327d407e30bSHaibo Chen of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1328d87fc966SDong Aisheng of_property_read_u32(np, "fsl,tuning-start-tap", 1329d87fc966SDong Aisheng &boarddata->tuning_start_tap); 1330d407e30bSHaibo Chen 1331ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 133286f495c5SStefan Agner host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1333ad93220dSDong Aisheng 1334602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1335602519b2SDong Aisheng boarddata->delay_line = 0; 1336602519b2SDong Aisheng 133707bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 133807bf2b54SSascha Hauer 13392480b720SUlf Hansson if (esdhc_is_usdhc(imx_data)) { 134091fa4252SDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 134191fa4252SDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 134291fa4252SDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 134391fa4252SDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 134491fa4252SDong Aisheng } 134591fa4252SDong Aisheng 134615064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 13474800e87aSDong Aisheng ret = mmc_of_parse(host->mmc); 13484800e87aSDong Aisheng if (ret) 13494800e87aSDong Aisheng return ret; 13504800e87aSDong Aisheng 1351287980e4SArnd Bergmann if (mmc_gpio_get_cd(host->mmc) >= 0) 13524800e87aSDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 13534800e87aSDong Aisheng 13544800e87aSDong Aisheng return 0; 1355abfafc2dSShawn Guo } 1356abfafc2dSShawn Guo #else 1357abfafc2dSShawn Guo static inline int 1358abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 135907bf2b54SSascha Hauer struct sdhci_host *host, 136091fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1361abfafc2dSShawn Guo { 1362abfafc2dSShawn Guo return -ENODEV; 1363abfafc2dSShawn Guo } 1364abfafc2dSShawn Guo #endif 1365abfafc2dSShawn Guo 136691fa4252SDong Aisheng static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 136791fa4252SDong Aisheng struct sdhci_host *host, 136891fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 136991fa4252SDong Aisheng { 137091fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 137191fa4252SDong Aisheng int err; 137291fa4252SDong Aisheng 137391fa4252SDong Aisheng if (!host->mmc->parent->platform_data) { 137491fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), "no board data!\n"); 137591fa4252SDong Aisheng return -EINVAL; 137691fa4252SDong Aisheng } 137791fa4252SDong Aisheng 137891fa4252SDong Aisheng imx_data->boarddata = *((struct esdhc_platform_data *) 137991fa4252SDong Aisheng host->mmc->parent->platform_data); 138091fa4252SDong Aisheng /* write_protect */ 138191fa4252SDong Aisheng if (boarddata->wp_type == ESDHC_WP_GPIO) { 13829073d10bSMichał Mirosław host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 13839073d10bSMichał Mirosław 1384a2b760a6SLinus Walleij err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0, NULL); 138591fa4252SDong Aisheng if (err) { 138691fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 138791fa4252SDong Aisheng "failed to request write-protect gpio!\n"); 138891fa4252SDong Aisheng return err; 138991fa4252SDong Aisheng } 139091fa4252SDong Aisheng } 139191fa4252SDong Aisheng 139291fa4252SDong Aisheng /* card_detect */ 139391fa4252SDong Aisheng switch (boarddata->cd_type) { 139491fa4252SDong Aisheng case ESDHC_CD_GPIO: 139574ff81e1SLinus Walleij err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0, NULL); 139691fa4252SDong Aisheng if (err) { 139791fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 139891fa4252SDong Aisheng "failed to request card-detect gpio!\n"); 139991fa4252SDong Aisheng return err; 140091fa4252SDong Aisheng } 140191fa4252SDong Aisheng /* fall through */ 140291fa4252SDong Aisheng 140391fa4252SDong Aisheng case ESDHC_CD_CONTROLLER: 140491fa4252SDong Aisheng /* we have a working card_detect back */ 140591fa4252SDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 140691fa4252SDong Aisheng break; 140791fa4252SDong Aisheng 140891fa4252SDong Aisheng case ESDHC_CD_PERMANENT: 140991fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 141091fa4252SDong Aisheng break; 141191fa4252SDong Aisheng 141291fa4252SDong Aisheng case ESDHC_CD_NONE: 141391fa4252SDong Aisheng break; 141491fa4252SDong Aisheng } 141591fa4252SDong Aisheng 141691fa4252SDong Aisheng switch (boarddata->max_bus_width) { 141791fa4252SDong Aisheng case 8: 141891fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 141991fa4252SDong Aisheng break; 142091fa4252SDong Aisheng case 4: 142191fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_4_BIT_DATA; 142291fa4252SDong Aisheng break; 142391fa4252SDong Aisheng case 1: 142491fa4252SDong Aisheng default: 142591fa4252SDong Aisheng host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 142691fa4252SDong Aisheng break; 142791fa4252SDong Aisheng } 142891fa4252SDong Aisheng 142991fa4252SDong Aisheng return 0; 143091fa4252SDong Aisheng } 143191fa4252SDong Aisheng 1432c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 143395f25efeSWolfram Sang { 1434abfafc2dSShawn Guo const struct of_device_id *of_id = 1435abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 143685d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 143785d6509dSShawn Guo struct sdhci_host *host; 1438bb6e3581SBOUGH CHEN struct cqhci_host *cq_host; 14390c6d49ceSWolfram Sang int err; 1440e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 144195f25efeSWolfram Sang 1442070e6d3fSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1443070e6d3fSJisheng Zhang sizeof(*imx_data)); 144485d6509dSShawn Guo if (IS_ERR(host)) 144585d6509dSShawn Guo return PTR_ERR(host); 144685d6509dSShawn Guo 144785d6509dSShawn Guo pltfm_host = sdhci_priv(host); 144885d6509dSShawn Guo 1449070e6d3fSJisheng Zhang imx_data = sdhci_pltfm_priv(pltfm_host); 145057ed3314SShawn Guo 1451f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 14523770ee8fSShawn Guo pdev->id_entry->driver_data; 145385d6509dSShawn Guo 14541c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 14551c4989b0SBOUGH CHEN pm_qos_add_request(&imx_data->pm_qos_req, 14561c4989b0SBOUGH CHEN PM_QOS_CPU_DMA_LATENCY, 0); 14571c4989b0SBOUGH CHEN 145852dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 145952dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 146052dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 1461e3af31c6SShawn Guo goto free_sdhci; 146295f25efeSWolfram Sang } 146352dac615SSascha Hauer 146452dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 146552dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 146652dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 1467e3af31c6SShawn Guo goto free_sdhci; 146852dac615SSascha Hauer } 146952dac615SSascha Hauer 147052dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 147152dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 147252dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 1473e3af31c6SShawn Guo goto free_sdhci; 147452dac615SSascha Hauer } 147552dac615SSascha Hauer 147652dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 1477a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 147817b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 147917b1eb7fSFabio Estevam if (err) 148017b1eb7fSFabio Estevam goto free_sdhci; 148117b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 148217b1eb7fSFabio Estevam if (err) 148317b1eb7fSFabio Estevam goto disable_per_clk; 148417b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ahb); 148517b1eb7fSFabio Estevam if (err) 148617b1eb7fSFabio Estevam goto disable_ipg_clk; 148795f25efeSWolfram Sang 1488ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1489e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1490e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 149117b1eb7fSFabio Estevam goto disable_ahb_clk; 1492e62d8b8fSDong Aisheng } 1493e62d8b8fSDong Aisheng 149469ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 149569ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 149609c8192bSStefan Agner host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 14974245afffSDong Aisheng if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 14984245afffSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1499a75dcbf4SDong Aisheng 1500a75dcbf4SDong Aisheng /* clear tuning bits in case ROM has set it already */ 1501a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1502869f8a69SAdrian Hunter writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1503a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1504de3e1dd0SBOUGH CHEN 1505de3e1dd0SBOUGH CHEN /* 1506de3e1dd0SBOUGH CHEN * Link usdhc specific mmc_host_ops execute_tuning function, 1507de3e1dd0SBOUGH CHEN * to replace the standard one in sdhci_ops. 1508de3e1dd0SBOUGH CHEN */ 1509de3e1dd0SBOUGH CHEN host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; 151069ed60e0SDong Aisheng } 1511f750ba9bSShawn Guo 15126e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 15136e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 15146e9fd28eSDong Aisheng esdhc_executing_tuning; 15158b2bb0adSDong Aisheng 151618094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 151718094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 151818094430SDong Aisheng 151928b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 152028b07674SHaibo Chen host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 152128b07674SHaibo Chen 1522029e2476SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { 1523029e2476SBOUGH CHEN host->mmc->caps2 |= MMC_CAP2_HS400_ES; 1524029e2476SBOUGH CHEN host->mmc_host_ops.hs400_enhanced_strobe = 1525029e2476SBOUGH CHEN esdhc_hs400_enhanced_strobe; 1526029e2476SBOUGH CHEN } 1527029e2476SBOUGH CHEN 1528bb6e3581SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1529bcdb5301SBOUGH CHEN host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1530bb6e3581SBOUGH CHEN cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 15319a633f3bSWei Yongjun if (!cq_host) { 15329a633f3bSWei Yongjun err = -ENOMEM; 1533bb6e3581SBOUGH CHEN goto disable_ahb_clk; 1534bb6e3581SBOUGH CHEN } 1535bb6e3581SBOUGH CHEN 1536bb6e3581SBOUGH CHEN cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; 1537bb6e3581SBOUGH CHEN cq_host->ops = &esdhc_cqhci_ops; 1538bb6e3581SBOUGH CHEN 1539bb6e3581SBOUGH CHEN err = cqhci_init(cq_host, host->mmc, false); 1540bb6e3581SBOUGH CHEN if (err) 1541bb6e3581SBOUGH CHEN goto disable_ahb_clk; 1542bb6e3581SBOUGH CHEN } 1543bb6e3581SBOUGH CHEN 154491fa4252SDong Aisheng if (of_id) 154591fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 154691fa4252SDong Aisheng else 154791fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 154891fa4252SDong Aisheng if (err) 154917b1eb7fSFabio Estevam goto disable_ahb_clk; 1550ad93220dSDong Aisheng 1551d00ab101SBOUGH CHEN host->tuning_delay = 1; 1552d00ab101SBOUGH CHEN 1553f3f5cf3dSDong Aisheng sdhci_esdhc_imx_hwinit(host); 1554f3f5cf3dSDong Aisheng 155585d6509dSShawn Guo err = sdhci_add_host(host); 155685d6509dSShawn Guo if (err) 155717b1eb7fSFabio Estevam goto disable_ahb_clk; 155885d6509dSShawn Guo 155989d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 156089d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 156189d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 156289d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 156377903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 156489d7e5c1SDong Aisheng 15657e29c306SWolfram Sang return 0; 15667e29c306SWolfram Sang 156717b1eb7fSFabio Estevam disable_ahb_clk: 156852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 156917b1eb7fSFabio Estevam disable_ipg_clk: 157017b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 157117b1eb7fSFabio Estevam disable_per_clk: 157217b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1573e3af31c6SShawn Guo free_sdhci: 15741c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 15751c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 157685d6509dSShawn Guo sdhci_pltfm_free(pdev); 157785d6509dSShawn Guo return err; 157895f25efeSWolfram Sang } 157995f25efeSWolfram Sang 15806e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 158195f25efeSWolfram Sang { 158285d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 158395f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1584070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 158585d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 158685d6509dSShawn Guo 15870b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 15880b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 15890b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 15900b414368SUlf Hansson 159185d6509dSShawn Guo sdhci_remove_host(host, dead); 15920c6d49ceSWolfram Sang 159352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 159452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 159552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 159652dac615SSascha Hauer 15971c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 15981c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 15991c4989b0SBOUGH CHEN 160085d6509dSShawn Guo sdhci_pltfm_free(pdev); 160185d6509dSShawn Guo 160285d6509dSShawn Guo return 0; 160395f25efeSWolfram Sang } 160495f25efeSWolfram Sang 16052788ed42SUlf Hansson #ifdef CONFIG_PM_SLEEP 160604143fbaSDong Aisheng static int sdhci_esdhc_suspend(struct device *dev) 160704143fbaSDong Aisheng { 16083e3274abSUlf Hansson struct sdhci_host *host = dev_get_drvdata(dev); 1609bb6e3581SBOUGH CHEN int ret; 1610bb6e3581SBOUGH CHEN 1611bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) { 1612bb6e3581SBOUGH CHEN ret = cqhci_suspend(host->mmc); 1613bb6e3581SBOUGH CHEN if (ret) 1614bb6e3581SBOUGH CHEN return ret; 1615bb6e3581SBOUGH CHEN } 16163e3274abSUlf Hansson 1617d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1618d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1619d38dcad4SAdrian Hunter 16203e3274abSUlf Hansson return sdhci_suspend_host(host); 162104143fbaSDong Aisheng } 162204143fbaSDong Aisheng 162304143fbaSDong Aisheng static int sdhci_esdhc_resume(struct device *dev) 162404143fbaSDong Aisheng { 1625cc17e129SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 1626bb6e3581SBOUGH CHEN int ret; 1627cc17e129SDong Aisheng 162819dbfdd3SDong Aisheng /* re-initialize hw state in case it's lost in low power mode */ 162919dbfdd3SDong Aisheng sdhci_esdhc_imx_hwinit(host); 1630cc17e129SDong Aisheng 1631bb6e3581SBOUGH CHEN ret = sdhci_resume_host(host); 1632bb6e3581SBOUGH CHEN if (ret) 1633bb6e3581SBOUGH CHEN return ret; 1634bb6e3581SBOUGH CHEN 1635bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) 1636bb6e3581SBOUGH CHEN ret = cqhci_resume(host->mmc); 1637bb6e3581SBOUGH CHEN 1638bb6e3581SBOUGH CHEN return ret; 163904143fbaSDong Aisheng } 16402788ed42SUlf Hansson #endif 164104143fbaSDong Aisheng 16422788ed42SUlf Hansson #ifdef CONFIG_PM 164389d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 164489d7e5c1SDong Aisheng { 164589d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 164689d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1647070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 164889d7e5c1SDong Aisheng int ret; 164989d7e5c1SDong Aisheng 1650bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) { 1651bb6e3581SBOUGH CHEN ret = cqhci_suspend(host->mmc); 1652bb6e3581SBOUGH CHEN if (ret) 1653bb6e3581SBOUGH CHEN return ret; 1654bb6e3581SBOUGH CHEN } 1655bb6e3581SBOUGH CHEN 165689d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 1657371d39faSMichael Trimarchi if (ret) 1658371d39faSMichael Trimarchi return ret; 165989d7e5c1SDong Aisheng 1660d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1661d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1662d38dcad4SAdrian Hunter 16633602785bSMichael Trimarchi imx_data->actual_clock = host->mmc->actual_clock; 16643602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, 0); 166589d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 166689d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 166789d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 166889d7e5c1SDong Aisheng 16691c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 16701c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 16711c4989b0SBOUGH CHEN 167289d7e5c1SDong Aisheng return ret; 167389d7e5c1SDong Aisheng } 167489d7e5c1SDong Aisheng 167589d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 167689d7e5c1SDong Aisheng { 167789d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 167889d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1679070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 168017b1eb7fSFabio Estevam int err; 168189d7e5c1SDong Aisheng 16821c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 16831c4989b0SBOUGH CHEN pm_qos_add_request(&imx_data->pm_qos_req, 16841c4989b0SBOUGH CHEN PM_QOS_CPU_DMA_LATENCY, 0); 16851c4989b0SBOUGH CHEN 1686a0ad3087SMichael Trimarchi err = clk_prepare_enable(imx_data->clk_ahb); 1687a0ad3087SMichael Trimarchi if (err) 16881c4989b0SBOUGH CHEN goto remove_pm_qos_request; 1689a0ad3087SMichael Trimarchi 169017b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 169117b1eb7fSFabio Estevam if (err) 1692a0ad3087SMichael Trimarchi goto disable_ahb_clk; 1693af5d2b7bSUlf Hansson 169417b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 169517b1eb7fSFabio Estevam if (err) 169617b1eb7fSFabio Estevam goto disable_per_clk; 1697af5d2b7bSUlf Hansson 16983602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1699a0ad3087SMichael Trimarchi 1700c6303c5dSBaolin Wang err = sdhci_runtime_resume_host(host, 0); 170117b1eb7fSFabio Estevam if (err) 1702a0ad3087SMichael Trimarchi goto disable_ipg_clk; 170389d7e5c1SDong Aisheng 1704bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) 1705bb6e3581SBOUGH CHEN err = cqhci_resume(host->mmc); 1706bb6e3581SBOUGH CHEN 1707bb6e3581SBOUGH CHEN return err; 170817b1eb7fSFabio Estevam 170917b1eb7fSFabio Estevam disable_ipg_clk: 171017b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 171117b1eb7fSFabio Estevam disable_per_clk: 171217b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1713a0ad3087SMichael Trimarchi disable_ahb_clk: 1714a0ad3087SMichael Trimarchi clk_disable_unprepare(imx_data->clk_ahb); 17151c4989b0SBOUGH CHEN remove_pm_qos_request: 17161c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 17171c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 171817b1eb7fSFabio Estevam return err; 171989d7e5c1SDong Aisheng } 172089d7e5c1SDong Aisheng #endif 172189d7e5c1SDong Aisheng 172289d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 172304143fbaSDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 172489d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 172589d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 172689d7e5c1SDong Aisheng }; 172789d7e5c1SDong Aisheng 172885d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 172985d6509dSShawn Guo .driver = { 173085d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1731abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 173289d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 173385d6509dSShawn Guo }, 173457ed3314SShawn Guo .id_table = imx_esdhc_devtype, 173585d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 17360433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 173795f25efeSWolfram Sang }; 173885d6509dSShawn Guo 1739d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 174085d6509dSShawn Guo 174185d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1742035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 174385d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1744