195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 795f25efeSWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3089d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 3195f25efeSWolfram Sang #include "sdhci-pltfm.h" 3295f25efeSWolfram Sang #include "sdhci-esdhc.h" 3395f25efeSWolfram Sang 3460bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 3558ac8177SRichard Zhu /* VENDOR SPEC register */ 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3760bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 380322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 39fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 4060bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 4160bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 42de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 432a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 440322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 450322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 460322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 472a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 482a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 49d131a71cSDong Aisheng /* Tuning bits */ 50d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 5158ac8177SRichard Zhu 52602519b2SDong Aisheng /* dll control register */ 53602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 54602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 55602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 56602519b2SDong Aisheng 570322191eSDong Aisheng /* tune control register */ 580322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 590322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 600322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 610322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 620322191eSDong Aisheng 636e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 646e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 656e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 666e9fd28eSDong Aisheng #define ESDHC_TUNING_START_TAP 0x1 676e9fd28eSDong Aisheng 680322191eSDong Aisheng #define ESDHC_TUNING_BLOCK_PATTERN_LEN 64 690322191eSDong Aisheng 70ad93220dSDong Aisheng /* pinctrl state */ 71ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 72ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 73ad93220dSDong Aisheng 7458ac8177SRichard Zhu /* 75af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 76af51079eSSascha Hauer */ 77af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 78af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 79af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 80af51079eSSascha Hauer 81af51079eSSascha Hauer /* 8297e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 8397e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 8497e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 8597e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 8697e4ba6aSRichard Zhu */ 8760bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 8897e4ba6aSRichard Zhu 8997e4ba6aSRichard Zhu /* 9058ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 9158ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 9258ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 9358ac8177SRichard Zhu * be generated. 9458ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 9558ac8177SRichard Zhu * operations automatically as required at the end of the 9658ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 9758ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 9858ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 9958ac8177SRichard Zhu */ 10031fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 10131fbb301SShawn Guo /* 10231fbb301SShawn Guo * The flag enables the workaround for ESDHC errata ENGcm07207 which 10331fbb301SShawn Guo * affects i.MX25 and i.MX35. 10431fbb301SShawn Guo */ 10531fbb301SShawn Guo #define ESDHC_FLAG_ENGCM07207 BIT(2) 1069d61c009SShawn Guo /* 1079d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1089d61c009SShawn Guo * integrated on the i.MX6 series. 1099d61c009SShawn Guo */ 1109d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1116e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1126e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1136e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1146e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1156e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1166e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 117e149860dSRichard Zhu 118f47c4bbfSShawn Guo struct esdhc_soc_data { 119f47c4bbfSShawn Guo u32 flags; 120f47c4bbfSShawn Guo }; 121f47c4bbfSShawn Guo 122f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx25_data = { 123f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 124f47c4bbfSShawn Guo }; 125f47c4bbfSShawn Guo 126f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx35_data = { 127f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 128f47c4bbfSShawn Guo }; 129f47c4bbfSShawn Guo 130f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx51_data = { 131f47c4bbfSShawn Guo .flags = 0, 132f47c4bbfSShawn Guo }; 133f47c4bbfSShawn Guo 134f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx53_data = { 135f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 136f47c4bbfSShawn Guo }; 137f47c4bbfSShawn Guo 138f47c4bbfSShawn Guo static struct esdhc_soc_data usdhc_imx6q_data = { 1396e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1406e9fd28eSDong Aisheng }; 1416e9fd28eSDong Aisheng 1426e9fd28eSDong Aisheng static struct esdhc_soc_data usdhc_imx6sl_data = { 1436e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1446e9fd28eSDong Aisheng | ESDHC_FLAG_HAVE_CAP1, 14557ed3314SShawn Guo }; 14657ed3314SShawn Guo 147e149860dSRichard Zhu struct pltfm_imx_data { 148e149860dSRichard Zhu u32 scratchpad; 149e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 150ad93220dSDong Aisheng struct pinctrl_state *pins_default; 151ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 152ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 153f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 154842afc02SShawn Guo struct esdhc_platform_data boarddata; 15552dac615SSascha Hauer struct clk *clk_ipg; 15652dac615SSascha Hauer struct clk *clk_ahb; 15752dac615SSascha Hauer struct clk *clk_per; 158361b8482SLucas Stach enum { 159361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending*/ 160361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 161361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 162361b8482SLucas Stach } multiblock_status; 1630322191eSDong Aisheng u32 uhs_mode; 164de5bdbffSDong Aisheng u32 is_ddr; 165e149860dSRichard Zhu }; 166e149860dSRichard Zhu 16757ed3314SShawn Guo static struct platform_device_id imx_esdhc_devtype[] = { 16857ed3314SShawn Guo { 16957ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 170f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 17157ed3314SShawn Guo }, { 17257ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 173f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 17457ed3314SShawn Guo }, { 17557ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 176f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 17757ed3314SShawn Guo }, { 17857ed3314SShawn Guo /* sentinel */ 17957ed3314SShawn Guo } 18057ed3314SShawn Guo }; 18157ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 18257ed3314SShawn Guo 183abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 184f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 185f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 186f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 187f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 1886e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 189f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 190abfafc2dSShawn Guo { /* sentinel */ } 191abfafc2dSShawn Guo }; 192abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 193abfafc2dSShawn Guo 19457ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 19557ed3314SShawn Guo { 196f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 19757ed3314SShawn Guo } 19857ed3314SShawn Guo 19957ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 20057ed3314SShawn Guo { 201f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 20257ed3314SShawn Guo } 20357ed3314SShawn Guo 20495a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 20595a2482aSShawn Guo { 206f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 20795a2482aSShawn Guo } 20895a2482aSShawn Guo 2099d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2109d61c009SShawn Guo { 211f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2129d61c009SShawn Guo } 2139d61c009SShawn Guo 21495f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 21595f25efeSWolfram Sang { 21695f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 21795f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 21895f25efeSWolfram Sang 21995f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 22095f25efeSWolfram Sang } 22195f25efeSWolfram Sang 2227e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 2237e29c306SWolfram Sang { 224361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 225361b8482SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 226913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 227913413c3SShawn Guo 2280322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 2290322191eSDong Aisheng u32 fsl_prss = val; 2300322191eSDong Aisheng /* save the least 20 bits */ 2310322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 2320322191eSDong Aisheng /* move dat[0-3] bits */ 2330322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 2340322191eSDong Aisheng /* move cmd line bit */ 2350322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 2360322191eSDong Aisheng } 2370322191eSDong Aisheng 23897e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 2396b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 2406b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2416b4fb671SDong Aisheng val &= 0xffff0000; 2426b4fb671SDong Aisheng 24397e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 24497e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 24597e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 24697e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 24797e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 24897e4ba6aSRichard Zhu */ 24997e4ba6aSRichard Zhu 25097e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 25197e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 25297e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 25397e4ba6aSRichard Zhu } 25497e4ba6aSRichard Zhu } 25597e4ba6aSRichard Zhu 2566e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 2576e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 2586e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2596e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 2606e9fd28eSDong Aisheng else 2616e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 2620322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 263888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 264888824bbSDong Aisheng | SDHCI_USE_SDR50_TUNING; 2656e9fd28eSDong Aisheng } 2666e9fd28eSDong Aisheng } 2670322191eSDong Aisheng 2689d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 2690322191eSDong Aisheng val = 0; 2700322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 2710322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 2720322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 2730322191eSDong Aisheng } 2740322191eSDong Aisheng 27597e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 27660bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 27760bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 27897e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 27997e4ba6aSRichard Zhu } 280361b8482SLucas Stach 281361b8482SLucas Stach /* 282361b8482SLucas Stach * mask off the interrupt we get in response to the manually 283361b8482SLucas Stach * sent CMD12 284361b8482SLucas Stach */ 285361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 286361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 287361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 288361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 289361b8482SLucas Stach SDHCI_INT_STATUS); 290361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 291361b8482SLucas Stach } 29297e4ba6aSRichard Zhu } 29397e4ba6aSRichard Zhu 2947e29c306SWolfram Sang return val; 2957e29c306SWolfram Sang } 2967e29c306SWolfram Sang 2977e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 2987e29c306SWolfram Sang { 299e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 300e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 3010d58864bSTony Lin u32 data; 302e149860dSRichard Zhu 3030d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 3040d58864bSTony Lin if (val & SDHCI_INT_CARD_INT) { 3050d58864bSTony Lin /* 3060d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 3070d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 3080d58864bSTony Lin * so we need to apply the following workaround: clear 3090d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 3100d58864bSTony Lin * interrupt. In case a card interrupt was lost, 3110d58864bSTony Lin * re-sample it by the following steps. 3120d58864bSTony Lin */ 3130d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 31460bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 3150d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 31660bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 3170d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 3180d58864bSTony Lin } 3190d58864bSTony Lin } 3200d58864bSTony Lin 321f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 32258ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 32358ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 32458ac8177SRichard Zhu u32 v; 32560bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 32660bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 32760bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 328361b8482SLucas Stach 329361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 330361b8482SLucas Stach { 331361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 332361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 333361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 334361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 335361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 336361b8482SLucas Stach } 33758ac8177SRichard Zhu } 33858ac8177SRichard Zhu 33997e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 34097e4ba6aSRichard Zhu if (val & SDHCI_INT_ADMA_ERROR) { 34197e4ba6aSRichard Zhu val &= ~SDHCI_INT_ADMA_ERROR; 34260bf6396SShawn Guo val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 34397e4ba6aSRichard Zhu } 34497e4ba6aSRichard Zhu } 34597e4ba6aSRichard Zhu 3467e29c306SWolfram Sang writel(val, host->ioaddr + reg); 3477e29c306SWolfram Sang } 3487e29c306SWolfram Sang 34995f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 35095f25efeSWolfram Sang { 351ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 352ef4d0888SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 3530322191eSDong Aisheng u16 ret = 0; 3540322191eSDong Aisheng u32 val; 355ef4d0888SShawn Guo 35695a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 357ef4d0888SShawn Guo reg ^= 2; 3589d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 35995a2482aSShawn Guo /* 360ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 361ef4d0888SShawn Guo * Correct it here. 36295a2482aSShawn Guo */ 363ef4d0888SShawn Guo return SDHCI_SPEC_300; 364ef4d0888SShawn Guo } 36595a2482aSShawn Guo } 36695f25efeSWolfram Sang 3670322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 3680322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 3690322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 3700322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 3710322191eSDong Aisheng 3729d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 3736e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 3740322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 3756e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 3766e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 3776e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 3786e9fd28eSDong Aisheng } 3796e9fd28eSDong Aisheng 3800322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 3810322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 3820322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 3830322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 3840322191eSDong Aisheng 3850322191eSDong Aisheng ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK); 3860322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 3870322191eSDong Aisheng 3880322191eSDong Aisheng return ret; 3890322191eSDong Aisheng } 3900322191eSDong Aisheng 3917dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 3927dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 3937dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 3947dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 3957dd109efSDong Aisheng /* Swap AC23 bit */ 3967dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 3977dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 3987dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 3997dd109efSDong Aisheng } 4007dd109efSDong Aisheng } else { 4017dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 4027dd109efSDong Aisheng } 4037dd109efSDong Aisheng 4047dd109efSDong Aisheng return ret; 4057dd109efSDong Aisheng } 4067dd109efSDong Aisheng 40795f25efeSWolfram Sang return readw(host->ioaddr + reg); 40895f25efeSWolfram Sang } 40995f25efeSWolfram Sang 41095f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 41195f25efeSWolfram Sang { 41295f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 413e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 4140322191eSDong Aisheng u32 new_val = 0; 41595f25efeSWolfram Sang 41695f25efeSWolfram Sang switch (reg) { 4170322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 4180322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4190322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 4200322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4210322191eSDong Aisheng else 4220322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4230322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4240322191eSDong Aisheng return; 4250322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 4260322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4270322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 4280322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 4290322191eSDong Aisheng else 4300322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 4310322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4320322191eSDong Aisheng imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK; 4336e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 4340322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4350322191eSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) 4360322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4370322191eSDong Aisheng else 4380322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4390322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 4406e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 4416e9fd28eSDong Aisheng u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4426e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4438b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4448b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4456e9fd28eSDong Aisheng } else { 4468b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4476e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 4486e9fd28eSDong Aisheng } 4496e9fd28eSDong Aisheng 4508b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 4518b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 4528b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 4538b2bb0adSDong Aisheng } else { 4548b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 4558b2bb0adSDong Aisheng } 4566e9fd28eSDong Aisheng 4576e9fd28eSDong Aisheng writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 4586e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 4596e9fd28eSDong Aisheng } 4600322191eSDong Aisheng return; 46195f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 462f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 46358ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 46458ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 46558ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 46658ac8177SRichard Zhu u32 v; 46760bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 46860bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 46960bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 47058ac8177SRichard Zhu } 47169f54698SShawn Guo 4729d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 47369f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4742a15f981SShawn Guo /* Swap AC23 bit */ 4752a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 4762a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 4772a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 4782a15f981SShawn Guo } 4792a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 48069f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 48169f54698SShawn Guo } else { 48269f54698SShawn Guo /* 48369f54698SShawn Guo * Postpone this write, we must do it together with a 48469f54698SShawn Guo * command write that is down below. 48569f54698SShawn Guo */ 486e149860dSRichard Zhu imx_data->scratchpad = val; 48769f54698SShawn Guo } 48895f25efeSWolfram Sang return; 48995f25efeSWolfram Sang case SDHCI_COMMAND: 490361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 49158ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 49295a2482aSShawn Guo 493361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 494f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 495361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 496361b8482SLucas Stach 4979d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 49895a2482aSShawn Guo writel(val << 16, 49995a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 50069f54698SShawn Guo else 501e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 50295f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 50395f25efeSWolfram Sang return; 50495f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 50595f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 50695f25efeSWolfram Sang break; 50795f25efeSWolfram Sang } 50895f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 50995f25efeSWolfram Sang } 51095f25efeSWolfram Sang 51195f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 51295f25efeSWolfram Sang { 5139a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5149a0985b7SWilson Callan struct pltfm_imx_data *imx_data = pltfm_host->priv; 51595f25efeSWolfram Sang u32 new_val; 516af51079eSSascha Hauer u32 mask; 51795f25efeSWolfram Sang 51895f25efeSWolfram Sang switch (reg) { 51995f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 52095f25efeSWolfram Sang /* 52195f25efeSWolfram Sang * FSL put some DMA bits here 52295f25efeSWolfram Sang * If your board has a regulator, code should be here 52395f25efeSWolfram Sang */ 52495f25efeSWolfram Sang return; 52595f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 5266b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 527af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 5287122bbb0SMasanari Iida /* ensure the endianness */ 52995f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 5309a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 5319a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 53295f25efeSWolfram Sang /* DMA mode bits are shifted */ 53395f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 5349a0985b7SWilson Callan } 53595f25efeSWolfram Sang 536af51079eSSascha Hauer /* 537af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 538af51079eSSascha Hauer * esdhc_pltfm_bus_width. 539f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 540f6825748SMartin Fuzzey * SDIO interrupt errata workaround. 541af51079eSSascha Hauer */ 542f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 543af51079eSSascha Hauer 544af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 54595f25efeSWolfram Sang return; 54695f25efeSWolfram Sang } 54795f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 548913413c3SShawn Guo 549913413c3SShawn Guo /* 550913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 551913413c3SShawn Guo * that software reset should not affect card detection circuit. 552913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 553913413c3SShawn Guo * software reset. This will stop those clocks that card detection 554913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 555913413c3SShawn Guo * to keep card detection circuit functional. 556913413c3SShawn Guo */ 55758c8c4fbSShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 558913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 55958c8c4fbSShawn Guo /* 56058c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 56158c8c4fbSShawn Guo * Do it manually here. 56258c8c4fbSShawn Guo */ 563de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 564d131a71cSDong Aisheng /* the tuning bits should be kept during reset */ 565d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 566d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 567d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 568de5bdbffSDong Aisheng imx_data->is_ddr = 0; 569de5bdbffSDong Aisheng } 57058c8c4fbSShawn Guo } 57195f25efeSWolfram Sang } 57295f25efeSWolfram Sang 5730ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 5740ddf03c9SLucas Stach { 5750ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5760ddf03c9SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 5770ddf03c9SLucas Stach struct esdhc_platform_data *boarddata = &imx_data->boarddata; 5780ddf03c9SLucas Stach 5790ddf03c9SLucas Stach u32 f_host = clk_get_rate(pltfm_host->clk); 5800ddf03c9SLucas Stach 5810ddf03c9SLucas Stach if (boarddata->f_max && (boarddata->f_max < f_host)) 5820ddf03c9SLucas Stach return boarddata->f_max; 5830ddf03c9SLucas Stach else 5840ddf03c9SLucas Stach return f_host; 5850ddf03c9SLucas Stach } 5860ddf03c9SLucas Stach 58795f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 58895f25efeSWolfram Sang { 58995f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 59095f25efeSWolfram Sang 59195f25efeSWolfram Sang return clk_get_rate(pltfm_host->clk) / 256 / 16; 59295f25efeSWolfram Sang } 59395f25efeSWolfram Sang 5948ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 5958ba9580aSLucas Stach unsigned int clock) 5968ba9580aSLucas Stach { 5978ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 598fed2f6e2SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 599d31fc00aSDong Aisheng unsigned int host_clock = clk_get_rate(pltfm_host->clk); 600d31fc00aSDong Aisheng int pre_div = 2; 601d31fc00aSDong Aisheng int div = 1; 602fed2f6e2SDong Aisheng u32 temp, val; 6038ba9580aSLucas Stach 604fed2f6e2SDong Aisheng if (clock == 0) { 6059d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 606fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 607fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 608fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 609fed2f6e2SDong Aisheng } 610d31fc00aSDong Aisheng goto out; 611fed2f6e2SDong Aisheng } 612d31fc00aSDong Aisheng 613de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) 6145f7886c5SDong Aisheng pre_div = 1; 6155f7886c5SDong Aisheng 616d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 617d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 618d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 619d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 620d31fc00aSDong Aisheng 621d31fc00aSDong Aisheng while (host_clock / pre_div / 16 > clock && pre_div < 256) 622d31fc00aSDong Aisheng pre_div *= 2; 623d31fc00aSDong Aisheng 624d31fc00aSDong Aisheng while (host_clock / pre_div / div > clock && div < 16) 625d31fc00aSDong Aisheng div++; 626d31fc00aSDong Aisheng 627e76b8559SDong Aisheng host->mmc->actual_clock = host_clock / pre_div / div; 628d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 629e76b8559SDong Aisheng clock, host->mmc->actual_clock); 630d31fc00aSDong Aisheng 631de5bdbffSDong Aisheng if (imx_data->is_ddr) 632de5bdbffSDong Aisheng pre_div >>= 2; 633de5bdbffSDong Aisheng else 634d31fc00aSDong Aisheng pre_div >>= 1; 635d31fc00aSDong Aisheng div--; 636d31fc00aSDong Aisheng 637d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 638d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 639d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 640d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 641d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 642fed2f6e2SDong Aisheng 6439d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 644fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 645fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 646fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 647fed2f6e2SDong Aisheng } 648fed2f6e2SDong Aisheng 649d31fc00aSDong Aisheng mdelay(1); 650d31fc00aSDong Aisheng out: 651d31fc00aSDong Aisheng host->clock = clock; 6528ba9580aSLucas Stach } 6538ba9580aSLucas Stach 654913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 655913413c3SShawn Guo { 656842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 657842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 658842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 659913413c3SShawn Guo 660913413c3SShawn Guo switch (boarddata->wp_type) { 661913413c3SShawn Guo case ESDHC_WP_GPIO: 662fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 663913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 664913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 665913413c3SShawn Guo SDHCI_WRITE_PROTECT); 666913413c3SShawn Guo case ESDHC_WP_NONE: 667913413c3SShawn Guo break; 668913413c3SShawn Guo } 669913413c3SShawn Guo 670913413c3SShawn Guo return -ENOSYS; 671913413c3SShawn Guo } 672913413c3SShawn Guo 673af51079eSSascha Hauer static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) 674af51079eSSascha Hauer { 675af51079eSSascha Hauer u32 ctrl; 676af51079eSSascha Hauer 677af51079eSSascha Hauer switch (width) { 678af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 679af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 680af51079eSSascha Hauer break; 681af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 682af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 683af51079eSSascha Hauer break; 684af51079eSSascha Hauer default: 685af51079eSSascha Hauer ctrl = 0; 686af51079eSSascha Hauer break; 687af51079eSSascha Hauer } 688af51079eSSascha Hauer 689af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 690af51079eSSascha Hauer SDHCI_HOST_CONTROL); 691af51079eSSascha Hauer 692af51079eSSascha Hauer return 0; 693af51079eSSascha Hauer } 694af51079eSSascha Hauer 6950322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 6960322191eSDong Aisheng { 6970322191eSDong Aisheng u32 reg; 6980322191eSDong Aisheng 6990322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 7000322191eSDong Aisheng mdelay(1); 7010322191eSDong Aisheng 702ce090a4eSDong Aisheng pm_runtime_get_sync(host->mmc->parent); 7030322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7040322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 7050322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 7060322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7070322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 7080322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 7090322191eSDong Aisheng "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 7100322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 7110322191eSDong Aisheng } 7120322191eSDong Aisheng 7130322191eSDong Aisheng static void esdhc_request_done(struct mmc_request *mrq) 7140322191eSDong Aisheng { 7150322191eSDong Aisheng complete(&mrq->completion); 7160322191eSDong Aisheng } 7170322191eSDong Aisheng 7180322191eSDong Aisheng static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode) 7190322191eSDong Aisheng { 7200322191eSDong Aisheng struct mmc_command cmd = {0}; 7210322191eSDong Aisheng struct mmc_request mrq = {0}; 7220322191eSDong Aisheng struct mmc_data data = {0}; 7230322191eSDong Aisheng struct scatterlist sg; 7240322191eSDong Aisheng char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN]; 7250322191eSDong Aisheng 7260322191eSDong Aisheng cmd.opcode = opcode; 7270322191eSDong Aisheng cmd.arg = 0; 7280322191eSDong Aisheng cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 7290322191eSDong Aisheng 7300322191eSDong Aisheng data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN; 7310322191eSDong Aisheng data.blocks = 1; 7320322191eSDong Aisheng data.flags = MMC_DATA_READ; 7330322191eSDong Aisheng data.sg = &sg; 7340322191eSDong Aisheng data.sg_len = 1; 7350322191eSDong Aisheng 7360322191eSDong Aisheng sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern)); 7370322191eSDong Aisheng 7380322191eSDong Aisheng mrq.cmd = &cmd; 7390322191eSDong Aisheng mrq.cmd->mrq = &mrq; 7400322191eSDong Aisheng mrq.data = &data; 7410322191eSDong Aisheng mrq.data->mrq = &mrq; 7420322191eSDong Aisheng mrq.cmd->data = mrq.data; 7430322191eSDong Aisheng 7440322191eSDong Aisheng mrq.done = esdhc_request_done; 7450322191eSDong Aisheng init_completion(&(mrq.completion)); 7460322191eSDong Aisheng 7470322191eSDong Aisheng disable_irq(host->irq); 7480322191eSDong Aisheng spin_lock(&host->lock); 7490322191eSDong Aisheng host->mrq = &mrq; 7500322191eSDong Aisheng 7510322191eSDong Aisheng sdhci_send_command(host, mrq.cmd); 7520322191eSDong Aisheng 7530322191eSDong Aisheng spin_unlock(&host->lock); 7540322191eSDong Aisheng enable_irq(host->irq); 7550322191eSDong Aisheng 7560322191eSDong Aisheng wait_for_completion(&mrq.completion); 7570322191eSDong Aisheng 7580322191eSDong Aisheng if (cmd.error) 7590322191eSDong Aisheng return cmd.error; 7600322191eSDong Aisheng if (data.error) 7610322191eSDong Aisheng return data.error; 7620322191eSDong Aisheng 7630322191eSDong Aisheng return 0; 7640322191eSDong Aisheng } 7650322191eSDong Aisheng 7660322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 7670322191eSDong Aisheng { 7680322191eSDong Aisheng u32 reg; 7690322191eSDong Aisheng 7700322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7710322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 7720322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7730322191eSDong Aisheng } 7740322191eSDong Aisheng 7750322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 7760322191eSDong Aisheng { 7770322191eSDong Aisheng int min, max, avg, ret; 7780322191eSDong Aisheng 7790322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 7800322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 7810322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 7820322191eSDong Aisheng esdhc_prepare_tuning(host, min); 7830322191eSDong Aisheng if (!esdhc_send_tuning_cmd(host, opcode)) 7840322191eSDong Aisheng break; 7850322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 7860322191eSDong Aisheng } 7870322191eSDong Aisheng 7880322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 7890322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 7900322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 7910322191eSDong Aisheng esdhc_prepare_tuning(host, max); 7920322191eSDong Aisheng if (esdhc_send_tuning_cmd(host, opcode)) { 7930322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 7940322191eSDong Aisheng break; 7950322191eSDong Aisheng } 7960322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 7970322191eSDong Aisheng } 7980322191eSDong Aisheng 7990322191eSDong Aisheng /* use average delay to get the best timing */ 8000322191eSDong Aisheng avg = (min + max) / 2; 8010322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 8020322191eSDong Aisheng ret = esdhc_send_tuning_cmd(host, opcode); 8030322191eSDong Aisheng esdhc_post_tuning(host); 8040322191eSDong Aisheng 8050322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 8060322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 8070322191eSDong Aisheng 8080322191eSDong Aisheng return ret; 8090322191eSDong Aisheng } 8100322191eSDong Aisheng 811ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 812ad93220dSDong Aisheng unsigned int uhs) 813ad93220dSDong Aisheng { 814ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 815ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 816ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 817ad93220dSDong Aisheng 818ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 819ad93220dSDong Aisheng 820ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 821ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 822ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 823ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 824ad93220dSDong Aisheng return -EINVAL; 825ad93220dSDong Aisheng 826ad93220dSDong Aisheng switch (uhs) { 827ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 828ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 829ad93220dSDong Aisheng break; 830ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 831429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 832ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 833ad93220dSDong Aisheng break; 834ad93220dSDong Aisheng default: 835ad93220dSDong Aisheng /* back to default state for other legacy timing */ 836ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 837ad93220dSDong Aisheng } 838ad93220dSDong Aisheng 839ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 840ad93220dSDong Aisheng } 841ad93220dSDong Aisheng 842ad93220dSDong Aisheng static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) 843ad93220dSDong Aisheng { 844ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 845ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 846602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 847ad93220dSDong Aisheng 848ad93220dSDong Aisheng switch (uhs) { 849ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 850ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12; 851ad93220dSDong Aisheng break; 852ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 853ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25; 854ad93220dSDong Aisheng break; 855ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 856ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50; 857ad93220dSDong Aisheng break; 858ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 859429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 860ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104; 861ad93220dSDong Aisheng break; 862ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 863ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50; 864de5bdbffSDong Aisheng writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | 865de5bdbffSDong Aisheng ESDHC_MIX_CTRL_DDREN, 866de5bdbffSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 867de5bdbffSDong Aisheng imx_data->is_ddr = 1; 868602519b2SDong Aisheng if (boarddata->delay_line) { 869602519b2SDong Aisheng u32 v; 870602519b2SDong Aisheng v = boarddata->delay_line << 871602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 872602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 873602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 874602519b2SDong Aisheng v <<= 1; 875602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 876602519b2SDong Aisheng } 877ad93220dSDong Aisheng break; 878ad93220dSDong Aisheng } 879ad93220dSDong Aisheng 880ad93220dSDong Aisheng return esdhc_change_pinstate(host, uhs); 881ad93220dSDong Aisheng } 882ad93220dSDong Aisheng 8836e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 884e149860dSRichard Zhu .read_l = esdhc_readl_le, 8850c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 886e149860dSRichard Zhu .write_l = esdhc_writel_le, 8870c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 8880c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 8898ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 8900ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 8910c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 892913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 893af51079eSSascha Hauer .platform_bus_width = esdhc_pltfm_bus_width, 894ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 8950c6d49ceSWolfram Sang }; 8960c6d49ceSWolfram Sang 8971db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 89897e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 89997e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 90097e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 90185d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 90285d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 90385d6509dSShawn Guo }; 90485d6509dSShawn Guo 905abfafc2dSShawn Guo #ifdef CONFIG_OF 906c3be1efdSBill Pemberton static int 907abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 908abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 909abfafc2dSShawn Guo { 910abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 911abfafc2dSShawn Guo 912abfafc2dSShawn Guo if (!np) 913abfafc2dSShawn Guo return -ENODEV; 914abfafc2dSShawn Guo 9157f217794SArnd Bergmann if (of_get_property(np, "non-removable", NULL)) 916abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_PERMANENT; 917abfafc2dSShawn Guo 918abfafc2dSShawn Guo if (of_get_property(np, "fsl,cd-controller", NULL)) 919abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_CONTROLLER; 920abfafc2dSShawn Guo 921abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 922abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 923abfafc2dSShawn Guo 924abfafc2dSShawn Guo boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 925abfafc2dSShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 926abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_GPIO; 927abfafc2dSShawn Guo 928abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 929abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 930abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 931abfafc2dSShawn Guo 932af51079eSSascha Hauer of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); 933af51079eSSascha Hauer 9340ddf03c9SLucas Stach of_property_read_u32(np, "max-frequency", &boarddata->f_max); 9350ddf03c9SLucas Stach 936ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 937ad93220dSDong Aisheng boarddata->support_vsel = false; 938ad93220dSDong Aisheng else 939ad93220dSDong Aisheng boarddata->support_vsel = true; 940ad93220dSDong Aisheng 941602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 942602519b2SDong Aisheng boarddata->delay_line = 0; 943602519b2SDong Aisheng 944abfafc2dSShawn Guo return 0; 945abfafc2dSShawn Guo } 946abfafc2dSShawn Guo #else 947abfafc2dSShawn Guo static inline int 948abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 949abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 950abfafc2dSShawn Guo { 951abfafc2dSShawn Guo return -ENODEV; 952abfafc2dSShawn Guo } 953abfafc2dSShawn Guo #endif 954abfafc2dSShawn Guo 955c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 95695f25efeSWolfram Sang { 957abfafc2dSShawn Guo const struct of_device_id *of_id = 958abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 95985d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 96085d6509dSShawn Guo struct sdhci_host *host; 96185d6509dSShawn Guo struct esdhc_platform_data *boarddata; 9620c6d49ceSWolfram Sang int err; 963e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 96495f25efeSWolfram Sang 9650e748234SChristian Daudt host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); 96685d6509dSShawn Guo if (IS_ERR(host)) 96785d6509dSShawn Guo return PTR_ERR(host); 96885d6509dSShawn Guo 96985d6509dSShawn Guo pltfm_host = sdhci_priv(host); 97085d6509dSShawn Guo 971e3af31c6SShawn Guo imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 972abfafc2dSShawn Guo if (!imx_data) { 973abfafc2dSShawn Guo err = -ENOMEM; 974e3af31c6SShawn Guo goto free_sdhci; 975abfafc2dSShawn Guo } 97657ed3314SShawn Guo 977f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 9783770ee8fSShawn Guo pdev->id_entry->driver_data; 97985d6509dSShawn Guo pltfm_host->priv = imx_data; 98085d6509dSShawn Guo 98152dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 98252dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 98352dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 984e3af31c6SShawn Guo goto free_sdhci; 98595f25efeSWolfram Sang } 98652dac615SSascha Hauer 98752dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 98852dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 98952dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 990e3af31c6SShawn Guo goto free_sdhci; 99152dac615SSascha Hauer } 99252dac615SSascha Hauer 99352dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 99452dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 99552dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 996e3af31c6SShawn Guo goto free_sdhci; 99752dac615SSascha Hauer } 99852dac615SSascha Hauer 99952dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 100052dac615SSascha Hauer 100152dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 100252dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 100352dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 100495f25efeSWolfram Sang 1005ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1006e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1007e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 1008e3af31c6SShawn Guo goto disable_clk; 1009e62d8b8fSDong Aisheng } 1010e62d8b8fSDong Aisheng 1011ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 1012ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 1013ad93220dSDong Aisheng if (IS_ERR(imx_data->pins_default)) { 1014ad93220dSDong Aisheng err = PTR_ERR(imx_data->pins_default); 1015ad93220dSDong Aisheng dev_err(mmc_dev(host->mmc), "could not get default state\n"); 1016ad93220dSDong Aisheng goto disable_clk; 1017ad93220dSDong Aisheng } 1018ad93220dSDong Aisheng 101937865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 102037865fe9SEric Bénard 1021f47c4bbfSShawn Guo if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 10220c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 102397e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 102497e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 10250c6d49ceSWolfram Sang 1026f750ba9bSShawn Guo /* 1027f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 1028f750ba9bSShawn Guo * to something insane. Change it back here. 1029f750ba9bSShawn Guo */ 103069ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 103160bf6396SShawn Guo writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 103269ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1033e2997c94SDong Aisheng host->mmc->caps |= MMC_CAP_1_8V_DDR; 103469ed60e0SDong Aisheng } 1035f750ba9bSShawn Guo 10366e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 10376e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 10386e9fd28eSDong Aisheng esdhc_executing_tuning; 10398b2bb0adSDong Aisheng 10408b2bb0adSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 10418b2bb0adSDong Aisheng writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | 10428b2bb0adSDong Aisheng ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, 10438b2bb0adSDong Aisheng host->ioaddr + ESDHC_TUNING_CTRL); 10448b2bb0adSDong Aisheng 1045abfafc2dSShawn Guo boarddata = &imx_data->boarddata; 1046abfafc2dSShawn Guo if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { 1047842afc02SShawn Guo if (!host->mmc->parent->platform_data) { 1048913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "no board data!\n"); 1049913413c3SShawn Guo err = -EINVAL; 1050e3af31c6SShawn Guo goto disable_clk; 1051913413c3SShawn Guo } 1052842afc02SShawn Guo imx_data->boarddata = *((struct esdhc_platform_data *) 1053842afc02SShawn Guo host->mmc->parent->platform_data); 1054abfafc2dSShawn Guo } 1055913413c3SShawn Guo 1056913413c3SShawn Guo /* write_protect */ 1057913413c3SShawn Guo if (boarddata->wp_type == ESDHC_WP_GPIO) { 1058fbe5fdd1SShawn Guo err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 10590c6d49ceSWolfram Sang if (err) { 1060fbe5fdd1SShawn Guo dev_err(mmc_dev(host->mmc), 1061fbe5fdd1SShawn Guo "failed to request write-protect gpio!\n"); 1062fbe5fdd1SShawn Guo goto disable_clk; 1063913413c3SShawn Guo } 1064fbe5fdd1SShawn Guo host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 10650c6d49ceSWolfram Sang } 10667e29c306SWolfram Sang 1067913413c3SShawn Guo /* card_detect */ 1068913413c3SShawn Guo switch (boarddata->cd_type) { 1069913413c3SShawn Guo case ESDHC_CD_GPIO: 1070214fc309SLaurent Pinchart err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 10717e29c306SWolfram Sang if (err) { 1072913413c3SShawn Guo dev_err(mmc_dev(host->mmc), 1073fbe5fdd1SShawn Guo "failed to request card-detect gpio!\n"); 1074e3af31c6SShawn Guo goto disable_clk; 10757e29c306SWolfram Sang } 1076913413c3SShawn Guo /* fall through */ 10777e29c306SWolfram Sang 1078913413c3SShawn Guo case ESDHC_CD_CONTROLLER: 1079913413c3SShawn Guo /* we have a working card_detect back */ 10807e29c306SWolfram Sang host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1081913413c3SShawn Guo break; 1082913413c3SShawn Guo 1083913413c3SShawn Guo case ESDHC_CD_PERMANENT: 1084e526003bSDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 1085913413c3SShawn Guo break; 1086913413c3SShawn Guo 1087913413c3SShawn Guo case ESDHC_CD_NONE: 1088913413c3SShawn Guo break; 10897e29c306SWolfram Sang } 10907e29c306SWolfram Sang 1091af51079eSSascha Hauer switch (boarddata->max_bus_width) { 1092af51079eSSascha Hauer case 8: 1093af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 1094af51079eSSascha Hauer break; 1095af51079eSSascha Hauer case 4: 1096af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_4_BIT_DATA; 1097af51079eSSascha Hauer break; 1098af51079eSSascha Hauer case 1: 1099af51079eSSascha Hauer default: 1100af51079eSSascha Hauer host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 1101af51079eSSascha Hauer break; 1102af51079eSSascha Hauer } 1103af51079eSSascha Hauer 1104ad93220dSDong Aisheng /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 11059d61c009SShawn Guo if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) { 1106ad93220dSDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1107ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 1108ad93220dSDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1109ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 1110ad93220dSDong Aisheng if (IS_ERR(imx_data->pins_100mhz) || 1111ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) { 1112ad93220dSDong Aisheng dev_warn(mmc_dev(host->mmc), 1113ad93220dSDong Aisheng "could not get ultra high speed state, work on normal mode\n"); 1114ad93220dSDong Aisheng /* fall back to not support uhs by specify no 1.8v quirk */ 1115ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1116ad93220dSDong Aisheng } 1117ad93220dSDong Aisheng } else { 1118ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1119ad93220dSDong Aisheng } 1120ad93220dSDong Aisheng 112185d6509dSShawn Guo err = sdhci_add_host(host); 112285d6509dSShawn Guo if (err) 1123e3af31c6SShawn Guo goto disable_clk; 112485d6509dSShawn Guo 112589d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 112689d7e5c1SDong Aisheng pm_runtime_enable(&pdev->dev); 112789d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 112889d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 112989d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 113089d7e5c1SDong Aisheng 11317e29c306SWolfram Sang return 0; 11327e29c306SWolfram Sang 1133e3af31c6SShawn Guo disable_clk: 113452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 113552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 113652dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 1137e3af31c6SShawn Guo free_sdhci: 113885d6509dSShawn Guo sdhci_pltfm_free(pdev); 113985d6509dSShawn Guo return err; 114095f25efeSWolfram Sang } 114195f25efeSWolfram Sang 11426e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 114395f25efeSWolfram Sang { 114485d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 114595f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1146e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 114785d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 114885d6509dSShawn Guo 114985d6509dSShawn Guo sdhci_remove_host(host, dead); 11500c6d49ceSWolfram Sang 115189d7e5c1SDong Aisheng pm_runtime_dont_use_autosuspend(&pdev->dev); 115289d7e5c1SDong Aisheng pm_runtime_disable(&pdev->dev); 115389d7e5c1SDong Aisheng 115452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 115552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 115652dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 115752dac615SSascha Hauer 115885d6509dSShawn Guo sdhci_pltfm_free(pdev); 115985d6509dSShawn Guo 116085d6509dSShawn Guo return 0; 116195f25efeSWolfram Sang } 116295f25efeSWolfram Sang 116389d7e5c1SDong Aisheng #ifdef CONFIG_PM_RUNTIME 116489d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 116589d7e5c1SDong Aisheng { 116689d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 116789d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 116889d7e5c1SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 116989d7e5c1SDong Aisheng int ret; 117089d7e5c1SDong Aisheng 117189d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 117289d7e5c1SDong Aisheng 117389d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 117489d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 117589d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 117689d7e5c1SDong Aisheng 117789d7e5c1SDong Aisheng return ret; 117889d7e5c1SDong Aisheng } 117989d7e5c1SDong Aisheng 118089d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 118189d7e5c1SDong Aisheng { 118289d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 118389d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 118489d7e5c1SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 118589d7e5c1SDong Aisheng 118689d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_per); 118789d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ipg); 118889d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ahb); 118989d7e5c1SDong Aisheng 119089d7e5c1SDong Aisheng return sdhci_runtime_resume_host(host); 119189d7e5c1SDong Aisheng } 119289d7e5c1SDong Aisheng #endif 119389d7e5c1SDong Aisheng 119489d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 119589d7e5c1SDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) 119689d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 119789d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 119889d7e5c1SDong Aisheng }; 119989d7e5c1SDong Aisheng 120085d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 120185d6509dSShawn Guo .driver = { 120285d6509dSShawn Guo .name = "sdhci-esdhc-imx", 120385d6509dSShawn Guo .owner = THIS_MODULE, 1204abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 120589d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 120685d6509dSShawn Guo }, 120757ed3314SShawn Guo .id_table = imx_esdhc_devtype, 120885d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 12090433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 121095f25efeSWolfram Sang }; 121185d6509dSShawn Guo 1212d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 121385d6509dSShawn Guo 121485d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 121585d6509dSShawn Guo MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 121685d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1217