195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 795f25efeSWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3095f25efeSWolfram Sang #include "sdhci-pltfm.h" 3195f25efeSWolfram Sang #include "sdhci-esdhc.h" 3295f25efeSWolfram Sang 330d58864bSTony Lin #define SDHCI_CTRL_D3CD 0x08 3458ac8177SRichard Zhu /* VENDOR SPEC register */ 3558ac8177SRichard Zhu #define SDHCI_VENDOR_SPEC 0xC0 3658ac8177SRichard Zhu #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002 37f750ba9bSShawn Guo #define SDHCI_WTMK_LVL 0x44 3895a2482aSShawn Guo #define SDHCI_MIX_CTRL 0x48 3958ac8177SRichard Zhu 4058ac8177SRichard Zhu /* 4197e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 4297e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 4397e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 4497e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 4597e4ba6aSRichard Zhu */ 4697e4ba6aSRichard Zhu #define SDHCI_INT_VENDOR_SPEC_DMA_ERR 0x10000000 4797e4ba6aSRichard Zhu 4897e4ba6aSRichard Zhu /* 4958ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 5058ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 5158ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 5258ac8177SRichard Zhu * be generated. 5358ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 5458ac8177SRichard Zhu * operations automatically as required at the end of the 5558ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 5658ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 5758ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 5858ac8177SRichard Zhu */ 5958ac8177SRichard Zhu #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1) 60e149860dSRichard Zhu 6157ed3314SShawn Guo enum imx_esdhc_type { 6257ed3314SShawn Guo IMX25_ESDHC, 6357ed3314SShawn Guo IMX35_ESDHC, 6457ed3314SShawn Guo IMX51_ESDHC, 6557ed3314SShawn Guo IMX53_ESDHC, 6695a2482aSShawn Guo IMX6Q_USDHC, 6757ed3314SShawn Guo }; 6857ed3314SShawn Guo 69e149860dSRichard Zhu struct pltfm_imx_data { 70e149860dSRichard Zhu int flags; 71e149860dSRichard Zhu u32 scratchpad; 7257ed3314SShawn Guo enum imx_esdhc_type devtype; 73e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 74842afc02SShawn Guo struct esdhc_platform_data boarddata; 7552dac615SSascha Hauer struct clk *clk_ipg; 7652dac615SSascha Hauer struct clk *clk_ahb; 7752dac615SSascha Hauer struct clk *clk_per; 78e149860dSRichard Zhu }; 79e149860dSRichard Zhu 8057ed3314SShawn Guo static struct platform_device_id imx_esdhc_devtype[] = { 8157ed3314SShawn Guo { 8257ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 8357ed3314SShawn Guo .driver_data = IMX25_ESDHC, 8457ed3314SShawn Guo }, { 8557ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 8657ed3314SShawn Guo .driver_data = IMX35_ESDHC, 8757ed3314SShawn Guo }, { 8857ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 8957ed3314SShawn Guo .driver_data = IMX51_ESDHC, 9057ed3314SShawn Guo }, { 9157ed3314SShawn Guo .name = "sdhci-esdhc-imx53", 9257ed3314SShawn Guo .driver_data = IMX53_ESDHC, 9357ed3314SShawn Guo }, { 9495a2482aSShawn Guo .name = "sdhci-usdhc-imx6q", 9595a2482aSShawn Guo .driver_data = IMX6Q_USDHC, 9695a2482aSShawn Guo }, { 9757ed3314SShawn Guo /* sentinel */ 9857ed3314SShawn Guo } 9957ed3314SShawn Guo }; 10057ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 10157ed3314SShawn Guo 102abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 103abfafc2dSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], }, 104abfafc2dSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], }, 105abfafc2dSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], }, 106abfafc2dSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], }, 10795a2482aSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], }, 108abfafc2dSShawn Guo { /* sentinel */ } 109abfafc2dSShawn Guo }; 110abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 111abfafc2dSShawn Guo 11257ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 11357ed3314SShawn Guo { 11457ed3314SShawn Guo return data->devtype == IMX25_ESDHC; 11557ed3314SShawn Guo } 11657ed3314SShawn Guo 11757ed3314SShawn Guo static inline int is_imx35_esdhc(struct pltfm_imx_data *data) 11857ed3314SShawn Guo { 11957ed3314SShawn Guo return data->devtype == IMX35_ESDHC; 12057ed3314SShawn Guo } 12157ed3314SShawn Guo 12257ed3314SShawn Guo static inline int is_imx51_esdhc(struct pltfm_imx_data *data) 12357ed3314SShawn Guo { 12457ed3314SShawn Guo return data->devtype == IMX51_ESDHC; 12557ed3314SShawn Guo } 12657ed3314SShawn Guo 12757ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 12857ed3314SShawn Guo { 12957ed3314SShawn Guo return data->devtype == IMX53_ESDHC; 13057ed3314SShawn Guo } 13157ed3314SShawn Guo 13295a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 13395a2482aSShawn Guo { 13495a2482aSShawn Guo return data->devtype == IMX6Q_USDHC; 13595a2482aSShawn Guo } 13695a2482aSShawn Guo 13795f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 13895f25efeSWolfram Sang { 13995f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 14095f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 14195f25efeSWolfram Sang 14295f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 14395f25efeSWolfram Sang } 14495f25efeSWolfram Sang 1457e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 1467e29c306SWolfram Sang { 147842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 148842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 149842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1507e29c306SWolfram Sang 151913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 152913413c3SShawn Guo 15397e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 15497e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 15597e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 15697e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 15797e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 15897e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 15997e4ba6aSRichard Zhu */ 16097e4ba6aSRichard Zhu 16197e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 16297e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 16397e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 16497e4ba6aSRichard Zhu } 16597e4ba6aSRichard Zhu } 16697e4ba6aSRichard Zhu 16797e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 16897e4ba6aSRichard Zhu if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) { 16997e4ba6aSRichard Zhu val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR; 17097e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 17197e4ba6aSRichard Zhu } 17297e4ba6aSRichard Zhu } 17397e4ba6aSRichard Zhu 1747e29c306SWolfram Sang return val; 1757e29c306SWolfram Sang } 1767e29c306SWolfram Sang 1777e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 1787e29c306SWolfram Sang { 179e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 180e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 181842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1820d58864bSTony Lin u32 data; 183e149860dSRichard Zhu 1840d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 1850d58864bSTony Lin if (val & SDHCI_INT_CARD_INT) { 1860d58864bSTony Lin /* 1870d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 1880d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 1890d58864bSTony Lin * so we need to apply the following workaround: clear 1900d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 1910d58864bSTony Lin * interrupt. In case a card interrupt was lost, 1920d58864bSTony Lin * re-sample it by the following steps. 1930d58864bSTony Lin */ 1940d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 1950d58864bSTony Lin data &= ~SDHCI_CTRL_D3CD; 1960d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 1970d58864bSTony Lin data |= SDHCI_CTRL_D3CD; 1980d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 1990d58864bSTony Lin } 2000d58864bSTony Lin } 2010d58864bSTony Lin 20258ac8177SRichard Zhu if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 20358ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 20458ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 20558ac8177SRichard Zhu u32 v; 20658ac8177SRichard Zhu v = readl(host->ioaddr + SDHCI_VENDOR_SPEC); 20758ac8177SRichard Zhu v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK; 20858ac8177SRichard Zhu writel(v, host->ioaddr + SDHCI_VENDOR_SPEC); 20958ac8177SRichard Zhu } 21058ac8177SRichard Zhu 21197e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 21297e4ba6aSRichard Zhu if (val & SDHCI_INT_ADMA_ERROR) { 21397e4ba6aSRichard Zhu val &= ~SDHCI_INT_ADMA_ERROR; 21497e4ba6aSRichard Zhu val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR; 21597e4ba6aSRichard Zhu } 21697e4ba6aSRichard Zhu } 21797e4ba6aSRichard Zhu 2187e29c306SWolfram Sang writel(val, host->ioaddr + reg); 2197e29c306SWolfram Sang } 2207e29c306SWolfram Sang 22195f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 22295f25efeSWolfram Sang { 223ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 224ef4d0888SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 225ef4d0888SShawn Guo 22695a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 227ef4d0888SShawn Guo reg ^= 2; 228ef4d0888SShawn Guo if (is_imx6q_usdhc(imx_data)) { 22995a2482aSShawn Guo /* 230ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 231ef4d0888SShawn Guo * Correct it here. 23295a2482aSShawn Guo */ 233ef4d0888SShawn Guo return SDHCI_SPEC_300; 234ef4d0888SShawn Guo } 23595a2482aSShawn Guo } 23695f25efeSWolfram Sang 23795f25efeSWolfram Sang return readw(host->ioaddr + reg); 23895f25efeSWolfram Sang } 23995f25efeSWolfram Sang 24095f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 24195f25efeSWolfram Sang { 24295f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 243e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 24495f25efeSWolfram Sang 24595f25efeSWolfram Sang switch (reg) { 24695f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 24795f25efeSWolfram Sang /* 24895f25efeSWolfram Sang * Postpone this write, we must do it together with a 24995f25efeSWolfram Sang * command write that is down below. 25095f25efeSWolfram Sang */ 25158ac8177SRichard Zhu if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 25258ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 25358ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 25458ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 25558ac8177SRichard Zhu u32 v; 25658ac8177SRichard Zhu v = readl(host->ioaddr + SDHCI_VENDOR_SPEC); 25758ac8177SRichard Zhu v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK; 25858ac8177SRichard Zhu writel(v, host->ioaddr + SDHCI_VENDOR_SPEC); 25958ac8177SRichard Zhu } 260e149860dSRichard Zhu imx_data->scratchpad = val; 26195f25efeSWolfram Sang return; 26295f25efeSWolfram Sang case SDHCI_COMMAND: 2635b6b0ad6SSascha Hauer if ((host->cmd->opcode == MMC_STOP_TRANSMISSION || 2645b6b0ad6SSascha Hauer host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 2655b6b0ad6SSascha Hauer (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 26658ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 26795a2482aSShawn Guo 26895a2482aSShawn Guo if (is_imx6q_usdhc(imx_data)) { 26995a2482aSShawn Guo u32 m = readl(host->ioaddr + SDHCI_MIX_CTRL); 27095a2482aSShawn Guo m = imx_data->scratchpad | (m & 0xffff0000); 27195a2482aSShawn Guo writel(m, host->ioaddr + SDHCI_MIX_CTRL); 27295a2482aSShawn Guo writel(val << 16, 27395a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 27495a2482aSShawn Guo } else { 275e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 27695f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 27795a2482aSShawn Guo } 27895f25efeSWolfram Sang return; 27995f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 28095f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 28195f25efeSWolfram Sang break; 28295f25efeSWolfram Sang } 28395f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 28495f25efeSWolfram Sang } 28595f25efeSWolfram Sang 28695f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 28795f25efeSWolfram Sang { 2889a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2899a0985b7SWilson Callan struct pltfm_imx_data *imx_data = pltfm_host->priv; 29095f25efeSWolfram Sang u32 new_val; 29195f25efeSWolfram Sang 29295f25efeSWolfram Sang switch (reg) { 29395f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 29495f25efeSWolfram Sang /* 29595f25efeSWolfram Sang * FSL put some DMA bits here 29695f25efeSWolfram Sang * If your board has a regulator, code should be here 29795f25efeSWolfram Sang */ 29895f25efeSWolfram Sang return; 29995f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 3006b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 3016b40d182SShawn Guo new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS); 3027122bbb0SMasanari Iida /* ensure the endianness */ 30395f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 3049a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 3059a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 30695f25efeSWolfram Sang /* DMA mode bits are shifted */ 30795f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 3089a0985b7SWilson Callan } 30995f25efeSWolfram Sang 31095f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, new_val, reg); 31195f25efeSWolfram Sang return; 31295f25efeSWolfram Sang } 31395f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 314913413c3SShawn Guo 315913413c3SShawn Guo /* 316913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 317913413c3SShawn Guo * that software reset should not affect card detection circuit. 318913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 319913413c3SShawn Guo * software reset. This will stop those clocks that card detection 320913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 321913413c3SShawn Guo * to keep card detection circuit functional. 322913413c3SShawn Guo */ 323913413c3SShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) 324913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 32595f25efeSWolfram Sang } 32695f25efeSWolfram Sang 32795f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 32895f25efeSWolfram Sang { 32995f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 33095f25efeSWolfram Sang 33195f25efeSWolfram Sang return clk_get_rate(pltfm_host->clk); 33295f25efeSWolfram Sang } 33395f25efeSWolfram Sang 33495f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 33595f25efeSWolfram Sang { 33695f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 33795f25efeSWolfram Sang 33895f25efeSWolfram Sang return clk_get_rate(pltfm_host->clk) / 256 / 16; 33995f25efeSWolfram Sang } 34095f25efeSWolfram Sang 341913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 342913413c3SShawn Guo { 343842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 344842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 345842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 346913413c3SShawn Guo 347913413c3SShawn Guo switch (boarddata->wp_type) { 348913413c3SShawn Guo case ESDHC_WP_GPIO: 349fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 350913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 351913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 352913413c3SShawn Guo SDHCI_WRITE_PROTECT); 353913413c3SShawn Guo case ESDHC_WP_NONE: 354913413c3SShawn Guo break; 355913413c3SShawn Guo } 356913413c3SShawn Guo 357913413c3SShawn Guo return -ENOSYS; 358913413c3SShawn Guo } 359913413c3SShawn Guo 3600c6d49ceSWolfram Sang static struct sdhci_ops sdhci_esdhc_ops = { 361e149860dSRichard Zhu .read_l = esdhc_readl_le, 3620c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 363e149860dSRichard Zhu .write_l = esdhc_writel_le, 3640c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 3650c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 3660c6d49ceSWolfram Sang .set_clock = esdhc_set_clock, 3670c6d49ceSWolfram Sang .get_max_clock = esdhc_pltfm_get_max_clock, 3680c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 369913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 3700c6d49ceSWolfram Sang }; 3710c6d49ceSWolfram Sang 37285d6509dSShawn Guo static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 37397e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 37497e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 37597e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 37685d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 37785d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 37885d6509dSShawn Guo }; 37985d6509dSShawn Guo 380abfafc2dSShawn Guo #ifdef CONFIG_OF 381c3be1efdSBill Pemberton static int 382abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 383abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 384abfafc2dSShawn Guo { 385abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 386abfafc2dSShawn Guo 387abfafc2dSShawn Guo if (!np) 388abfafc2dSShawn Guo return -ENODEV; 389abfafc2dSShawn Guo 3907f217794SArnd Bergmann if (of_get_property(np, "non-removable", NULL)) 391abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_PERMANENT; 392abfafc2dSShawn Guo 393abfafc2dSShawn Guo if (of_get_property(np, "fsl,cd-controller", NULL)) 394abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_CONTROLLER; 395abfafc2dSShawn Guo 396abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 397abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 398abfafc2dSShawn Guo 399abfafc2dSShawn Guo boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 400abfafc2dSShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 401abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_GPIO; 402abfafc2dSShawn Guo 403abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 404abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 405abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 406abfafc2dSShawn Guo 407abfafc2dSShawn Guo return 0; 408abfafc2dSShawn Guo } 409abfafc2dSShawn Guo #else 410abfafc2dSShawn Guo static inline int 411abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 412abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 413abfafc2dSShawn Guo { 414abfafc2dSShawn Guo return -ENODEV; 415abfafc2dSShawn Guo } 416abfafc2dSShawn Guo #endif 417abfafc2dSShawn Guo 418c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 41995f25efeSWolfram Sang { 420abfafc2dSShawn Guo const struct of_device_id *of_id = 421abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 42285d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 42385d6509dSShawn Guo struct sdhci_host *host; 42485d6509dSShawn Guo struct esdhc_platform_data *boarddata; 4250c6d49ceSWolfram Sang int err; 426e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 42795f25efeSWolfram Sang 42885d6509dSShawn Guo host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata); 42985d6509dSShawn Guo if (IS_ERR(host)) 43085d6509dSShawn Guo return PTR_ERR(host); 43185d6509dSShawn Guo 43285d6509dSShawn Guo pltfm_host = sdhci_priv(host); 43385d6509dSShawn Guo 434e3af31c6SShawn Guo imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 435abfafc2dSShawn Guo if (!imx_data) { 436abfafc2dSShawn Guo err = -ENOMEM; 437e3af31c6SShawn Guo goto free_sdhci; 438abfafc2dSShawn Guo } 43957ed3314SShawn Guo 440abfafc2dSShawn Guo if (of_id) 441abfafc2dSShawn Guo pdev->id_entry = of_id->data; 44257ed3314SShawn Guo imx_data->devtype = pdev->id_entry->driver_data; 44385d6509dSShawn Guo pltfm_host->priv = imx_data; 44485d6509dSShawn Guo 44552dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 44652dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 44752dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 448e3af31c6SShawn Guo goto free_sdhci; 44995f25efeSWolfram Sang } 45052dac615SSascha Hauer 45152dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 45252dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 45352dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 454e3af31c6SShawn Guo goto free_sdhci; 45552dac615SSascha Hauer } 45652dac615SSascha Hauer 45752dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 45852dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 45952dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 460e3af31c6SShawn Guo goto free_sdhci; 46152dac615SSascha Hauer } 46252dac615SSascha Hauer 46352dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 46452dac615SSascha Hauer 46552dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 46652dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 46752dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 46895f25efeSWolfram Sang 469e62d8b8fSDong Aisheng imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 470e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 471e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 472e3af31c6SShawn Guo goto disable_clk; 473e62d8b8fSDong Aisheng } 474e62d8b8fSDong Aisheng 47537865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 47637865fe9SEric Bénard 47757ed3314SShawn Guo if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) 4780c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 47997e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 48097e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 4810c6d49ceSWolfram Sang 48257ed3314SShawn Guo if (is_imx53_esdhc(imx_data)) 48358ac8177SRichard Zhu imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT; 48458ac8177SRichard Zhu 485f750ba9bSShawn Guo /* 486f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 487f750ba9bSShawn Guo * to something insane. Change it back here. 488f750ba9bSShawn Guo */ 489f750ba9bSShawn Guo if (is_imx6q_usdhc(imx_data)) 490f750ba9bSShawn Guo writel(0x08100810, host->ioaddr + SDHCI_WTMK_LVL); 491f750ba9bSShawn Guo 492abfafc2dSShawn Guo boarddata = &imx_data->boarddata; 493abfafc2dSShawn Guo if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { 494842afc02SShawn Guo if (!host->mmc->parent->platform_data) { 495913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "no board data!\n"); 496913413c3SShawn Guo err = -EINVAL; 497e3af31c6SShawn Guo goto disable_clk; 498913413c3SShawn Guo } 499842afc02SShawn Guo imx_data->boarddata = *((struct esdhc_platform_data *) 500842afc02SShawn Guo host->mmc->parent->platform_data); 501abfafc2dSShawn Guo } 502913413c3SShawn Guo 503913413c3SShawn Guo /* write_protect */ 504913413c3SShawn Guo if (boarddata->wp_type == ESDHC_WP_GPIO) { 505fbe5fdd1SShawn Guo err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 5060c6d49ceSWolfram Sang if (err) { 507fbe5fdd1SShawn Guo dev_err(mmc_dev(host->mmc), 508fbe5fdd1SShawn Guo "failed to request write-protect gpio!\n"); 509fbe5fdd1SShawn Guo goto disable_clk; 510913413c3SShawn Guo } 511fbe5fdd1SShawn Guo host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 5120c6d49ceSWolfram Sang } 5137e29c306SWolfram Sang 514913413c3SShawn Guo /* card_detect */ 515913413c3SShawn Guo switch (boarddata->cd_type) { 516913413c3SShawn Guo case ESDHC_CD_GPIO: 517fbe5fdd1SShawn Guo err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio); 5187e29c306SWolfram Sang if (err) { 519913413c3SShawn Guo dev_err(mmc_dev(host->mmc), 520fbe5fdd1SShawn Guo "failed to request card-detect gpio!\n"); 521e3af31c6SShawn Guo goto disable_clk; 5227e29c306SWolfram Sang } 523913413c3SShawn Guo /* fall through */ 5247e29c306SWolfram Sang 525913413c3SShawn Guo case ESDHC_CD_CONTROLLER: 526913413c3SShawn Guo /* we have a working card_detect back */ 5277e29c306SWolfram Sang host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 528913413c3SShawn Guo break; 529913413c3SShawn Guo 530913413c3SShawn Guo case ESDHC_CD_PERMANENT: 531913413c3SShawn Guo host->mmc->caps = MMC_CAP_NONREMOVABLE; 532913413c3SShawn Guo break; 533913413c3SShawn Guo 534913413c3SShawn Guo case ESDHC_CD_NONE: 535913413c3SShawn Guo break; 5367e29c306SWolfram Sang } 5377e29c306SWolfram Sang 53885d6509dSShawn Guo err = sdhci_add_host(host); 53985d6509dSShawn Guo if (err) 540e3af31c6SShawn Guo goto disable_clk; 54185d6509dSShawn Guo 5427e29c306SWolfram Sang return 0; 5437e29c306SWolfram Sang 544e3af31c6SShawn Guo disable_clk: 54552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 54652dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 54752dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 548e3af31c6SShawn Guo free_sdhci: 54985d6509dSShawn Guo sdhci_pltfm_free(pdev); 55085d6509dSShawn Guo return err; 55195f25efeSWolfram Sang } 55295f25efeSWolfram Sang 5536e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 55495f25efeSWolfram Sang { 55585d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 55695f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 557e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 55885d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 55985d6509dSShawn Guo 56085d6509dSShawn Guo sdhci_remove_host(host, dead); 5610c6d49ceSWolfram Sang 56252dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 56352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 56452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 56552dac615SSascha Hauer 56685d6509dSShawn Guo sdhci_pltfm_free(pdev); 56785d6509dSShawn Guo 56885d6509dSShawn Guo return 0; 56995f25efeSWolfram Sang } 57095f25efeSWolfram Sang 57185d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 57285d6509dSShawn Guo .driver = { 57385d6509dSShawn Guo .name = "sdhci-esdhc-imx", 57485d6509dSShawn Guo .owner = THIS_MODULE, 575abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 57629495aa0SManuel Lauss .pm = SDHCI_PLTFM_PMOPS, 57785d6509dSShawn Guo }, 57857ed3314SShawn Guo .id_table = imx_esdhc_devtype, 57985d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 5800433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 58195f25efeSWolfram Sang }; 58285d6509dSShawn Guo 583d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 58485d6509dSShawn Guo 58585d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 58685d6509dSShawn Guo MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 58785d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 588