195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 795f25efeSWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3095f25efeSWolfram Sang #include "sdhci-pltfm.h" 3195f25efeSWolfram Sang #include "sdhci-esdhc.h" 3295f25efeSWolfram Sang 3360bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 3458ac8177SRichard Zhu /* VENDOR SPEC register */ 3560bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 370322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 38fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 3960bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 4060bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 41de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 422a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 430322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 440322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 450322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 462a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 472a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 4858ac8177SRichard Zhu 49602519b2SDong Aisheng /* dll control register */ 50602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 51602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 52602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 53602519b2SDong Aisheng 540322191eSDong Aisheng /* tune control register */ 550322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 560322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 570322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 580322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 590322191eSDong Aisheng 606e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 616e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 626e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 636e9fd28eSDong Aisheng #define ESDHC_TUNING_START_TAP 0x1 646e9fd28eSDong Aisheng 650322191eSDong Aisheng #define ESDHC_TUNING_BLOCK_PATTERN_LEN 64 660322191eSDong Aisheng 67ad93220dSDong Aisheng /* pinctrl state */ 68ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 69ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 70ad93220dSDong Aisheng 7158ac8177SRichard Zhu /* 72af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 73af51079eSSascha Hauer */ 74af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 75af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 76af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 77af51079eSSascha Hauer 78af51079eSSascha Hauer /* 7997e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 8097e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 8197e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 8297e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 8397e4ba6aSRichard Zhu */ 8460bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 8597e4ba6aSRichard Zhu 8697e4ba6aSRichard Zhu /* 8758ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 8858ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 8958ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 9058ac8177SRichard Zhu * be generated. 9158ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 9258ac8177SRichard Zhu * operations automatically as required at the end of the 9358ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 9458ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 9558ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 9658ac8177SRichard Zhu */ 9731fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 9831fbb301SShawn Guo /* 9931fbb301SShawn Guo * The flag enables the workaround for ESDHC errata ENGcm07207 which 10031fbb301SShawn Guo * affects i.MX25 and i.MX35. 10131fbb301SShawn Guo */ 10231fbb301SShawn Guo #define ESDHC_FLAG_ENGCM07207 BIT(2) 1039d61c009SShawn Guo /* 1049d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1059d61c009SShawn Guo * integrated on the i.MX6 series. 1069d61c009SShawn Guo */ 1079d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1086e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1096e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1106e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1116e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1126e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1136e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 114e149860dSRichard Zhu 115f47c4bbfSShawn Guo struct esdhc_soc_data { 116f47c4bbfSShawn Guo u32 flags; 117f47c4bbfSShawn Guo }; 118f47c4bbfSShawn Guo 119f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx25_data = { 120f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 121f47c4bbfSShawn Guo }; 122f47c4bbfSShawn Guo 123f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx35_data = { 124f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 125f47c4bbfSShawn Guo }; 126f47c4bbfSShawn Guo 127f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx51_data = { 128f47c4bbfSShawn Guo .flags = 0, 129f47c4bbfSShawn Guo }; 130f47c4bbfSShawn Guo 131f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx53_data = { 132f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 133f47c4bbfSShawn Guo }; 134f47c4bbfSShawn Guo 135f47c4bbfSShawn Guo static struct esdhc_soc_data usdhc_imx6q_data = { 1366e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1376e9fd28eSDong Aisheng }; 1386e9fd28eSDong Aisheng 1396e9fd28eSDong Aisheng static struct esdhc_soc_data usdhc_imx6sl_data = { 1406e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1416e9fd28eSDong Aisheng | ESDHC_FLAG_HAVE_CAP1, 14257ed3314SShawn Guo }; 14357ed3314SShawn Guo 144e149860dSRichard Zhu struct pltfm_imx_data { 145e149860dSRichard Zhu u32 scratchpad; 146e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 147ad93220dSDong Aisheng struct pinctrl_state *pins_default; 148ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 149ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 150f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 151842afc02SShawn Guo struct esdhc_platform_data boarddata; 15252dac615SSascha Hauer struct clk *clk_ipg; 15352dac615SSascha Hauer struct clk *clk_ahb; 15452dac615SSascha Hauer struct clk *clk_per; 155361b8482SLucas Stach enum { 156361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending*/ 157361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 158361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 159361b8482SLucas Stach } multiblock_status; 1600322191eSDong Aisheng u32 uhs_mode; 161de5bdbffSDong Aisheng u32 is_ddr; 162e149860dSRichard Zhu }; 163e149860dSRichard Zhu 16457ed3314SShawn Guo static struct platform_device_id imx_esdhc_devtype[] = { 16557ed3314SShawn Guo { 16657ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 167f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 16857ed3314SShawn Guo }, { 16957ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 170f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 17157ed3314SShawn Guo }, { 17257ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 173f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 17457ed3314SShawn Guo }, { 17557ed3314SShawn Guo /* sentinel */ 17657ed3314SShawn Guo } 17757ed3314SShawn Guo }; 17857ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 17957ed3314SShawn Guo 180abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 181f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 182f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 183f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 184f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 1856e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 186f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 187abfafc2dSShawn Guo { /* sentinel */ } 188abfafc2dSShawn Guo }; 189abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 190abfafc2dSShawn Guo 19157ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 19257ed3314SShawn Guo { 193f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 19457ed3314SShawn Guo } 19557ed3314SShawn Guo 19657ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 19757ed3314SShawn Guo { 198f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 19957ed3314SShawn Guo } 20057ed3314SShawn Guo 20195a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 20295a2482aSShawn Guo { 203f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 20495a2482aSShawn Guo } 20595a2482aSShawn Guo 2069d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2079d61c009SShawn Guo { 208f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2099d61c009SShawn Guo } 2109d61c009SShawn Guo 21195f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 21295f25efeSWolfram Sang { 21395f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 21495f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 21595f25efeSWolfram Sang 21695f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 21795f25efeSWolfram Sang } 21895f25efeSWolfram Sang 2197e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 2207e29c306SWolfram Sang { 221361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 222361b8482SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 223913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 224913413c3SShawn Guo 2250322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 2260322191eSDong Aisheng u32 fsl_prss = val; 2270322191eSDong Aisheng /* save the least 20 bits */ 2280322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 2290322191eSDong Aisheng /* move dat[0-3] bits */ 2300322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 2310322191eSDong Aisheng /* move cmd line bit */ 2320322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 2330322191eSDong Aisheng } 2340322191eSDong Aisheng 23597e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 2366b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 2376b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2386b4fb671SDong Aisheng val &= 0xffff0000; 2396b4fb671SDong Aisheng 24097e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 24197e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 24297e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 24397e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 24497e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 24597e4ba6aSRichard Zhu */ 24697e4ba6aSRichard Zhu 24797e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 24897e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 24997e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 25097e4ba6aSRichard Zhu } 25197e4ba6aSRichard Zhu } 25297e4ba6aSRichard Zhu 2536e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 2546e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 2556e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2566e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 2576e9fd28eSDong Aisheng else 2586e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 2590322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 260888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 261888824bbSDong Aisheng | SDHCI_USE_SDR50_TUNING; 2626e9fd28eSDong Aisheng } 2636e9fd28eSDong Aisheng } 2640322191eSDong Aisheng 2659d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 2660322191eSDong Aisheng val = 0; 2670322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 2680322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 2690322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 2700322191eSDong Aisheng } 2710322191eSDong Aisheng 27297e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 27360bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 27460bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 27597e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 27697e4ba6aSRichard Zhu } 277361b8482SLucas Stach 278361b8482SLucas Stach /* 279361b8482SLucas Stach * mask off the interrupt we get in response to the manually 280361b8482SLucas Stach * sent CMD12 281361b8482SLucas Stach */ 282361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 283361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 284361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 285361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 286361b8482SLucas Stach SDHCI_INT_STATUS); 287361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 288361b8482SLucas Stach } 28997e4ba6aSRichard Zhu } 29097e4ba6aSRichard Zhu 2917e29c306SWolfram Sang return val; 2927e29c306SWolfram Sang } 2937e29c306SWolfram Sang 2947e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 2957e29c306SWolfram Sang { 296e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 297e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 2980d58864bSTony Lin u32 data; 299e149860dSRichard Zhu 3000d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 3010d58864bSTony Lin if (val & SDHCI_INT_CARD_INT) { 3020d58864bSTony Lin /* 3030d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 3040d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 3050d58864bSTony Lin * so we need to apply the following workaround: clear 3060d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 3070d58864bSTony Lin * interrupt. In case a card interrupt was lost, 3080d58864bSTony Lin * re-sample it by the following steps. 3090d58864bSTony Lin */ 3100d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 31160bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 3120d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 31360bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 3140d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 3150d58864bSTony Lin } 3160d58864bSTony Lin } 3170d58864bSTony Lin 318f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 31958ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 32058ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 32158ac8177SRichard Zhu u32 v; 32260bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 32360bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 32460bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 325361b8482SLucas Stach 326361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 327361b8482SLucas Stach { 328361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 329361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 330361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 331361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 332361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 333361b8482SLucas Stach } 33458ac8177SRichard Zhu } 33558ac8177SRichard Zhu 33697e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 33797e4ba6aSRichard Zhu if (val & SDHCI_INT_ADMA_ERROR) { 33897e4ba6aSRichard Zhu val &= ~SDHCI_INT_ADMA_ERROR; 33960bf6396SShawn Guo val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 34097e4ba6aSRichard Zhu } 34197e4ba6aSRichard Zhu } 34297e4ba6aSRichard Zhu 3437e29c306SWolfram Sang writel(val, host->ioaddr + reg); 3447e29c306SWolfram Sang } 3457e29c306SWolfram Sang 34695f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 34795f25efeSWolfram Sang { 348ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 349ef4d0888SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 3500322191eSDong Aisheng u16 ret = 0; 3510322191eSDong Aisheng u32 val; 352ef4d0888SShawn Guo 35395a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 354ef4d0888SShawn Guo reg ^= 2; 3559d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 35695a2482aSShawn Guo /* 357ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 358ef4d0888SShawn Guo * Correct it here. 35995a2482aSShawn Guo */ 360ef4d0888SShawn Guo return SDHCI_SPEC_300; 361ef4d0888SShawn Guo } 36295a2482aSShawn Guo } 36395f25efeSWolfram Sang 3640322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 3650322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 3660322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 3670322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 3680322191eSDong Aisheng 3699d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 3706e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 3710322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 3726e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 3736e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 3746e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 3756e9fd28eSDong Aisheng } 3766e9fd28eSDong Aisheng 3770322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 3780322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 3790322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 3800322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 3810322191eSDong Aisheng 3820322191eSDong Aisheng ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK); 3830322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 3840322191eSDong Aisheng 3850322191eSDong Aisheng return ret; 3860322191eSDong Aisheng } 3870322191eSDong Aisheng 38895f25efeSWolfram Sang return readw(host->ioaddr + reg); 38995f25efeSWolfram Sang } 39095f25efeSWolfram Sang 39195f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 39295f25efeSWolfram Sang { 39395f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 394e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 3950322191eSDong Aisheng u32 new_val = 0; 39695f25efeSWolfram Sang 39795f25efeSWolfram Sang switch (reg) { 3980322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 3990322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4000322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 4010322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4020322191eSDong Aisheng else 4030322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4040322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4050322191eSDong Aisheng return; 4060322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 4070322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4080322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 4090322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 4100322191eSDong Aisheng else 4110322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 4120322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4130322191eSDong Aisheng imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK; 4146e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 4150322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4160322191eSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) 4170322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4180322191eSDong Aisheng else 4190322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4200322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 4216e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 4226e9fd28eSDong Aisheng u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4236e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4246e9fd28eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_TUNING_CTRL); 4256e9fd28eSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 4266e9fd28eSDong Aisheng new_val |= ESDHC_STD_TUNING_EN | 4276e9fd28eSDong Aisheng ESDHC_TUNING_START_TAP; 4286e9fd28eSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 4296e9fd28eSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 4306e9fd28eSDong Aisheng } else { 4316e9fd28eSDong Aisheng new_val &= ~ESDHC_STD_TUNING_EN; 4326e9fd28eSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 4336e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 4346e9fd28eSDong Aisheng } 4356e9fd28eSDong Aisheng 4366e9fd28eSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) 4376e9fd28eSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4386e9fd28eSDong Aisheng else 4396e9fd28eSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4406e9fd28eSDong Aisheng 4416e9fd28eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_TUNING_CTRL); 4426e9fd28eSDong Aisheng writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 4436e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 4446e9fd28eSDong Aisheng } 4450322191eSDong Aisheng return; 44695f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 447f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 44858ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 44958ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 45058ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 45158ac8177SRichard Zhu u32 v; 45260bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 45360bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 45460bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 45558ac8177SRichard Zhu } 45669f54698SShawn Guo 4579d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 45869f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4592a15f981SShawn Guo /* Swap AC23 bit */ 4602a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 4612a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 4622a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 4632a15f981SShawn Guo } 4642a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 46569f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 46669f54698SShawn Guo } else { 46769f54698SShawn Guo /* 46869f54698SShawn Guo * Postpone this write, we must do it together with a 46969f54698SShawn Guo * command write that is down below. 47069f54698SShawn Guo */ 471e149860dSRichard Zhu imx_data->scratchpad = val; 47269f54698SShawn Guo } 47395f25efeSWolfram Sang return; 47495f25efeSWolfram Sang case SDHCI_COMMAND: 475361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 47658ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 47795a2482aSShawn Guo 478361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 479f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 480361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 481361b8482SLucas Stach 4829d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 48395a2482aSShawn Guo writel(val << 16, 48495a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 48569f54698SShawn Guo else 486e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 48795f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 48895f25efeSWolfram Sang return; 48995f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 49095f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 49195f25efeSWolfram Sang break; 49295f25efeSWolfram Sang } 49395f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 49495f25efeSWolfram Sang } 49595f25efeSWolfram Sang 49695f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 49795f25efeSWolfram Sang { 4989a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 4999a0985b7SWilson Callan struct pltfm_imx_data *imx_data = pltfm_host->priv; 50095f25efeSWolfram Sang u32 new_val; 501af51079eSSascha Hauer u32 mask; 50295f25efeSWolfram Sang 50395f25efeSWolfram Sang switch (reg) { 50495f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 50595f25efeSWolfram Sang /* 50695f25efeSWolfram Sang * FSL put some DMA bits here 50795f25efeSWolfram Sang * If your board has a regulator, code should be here 50895f25efeSWolfram Sang */ 50995f25efeSWolfram Sang return; 51095f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 5116b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 512af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 5137122bbb0SMasanari Iida /* ensure the endianness */ 51495f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 5159a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 5169a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 51795f25efeSWolfram Sang /* DMA mode bits are shifted */ 51895f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 5199a0985b7SWilson Callan } 52095f25efeSWolfram Sang 521af51079eSSascha Hauer /* 522af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 523af51079eSSascha Hauer * esdhc_pltfm_bus_width. 524f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 525f6825748SMartin Fuzzey * SDIO interrupt errata workaround. 526af51079eSSascha Hauer */ 527f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 528af51079eSSascha Hauer 529af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 53095f25efeSWolfram Sang return; 53195f25efeSWolfram Sang } 53295f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 533913413c3SShawn Guo 534913413c3SShawn Guo /* 535913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 536913413c3SShawn Guo * that software reset should not affect card detection circuit. 537913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 538913413c3SShawn Guo * software reset. This will stop those clocks that card detection 539913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 540913413c3SShawn Guo * to keep card detection circuit functional. 541913413c3SShawn Guo */ 54258c8c4fbSShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 543913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 54458c8c4fbSShawn Guo /* 54558c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 54658c8c4fbSShawn Guo * Do it manually here. 54758c8c4fbSShawn Guo */ 548de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 54958c8c4fbSShawn Guo writel(0, host->ioaddr + ESDHC_MIX_CTRL); 550de5bdbffSDong Aisheng imx_data->is_ddr = 0; 551de5bdbffSDong Aisheng } 55258c8c4fbSShawn Guo } 55395f25efeSWolfram Sang } 55495f25efeSWolfram Sang 5550ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 5560ddf03c9SLucas Stach { 5570ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5580ddf03c9SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 5590ddf03c9SLucas Stach struct esdhc_platform_data *boarddata = &imx_data->boarddata; 5600ddf03c9SLucas Stach 5610ddf03c9SLucas Stach u32 f_host = clk_get_rate(pltfm_host->clk); 5620ddf03c9SLucas Stach 5630ddf03c9SLucas Stach if (boarddata->f_max && (boarddata->f_max < f_host)) 5640ddf03c9SLucas Stach return boarddata->f_max; 5650ddf03c9SLucas Stach else 5660ddf03c9SLucas Stach return f_host; 5670ddf03c9SLucas Stach } 5680ddf03c9SLucas Stach 56995f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 57095f25efeSWolfram Sang { 57195f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 57295f25efeSWolfram Sang 57395f25efeSWolfram Sang return clk_get_rate(pltfm_host->clk) / 256 / 16; 57495f25efeSWolfram Sang } 57595f25efeSWolfram Sang 5768ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 5778ba9580aSLucas Stach unsigned int clock) 5788ba9580aSLucas Stach { 5798ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 580fed2f6e2SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 581d31fc00aSDong Aisheng unsigned int host_clock = clk_get_rate(pltfm_host->clk); 582d31fc00aSDong Aisheng int pre_div = 2; 583d31fc00aSDong Aisheng int div = 1; 584fed2f6e2SDong Aisheng u32 temp, val; 5858ba9580aSLucas Stach 586fed2f6e2SDong Aisheng if (clock == 0) { 5879d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 588fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 589fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 590fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 591fed2f6e2SDong Aisheng } 592d31fc00aSDong Aisheng goto out; 593fed2f6e2SDong Aisheng } 594d31fc00aSDong Aisheng 595de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) 5965f7886c5SDong Aisheng pre_div = 1; 5975f7886c5SDong Aisheng 598d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 599d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 600d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 601d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 602d31fc00aSDong Aisheng 603d31fc00aSDong Aisheng while (host_clock / pre_div / 16 > clock && pre_div < 256) 604d31fc00aSDong Aisheng pre_div *= 2; 605d31fc00aSDong Aisheng 606d31fc00aSDong Aisheng while (host_clock / pre_div / div > clock && div < 16) 607d31fc00aSDong Aisheng div++; 608d31fc00aSDong Aisheng 609e76b8559SDong Aisheng host->mmc->actual_clock = host_clock / pre_div / div; 610d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 611e76b8559SDong Aisheng clock, host->mmc->actual_clock); 612d31fc00aSDong Aisheng 613de5bdbffSDong Aisheng if (imx_data->is_ddr) 614de5bdbffSDong Aisheng pre_div >>= 2; 615de5bdbffSDong Aisheng else 616d31fc00aSDong Aisheng pre_div >>= 1; 617d31fc00aSDong Aisheng div--; 618d31fc00aSDong Aisheng 619d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 620d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 621d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 622d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 623d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 624fed2f6e2SDong Aisheng 6259d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 626fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 627fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 628fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 629fed2f6e2SDong Aisheng } 630fed2f6e2SDong Aisheng 631d31fc00aSDong Aisheng mdelay(1); 632d31fc00aSDong Aisheng out: 633d31fc00aSDong Aisheng host->clock = clock; 6348ba9580aSLucas Stach } 6358ba9580aSLucas Stach 636913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 637913413c3SShawn Guo { 638842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 639842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 640842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 641913413c3SShawn Guo 642913413c3SShawn Guo switch (boarddata->wp_type) { 643913413c3SShawn Guo case ESDHC_WP_GPIO: 644fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 645913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 646913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 647913413c3SShawn Guo SDHCI_WRITE_PROTECT); 648913413c3SShawn Guo case ESDHC_WP_NONE: 649913413c3SShawn Guo break; 650913413c3SShawn Guo } 651913413c3SShawn Guo 652913413c3SShawn Guo return -ENOSYS; 653913413c3SShawn Guo } 654913413c3SShawn Guo 655af51079eSSascha Hauer static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) 656af51079eSSascha Hauer { 657af51079eSSascha Hauer u32 ctrl; 658af51079eSSascha Hauer 659af51079eSSascha Hauer switch (width) { 660af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 661af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 662af51079eSSascha Hauer break; 663af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 664af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 665af51079eSSascha Hauer break; 666af51079eSSascha Hauer default: 667af51079eSSascha Hauer ctrl = 0; 668af51079eSSascha Hauer break; 669af51079eSSascha Hauer } 670af51079eSSascha Hauer 671af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 672af51079eSSascha Hauer SDHCI_HOST_CONTROL); 673af51079eSSascha Hauer 674af51079eSSascha Hauer return 0; 675af51079eSSascha Hauer } 676af51079eSSascha Hauer 6770322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 6780322191eSDong Aisheng { 6790322191eSDong Aisheng u32 reg; 6800322191eSDong Aisheng 6810322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 6820322191eSDong Aisheng mdelay(1); 6830322191eSDong Aisheng 6840322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 6850322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 6860322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 6870322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 6880322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 6890322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 6900322191eSDong Aisheng "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 6910322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 6920322191eSDong Aisheng } 6930322191eSDong Aisheng 6940322191eSDong Aisheng static void esdhc_request_done(struct mmc_request *mrq) 6950322191eSDong Aisheng { 6960322191eSDong Aisheng complete(&mrq->completion); 6970322191eSDong Aisheng } 6980322191eSDong Aisheng 6990322191eSDong Aisheng static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode) 7000322191eSDong Aisheng { 7010322191eSDong Aisheng struct mmc_command cmd = {0}; 7020322191eSDong Aisheng struct mmc_request mrq = {0}; 7030322191eSDong Aisheng struct mmc_data data = {0}; 7040322191eSDong Aisheng struct scatterlist sg; 7050322191eSDong Aisheng char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN]; 7060322191eSDong Aisheng 7070322191eSDong Aisheng cmd.opcode = opcode; 7080322191eSDong Aisheng cmd.arg = 0; 7090322191eSDong Aisheng cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 7100322191eSDong Aisheng 7110322191eSDong Aisheng data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN; 7120322191eSDong Aisheng data.blocks = 1; 7130322191eSDong Aisheng data.flags = MMC_DATA_READ; 7140322191eSDong Aisheng data.sg = &sg; 7150322191eSDong Aisheng data.sg_len = 1; 7160322191eSDong Aisheng 7170322191eSDong Aisheng sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern)); 7180322191eSDong Aisheng 7190322191eSDong Aisheng mrq.cmd = &cmd; 7200322191eSDong Aisheng mrq.cmd->mrq = &mrq; 7210322191eSDong Aisheng mrq.data = &data; 7220322191eSDong Aisheng mrq.data->mrq = &mrq; 7230322191eSDong Aisheng mrq.cmd->data = mrq.data; 7240322191eSDong Aisheng 7250322191eSDong Aisheng mrq.done = esdhc_request_done; 7260322191eSDong Aisheng init_completion(&(mrq.completion)); 7270322191eSDong Aisheng 7280322191eSDong Aisheng disable_irq(host->irq); 7290322191eSDong Aisheng spin_lock(&host->lock); 7300322191eSDong Aisheng host->mrq = &mrq; 7310322191eSDong Aisheng 7320322191eSDong Aisheng sdhci_send_command(host, mrq.cmd); 7330322191eSDong Aisheng 7340322191eSDong Aisheng spin_unlock(&host->lock); 7350322191eSDong Aisheng enable_irq(host->irq); 7360322191eSDong Aisheng 7370322191eSDong Aisheng wait_for_completion(&mrq.completion); 7380322191eSDong Aisheng 7390322191eSDong Aisheng if (cmd.error) 7400322191eSDong Aisheng return cmd.error; 7410322191eSDong Aisheng if (data.error) 7420322191eSDong Aisheng return data.error; 7430322191eSDong Aisheng 7440322191eSDong Aisheng return 0; 7450322191eSDong Aisheng } 7460322191eSDong Aisheng 7470322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 7480322191eSDong Aisheng { 7490322191eSDong Aisheng u32 reg; 7500322191eSDong Aisheng 7510322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7520322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 7530322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7540322191eSDong Aisheng } 7550322191eSDong Aisheng 7560322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 7570322191eSDong Aisheng { 7580322191eSDong Aisheng int min, max, avg, ret; 7590322191eSDong Aisheng 7600322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 7610322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 7620322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 7630322191eSDong Aisheng esdhc_prepare_tuning(host, min); 7640322191eSDong Aisheng if (!esdhc_send_tuning_cmd(host, opcode)) 7650322191eSDong Aisheng break; 7660322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 7670322191eSDong Aisheng } 7680322191eSDong Aisheng 7690322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 7700322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 7710322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 7720322191eSDong Aisheng esdhc_prepare_tuning(host, max); 7730322191eSDong Aisheng if (esdhc_send_tuning_cmd(host, opcode)) { 7740322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 7750322191eSDong Aisheng break; 7760322191eSDong Aisheng } 7770322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 7780322191eSDong Aisheng } 7790322191eSDong Aisheng 7800322191eSDong Aisheng /* use average delay to get the best timing */ 7810322191eSDong Aisheng avg = (min + max) / 2; 7820322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 7830322191eSDong Aisheng ret = esdhc_send_tuning_cmd(host, opcode); 7840322191eSDong Aisheng esdhc_post_tuning(host); 7850322191eSDong Aisheng 7860322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 7870322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 7880322191eSDong Aisheng 7890322191eSDong Aisheng return ret; 7900322191eSDong Aisheng } 7910322191eSDong Aisheng 792ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 793ad93220dSDong Aisheng unsigned int uhs) 794ad93220dSDong Aisheng { 795ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 796ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 797ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 798ad93220dSDong Aisheng 799ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 800ad93220dSDong Aisheng 801ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 802ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 803ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 804ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 805ad93220dSDong Aisheng return -EINVAL; 806ad93220dSDong Aisheng 807ad93220dSDong Aisheng switch (uhs) { 808ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 809ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 810ad93220dSDong Aisheng break; 811ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 812ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 813ad93220dSDong Aisheng break; 814ad93220dSDong Aisheng default: 815ad93220dSDong Aisheng /* back to default state for other legacy timing */ 816ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 817ad93220dSDong Aisheng } 818ad93220dSDong Aisheng 819ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 820ad93220dSDong Aisheng } 821ad93220dSDong Aisheng 822ad93220dSDong Aisheng static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) 823ad93220dSDong Aisheng { 824ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 825ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 826602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 827ad93220dSDong Aisheng 828ad93220dSDong Aisheng switch (uhs) { 829ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 830ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12; 831ad93220dSDong Aisheng break; 832ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 833ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25; 834ad93220dSDong Aisheng break; 835ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 836ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50; 837ad93220dSDong Aisheng break; 838ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 839ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104; 840ad93220dSDong Aisheng break; 841ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 842ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50; 843de5bdbffSDong Aisheng writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | 844de5bdbffSDong Aisheng ESDHC_MIX_CTRL_DDREN, 845de5bdbffSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 846de5bdbffSDong Aisheng imx_data->is_ddr = 1; 847602519b2SDong Aisheng if (boarddata->delay_line) { 848602519b2SDong Aisheng u32 v; 849602519b2SDong Aisheng v = boarddata->delay_line << 850602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 851602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 852602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 853602519b2SDong Aisheng v <<= 1; 854602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 855602519b2SDong Aisheng } 856ad93220dSDong Aisheng break; 857ad93220dSDong Aisheng } 858ad93220dSDong Aisheng 859ad93220dSDong Aisheng return esdhc_change_pinstate(host, uhs); 860ad93220dSDong Aisheng } 861ad93220dSDong Aisheng 8626e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 863e149860dSRichard Zhu .read_l = esdhc_readl_le, 8640c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 865e149860dSRichard Zhu .write_l = esdhc_writel_le, 8660c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 8670c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 8688ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 8690ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 8700c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 871913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 872af51079eSSascha Hauer .platform_bus_width = esdhc_pltfm_bus_width, 873ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 8740c6d49ceSWolfram Sang }; 8750c6d49ceSWolfram Sang 8761db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 87797e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 87897e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 87997e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 88085d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 88185d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 88285d6509dSShawn Guo }; 88385d6509dSShawn Guo 884abfafc2dSShawn Guo #ifdef CONFIG_OF 885c3be1efdSBill Pemberton static int 886abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 887abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 888abfafc2dSShawn Guo { 889abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 890abfafc2dSShawn Guo 891abfafc2dSShawn Guo if (!np) 892abfafc2dSShawn Guo return -ENODEV; 893abfafc2dSShawn Guo 8947f217794SArnd Bergmann if (of_get_property(np, "non-removable", NULL)) 895abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_PERMANENT; 896abfafc2dSShawn Guo 897abfafc2dSShawn Guo if (of_get_property(np, "fsl,cd-controller", NULL)) 898abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_CONTROLLER; 899abfafc2dSShawn Guo 900abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 901abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 902abfafc2dSShawn Guo 903abfafc2dSShawn Guo boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 904abfafc2dSShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 905abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_GPIO; 906abfafc2dSShawn Guo 907abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 908abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 909abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 910abfafc2dSShawn Guo 911af51079eSSascha Hauer of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); 912af51079eSSascha Hauer 9130ddf03c9SLucas Stach of_property_read_u32(np, "max-frequency", &boarddata->f_max); 9140ddf03c9SLucas Stach 915ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 916ad93220dSDong Aisheng boarddata->support_vsel = false; 917ad93220dSDong Aisheng else 918ad93220dSDong Aisheng boarddata->support_vsel = true; 919ad93220dSDong Aisheng 920602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 921602519b2SDong Aisheng boarddata->delay_line = 0; 922602519b2SDong Aisheng 923abfafc2dSShawn Guo return 0; 924abfafc2dSShawn Guo } 925abfafc2dSShawn Guo #else 926abfafc2dSShawn Guo static inline int 927abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 928abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 929abfafc2dSShawn Guo { 930abfafc2dSShawn Guo return -ENODEV; 931abfafc2dSShawn Guo } 932abfafc2dSShawn Guo #endif 933abfafc2dSShawn Guo 934c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 93595f25efeSWolfram Sang { 936abfafc2dSShawn Guo const struct of_device_id *of_id = 937abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 93885d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 93985d6509dSShawn Guo struct sdhci_host *host; 94085d6509dSShawn Guo struct esdhc_platform_data *boarddata; 9410c6d49ceSWolfram Sang int err; 942e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 94395f25efeSWolfram Sang 9440e748234SChristian Daudt host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); 94585d6509dSShawn Guo if (IS_ERR(host)) 94685d6509dSShawn Guo return PTR_ERR(host); 94785d6509dSShawn Guo 94885d6509dSShawn Guo pltfm_host = sdhci_priv(host); 94985d6509dSShawn Guo 950e3af31c6SShawn Guo imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 951abfafc2dSShawn Guo if (!imx_data) { 952abfafc2dSShawn Guo err = -ENOMEM; 953e3af31c6SShawn Guo goto free_sdhci; 954abfafc2dSShawn Guo } 95557ed3314SShawn Guo 956f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 9573770ee8fSShawn Guo pdev->id_entry->driver_data; 95885d6509dSShawn Guo pltfm_host->priv = imx_data; 95985d6509dSShawn Guo 96052dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 96152dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 96252dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 963e3af31c6SShawn Guo goto free_sdhci; 96495f25efeSWolfram Sang } 96552dac615SSascha Hauer 96652dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 96752dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 96852dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 969e3af31c6SShawn Guo goto free_sdhci; 97052dac615SSascha Hauer } 97152dac615SSascha Hauer 97252dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 97352dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 97452dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 975e3af31c6SShawn Guo goto free_sdhci; 97652dac615SSascha Hauer } 97752dac615SSascha Hauer 97852dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 97952dac615SSascha Hauer 98052dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 98152dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 98252dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 98395f25efeSWolfram Sang 984ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 985e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 986e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 987e3af31c6SShawn Guo goto disable_clk; 988e62d8b8fSDong Aisheng } 989e62d8b8fSDong Aisheng 990ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 991ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 992ad93220dSDong Aisheng if (IS_ERR(imx_data->pins_default)) { 993ad93220dSDong Aisheng err = PTR_ERR(imx_data->pins_default); 994ad93220dSDong Aisheng dev_err(mmc_dev(host->mmc), "could not get default state\n"); 995ad93220dSDong Aisheng goto disable_clk; 996ad93220dSDong Aisheng } 997ad93220dSDong Aisheng 99837865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 99937865fe9SEric Bénard 1000f47c4bbfSShawn Guo if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 10010c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 100297e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 100397e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 10040c6d49ceSWolfram Sang 1005f750ba9bSShawn Guo /* 1006f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 1007f750ba9bSShawn Guo * to something insane. Change it back here. 1008f750ba9bSShawn Guo */ 100969ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 101060bf6396SShawn Guo writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 101169ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 101269ed60e0SDong Aisheng } 1013f750ba9bSShawn Guo 10146e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 10156e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 10166e9fd28eSDong Aisheng esdhc_executing_tuning; 1017abfafc2dSShawn Guo boarddata = &imx_data->boarddata; 1018abfafc2dSShawn Guo if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { 1019842afc02SShawn Guo if (!host->mmc->parent->platform_data) { 1020913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "no board data!\n"); 1021913413c3SShawn Guo err = -EINVAL; 1022e3af31c6SShawn Guo goto disable_clk; 1023913413c3SShawn Guo } 1024842afc02SShawn Guo imx_data->boarddata = *((struct esdhc_platform_data *) 1025842afc02SShawn Guo host->mmc->parent->platform_data); 1026abfafc2dSShawn Guo } 1027913413c3SShawn Guo 1028913413c3SShawn Guo /* write_protect */ 1029913413c3SShawn Guo if (boarddata->wp_type == ESDHC_WP_GPIO) { 1030fbe5fdd1SShawn Guo err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 10310c6d49ceSWolfram Sang if (err) { 1032fbe5fdd1SShawn Guo dev_err(mmc_dev(host->mmc), 1033fbe5fdd1SShawn Guo "failed to request write-protect gpio!\n"); 1034fbe5fdd1SShawn Guo goto disable_clk; 1035913413c3SShawn Guo } 1036fbe5fdd1SShawn Guo host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 10370c6d49ceSWolfram Sang } 10387e29c306SWolfram Sang 1039913413c3SShawn Guo /* card_detect */ 1040913413c3SShawn Guo switch (boarddata->cd_type) { 1041913413c3SShawn Guo case ESDHC_CD_GPIO: 1042214fc309SLaurent Pinchart err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 10437e29c306SWolfram Sang if (err) { 1044913413c3SShawn Guo dev_err(mmc_dev(host->mmc), 1045fbe5fdd1SShawn Guo "failed to request card-detect gpio!\n"); 1046e3af31c6SShawn Guo goto disable_clk; 10477e29c306SWolfram Sang } 1048913413c3SShawn Guo /* fall through */ 10497e29c306SWolfram Sang 1050913413c3SShawn Guo case ESDHC_CD_CONTROLLER: 1051913413c3SShawn Guo /* we have a working card_detect back */ 10527e29c306SWolfram Sang host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1053913413c3SShawn Guo break; 1054913413c3SShawn Guo 1055913413c3SShawn Guo case ESDHC_CD_PERMANENT: 1056913413c3SShawn Guo host->mmc->caps = MMC_CAP_NONREMOVABLE; 1057913413c3SShawn Guo break; 1058913413c3SShawn Guo 1059913413c3SShawn Guo case ESDHC_CD_NONE: 1060913413c3SShawn Guo break; 10617e29c306SWolfram Sang } 10627e29c306SWolfram Sang 1063af51079eSSascha Hauer switch (boarddata->max_bus_width) { 1064af51079eSSascha Hauer case 8: 1065af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 1066af51079eSSascha Hauer break; 1067af51079eSSascha Hauer case 4: 1068af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_4_BIT_DATA; 1069af51079eSSascha Hauer break; 1070af51079eSSascha Hauer case 1: 1071af51079eSSascha Hauer default: 1072af51079eSSascha Hauer host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 1073af51079eSSascha Hauer break; 1074af51079eSSascha Hauer } 1075af51079eSSascha Hauer 1076ad93220dSDong Aisheng /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 10779d61c009SShawn Guo if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) { 1078ad93220dSDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1079ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 1080ad93220dSDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1081ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 1082ad93220dSDong Aisheng if (IS_ERR(imx_data->pins_100mhz) || 1083ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) { 1084ad93220dSDong Aisheng dev_warn(mmc_dev(host->mmc), 1085ad93220dSDong Aisheng "could not get ultra high speed state, work on normal mode\n"); 1086ad93220dSDong Aisheng /* fall back to not support uhs by specify no 1.8v quirk */ 1087ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1088ad93220dSDong Aisheng } 1089ad93220dSDong Aisheng } else { 1090ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1091ad93220dSDong Aisheng } 1092ad93220dSDong Aisheng 109385d6509dSShawn Guo err = sdhci_add_host(host); 109485d6509dSShawn Guo if (err) 1095e3af31c6SShawn Guo goto disable_clk; 109685d6509dSShawn Guo 10977e29c306SWolfram Sang return 0; 10987e29c306SWolfram Sang 1099e3af31c6SShawn Guo disable_clk: 110052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 110152dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 110252dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 1103e3af31c6SShawn Guo free_sdhci: 110485d6509dSShawn Guo sdhci_pltfm_free(pdev); 110585d6509dSShawn Guo return err; 110695f25efeSWolfram Sang } 110795f25efeSWolfram Sang 11086e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 110995f25efeSWolfram Sang { 111085d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 111195f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1112e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 111385d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 111485d6509dSShawn Guo 111585d6509dSShawn Guo sdhci_remove_host(host, dead); 11160c6d49ceSWolfram Sang 111752dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 111852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 111952dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 112052dac615SSascha Hauer 112185d6509dSShawn Guo sdhci_pltfm_free(pdev); 112285d6509dSShawn Guo 112385d6509dSShawn Guo return 0; 112495f25efeSWolfram Sang } 112595f25efeSWolfram Sang 112685d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 112785d6509dSShawn Guo .driver = { 112885d6509dSShawn Guo .name = "sdhci-esdhc-imx", 112985d6509dSShawn Guo .owner = THIS_MODULE, 1130abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 113129495aa0SManuel Lauss .pm = SDHCI_PLTFM_PMOPS, 113285d6509dSShawn Guo }, 113357ed3314SShawn Guo .id_table = imx_esdhc_devtype, 113485d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 11350433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 113695f25efeSWolfram Sang }; 113785d6509dSShawn Guo 1138d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 113985d6509dSShawn Guo 114085d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 114185d6509dSShawn Guo MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 114285d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1143