1a6e7e407SFabio Estevam // SPDX-License-Identifier: GPL-2.0 295f25efeSWolfram Sang /* 395f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 495f25efeSWolfram Sang * 595f25efeSWolfram Sang * derived from the OF-version. 695f25efeSWolfram Sang * 795f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 8035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 995f25efeSWolfram Sang */ 1095f25efeSWolfram Sang 1195f25efeSWolfram Sang #include <linux/io.h> 1295f25efeSWolfram Sang #include <linux/delay.h> 1395f25efeSWolfram Sang #include <linux/err.h> 1495f25efeSWolfram Sang #include <linux/clk.h> 1566506f76SShawn Guo #include <linux/module.h> 16e149860dSRichard Zhu #include <linux/slab.h> 171c4989b0SBOUGH CHEN #include <linux/pm_qos.h> 1895f25efeSWolfram Sang #include <linux/mmc/host.h> 1958ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2058ac8177SRichard Zhu #include <linux/mmc/sdio.h> 21fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 22abfafc2dSShawn Guo #include <linux/of.h> 23abfafc2dSShawn Guo #include <linux/of_device.h> 24e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2582906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 2689d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 2795f25efeSWolfram Sang #include "sdhci-pltfm.h" 2895f25efeSWolfram Sang #include "sdhci-esdhc.h" 29bb6e3581SBOUGH CHEN #include "cqhci.h" 3095f25efeSWolfram Sang 31a215186dSHaibo Chen #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 3260bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 33fd44954eSHaibo Chen #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 3458ac8177SRichard Zhu /* VENDOR SPEC register */ 3560bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 370322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 38fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 3960bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 40cc17e129SDong Aisheng #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 413fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 423fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 433fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 443fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 453fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 463fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 4760bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 48de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 492a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 500322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 510322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 520b330e38SDong Aisheng #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 530322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 5428b07674SHaibo Chen #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 55029e2476SBOUGH CHEN #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27) 562a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 572a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 58d131a71cSDong Aisheng /* Tuning bits */ 59d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 6058ac8177SRichard Zhu 61602519b2SDong Aisheng /* dll control register */ 62602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 63602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 64602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 65602519b2SDong Aisheng 660322191eSDong Aisheng /* tune control register */ 670322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 680322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 690322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 700322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 710322191eSDong Aisheng 7228b07674SHaibo Chen /* strobe dll register */ 7328b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL 0x70 7428b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 7528b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 7628b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 772eaf5a53SBOUGH CHEN #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) 7828b07674SHaibo Chen 7928b07674SHaibo Chen #define ESDHC_STROBE_DLL_STATUS 0x74 8028b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 8128b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 8228b07674SHaibo Chen 83bcdb5301SBOUGH CHEN #define ESDHC_VEND_SPEC2 0xc8 84bcdb5301SBOUGH CHEN #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8) 85bcdb5301SBOUGH CHEN 866e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 876e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 886e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 89d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 90d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_MASK 0xff 91260ecb3cSHaibo Chen #define ESDHC_TUNING_STEP_MASK 0x00070000 92d407e30bSHaibo Chen #define ESDHC_TUNING_STEP_SHIFT 16 936e9fd28eSDong Aisheng 94ad93220dSDong Aisheng /* pinctrl state */ 95ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 96ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 97ad93220dSDong Aisheng 9858ac8177SRichard Zhu /* 99af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 100af51079eSSascha Hauer */ 101af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 102af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 103af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 104af51079eSSascha Hauer 105af51079eSSascha Hauer /* 106d04f8d5bSBenoît Thébaudeau * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 10797e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 10897e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 10997e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 11097e4ba6aSRichard Zhu */ 11160bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 11297e4ba6aSRichard Zhu 113bb6e3581SBOUGH CHEN /* the address offset of CQHCI */ 114bb6e3581SBOUGH CHEN #define ESDHC_CQHCI_ADDR_OFFSET 0x100 115bb6e3581SBOUGH CHEN 11697e4ba6aSRichard Zhu /* 11758ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 11858ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 11958ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 12058ac8177SRichard Zhu * be generated. 12158ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 12258ac8177SRichard Zhu * operations automatically as required at the end of the 12358ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 12458ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 125d04f8d5bSBenoît Thébaudeau * exception. Bit1 of Vendor Spec register is used to fix it. 12658ac8177SRichard Zhu */ 12731fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 12831fbb301SShawn Guo /* 1299d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1309d61c009SShawn Guo * integrated on the i.MX6 series. 1319d61c009SShawn Guo */ 1329d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1336e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1346e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1356e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1366e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1376e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1386e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 13918094430SDong Aisheng /* 140d04f8d5bSBenoît Thébaudeau * The IP has erratum ERR004536 14118094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 14218094430SDong Aisheng * when reading data from the card 143667123f6SBenoît Thébaudeau * This flag is also set for i.MX25 and i.MX35 in order to get 144667123f6SBenoît Thébaudeau * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 14518094430SDong Aisheng */ 14618094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 1474245afffSDong Aisheng /* The IP supports HS200 mode */ 1484245afffSDong Aisheng #define ESDHC_FLAG_HS200 BIT(8) 14928b07674SHaibo Chen /* The IP supports HS400 mode */ 15028b07674SHaibo Chen #define ESDHC_FLAG_HS400 BIT(9) 151af6a50d4SBOUGH CHEN /* 152af6a50d4SBOUGH CHEN * The IP has errata ERR010450 153af6a50d4SBOUGH CHEN * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't 154af6a50d4SBOUGH CHEN * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. 155af6a50d4SBOUGH CHEN */ 156af6a50d4SBOUGH CHEN #define ESDHC_FLAG_ERR010450 BIT(10) 157029e2476SBOUGH CHEN /* The IP supports HS400ES mode */ 158029e2476SBOUGH CHEN #define ESDHC_FLAG_HS400_ES BIT(11) 159bb6e3581SBOUGH CHEN /* The IP has Host Controller Interface for Command Queuing */ 160bb6e3581SBOUGH CHEN #define ESDHC_FLAG_CQHCI BIT(12) 1611c4989b0SBOUGH CHEN /* need request pmqos during low power */ 1621c4989b0SBOUGH CHEN #define ESDHC_FLAG_PMQOS BIT(13) 163a26a4f1bSHaibo Chen /* The IP state got lost in low power mode */ 164a26a4f1bSHaibo Chen #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14) 1655c11f1ffSHaibo Chen /* The IP lost clock rate in PM_RUNTIME */ 1665c11f1ffSHaibo Chen #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15) 167e149860dSRichard Zhu 168f47c4bbfSShawn Guo struct esdhc_soc_data { 169f47c4bbfSShawn Guo u32 flags; 170f47c4bbfSShawn Guo }; 171f47c4bbfSShawn Guo 1724f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx25_data = { 173667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 174f47c4bbfSShawn Guo }; 175f47c4bbfSShawn Guo 1764f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx35_data = { 177667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 178f47c4bbfSShawn Guo }; 179f47c4bbfSShawn Guo 1804f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx51_data = { 181f47c4bbfSShawn Guo .flags = 0, 182f47c4bbfSShawn Guo }; 183f47c4bbfSShawn Guo 1844f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx53_data = { 185f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 186f47c4bbfSShawn Guo }; 187f47c4bbfSShawn Guo 1884f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6q_data = { 1896e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1906e9fd28eSDong Aisheng }; 1916e9fd28eSDong Aisheng 1924f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sl_data = { 1936e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1944245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 1954245afffSDong Aisheng | ESDHC_FLAG_HS200, 19657ed3314SShawn Guo }; 19757ed3314SShawn Guo 1984f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sx_data = { 199913d4951SDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 200a26a4f1bSHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 201a26a4f1bSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 202913d4951SDong Aisheng }; 203913d4951SDong Aisheng 204af6a50d4SBOUGH CHEN static const struct esdhc_soc_data usdhc_imx6ull_data = { 205af6a50d4SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 206af6a50d4SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 207a26a4f1bSHaibo Chen | ESDHC_FLAG_ERR010450 208a26a4f1bSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 209af6a50d4SBOUGH CHEN }; 210af6a50d4SBOUGH CHEN 2114f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx7d_data = { 21228b07674SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 21328b07674SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 214a26a4f1bSHaibo Chen | ESDHC_FLAG_HS400 215a26a4f1bSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 21628b07674SHaibo Chen }; 21728b07674SHaibo Chen 2181c4989b0SBOUGH CHEN static struct esdhc_soc_data usdhc_imx7ulp_data = { 2191c4989b0SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 2201c4989b0SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 221a26a4f1bSHaibo Chen | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400 222a26a4f1bSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 2231c4989b0SBOUGH CHEN }; 2241c4989b0SBOUGH CHEN 225029e2476SBOUGH CHEN static struct esdhc_soc_data usdhc_imx8qxp_data = { 226029e2476SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 227029e2476SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 228bb6e3581SBOUGH CHEN | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 229a26a4f1bSHaibo Chen | ESDHC_FLAG_CQHCI 2305c11f1ffSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE 2315c11f1ffSHaibo Chen | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME, 232029e2476SBOUGH CHEN }; 233029e2476SBOUGH CHEN 234e149860dSRichard Zhu struct pltfm_imx_data { 235e149860dSRichard Zhu u32 scratchpad; 236e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 237ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 238ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 239f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 240842afc02SShawn Guo struct esdhc_platform_data boarddata; 24152dac615SSascha Hauer struct clk *clk_ipg; 24252dac615SSascha Hauer struct clk *clk_ahb; 24352dac615SSascha Hauer struct clk *clk_per; 2443602785bSMichael Trimarchi unsigned int actual_clock; 245361b8482SLucas Stach enum { 246361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending */ 247361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 248361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 249361b8482SLucas Stach } multiblock_status; 250de5bdbffSDong Aisheng u32 is_ddr; 2511c4989b0SBOUGH CHEN struct pm_qos_request pm_qos_req; 252e149860dSRichard Zhu }; 253e149860dSRichard Zhu 254f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 25557ed3314SShawn Guo { 25657ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 257f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 25857ed3314SShawn Guo }, { 25957ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 260f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 26157ed3314SShawn Guo }, { 26257ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 263f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 26457ed3314SShawn Guo }, { 26557ed3314SShawn Guo /* sentinel */ 26657ed3314SShawn Guo } 26757ed3314SShawn Guo }; 26857ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 26957ed3314SShawn Guo 270abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 271f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 272f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 273f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 274f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 275913d4951SDong Aisheng { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 2766e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 277f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 278af6a50d4SBOUGH CHEN { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, 27928b07674SHaibo Chen { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 2801c4989b0SBOUGH CHEN { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, }, 281029e2476SBOUGH CHEN { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, }, 282abfafc2dSShawn Guo { /* sentinel */ } 283abfafc2dSShawn Guo }; 284abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 285abfafc2dSShawn Guo 28657ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 28757ed3314SShawn Guo { 288f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 28957ed3314SShawn Guo } 29057ed3314SShawn Guo 29157ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 29257ed3314SShawn Guo { 293f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 29457ed3314SShawn Guo } 29557ed3314SShawn Guo 29695a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 29795a2482aSShawn Guo { 298f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 29995a2482aSShawn Guo } 30095a2482aSShawn Guo 3019d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 3029d61c009SShawn Guo { 303f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 3049d61c009SShawn Guo } 3059d61c009SShawn Guo 30695f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 30795f25efeSWolfram Sang { 30895f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 30995f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 31095f25efeSWolfram Sang 31195f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 31295f25efeSWolfram Sang } 31395f25efeSWolfram Sang 3147e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 3157e29c306SWolfram Sang { 316361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 317070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 318913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 319913413c3SShawn Guo 3200322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 3210322191eSDong Aisheng u32 fsl_prss = val; 3220322191eSDong Aisheng /* save the least 20 bits */ 3230322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 3240322191eSDong Aisheng /* move dat[0-3] bits */ 3250322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 3260322191eSDong Aisheng /* move cmd line bit */ 3270322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 3280322191eSDong Aisheng } 3290322191eSDong Aisheng 33097e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 3316b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 3326b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3336b4fb671SDong Aisheng val &= 0xffff0000; 3346b4fb671SDong Aisheng 33597e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 33697e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 33797e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 33897e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 339d04f8d5bSBenoît Thébaudeau * quirk on MX25/35 platforms. 34097e4ba6aSRichard Zhu */ 34197e4ba6aSRichard Zhu 34297e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 34397e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 34497e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 34597e4ba6aSRichard Zhu } 34697e4ba6aSRichard Zhu } 34797e4ba6aSRichard Zhu 3486e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 3496e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 3506e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3516e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 3526e9fd28eSDong Aisheng else 3536e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 3540322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 355888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 356da0295ffSDong Aisheng | SDHCI_USE_SDR50_TUNING 357da0295ffSDong Aisheng | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); 35828b07674SHaibo Chen 35928b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 36028b07674SHaibo Chen val |= SDHCI_SUPPORT_HS400; 36192748beaSStefan Agner 36292748beaSStefan Agner /* 36392748beaSStefan Agner * Do not advertise faster UHS modes if there are no 36492748beaSStefan Agner * pinctrl states for 100MHz/200MHz. 36592748beaSStefan Agner */ 36692748beaSStefan Agner if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || 36792748beaSStefan Agner IS_ERR_OR_NULL(imx_data->pins_200mhz)) 36892748beaSStefan Agner val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50 36992748beaSStefan Agner | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 3706e9fd28eSDong Aisheng } 3716e9fd28eSDong Aisheng } 3720322191eSDong Aisheng 3739d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 3740322191eSDong Aisheng val = 0; 3750322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 3760322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 3770322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 3780322191eSDong Aisheng } 3790322191eSDong Aisheng 38097e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 38160bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 38260bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 38397e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 38497e4ba6aSRichard Zhu } 385361b8482SLucas Stach 386361b8482SLucas Stach /* 387361b8482SLucas Stach * mask off the interrupt we get in response to the manually 388361b8482SLucas Stach * sent CMD12 389361b8482SLucas Stach */ 390361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 391361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 392361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 393361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 394361b8482SLucas Stach SDHCI_INT_STATUS); 395361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 396361b8482SLucas Stach } 39797e4ba6aSRichard Zhu } 39897e4ba6aSRichard Zhu 3997e29c306SWolfram Sang return val; 4007e29c306SWolfram Sang } 4017e29c306SWolfram Sang 4027e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 4037e29c306SWolfram Sang { 404e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 405070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 4060d58864bSTony Lin u32 data; 407e149860dSRichard Zhu 40877da3da0SAaron Brice if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 40977da3da0SAaron Brice reg == SDHCI_INT_STATUS)) { 410b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 4110d58864bSTony Lin /* 4120d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 413d04f8d5bSBenoît Thébaudeau * card interrupt. This is an eSDHC controller problem 4140d58864bSTony Lin * so we need to apply the following workaround: clear 4150d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 4160d58864bSTony Lin * interrupt. In case a card interrupt was lost, 4170d58864bSTony Lin * re-sample it by the following steps. 4180d58864bSTony Lin */ 4190d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 42060bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 4210d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 42260bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 4230d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 4240d58864bSTony Lin } 425915be485SDong Aisheng 426915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 427915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 428915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 429915be485SDong Aisheng } 4300d58864bSTony Lin } 4310d58864bSTony Lin 432f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 43358ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 43458ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 43558ac8177SRichard Zhu u32 v; 43660bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 43760bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 43860bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 439361b8482SLucas Stach 440361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 441361b8482SLucas Stach { 442361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 443361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 444361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 445361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 446361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 447361b8482SLucas Stach } 44858ac8177SRichard Zhu } 44958ac8177SRichard Zhu 4507e29c306SWolfram Sang writel(val, host->ioaddr + reg); 4517e29c306SWolfram Sang } 4527e29c306SWolfram Sang 45395f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 45495f25efeSWolfram Sang { 455ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 456070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 4570322191eSDong Aisheng u16 ret = 0; 4580322191eSDong Aisheng u32 val; 459ef4d0888SShawn Guo 46095a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 461ef4d0888SShawn Guo reg ^= 2; 4629d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 46395a2482aSShawn Guo /* 464ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 465ef4d0888SShawn Guo * Correct it here. 46695a2482aSShawn Guo */ 467ef4d0888SShawn Guo return SDHCI_SPEC_300; 468ef4d0888SShawn Guo } 46995a2482aSShawn Guo } 47095f25efeSWolfram Sang 4710322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 4720322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4730322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 4740322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 4750322191eSDong Aisheng 4769d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 4776e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 4780322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4796e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 4806e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 481869f8a69SAdrian Hunter val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 4826e9fd28eSDong Aisheng } 4836e9fd28eSDong Aisheng 4840322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 4850322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 4860322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 4870322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 4880322191eSDong Aisheng 4890322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 4900322191eSDong Aisheng 4910322191eSDong Aisheng return ret; 4920322191eSDong Aisheng } 4930322191eSDong Aisheng 4947dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 4957dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 4967dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4977dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 4987dd109efSDong Aisheng /* Swap AC23 bit */ 4997dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 5007dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 5017dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 5027dd109efSDong Aisheng } 5037dd109efSDong Aisheng } else { 5047dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 5057dd109efSDong Aisheng } 5067dd109efSDong Aisheng 5077dd109efSDong Aisheng return ret; 5087dd109efSDong Aisheng } 5097dd109efSDong Aisheng 51095f25efeSWolfram Sang return readw(host->ioaddr + reg); 51195f25efeSWolfram Sang } 51295f25efeSWolfram Sang 51395f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 51495f25efeSWolfram Sang { 51595f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 516070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 5170322191eSDong Aisheng u32 new_val = 0; 51895f25efeSWolfram Sang 51995f25efeSWolfram Sang switch (reg) { 5200322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 5210322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5220322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 5230322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 5240322191eSDong Aisheng else 5250322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 5260322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 5270322191eSDong Aisheng return; 5280322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 5290322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5300322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 5310322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 5320322191eSDong Aisheng else 5330322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 5340322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 5356e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 5360322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 537da0295ffSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 5380322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 539da0295ffSDong Aisheng new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 540da0295ffSDong Aisheng } else { 5410322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 542da0295ffSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 543da0295ffSDong Aisheng } 5440322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 5456e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 546869f8a69SAdrian Hunter u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 5476e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5488b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 5498b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 5506e9fd28eSDong Aisheng } else { 5518b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 5526e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 5530b330e38SDong Aisheng m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 5546e9fd28eSDong Aisheng } 5556e9fd28eSDong Aisheng 5568b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 5578b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 5588b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 5590b330e38SDong Aisheng m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 5608b2bb0adSDong Aisheng } else { 5618b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 5628b2bb0adSDong Aisheng } 5636e9fd28eSDong Aisheng 564869f8a69SAdrian Hunter writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 5656e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5666e9fd28eSDong Aisheng } 5670322191eSDong Aisheng return; 56895f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 569f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 57058ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 57158ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 57258ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 57358ac8177SRichard Zhu u32 v; 57460bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 57560bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 57660bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 57758ac8177SRichard Zhu } 57869f54698SShawn Guo 5799d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 5803fbd4322SAndrew Gabbasov u32 wml; 58169f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5822a15f981SShawn Guo /* Swap AC23 bit */ 5832a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 5842a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 5852a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 5862a15f981SShawn Guo } 5872a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 58869f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5893fbd4322SAndrew Gabbasov 5903fbd4322SAndrew Gabbasov /* Set watermark levels for PIO access to maximum value 5913fbd4322SAndrew Gabbasov * (128 words) to accommodate full 512 bytes buffer. 5923fbd4322SAndrew Gabbasov * For DMA access restore the levels to default value. 5933fbd4322SAndrew Gabbasov */ 5943fbd4322SAndrew Gabbasov m = readl(host->ioaddr + ESDHC_WTMK_LVL); 5953fbd4322SAndrew Gabbasov if (val & SDHCI_TRNS_DMA) 5963fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 5973fbd4322SAndrew Gabbasov else 5983fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 5993fbd4322SAndrew Gabbasov m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 6003fbd4322SAndrew Gabbasov ESDHC_WTMK_LVL_WR_WML_MASK); 6013fbd4322SAndrew Gabbasov m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 6023fbd4322SAndrew Gabbasov (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 6033fbd4322SAndrew Gabbasov writel(m, host->ioaddr + ESDHC_WTMK_LVL); 60469f54698SShawn Guo } else { 60569f54698SShawn Guo /* 60669f54698SShawn Guo * Postpone this write, we must do it together with a 60769f54698SShawn Guo * command write that is down below. 60869f54698SShawn Guo */ 609e149860dSRichard Zhu imx_data->scratchpad = val; 61069f54698SShawn Guo } 61195f25efeSWolfram Sang return; 61295f25efeSWolfram Sang case SDHCI_COMMAND: 613361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 61458ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 61595a2482aSShawn Guo 616361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 617f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 618361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 619361b8482SLucas Stach 6209d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 62195a2482aSShawn Guo writel(val << 16, 62295a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 62369f54698SShawn Guo else 624e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 62595f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 62695f25efeSWolfram Sang return; 62795f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 62895f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 62995f25efeSWolfram Sang break; 63095f25efeSWolfram Sang } 63195f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 63295f25efeSWolfram Sang } 63395f25efeSWolfram Sang 63477da3da0SAaron Brice static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 63577da3da0SAaron Brice { 63677da3da0SAaron Brice u8 ret; 63777da3da0SAaron Brice u32 val; 63877da3da0SAaron Brice 63977da3da0SAaron Brice switch (reg) { 64077da3da0SAaron Brice case SDHCI_HOST_CONTROL: 64177da3da0SAaron Brice val = readl(host->ioaddr + reg); 64277da3da0SAaron Brice 64377da3da0SAaron Brice ret = val & SDHCI_CTRL_LED; 64477da3da0SAaron Brice ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 64577da3da0SAaron Brice ret |= (val & ESDHC_CTRL_4BITBUS); 64677da3da0SAaron Brice ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 64777da3da0SAaron Brice return ret; 64877da3da0SAaron Brice } 64977da3da0SAaron Brice 65077da3da0SAaron Brice return readb(host->ioaddr + reg); 65177da3da0SAaron Brice } 65277da3da0SAaron Brice 65395f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 65495f25efeSWolfram Sang { 6559a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 656070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 65781a0a8bcSBenoît Thébaudeau u32 new_val = 0; 658af51079eSSascha Hauer u32 mask; 65995f25efeSWolfram Sang 66095f25efeSWolfram Sang switch (reg) { 66195f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 66295f25efeSWolfram Sang /* 66395f25efeSWolfram Sang * FSL put some DMA bits here 66495f25efeSWolfram Sang * If your board has a regulator, code should be here 66595f25efeSWolfram Sang */ 66695f25efeSWolfram Sang return; 66795f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 6686b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 669af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 6707122bbb0SMasanari Iida /* ensure the endianness */ 67195f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 6729a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 6739a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 67495f25efeSWolfram Sang /* DMA mode bits are shifted */ 67595f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 6769a0985b7SWilson Callan } 67795f25efeSWolfram Sang 678af51079eSSascha Hauer /* 679af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 680af51079eSSascha Hauer * esdhc_pltfm_bus_width. 681f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 682d04f8d5bSBenoît Thébaudeau * SDIO interrupt erratum workaround. 683af51079eSSascha Hauer */ 684f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 685af51079eSSascha Hauer 686af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 68795f25efeSWolfram Sang return; 68881a0a8bcSBenoît Thébaudeau case SDHCI_SOFTWARE_RESET: 68981a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_DATA) 69081a0a8bcSBenoît Thébaudeau new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 69181a0a8bcSBenoît Thébaudeau break; 69295f25efeSWolfram Sang } 69395f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 694913413c3SShawn Guo 69581a0a8bcSBenoît Thébaudeau if (reg == SDHCI_SOFTWARE_RESET) { 69681a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_ALL) { 697913413c3SShawn Guo /* 69881a0a8bcSBenoît Thébaudeau * The esdhc has a design violation to SDHC spec which 69981a0a8bcSBenoît Thébaudeau * tells that software reset should not affect card 70081a0a8bcSBenoît Thébaudeau * detection circuit. But esdhc clears its SYSCTL 70181a0a8bcSBenoît Thébaudeau * register bits [0..2] during the software reset. This 70281a0a8bcSBenoît Thébaudeau * will stop those clocks that card detection circuit 70381a0a8bcSBenoît Thébaudeau * relies on. To work around it, we turn the clocks on 70481a0a8bcSBenoît Thébaudeau * back to keep card detection circuit functional. 705913413c3SShawn Guo */ 706913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 70758c8c4fbSShawn Guo /* 70858c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 70958c8c4fbSShawn Guo * Do it manually here. 71058c8c4fbSShawn Guo */ 711de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 71281a0a8bcSBenoît Thébaudeau /* 71381a0a8bcSBenoît Thébaudeau * the tuning bits should be kept during reset 71481a0a8bcSBenoît Thébaudeau */ 715d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 716d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 717d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 718de5bdbffSDong Aisheng imx_data->is_ddr = 0; 719de5bdbffSDong Aisheng } 72081a0a8bcSBenoît Thébaudeau } else if (val & SDHCI_RESET_DATA) { 72181a0a8bcSBenoît Thébaudeau /* 72281a0a8bcSBenoît Thébaudeau * The eSDHC DAT line software reset clears at least the 72381a0a8bcSBenoît Thébaudeau * data transfer width on i.MX25, so make sure that the 72481a0a8bcSBenoît Thébaudeau * Host Control register is unaffected. 72581a0a8bcSBenoît Thébaudeau */ 72681a0a8bcSBenoît Thébaudeau esdhc_clrset_le(host, 0xff, new_val, 72781a0a8bcSBenoît Thébaudeau SDHCI_HOST_CONTROL); 72881a0a8bcSBenoît Thébaudeau } 72958c8c4fbSShawn Guo } 73095f25efeSWolfram Sang } 73195f25efeSWolfram Sang 7320ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 7330ddf03c9SLucas Stach { 7340ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 7350ddf03c9SLucas Stach 736a974862fSDong Aisheng return pltfm_host->clock; 7370ddf03c9SLucas Stach } 7380ddf03c9SLucas Stach 73995f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 74095f25efeSWolfram Sang { 74195f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 74295f25efeSWolfram Sang 743a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 74495f25efeSWolfram Sang } 74595f25efeSWolfram Sang 7468ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 7478ba9580aSLucas Stach unsigned int clock) 7488ba9580aSLucas Stach { 7498ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 750070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 751a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 7525143c953SBenoît Thébaudeau int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 7535143c953SBenoît Thébaudeau int pre_div = 1; 754d31fc00aSDong Aisheng int div = 1; 755fed2f6e2SDong Aisheng u32 temp, val; 7568ba9580aSLucas Stach 7579d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 758fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 759fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 760fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 761fed2f6e2SDong Aisheng } 76273e736f8SStefan Agner 76373e736f8SStefan Agner if (clock == 0) { 76473e736f8SStefan Agner host->mmc->actual_clock = 0; 765373073efSRussell King return; 766fed2f6e2SDong Aisheng } 767d31fc00aSDong Aisheng 768499ed50fSBenoît Thébaudeau /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 769499ed50fSBenoît Thébaudeau if (is_imx53_esdhc(imx_data)) { 770499ed50fSBenoît Thébaudeau /* 771499ed50fSBenoît Thébaudeau * According to the i.MX53 reference manual, if DLLCTRL[10] can 772499ed50fSBenoît Thébaudeau * be set, then the controller is eSDHCv3, else it is eSDHCv2. 773499ed50fSBenoît Thébaudeau */ 774499ed50fSBenoît Thébaudeau val = readl(host->ioaddr + ESDHC_DLL_CTRL); 775499ed50fSBenoît Thébaudeau writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 776499ed50fSBenoît Thébaudeau temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 777499ed50fSBenoît Thébaudeau writel(val, host->ioaddr + ESDHC_DLL_CTRL); 778499ed50fSBenoît Thébaudeau if (temp & BIT(10)) 779499ed50fSBenoît Thébaudeau pre_div = 2; 780499ed50fSBenoît Thébaudeau } 781499ed50fSBenoît Thébaudeau 782d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 783d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 784d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 785d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 786d31fc00aSDong Aisheng 787af6a50d4SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { 788af6a50d4SBOUGH CHEN unsigned int max_clock; 789af6a50d4SBOUGH CHEN 790af6a50d4SBOUGH CHEN max_clock = imx_data->is_ddr ? 45000000 : 150000000; 791af6a50d4SBOUGH CHEN 792af6a50d4SBOUGH CHEN clock = min(clock, max_clock); 793af6a50d4SBOUGH CHEN } 794af6a50d4SBOUGH CHEN 7955143c953SBenoît Thébaudeau while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 7965143c953SBenoît Thébaudeau pre_div < 256) 797d31fc00aSDong Aisheng pre_div *= 2; 798d31fc00aSDong Aisheng 7995143c953SBenoît Thébaudeau while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 800d31fc00aSDong Aisheng div++; 801d31fc00aSDong Aisheng 8025143c953SBenoît Thébaudeau host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 803d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 804e76b8559SDong Aisheng clock, host->mmc->actual_clock); 805d31fc00aSDong Aisheng 806d31fc00aSDong Aisheng pre_div >>= 1; 807d31fc00aSDong Aisheng div--; 808d31fc00aSDong Aisheng 809d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 810d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 811d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 812d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 813d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 814fed2f6e2SDong Aisheng 8159d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 816fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 817fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 818fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 819fed2f6e2SDong Aisheng } 820fed2f6e2SDong Aisheng 821d31fc00aSDong Aisheng mdelay(1); 8228ba9580aSLucas Stach } 8238ba9580aSLucas Stach 824913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 825913413c3SShawn Guo { 826842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 827070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 828842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 829913413c3SShawn Guo 830913413c3SShawn Guo switch (boarddata->wp_type) { 831913413c3SShawn Guo case ESDHC_WP_GPIO: 832fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 833913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 834913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 835913413c3SShawn Guo SDHCI_WRITE_PROTECT); 836913413c3SShawn Guo case ESDHC_WP_NONE: 837913413c3SShawn Guo break; 838913413c3SShawn Guo } 839913413c3SShawn Guo 840913413c3SShawn Guo return -ENOSYS; 841913413c3SShawn Guo } 842913413c3SShawn Guo 8432317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 844af51079eSSascha Hauer { 845af51079eSSascha Hauer u32 ctrl; 846af51079eSSascha Hauer 847af51079eSSascha Hauer switch (width) { 848af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 849af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 850af51079eSSascha Hauer break; 851af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 852af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 853af51079eSSascha Hauer break; 854af51079eSSascha Hauer default: 855af51079eSSascha Hauer ctrl = 0; 856af51079eSSascha Hauer break; 857af51079eSSascha Hauer } 858af51079eSSascha Hauer 859af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 860af51079eSSascha Hauer SDHCI_HOST_CONTROL); 861af51079eSSascha Hauer } 862af51079eSSascha Hauer 863de3e1dd0SBOUGH CHEN static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 864de3e1dd0SBOUGH CHEN { 865de3e1dd0SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 866de3e1dd0SBOUGH CHEN 867de3e1dd0SBOUGH CHEN /* 868de3e1dd0SBOUGH CHEN * i.MX uSDHC internally already uses a fixed optimized timing for 869de3e1dd0SBOUGH CHEN * DDR50, normally does not require tuning for DDR50 mode. 870de3e1dd0SBOUGH CHEN */ 871de3e1dd0SBOUGH CHEN if (host->timing == MMC_TIMING_UHS_DDR50) 872de3e1dd0SBOUGH CHEN return 0; 873de3e1dd0SBOUGH CHEN 874de3e1dd0SBOUGH CHEN return sdhci_execute_tuning(mmc, opcode); 875de3e1dd0SBOUGH CHEN } 876de3e1dd0SBOUGH CHEN 8770322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 8780322191eSDong Aisheng { 8790322191eSDong Aisheng u32 reg; 8800322191eSDong Aisheng 8810322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 8820322191eSDong Aisheng mdelay(1); 8830322191eSDong Aisheng 8840322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 8850322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 8860322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 8870322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 8880322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 8890322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 890d04f8d5bSBenoît Thébaudeau "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 8910322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 8920322191eSDong Aisheng } 8930322191eSDong Aisheng 8940322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 8950322191eSDong Aisheng { 8960322191eSDong Aisheng u32 reg; 8970322191eSDong Aisheng 8980322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 8990322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 900da0295ffSDong Aisheng reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 9010322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 9020322191eSDong Aisheng } 9030322191eSDong Aisheng 9040322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 9050322191eSDong Aisheng { 9060322191eSDong Aisheng int min, max, avg, ret; 9070322191eSDong Aisheng 9080322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 9090322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 9100322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 9110322191eSDong Aisheng esdhc_prepare_tuning(host, min); 9129979dbe5SChaotian Jing if (!mmc_send_tuning(host->mmc, opcode, NULL)) 9130322191eSDong Aisheng break; 9140322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 9150322191eSDong Aisheng } 9160322191eSDong Aisheng 9170322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 9180322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 9190322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 9200322191eSDong Aisheng esdhc_prepare_tuning(host, max); 9219979dbe5SChaotian Jing if (mmc_send_tuning(host->mmc, opcode, NULL)) { 9220322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 9230322191eSDong Aisheng break; 9240322191eSDong Aisheng } 9250322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 9260322191eSDong Aisheng } 9270322191eSDong Aisheng 9280322191eSDong Aisheng /* use average delay to get the best timing */ 9290322191eSDong Aisheng avg = (min + max) / 2; 9300322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 9319979dbe5SChaotian Jing ret = mmc_send_tuning(host->mmc, opcode, NULL); 9320322191eSDong Aisheng esdhc_post_tuning(host); 9330322191eSDong Aisheng 934d04f8d5bSBenoît Thébaudeau dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 9350322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 9360322191eSDong Aisheng 9370322191eSDong Aisheng return ret; 9380322191eSDong Aisheng } 9390322191eSDong Aisheng 940029e2476SBOUGH CHEN static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) 941029e2476SBOUGH CHEN { 942029e2476SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 943029e2476SBOUGH CHEN u32 m; 944029e2476SBOUGH CHEN 945029e2476SBOUGH CHEN m = readl(host->ioaddr + ESDHC_MIX_CTRL); 946029e2476SBOUGH CHEN if (ios->enhanced_strobe) 947029e2476SBOUGH CHEN m |= ESDHC_MIX_CTRL_HS400_ES_EN; 948029e2476SBOUGH CHEN else 949029e2476SBOUGH CHEN m &= ~ESDHC_MIX_CTRL_HS400_ES_EN; 950029e2476SBOUGH CHEN writel(m, host->ioaddr + ESDHC_MIX_CTRL); 951029e2476SBOUGH CHEN } 952029e2476SBOUGH CHEN 953ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 954ad93220dSDong Aisheng unsigned int uhs) 955ad93220dSDong Aisheng { 956ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 957070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 958ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 959ad93220dSDong Aisheng 960ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 961ad93220dSDong Aisheng 962ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 963ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 964ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 965ad93220dSDong Aisheng return -EINVAL; 966ad93220dSDong Aisheng 967ad93220dSDong Aisheng switch (uhs) { 968ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 9699f327845SHaibo Chen case MMC_TIMING_UHS_DDR50: 970ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 971ad93220dSDong Aisheng break; 972ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 973429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 97428b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 975ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 976ad93220dSDong Aisheng break; 977ad93220dSDong Aisheng default: 978ad93220dSDong Aisheng /* back to default state for other legacy timing */ 9792480b720SUlf Hansson return pinctrl_select_default_state(mmc_dev(host->mmc)); 980ad93220dSDong Aisheng } 981ad93220dSDong Aisheng 982ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 983ad93220dSDong Aisheng } 984ad93220dSDong Aisheng 98528b07674SHaibo Chen /* 986d04f8d5bSBenoît Thébaudeau * For HS400 eMMC, there is a data_strobe line. This signal is generated 98728b07674SHaibo Chen * by the device and used for data output and CRC status response output 98828b07674SHaibo Chen * in HS400 mode. The frequency of this signal follows the frequency of 989d04f8d5bSBenoît Thébaudeau * CLK generated by host. The host receives the data which is aligned to the 99028b07674SHaibo Chen * edge of data_strobe line. Due to the time delay between CLK line and 99128b07674SHaibo Chen * data_strobe line, if the delay time is larger than one clock cycle, 992d04f8d5bSBenoît Thébaudeau * then CLK and data_strobe line will be misaligned, read error shows up. 99328b07674SHaibo Chen */ 99428b07674SHaibo Chen static void esdhc_set_strobe_dll(struct sdhci_host *host) 99528b07674SHaibo Chen { 99628b07674SHaibo Chen u32 v; 99728b07674SHaibo Chen 9987ac6da26SDong Aisheng /* disable clock before enabling strobe dll */ 9997ac6da26SDong Aisheng writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 10007ac6da26SDong Aisheng ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 10017ac6da26SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 10027ac6da26SDong Aisheng 100328b07674SHaibo Chen /* force a reset on strobe dll */ 100428b07674SHaibo Chen writel(ESDHC_STROBE_DLL_CTRL_RESET, 100528b07674SHaibo Chen host->ioaddr + ESDHC_STROBE_DLL_CTRL); 10062eaf5a53SBOUGH CHEN /* clear the reset bit on strobe dll before any setting */ 10072eaf5a53SBOUGH CHEN writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 10082eaf5a53SBOUGH CHEN 100928b07674SHaibo Chen /* 101028b07674SHaibo Chen * enable strobe dll ctrl and adjust the delay target 101128b07674SHaibo Chen * for the uSDHC loopback read clock 101228b07674SHaibo Chen */ 101328b07674SHaibo Chen v = ESDHC_STROBE_DLL_CTRL_ENABLE | 10142eaf5a53SBOUGH CHEN ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | 101528b07674SHaibo Chen (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 101628b07674SHaibo Chen writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 10172eaf5a53SBOUGH CHEN /* wait 5us to make sure strobe dll status register stable */ 10182eaf5a53SBOUGH CHEN udelay(5); 101928b07674SHaibo Chen v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); 102028b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) 102128b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 102228b07674SHaibo Chen "warning! HS400 strobe DLL status REF not lock!\n"); 102328b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 102428b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 102528b07674SHaibo Chen "warning! HS400 strobe DLL status SLV not lock!\n"); 102628b07674SHaibo Chen } 102728b07674SHaibo Chen 1028d9370424SHaibo Chen static void esdhc_reset_tuning(struct sdhci_host *host) 1029d9370424SHaibo Chen { 1030d9370424SHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1031d9370424SHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1032d9370424SHaibo Chen u32 ctrl; 1033d9370424SHaibo Chen 1034d04f8d5bSBenoît Thébaudeau /* Reset the tuning circuit */ 1035d9370424SHaibo Chen if (esdhc_is_usdhc(imx_data)) { 1036d9370424SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1037d9370424SHaibo Chen ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1038d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1039d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1040d9370424SHaibo Chen writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1041d9370424SHaibo Chen writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1042d9370424SHaibo Chen } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1043869f8a69SAdrian Hunter ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1044d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1045869f8a69SAdrian Hunter writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1046d9370424SHaibo Chen } 1047d9370424SHaibo Chen } 1048d9370424SHaibo Chen } 1049d9370424SHaibo Chen 1050850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1051ad93220dSDong Aisheng { 105228b07674SHaibo Chen u32 m; 1053ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1054070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1055602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1056ad93220dSDong Aisheng 105728b07674SHaibo Chen /* disable ddr mode and disable HS400 mode */ 105828b07674SHaibo Chen m = readl(host->ioaddr + ESDHC_MIX_CTRL); 105928b07674SHaibo Chen m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 106028b07674SHaibo Chen imx_data->is_ddr = 0; 106128b07674SHaibo Chen 1062850a29b8SRussell King switch (timing) { 1063ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 1064ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 1065ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 1066ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 1067de0a0decSBOUGH CHEN case MMC_TIMING_MMC_HS: 1068429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 106928b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1070ad93220dSDong Aisheng break; 1071ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 107269f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 107328b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN; 107428b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1075de5bdbffSDong Aisheng imx_data->is_ddr = 1; 1076602519b2SDong Aisheng if (boarddata->delay_line) { 1077602519b2SDong Aisheng u32 v; 1078602519b2SDong Aisheng v = boarddata->delay_line << 1079602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 1080602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 1081602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 1082602519b2SDong Aisheng v <<= 1; 1083602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 1084602519b2SDong Aisheng } 1085ad93220dSDong Aisheng break; 108628b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 108728b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 108828b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 108928b07674SHaibo Chen imx_data->is_ddr = 1; 10907ac6da26SDong Aisheng /* update clock after enable DDR for strobe DLL lock */ 10917ac6da26SDong Aisheng host->ops->set_clock(host, host->clock); 109228b07674SHaibo Chen esdhc_set_strobe_dll(host); 109328b07674SHaibo Chen break; 1094d9370424SHaibo Chen case MMC_TIMING_LEGACY: 1095d9370424SHaibo Chen default: 1096d9370424SHaibo Chen esdhc_reset_tuning(host); 1097d9370424SHaibo Chen break; 1098ad93220dSDong Aisheng } 1099ad93220dSDong Aisheng 1100850a29b8SRussell King esdhc_change_pinstate(host, timing); 1101ad93220dSDong Aisheng } 1102ad93220dSDong Aisheng 11030718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 11040718e59aSRussell King { 11050718e59aSRussell King sdhci_reset(host, mask); 11060718e59aSRussell King 11070718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 11080718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 11090718e59aSRussell King } 11100718e59aSRussell King 111110fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 111210fd0ad9SAisheng Dong { 111310fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1114070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 111510fd0ad9SAisheng Dong 1116d04f8d5bSBenoît Thébaudeau /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 11172fb0b02bSHaibo Chen return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 111810fd0ad9SAisheng Dong } 111910fd0ad9SAisheng Dong 1120e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1121e33eb8e2SAisheng Dong { 1122e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1123070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1124e33eb8e2SAisheng Dong 1125e33eb8e2SAisheng Dong /* use maximum timeout counter */ 1126a215186dSHaibo Chen esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1127a215186dSHaibo Chen esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1128e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 1129e33eb8e2SAisheng Dong } 1130e33eb8e2SAisheng Dong 1131bb6e3581SBOUGH CHEN static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) 1132bb6e3581SBOUGH CHEN { 1133bb6e3581SBOUGH CHEN int cmd_error = 0; 1134bb6e3581SBOUGH CHEN int data_error = 0; 1135bb6e3581SBOUGH CHEN 1136bb6e3581SBOUGH CHEN if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1137bb6e3581SBOUGH CHEN return intmask; 1138bb6e3581SBOUGH CHEN 1139bb6e3581SBOUGH CHEN cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1140bb6e3581SBOUGH CHEN 1141bb6e3581SBOUGH CHEN return 0; 1142bb6e3581SBOUGH CHEN } 1143bb6e3581SBOUGH CHEN 11446e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 1145e149860dSRichard Zhu .read_l = esdhc_readl_le, 11460c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 114777da3da0SAaron Brice .read_b = esdhc_readb_le, 1148e149860dSRichard Zhu .write_l = esdhc_writel_le, 11490c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 11500c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 11518ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 11520ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 11530c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 115410fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 1155913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 1156e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 11572317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 1158ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 11590718e59aSRussell King .reset = esdhc_reset, 1160bb6e3581SBOUGH CHEN .irq = esdhc_cqhci_irq, 11610c6d49ceSWolfram Sang }; 11620c6d49ceSWolfram Sang 11631db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 116497e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 116597e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 116697e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 116785d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 116885d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 116985d6509dSShawn Guo }; 117085d6509dSShawn Guo 1171f3f5cf3dSDong Aisheng static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1172f3f5cf3dSDong Aisheng { 1173f3f5cf3dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1174f3f5cf3dSDong Aisheng struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 11752b16cf32SDong Aisheng int tmp; 1176f3f5cf3dSDong Aisheng 1177f3f5cf3dSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 1178f3f5cf3dSDong Aisheng /* 1179f3f5cf3dSDong Aisheng * The imx6q ROM code will change the default watermark 1180f3f5cf3dSDong Aisheng * level setting to something insane. Change it back here. 1181f3f5cf3dSDong Aisheng */ 1182f3f5cf3dSDong Aisheng writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1183f3f5cf3dSDong Aisheng 1184f3f5cf3dSDong Aisheng /* 1185f3f5cf3dSDong Aisheng * ROM code will change the bit burst_length_enable setting 1186d04f8d5bSBenoît Thébaudeau * to zero if this usdhc is chosen to boot system. Change 1187f3f5cf3dSDong Aisheng * it back here, otherwise it will impact the performance a 1188f3f5cf3dSDong Aisheng * lot. This bit is used to enable/disable the burst length 1189d04f8d5bSBenoît Thébaudeau * for the external AHB2AXI bridge. It's useful especially 1190f3f5cf3dSDong Aisheng * for INCR transfer because without burst length indicator, 1191f3f5cf3dSDong Aisheng * the AHB2AXI bridge does not know the burst length in 1192f3f5cf3dSDong Aisheng * advance. And without burst length indicator, AHB INCR 1193f3f5cf3dSDong Aisheng * transfer can only be converted to singles on the AXI side. 1194f3f5cf3dSDong Aisheng */ 1195f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1196f3f5cf3dSDong Aisheng | ESDHC_BURST_LEN_EN_INCR, 1197f3f5cf3dSDong Aisheng host->ioaddr + SDHCI_HOST_CONTROL); 1198e30be063SBOUGH CHEN 1199f3f5cf3dSDong Aisheng /* 1200d04f8d5bSBenoît Thébaudeau * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1201f3f5cf3dSDong Aisheng * TO1.1, it's harmless for MX6SL 1202f3f5cf3dSDong Aisheng */ 1203e30be063SBOUGH CHEN writel(readl(host->ioaddr + 0x6c) & ~BIT(7), 1204f3f5cf3dSDong Aisheng host->ioaddr + 0x6c); 1205f3f5cf3dSDong Aisheng 1206f3f5cf3dSDong Aisheng /* disable DLL_CTRL delay line settings */ 1207f3f5cf3dSDong Aisheng writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 12082b16cf32SDong Aisheng 1209bcdb5301SBOUGH CHEN /* 1210bcdb5301SBOUGH CHEN * For the case of command with busy, if set the bit 1211bcdb5301SBOUGH CHEN * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a 1212bcdb5301SBOUGH CHEN * transfer complete interrupt when busy is deasserted. 1213bcdb5301SBOUGH CHEN * When CQHCI use DCMD to send a CMD need R1b respons, 1214bcdb5301SBOUGH CHEN * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ, 1215bcdb5301SBOUGH CHEN * otherwise DCMD will always meet timeout waiting for 1216bcdb5301SBOUGH CHEN * hardware interrupt issue. 1217bcdb5301SBOUGH CHEN */ 1218bcdb5301SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1219bcdb5301SBOUGH CHEN tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); 1220bcdb5301SBOUGH CHEN tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ; 1221bcdb5301SBOUGH CHEN writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); 1222bcdb5301SBOUGH CHEN 1223bcdb5301SBOUGH CHEN host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1224bcdb5301SBOUGH CHEN } 1225bcdb5301SBOUGH CHEN 12262b16cf32SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 12272b16cf32SDong Aisheng tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 12282b16cf32SDong Aisheng tmp |= ESDHC_STD_TUNING_EN | 12292b16cf32SDong Aisheng ESDHC_TUNING_START_TAP_DEFAULT; 12302b16cf32SDong Aisheng if (imx_data->boarddata.tuning_start_tap) { 12312b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_START_TAP_MASK; 12322b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_start_tap; 12332b16cf32SDong Aisheng } 12342b16cf32SDong Aisheng 12352b16cf32SDong Aisheng if (imx_data->boarddata.tuning_step) { 12362b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_STEP_MASK; 12372b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_step 12382b16cf32SDong Aisheng << ESDHC_TUNING_STEP_SHIFT; 12392b16cf32SDong Aisheng } 12402b16cf32SDong Aisheng writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1241a98c557eSBOUGH CHEN } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1242a98c557eSBOUGH CHEN /* 1243a98c557eSBOUGH CHEN * ESDHC_STD_TUNING_EN may be configed in bootloader 1244a98c557eSBOUGH CHEN * or ROM code, so clear this bit here to make sure 1245a98c557eSBOUGH CHEN * the manual tuning can work. 1246a98c557eSBOUGH CHEN */ 1247a98c557eSBOUGH CHEN tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1248a98c557eSBOUGH CHEN tmp &= ~ESDHC_STD_TUNING_EN; 1249a98c557eSBOUGH CHEN writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 12502b16cf32SDong Aisheng } 1251f3f5cf3dSDong Aisheng } 1252f3f5cf3dSDong Aisheng } 1253f3f5cf3dSDong Aisheng 1254bb6e3581SBOUGH CHEN static void esdhc_cqe_enable(struct mmc_host *mmc) 1255bb6e3581SBOUGH CHEN { 1256bb6e3581SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 125785236d2bSBOUGH CHEN struct cqhci_host *cq_host = mmc->cqe_private; 1258bb6e3581SBOUGH CHEN u32 reg; 1259bb6e3581SBOUGH CHEN u16 mode; 1260bb6e3581SBOUGH CHEN int count = 10; 1261bb6e3581SBOUGH CHEN 1262bb6e3581SBOUGH CHEN /* 1263bb6e3581SBOUGH CHEN * CQE gets stuck if it sees Buffer Read Enable bit set, which can be 1264bb6e3581SBOUGH CHEN * the case after tuning, so ensure the buffer is drained. 1265bb6e3581SBOUGH CHEN */ 1266bb6e3581SBOUGH CHEN reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1267bb6e3581SBOUGH CHEN while (reg & SDHCI_DATA_AVAILABLE) { 1268bb6e3581SBOUGH CHEN sdhci_readl(host, SDHCI_BUFFER); 1269bb6e3581SBOUGH CHEN reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1270bb6e3581SBOUGH CHEN if (count-- == 0) { 1271bb6e3581SBOUGH CHEN dev_warn(mmc_dev(host->mmc), 1272bb6e3581SBOUGH CHEN "CQE may get stuck because the Buffer Read Enable bit is set\n"); 1273bb6e3581SBOUGH CHEN break; 1274bb6e3581SBOUGH CHEN } 1275bb6e3581SBOUGH CHEN mdelay(1); 1276bb6e3581SBOUGH CHEN } 1277bb6e3581SBOUGH CHEN 1278bb6e3581SBOUGH CHEN /* 1279bb6e3581SBOUGH CHEN * Runtime resume will reset the entire host controller, which 1280bb6e3581SBOUGH CHEN * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL. 1281bb6e3581SBOUGH CHEN * Here set DMAEN and BCEN when enable CMDQ. 1282bb6e3581SBOUGH CHEN */ 1283bb6e3581SBOUGH CHEN mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 1284bb6e3581SBOUGH CHEN if (host->flags & SDHCI_REQ_USE_DMA) 1285bb6e3581SBOUGH CHEN mode |= SDHCI_TRNS_DMA; 1286bb6e3581SBOUGH CHEN if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 1287bb6e3581SBOUGH CHEN mode |= SDHCI_TRNS_BLK_CNT_EN; 1288bb6e3581SBOUGH CHEN sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 1289bb6e3581SBOUGH CHEN 129085236d2bSBOUGH CHEN /* 129185236d2bSBOUGH CHEN * Though Runtime resume reset the entire host controller, 129285236d2bSBOUGH CHEN * but do not impact the CQHCI side, need to clear the 129385236d2bSBOUGH CHEN * HALT bit, avoid CQHCI stuck in the first request when 129485236d2bSBOUGH CHEN * system resume back. 129585236d2bSBOUGH CHEN */ 129685236d2bSBOUGH CHEN cqhci_writel(cq_host, 0, CQHCI_CTL); 129785236d2bSBOUGH CHEN if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT) 129885236d2bSBOUGH CHEN dev_err(mmc_dev(host->mmc), 129985236d2bSBOUGH CHEN "failed to exit halt state when enable CQE\n"); 130085236d2bSBOUGH CHEN 130185236d2bSBOUGH CHEN 1302bb6e3581SBOUGH CHEN sdhci_cqe_enable(mmc); 1303bb6e3581SBOUGH CHEN } 1304bb6e3581SBOUGH CHEN 1305bb6e3581SBOUGH CHEN static void esdhc_sdhci_dumpregs(struct mmc_host *mmc) 1306bb6e3581SBOUGH CHEN { 1307bb6e3581SBOUGH CHEN sdhci_dumpregs(mmc_priv(mmc)); 1308bb6e3581SBOUGH CHEN } 1309bb6e3581SBOUGH CHEN 1310bb6e3581SBOUGH CHEN static const struct cqhci_host_ops esdhc_cqhci_ops = { 1311bb6e3581SBOUGH CHEN .enable = esdhc_cqe_enable, 1312bb6e3581SBOUGH CHEN .disable = sdhci_cqe_disable, 1313bb6e3581SBOUGH CHEN .dumpregs = esdhc_sdhci_dumpregs, 1314bb6e3581SBOUGH CHEN }; 1315bb6e3581SBOUGH CHEN 1316abfafc2dSShawn Guo #ifdef CONFIG_OF 1317c3be1efdSBill Pemberton static int 1318abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 131907bf2b54SSascha Hauer struct sdhci_host *host, 132091fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1321abfafc2dSShawn Guo { 1322abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 132391fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 13244800e87aSDong Aisheng int ret; 1325abfafc2dSShawn Guo 1326abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 1327abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 1328abfafc2dSShawn Guo 132974ff81e1SLinus Walleij /* 133074ff81e1SLinus Walleij * If we have this property, then activate WP check. 133174ff81e1SLinus Walleij * Retrieveing and requesting the actual WP GPIO will happen 133274ff81e1SLinus Walleij * in the call to mmc_of_parse(). 133374ff81e1SLinus Walleij */ 133474ff81e1SLinus Walleij if (of_property_read_bool(np, "wp-gpios")) 1335abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 1336abfafc2dSShawn Guo 1337d407e30bSHaibo Chen of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1338d87fc966SDong Aisheng of_property_read_u32(np, "fsl,tuning-start-tap", 1339d87fc966SDong Aisheng &boarddata->tuning_start_tap); 1340d407e30bSHaibo Chen 1341ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 134286f495c5SStefan Agner host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1343ad93220dSDong Aisheng 1344602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1345602519b2SDong Aisheng boarddata->delay_line = 0; 1346602519b2SDong Aisheng 134707bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 134807bf2b54SSascha Hauer 13492480b720SUlf Hansson if (esdhc_is_usdhc(imx_data)) { 135091fa4252SDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 135191fa4252SDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 135291fa4252SDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 135391fa4252SDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 135491fa4252SDong Aisheng } 135591fa4252SDong Aisheng 135615064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 13574800e87aSDong Aisheng ret = mmc_of_parse(host->mmc); 13584800e87aSDong Aisheng if (ret) 13594800e87aSDong Aisheng return ret; 13604800e87aSDong Aisheng 1361287980e4SArnd Bergmann if (mmc_gpio_get_cd(host->mmc) >= 0) 13624800e87aSDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 13634800e87aSDong Aisheng 13644800e87aSDong Aisheng return 0; 1365abfafc2dSShawn Guo } 1366abfafc2dSShawn Guo #else 1367abfafc2dSShawn Guo static inline int 1368abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 136907bf2b54SSascha Hauer struct sdhci_host *host, 137091fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1371abfafc2dSShawn Guo { 1372abfafc2dSShawn Guo return -ENODEV; 1373abfafc2dSShawn Guo } 1374abfafc2dSShawn Guo #endif 1375abfafc2dSShawn Guo 137691fa4252SDong Aisheng static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 137791fa4252SDong Aisheng struct sdhci_host *host, 137891fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 137991fa4252SDong Aisheng { 138091fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 138191fa4252SDong Aisheng int err; 138291fa4252SDong Aisheng 138391fa4252SDong Aisheng if (!host->mmc->parent->platform_data) { 138491fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), "no board data!\n"); 138591fa4252SDong Aisheng return -EINVAL; 138691fa4252SDong Aisheng } 138791fa4252SDong Aisheng 138891fa4252SDong Aisheng imx_data->boarddata = *((struct esdhc_platform_data *) 138991fa4252SDong Aisheng host->mmc->parent->platform_data); 139091fa4252SDong Aisheng /* write_protect */ 139191fa4252SDong Aisheng if (boarddata->wp_type == ESDHC_WP_GPIO) { 13929073d10bSMichał Mirosław host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 13939073d10bSMichał Mirosław 1394d0052ad9SMichał Mirosław err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0); 139591fa4252SDong Aisheng if (err) { 139691fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 139791fa4252SDong Aisheng "failed to request write-protect gpio!\n"); 139891fa4252SDong Aisheng return err; 139991fa4252SDong Aisheng } 140091fa4252SDong Aisheng } 140191fa4252SDong Aisheng 140291fa4252SDong Aisheng /* card_detect */ 140391fa4252SDong Aisheng switch (boarddata->cd_type) { 140491fa4252SDong Aisheng case ESDHC_CD_GPIO: 1405d0052ad9SMichał Mirosław err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0); 140691fa4252SDong Aisheng if (err) { 140791fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 140891fa4252SDong Aisheng "failed to request card-detect gpio!\n"); 140991fa4252SDong Aisheng return err; 141091fa4252SDong Aisheng } 141191fa4252SDong Aisheng /* fall through */ 141291fa4252SDong Aisheng 141391fa4252SDong Aisheng case ESDHC_CD_CONTROLLER: 141491fa4252SDong Aisheng /* we have a working card_detect back */ 141591fa4252SDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 141691fa4252SDong Aisheng break; 141791fa4252SDong Aisheng 141891fa4252SDong Aisheng case ESDHC_CD_PERMANENT: 141991fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 142091fa4252SDong Aisheng break; 142191fa4252SDong Aisheng 142291fa4252SDong Aisheng case ESDHC_CD_NONE: 142391fa4252SDong Aisheng break; 142491fa4252SDong Aisheng } 142591fa4252SDong Aisheng 142691fa4252SDong Aisheng switch (boarddata->max_bus_width) { 142791fa4252SDong Aisheng case 8: 142891fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 142991fa4252SDong Aisheng break; 143091fa4252SDong Aisheng case 4: 143191fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_4_BIT_DATA; 143291fa4252SDong Aisheng break; 143391fa4252SDong Aisheng case 1: 143491fa4252SDong Aisheng default: 143591fa4252SDong Aisheng host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 143691fa4252SDong Aisheng break; 143791fa4252SDong Aisheng } 143891fa4252SDong Aisheng 143991fa4252SDong Aisheng return 0; 144091fa4252SDong Aisheng } 144191fa4252SDong Aisheng 1442c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 144395f25efeSWolfram Sang { 1444abfafc2dSShawn Guo const struct of_device_id *of_id = 1445abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 144685d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 144785d6509dSShawn Guo struct sdhci_host *host; 1448bb6e3581SBOUGH CHEN struct cqhci_host *cq_host; 14490c6d49ceSWolfram Sang int err; 1450e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 145195f25efeSWolfram Sang 1452070e6d3fSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1453070e6d3fSJisheng Zhang sizeof(*imx_data)); 145485d6509dSShawn Guo if (IS_ERR(host)) 145585d6509dSShawn Guo return PTR_ERR(host); 145685d6509dSShawn Guo 145785d6509dSShawn Guo pltfm_host = sdhci_priv(host); 145885d6509dSShawn Guo 1459070e6d3fSJisheng Zhang imx_data = sdhci_pltfm_priv(pltfm_host); 146057ed3314SShawn Guo 1461f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 14623770ee8fSShawn Guo pdev->id_entry->driver_data; 146385d6509dSShawn Guo 14641c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 14651c4989b0SBOUGH CHEN pm_qos_add_request(&imx_data->pm_qos_req, 14661c4989b0SBOUGH CHEN PM_QOS_CPU_DMA_LATENCY, 0); 14671c4989b0SBOUGH CHEN 146852dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 146952dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 147052dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 1471e3af31c6SShawn Guo goto free_sdhci; 147295f25efeSWolfram Sang } 147352dac615SSascha Hauer 147452dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 147552dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 147652dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 1477e3af31c6SShawn Guo goto free_sdhci; 147852dac615SSascha Hauer } 147952dac615SSascha Hauer 148052dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 148152dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 148252dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 1483e3af31c6SShawn Guo goto free_sdhci; 148452dac615SSascha Hauer } 148552dac615SSascha Hauer 148652dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 1487a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 148817b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 148917b1eb7fSFabio Estevam if (err) 149017b1eb7fSFabio Estevam goto free_sdhci; 149117b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 149217b1eb7fSFabio Estevam if (err) 149317b1eb7fSFabio Estevam goto disable_per_clk; 149417b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ahb); 149517b1eb7fSFabio Estevam if (err) 149617b1eb7fSFabio Estevam goto disable_ipg_clk; 149795f25efeSWolfram Sang 1498ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1499e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1500e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 1501b62eee9fSHaibo Chen dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); 1502e62d8b8fSDong Aisheng } 1503e62d8b8fSDong Aisheng 150469ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 150569ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 150609c8192bSStefan Agner host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 15074245afffSDong Aisheng if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 15084245afffSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1509a75dcbf4SDong Aisheng 1510a75dcbf4SDong Aisheng /* clear tuning bits in case ROM has set it already */ 1511a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1512869f8a69SAdrian Hunter writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1513a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1514de3e1dd0SBOUGH CHEN 1515de3e1dd0SBOUGH CHEN /* 1516de3e1dd0SBOUGH CHEN * Link usdhc specific mmc_host_ops execute_tuning function, 1517de3e1dd0SBOUGH CHEN * to replace the standard one in sdhci_ops. 1518de3e1dd0SBOUGH CHEN */ 1519de3e1dd0SBOUGH CHEN host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; 152069ed60e0SDong Aisheng } 1521f750ba9bSShawn Guo 15226e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 15236e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 15246e9fd28eSDong Aisheng esdhc_executing_tuning; 15258b2bb0adSDong Aisheng 152618094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 152718094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 152818094430SDong Aisheng 152928b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 153028b07674SHaibo Chen host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 153128b07674SHaibo Chen 1532029e2476SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { 1533029e2476SBOUGH CHEN host->mmc->caps2 |= MMC_CAP2_HS400_ES; 1534029e2476SBOUGH CHEN host->mmc_host_ops.hs400_enhanced_strobe = 1535029e2476SBOUGH CHEN esdhc_hs400_enhanced_strobe; 1536029e2476SBOUGH CHEN } 1537029e2476SBOUGH CHEN 1538bb6e3581SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1539bcdb5301SBOUGH CHEN host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1540bb6e3581SBOUGH CHEN cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 15419a633f3bSWei Yongjun if (!cq_host) { 15429a633f3bSWei Yongjun err = -ENOMEM; 1543bb6e3581SBOUGH CHEN goto disable_ahb_clk; 1544bb6e3581SBOUGH CHEN } 1545bb6e3581SBOUGH CHEN 1546bb6e3581SBOUGH CHEN cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; 1547bb6e3581SBOUGH CHEN cq_host->ops = &esdhc_cqhci_ops; 1548bb6e3581SBOUGH CHEN 1549bb6e3581SBOUGH CHEN err = cqhci_init(cq_host, host->mmc, false); 1550bb6e3581SBOUGH CHEN if (err) 1551bb6e3581SBOUGH CHEN goto disable_ahb_clk; 1552bb6e3581SBOUGH CHEN } 1553bb6e3581SBOUGH CHEN 155491fa4252SDong Aisheng if (of_id) 155591fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 155691fa4252SDong Aisheng else 155791fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 155891fa4252SDong Aisheng if (err) 155917b1eb7fSFabio Estevam goto disable_ahb_clk; 1560ad93220dSDong Aisheng 1561d00ab101SBOUGH CHEN host->tuning_delay = 1; 1562d00ab101SBOUGH CHEN 1563f3f5cf3dSDong Aisheng sdhci_esdhc_imx_hwinit(host); 1564f3f5cf3dSDong Aisheng 156585d6509dSShawn Guo err = sdhci_add_host(host); 156685d6509dSShawn Guo if (err) 156717b1eb7fSFabio Estevam goto disable_ahb_clk; 156885d6509dSShawn Guo 156989d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 157089d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 157189d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 157289d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 157377903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 157489d7e5c1SDong Aisheng 15757e29c306SWolfram Sang return 0; 15767e29c306SWolfram Sang 157717b1eb7fSFabio Estevam disable_ahb_clk: 157852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 157917b1eb7fSFabio Estevam disable_ipg_clk: 158017b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 158117b1eb7fSFabio Estevam disable_per_clk: 158217b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1583e3af31c6SShawn Guo free_sdhci: 15841c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 15851c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 158685d6509dSShawn Guo sdhci_pltfm_free(pdev); 158785d6509dSShawn Guo return err; 158895f25efeSWolfram Sang } 158995f25efeSWolfram Sang 15906e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 159195f25efeSWolfram Sang { 159285d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 159395f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1594070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 159585d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 159685d6509dSShawn Guo 15970b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 15980b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 15990b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 16000b414368SUlf Hansson 160185d6509dSShawn Guo sdhci_remove_host(host, dead); 16020c6d49ceSWolfram Sang 160352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 160452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 160552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 160652dac615SSascha Hauer 16071c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 16081c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 16091c4989b0SBOUGH CHEN 161085d6509dSShawn Guo sdhci_pltfm_free(pdev); 161185d6509dSShawn Guo 161285d6509dSShawn Guo return 0; 161395f25efeSWolfram Sang } 161495f25efeSWolfram Sang 16152788ed42SUlf Hansson #ifdef CONFIG_PM_SLEEP 161604143fbaSDong Aisheng static int sdhci_esdhc_suspend(struct device *dev) 161704143fbaSDong Aisheng { 16183e3274abSUlf Hansson struct sdhci_host *host = dev_get_drvdata(dev); 1619a26a4f1bSHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1620a26a4f1bSHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1621bb6e3581SBOUGH CHEN int ret; 1622bb6e3581SBOUGH CHEN 1623bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) { 1624bb6e3581SBOUGH CHEN ret = cqhci_suspend(host->mmc); 1625bb6e3581SBOUGH CHEN if (ret) 1626bb6e3581SBOUGH CHEN return ret; 1627bb6e3581SBOUGH CHEN } 16283e3274abSUlf Hansson 1629a26a4f1bSHaibo Chen if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && 1630a26a4f1bSHaibo Chen (host->tuning_mode != SDHCI_TUNING_MODE_1)) { 1631a26a4f1bSHaibo Chen mmc_retune_timer_stop(host->mmc); 1632a26a4f1bSHaibo Chen mmc_retune_needed(host->mmc); 1633a26a4f1bSHaibo Chen } 1634a26a4f1bSHaibo Chen 1635d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1636d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1637d38dcad4SAdrian Hunter 16383e3274abSUlf Hansson return sdhci_suspend_host(host); 163904143fbaSDong Aisheng } 164004143fbaSDong Aisheng 164104143fbaSDong Aisheng static int sdhci_esdhc_resume(struct device *dev) 164204143fbaSDong Aisheng { 1643cc17e129SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 1644bb6e3581SBOUGH CHEN int ret; 1645cc17e129SDong Aisheng 164619dbfdd3SDong Aisheng /* re-initialize hw state in case it's lost in low power mode */ 164719dbfdd3SDong Aisheng sdhci_esdhc_imx_hwinit(host); 1648cc17e129SDong Aisheng 1649bb6e3581SBOUGH CHEN ret = sdhci_resume_host(host); 1650bb6e3581SBOUGH CHEN if (ret) 1651bb6e3581SBOUGH CHEN return ret; 1652bb6e3581SBOUGH CHEN 1653bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) 1654bb6e3581SBOUGH CHEN ret = cqhci_resume(host->mmc); 1655bb6e3581SBOUGH CHEN 1656bb6e3581SBOUGH CHEN return ret; 165704143fbaSDong Aisheng } 16582788ed42SUlf Hansson #endif 165904143fbaSDong Aisheng 16602788ed42SUlf Hansson #ifdef CONFIG_PM 166189d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 166289d7e5c1SDong Aisheng { 166389d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 166489d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1665070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 166689d7e5c1SDong Aisheng int ret; 166789d7e5c1SDong Aisheng 1668bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) { 1669bb6e3581SBOUGH CHEN ret = cqhci_suspend(host->mmc); 1670bb6e3581SBOUGH CHEN if (ret) 1671bb6e3581SBOUGH CHEN return ret; 1672bb6e3581SBOUGH CHEN } 1673bb6e3581SBOUGH CHEN 167489d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 1675371d39faSMichael Trimarchi if (ret) 1676371d39faSMichael Trimarchi return ret; 167789d7e5c1SDong Aisheng 1678d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1679d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1680d38dcad4SAdrian Hunter 16813602785bSMichael Trimarchi imx_data->actual_clock = host->mmc->actual_clock; 16823602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, 0); 168389d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 168489d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 168589d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 168689d7e5c1SDong Aisheng 16871c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 16881c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 16891c4989b0SBOUGH CHEN 169089d7e5c1SDong Aisheng return ret; 169189d7e5c1SDong Aisheng } 169289d7e5c1SDong Aisheng 169389d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 169489d7e5c1SDong Aisheng { 169589d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 169689d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1697070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 169817b1eb7fSFabio Estevam int err; 169989d7e5c1SDong Aisheng 17001c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 17011c4989b0SBOUGH CHEN pm_qos_add_request(&imx_data->pm_qos_req, 17021c4989b0SBOUGH CHEN PM_QOS_CPU_DMA_LATENCY, 0); 17031c4989b0SBOUGH CHEN 17045c11f1ffSHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) 17055c11f1ffSHaibo Chen clk_set_rate(imx_data->clk_per, pltfm_host->clock); 17065c11f1ffSHaibo Chen 1707a0ad3087SMichael Trimarchi err = clk_prepare_enable(imx_data->clk_ahb); 1708a0ad3087SMichael Trimarchi if (err) 17091c4989b0SBOUGH CHEN goto remove_pm_qos_request; 1710a0ad3087SMichael Trimarchi 171117b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 171217b1eb7fSFabio Estevam if (err) 1713a0ad3087SMichael Trimarchi goto disable_ahb_clk; 1714af5d2b7bSUlf Hansson 171517b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 171617b1eb7fSFabio Estevam if (err) 171717b1eb7fSFabio Estevam goto disable_per_clk; 1718af5d2b7bSUlf Hansson 17193602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1720a0ad3087SMichael Trimarchi 1721c6303c5dSBaolin Wang err = sdhci_runtime_resume_host(host, 0); 172217b1eb7fSFabio Estevam if (err) 1723a0ad3087SMichael Trimarchi goto disable_ipg_clk; 172489d7e5c1SDong Aisheng 1725bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) 1726bb6e3581SBOUGH CHEN err = cqhci_resume(host->mmc); 1727bb6e3581SBOUGH CHEN 1728bb6e3581SBOUGH CHEN return err; 172917b1eb7fSFabio Estevam 173017b1eb7fSFabio Estevam disable_ipg_clk: 173117b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 173217b1eb7fSFabio Estevam disable_per_clk: 173317b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1734a0ad3087SMichael Trimarchi disable_ahb_clk: 1735a0ad3087SMichael Trimarchi clk_disable_unprepare(imx_data->clk_ahb); 17361c4989b0SBOUGH CHEN remove_pm_qos_request: 17371c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 17381c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 173917b1eb7fSFabio Estevam return err; 174089d7e5c1SDong Aisheng } 174189d7e5c1SDong Aisheng #endif 174289d7e5c1SDong Aisheng 174389d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 174404143fbaSDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 174589d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 174689d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 174789d7e5c1SDong Aisheng }; 174889d7e5c1SDong Aisheng 174985d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 175085d6509dSShawn Guo .driver = { 175185d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1752abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 175389d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 175485d6509dSShawn Guo }, 175557ed3314SShawn Guo .id_table = imx_esdhc_devtype, 175685d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 17570433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 175895f25efeSWolfram Sang }; 175985d6509dSShawn Guo 1760d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 176185d6509dSShawn Guo 176285d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1763035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 176485d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1765