195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 795f25efeSWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24abfafc2dSShawn Guo #include <linux/of.h> 25abfafc2dSShawn Guo #include <linux/of_device.h> 26abfafc2dSShawn Guo #include <linux/of_gpio.h> 270c6d49ceSWolfram Sang #include <mach/esdhc.h> 2895f25efeSWolfram Sang #include "sdhci-pltfm.h" 2995f25efeSWolfram Sang #include "sdhci-esdhc.h" 3095f25efeSWolfram Sang 310d58864bSTony Lin #define SDHCI_CTRL_D3CD 0x08 3258ac8177SRichard Zhu /* VENDOR SPEC register */ 3358ac8177SRichard Zhu #define SDHCI_VENDOR_SPEC 0xC0 3458ac8177SRichard Zhu #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002 35f750ba9bSShawn Guo #define SDHCI_WTMK_LVL 0x44 3695a2482aSShawn Guo #define SDHCI_MIX_CTRL 0x48 3758ac8177SRichard Zhu 3858ac8177SRichard Zhu /* 3997e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 4097e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 4197e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 4297e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 4397e4ba6aSRichard Zhu */ 4497e4ba6aSRichard Zhu #define SDHCI_INT_VENDOR_SPEC_DMA_ERR 0x10000000 4597e4ba6aSRichard Zhu 4697e4ba6aSRichard Zhu /* 4758ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 4858ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 4958ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 5058ac8177SRichard Zhu * be generated. 5158ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 5258ac8177SRichard Zhu * operations automatically as required at the end of the 5358ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 5458ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 5558ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 5658ac8177SRichard Zhu */ 5758ac8177SRichard Zhu #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1) 58e149860dSRichard Zhu 5957ed3314SShawn Guo enum imx_esdhc_type { 6057ed3314SShawn Guo IMX25_ESDHC, 6157ed3314SShawn Guo IMX35_ESDHC, 6257ed3314SShawn Guo IMX51_ESDHC, 6357ed3314SShawn Guo IMX53_ESDHC, 6495a2482aSShawn Guo IMX6Q_USDHC, 6557ed3314SShawn Guo }; 6657ed3314SShawn Guo 67e149860dSRichard Zhu struct pltfm_imx_data { 68e149860dSRichard Zhu int flags; 69e149860dSRichard Zhu u32 scratchpad; 7057ed3314SShawn Guo enum imx_esdhc_type devtype; 71842afc02SShawn Guo struct esdhc_platform_data boarddata; 7252dac615SSascha Hauer struct clk *clk_ipg; 7352dac615SSascha Hauer struct clk *clk_ahb; 7452dac615SSascha Hauer struct clk *clk_per; 75e149860dSRichard Zhu }; 76e149860dSRichard Zhu 7757ed3314SShawn Guo static struct platform_device_id imx_esdhc_devtype[] = { 7857ed3314SShawn Guo { 7957ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 8057ed3314SShawn Guo .driver_data = IMX25_ESDHC, 8157ed3314SShawn Guo }, { 8257ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 8357ed3314SShawn Guo .driver_data = IMX35_ESDHC, 8457ed3314SShawn Guo }, { 8557ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 8657ed3314SShawn Guo .driver_data = IMX51_ESDHC, 8757ed3314SShawn Guo }, { 8857ed3314SShawn Guo .name = "sdhci-esdhc-imx53", 8957ed3314SShawn Guo .driver_data = IMX53_ESDHC, 9057ed3314SShawn Guo }, { 9195a2482aSShawn Guo .name = "sdhci-usdhc-imx6q", 9295a2482aSShawn Guo .driver_data = IMX6Q_USDHC, 9395a2482aSShawn Guo }, { 9457ed3314SShawn Guo /* sentinel */ 9557ed3314SShawn Guo } 9657ed3314SShawn Guo }; 9757ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 9857ed3314SShawn Guo 99abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 100abfafc2dSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], }, 101abfafc2dSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], }, 102abfafc2dSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], }, 103abfafc2dSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], }, 10495a2482aSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], }, 105abfafc2dSShawn Guo { /* sentinel */ } 106abfafc2dSShawn Guo }; 107abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 108abfafc2dSShawn Guo 10957ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 11057ed3314SShawn Guo { 11157ed3314SShawn Guo return data->devtype == IMX25_ESDHC; 11257ed3314SShawn Guo } 11357ed3314SShawn Guo 11457ed3314SShawn Guo static inline int is_imx35_esdhc(struct pltfm_imx_data *data) 11557ed3314SShawn Guo { 11657ed3314SShawn Guo return data->devtype == IMX35_ESDHC; 11757ed3314SShawn Guo } 11857ed3314SShawn Guo 11957ed3314SShawn Guo static inline int is_imx51_esdhc(struct pltfm_imx_data *data) 12057ed3314SShawn Guo { 12157ed3314SShawn Guo return data->devtype == IMX51_ESDHC; 12257ed3314SShawn Guo } 12357ed3314SShawn Guo 12457ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 12557ed3314SShawn Guo { 12657ed3314SShawn Guo return data->devtype == IMX53_ESDHC; 12757ed3314SShawn Guo } 12857ed3314SShawn Guo 12995a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 13095a2482aSShawn Guo { 13195a2482aSShawn Guo return data->devtype == IMX6Q_USDHC; 13295a2482aSShawn Guo } 13395a2482aSShawn Guo 13495f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 13595f25efeSWolfram Sang { 13695f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 13795f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 13895f25efeSWolfram Sang 13995f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 14095f25efeSWolfram Sang } 14195f25efeSWolfram Sang 1427e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 1437e29c306SWolfram Sang { 144842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 145842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 146842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1477e29c306SWolfram Sang 148913413c3SShawn Guo /* fake CARD_PRESENT flag */ 149913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 150913413c3SShawn Guo 151913413c3SShawn Guo if (unlikely((reg == SDHCI_PRESENT_STATE) 152913413c3SShawn Guo && gpio_is_valid(boarddata->cd_gpio))) { 153913413c3SShawn Guo if (gpio_get_value(boarddata->cd_gpio)) 1547e29c306SWolfram Sang /* no card, if a valid gpio says so... */ 155803862a6SShawn Guo val &= ~SDHCI_CARD_PRESENT; 1567e29c306SWolfram Sang else 1577e29c306SWolfram Sang /* ... in all other cases assume card is present */ 1587e29c306SWolfram Sang val |= SDHCI_CARD_PRESENT; 1597e29c306SWolfram Sang } 1607e29c306SWolfram Sang 16197e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 16297e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 16397e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 16497e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 16597e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 16697e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 16797e4ba6aSRichard Zhu */ 16897e4ba6aSRichard Zhu 16997e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 17097e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 17197e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 17297e4ba6aSRichard Zhu } 17397e4ba6aSRichard Zhu } 17497e4ba6aSRichard Zhu 17597e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 17697e4ba6aSRichard Zhu if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) { 17797e4ba6aSRichard Zhu val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR; 17897e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 17997e4ba6aSRichard Zhu } 18097e4ba6aSRichard Zhu } 18197e4ba6aSRichard Zhu 1827e29c306SWolfram Sang return val; 1837e29c306SWolfram Sang } 1847e29c306SWolfram Sang 1857e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 1867e29c306SWolfram Sang { 187e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 188e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 189842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1900d58864bSTony Lin u32 data; 191e149860dSRichard Zhu 1920d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 1930d58864bSTony Lin if (boarddata->cd_type == ESDHC_CD_GPIO) 1947e29c306SWolfram Sang /* 1950d58864bSTony Lin * These interrupts won't work with a custom 1960d58864bSTony Lin * card_detect gpio (only applied to mx25/35) 1977e29c306SWolfram Sang */ 1987e29c306SWolfram Sang val &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 1997e29c306SWolfram Sang 2000d58864bSTony Lin if (val & SDHCI_INT_CARD_INT) { 2010d58864bSTony Lin /* 2020d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 2030d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 2040d58864bSTony Lin * so we need to apply the following workaround: clear 2050d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 2060d58864bSTony Lin * interrupt. In case a card interrupt was lost, 2070d58864bSTony Lin * re-sample it by the following steps. 2080d58864bSTony Lin */ 2090d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 2100d58864bSTony Lin data &= ~SDHCI_CTRL_D3CD; 2110d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 2120d58864bSTony Lin data |= SDHCI_CTRL_D3CD; 2130d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 2140d58864bSTony Lin } 2150d58864bSTony Lin } 2160d58864bSTony Lin 21758ac8177SRichard Zhu if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 21858ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 21958ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 22058ac8177SRichard Zhu u32 v; 22158ac8177SRichard Zhu v = readl(host->ioaddr + SDHCI_VENDOR_SPEC); 22258ac8177SRichard Zhu v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK; 22358ac8177SRichard Zhu writel(v, host->ioaddr + SDHCI_VENDOR_SPEC); 22458ac8177SRichard Zhu } 22558ac8177SRichard Zhu 22697e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 22797e4ba6aSRichard Zhu if (val & SDHCI_INT_ADMA_ERROR) { 22897e4ba6aSRichard Zhu val &= ~SDHCI_INT_ADMA_ERROR; 22997e4ba6aSRichard Zhu val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR; 23097e4ba6aSRichard Zhu } 23197e4ba6aSRichard Zhu } 23297e4ba6aSRichard Zhu 2337e29c306SWolfram Sang writel(val, host->ioaddr + reg); 2347e29c306SWolfram Sang } 2357e29c306SWolfram Sang 23695f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 23795f25efeSWolfram Sang { 23895a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 23995a2482aSShawn Guo u16 val = readw(host->ioaddr + (reg ^ 2)); 24095a2482aSShawn Guo /* 24195a2482aSShawn Guo * uSDHC supports SDHCI v3.0, but it's encoded as value 24295a2482aSShawn Guo * 0x3 in host controller version register, which violates 24395a2482aSShawn Guo * SDHCI_SPEC_300 definition. Work it around here. 24495a2482aSShawn Guo */ 24595a2482aSShawn Guo if ((val & SDHCI_SPEC_VER_MASK) == 3) 24695a2482aSShawn Guo return --val; 24795a2482aSShawn Guo } 24895f25efeSWolfram Sang 24995f25efeSWolfram Sang return readw(host->ioaddr + reg); 25095f25efeSWolfram Sang } 25195f25efeSWolfram Sang 25295f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 25395f25efeSWolfram Sang { 25495f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 255e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 25695f25efeSWolfram Sang 25795f25efeSWolfram Sang switch (reg) { 25895f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 25995f25efeSWolfram Sang /* 26095f25efeSWolfram Sang * Postpone this write, we must do it together with a 26195f25efeSWolfram Sang * command write that is down below. 26295f25efeSWolfram Sang */ 26358ac8177SRichard Zhu if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 26458ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 26558ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 26658ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 26758ac8177SRichard Zhu u32 v; 26858ac8177SRichard Zhu v = readl(host->ioaddr + SDHCI_VENDOR_SPEC); 26958ac8177SRichard Zhu v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK; 27058ac8177SRichard Zhu writel(v, host->ioaddr + SDHCI_VENDOR_SPEC); 27158ac8177SRichard Zhu } 272e149860dSRichard Zhu imx_data->scratchpad = val; 27395f25efeSWolfram Sang return; 27495f25efeSWolfram Sang case SDHCI_COMMAND: 2755b6b0ad6SSascha Hauer if ((host->cmd->opcode == MMC_STOP_TRANSMISSION || 2765b6b0ad6SSascha Hauer host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 2775b6b0ad6SSascha Hauer (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 27858ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 27995a2482aSShawn Guo 28095a2482aSShawn Guo if (is_imx6q_usdhc(imx_data)) { 28195a2482aSShawn Guo u32 m = readl(host->ioaddr + SDHCI_MIX_CTRL); 28295a2482aSShawn Guo m = imx_data->scratchpad | (m & 0xffff0000); 28395a2482aSShawn Guo writel(m, host->ioaddr + SDHCI_MIX_CTRL); 28495a2482aSShawn Guo writel(val << 16, 28595a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 28695a2482aSShawn Guo } else { 287e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 28895f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 28995a2482aSShawn Guo } 29095f25efeSWolfram Sang return; 29195f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 29295f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 29395f25efeSWolfram Sang break; 29495f25efeSWolfram Sang } 29595f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 29695f25efeSWolfram Sang } 29795f25efeSWolfram Sang 29895f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 29995f25efeSWolfram Sang { 30095f25efeSWolfram Sang u32 new_val; 30195f25efeSWolfram Sang 30295f25efeSWolfram Sang switch (reg) { 30395f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 30495f25efeSWolfram Sang /* 30595f25efeSWolfram Sang * FSL put some DMA bits here 30695f25efeSWolfram Sang * If your board has a regulator, code should be here 30795f25efeSWolfram Sang */ 30895f25efeSWolfram Sang return; 30995f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 3100d58864bSTony Lin /* FSL messed up here, so we can just keep those three */ 3110d58864bSTony Lin new_val = val & (SDHCI_CTRL_LED | \ 3120d58864bSTony Lin SDHCI_CTRL_4BITBUS | \ 3130d58864bSTony Lin SDHCI_CTRL_D3CD); 31495f25efeSWolfram Sang /* ensure the endianess */ 31595f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 31695f25efeSWolfram Sang /* DMA mode bits are shifted */ 31795f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 31895f25efeSWolfram Sang 31995f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, new_val, reg); 32095f25efeSWolfram Sang return; 32195f25efeSWolfram Sang } 32295f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 323913413c3SShawn Guo 324913413c3SShawn Guo /* 325913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 326913413c3SShawn Guo * that software reset should not affect card detection circuit. 327913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 328913413c3SShawn Guo * software reset. This will stop those clocks that card detection 329913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 330913413c3SShawn Guo * to keep card detection circuit functional. 331913413c3SShawn Guo */ 332913413c3SShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) 333913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 33495f25efeSWolfram Sang } 33595f25efeSWolfram Sang 33695f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 33795f25efeSWolfram Sang { 33895f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 33995f25efeSWolfram Sang 34095f25efeSWolfram Sang return clk_get_rate(pltfm_host->clk); 34195f25efeSWolfram Sang } 34295f25efeSWolfram Sang 34395f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 34495f25efeSWolfram Sang { 34595f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 34695f25efeSWolfram Sang 34795f25efeSWolfram Sang return clk_get_rate(pltfm_host->clk) / 256 / 16; 34895f25efeSWolfram Sang } 34995f25efeSWolfram Sang 350913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 351913413c3SShawn Guo { 352842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 353842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 354842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 355913413c3SShawn Guo 356913413c3SShawn Guo switch (boarddata->wp_type) { 357913413c3SShawn Guo case ESDHC_WP_GPIO: 358913413c3SShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 359913413c3SShawn Guo return gpio_get_value(boarddata->wp_gpio); 360913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 361913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 362913413c3SShawn Guo SDHCI_WRITE_PROTECT); 363913413c3SShawn Guo case ESDHC_WP_NONE: 364913413c3SShawn Guo break; 365913413c3SShawn Guo } 366913413c3SShawn Guo 367913413c3SShawn Guo return -ENOSYS; 368913413c3SShawn Guo } 369913413c3SShawn Guo 3700c6d49ceSWolfram Sang static struct sdhci_ops sdhci_esdhc_ops = { 371e149860dSRichard Zhu .read_l = esdhc_readl_le, 3720c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 373e149860dSRichard Zhu .write_l = esdhc_writel_le, 3740c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 3750c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 3760c6d49ceSWolfram Sang .set_clock = esdhc_set_clock, 3770c6d49ceSWolfram Sang .get_max_clock = esdhc_pltfm_get_max_clock, 3780c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 379913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 3800c6d49ceSWolfram Sang }; 3810c6d49ceSWolfram Sang 38285d6509dSShawn Guo static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 38397e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 38497e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 38597e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 38685d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 38785d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 38885d6509dSShawn Guo }; 38985d6509dSShawn Guo 3907e29c306SWolfram Sang static irqreturn_t cd_irq(int irq, void *data) 3917e29c306SWolfram Sang { 3927e29c306SWolfram Sang struct sdhci_host *sdhost = (struct sdhci_host *)data; 3937e29c306SWolfram Sang 3947e29c306SWolfram Sang tasklet_schedule(&sdhost->card_tasklet); 3957e29c306SWolfram Sang return IRQ_HANDLED; 3967e29c306SWolfram Sang }; 3977e29c306SWolfram Sang 398abfafc2dSShawn Guo #ifdef CONFIG_OF 399abfafc2dSShawn Guo static int __devinit 400abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 401abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 402abfafc2dSShawn Guo { 403abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 404abfafc2dSShawn Guo 405abfafc2dSShawn Guo if (!np) 406abfafc2dSShawn Guo return -ENODEV; 407abfafc2dSShawn Guo 408abfafc2dSShawn Guo if (of_get_property(np, "fsl,card-wired", NULL)) 409abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_PERMANENT; 410abfafc2dSShawn Guo 411abfafc2dSShawn Guo if (of_get_property(np, "fsl,cd-controller", NULL)) 412abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_CONTROLLER; 413abfafc2dSShawn Guo 414abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 415abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 416abfafc2dSShawn Guo 417abfafc2dSShawn Guo boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 418abfafc2dSShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 419abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_GPIO; 420abfafc2dSShawn Guo 421abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 422abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 423abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 424abfafc2dSShawn Guo 425abfafc2dSShawn Guo return 0; 426abfafc2dSShawn Guo } 427abfafc2dSShawn Guo #else 428abfafc2dSShawn Guo static inline int 429abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 430abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 431abfafc2dSShawn Guo { 432abfafc2dSShawn Guo return -ENODEV; 433abfafc2dSShawn Guo } 434abfafc2dSShawn Guo #endif 435abfafc2dSShawn Guo 43685d6509dSShawn Guo static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev) 43795f25efeSWolfram Sang { 438abfafc2dSShawn Guo const struct of_device_id *of_id = 439abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 44085d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 44185d6509dSShawn Guo struct sdhci_host *host; 44285d6509dSShawn Guo struct esdhc_platform_data *boarddata; 4430c6d49ceSWolfram Sang int err; 444e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 44595f25efeSWolfram Sang 44685d6509dSShawn Guo host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata); 44785d6509dSShawn Guo if (IS_ERR(host)) 44885d6509dSShawn Guo return PTR_ERR(host); 44985d6509dSShawn Guo 45085d6509dSShawn Guo pltfm_host = sdhci_priv(host); 45185d6509dSShawn Guo 45285d6509dSShawn Guo imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL); 453abfafc2dSShawn Guo if (!imx_data) { 454abfafc2dSShawn Guo err = -ENOMEM; 455abfafc2dSShawn Guo goto err_imx_data; 456abfafc2dSShawn Guo } 45757ed3314SShawn Guo 458abfafc2dSShawn Guo if (of_id) 459abfafc2dSShawn Guo pdev->id_entry = of_id->data; 46057ed3314SShawn Guo imx_data->devtype = pdev->id_entry->driver_data; 46185d6509dSShawn Guo pltfm_host->priv = imx_data; 46285d6509dSShawn Guo 46352dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 46452dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 46552dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 46685d6509dSShawn Guo goto err_clk_get; 46795f25efeSWolfram Sang } 46852dac615SSascha Hauer 46952dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 47052dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 47152dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 47252dac615SSascha Hauer goto err_clk_get; 47352dac615SSascha Hauer } 47452dac615SSascha Hauer 47552dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 47652dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 47752dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 47852dac615SSascha Hauer goto err_clk_get; 47952dac615SSascha Hauer } 48052dac615SSascha Hauer 48152dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 48252dac615SSascha Hauer 48352dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 48452dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 48552dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 48695f25efeSWolfram Sang 48737865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 48837865fe9SEric Bénard 48957ed3314SShawn Guo if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) 4900c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 49197e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 49297e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 4930c6d49ceSWolfram Sang 49457ed3314SShawn Guo if (is_imx53_esdhc(imx_data)) 49558ac8177SRichard Zhu imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT; 49658ac8177SRichard Zhu 497f750ba9bSShawn Guo /* 498f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 499f750ba9bSShawn Guo * to something insane. Change it back here. 500f750ba9bSShawn Guo */ 501f750ba9bSShawn Guo if (is_imx6q_usdhc(imx_data)) 502f750ba9bSShawn Guo writel(0x08100810, host->ioaddr + SDHCI_WTMK_LVL); 503f750ba9bSShawn Guo 504abfafc2dSShawn Guo boarddata = &imx_data->boarddata; 505abfafc2dSShawn Guo if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { 506842afc02SShawn Guo if (!host->mmc->parent->platform_data) { 507913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "no board data!\n"); 508913413c3SShawn Guo err = -EINVAL; 509913413c3SShawn Guo goto no_board_data; 510913413c3SShawn Guo } 511842afc02SShawn Guo imx_data->boarddata = *((struct esdhc_platform_data *) 512842afc02SShawn Guo host->mmc->parent->platform_data); 513abfafc2dSShawn Guo } 514913413c3SShawn Guo 515913413c3SShawn Guo /* write_protect */ 516913413c3SShawn Guo if (boarddata->wp_type == ESDHC_WP_GPIO) { 5170c6d49ceSWolfram Sang err = gpio_request_one(boarddata->wp_gpio, GPIOF_IN, "ESDHC_WP"); 5180c6d49ceSWolfram Sang if (err) { 5190c6d49ceSWolfram Sang dev_warn(mmc_dev(host->mmc), 5200c6d49ceSWolfram Sang "no write-protect pin available!\n"); 521913413c3SShawn Guo boarddata->wp_gpio = -EINVAL; 522913413c3SShawn Guo } 523913413c3SShawn Guo } else { 524913413c3SShawn Guo boarddata->wp_gpio = -EINVAL; 5250c6d49ceSWolfram Sang } 5267e29c306SWolfram Sang 527913413c3SShawn Guo /* card_detect */ 528913413c3SShawn Guo if (boarddata->cd_type != ESDHC_CD_GPIO) 529913413c3SShawn Guo boarddata->cd_gpio = -EINVAL; 530913413c3SShawn Guo 531913413c3SShawn Guo switch (boarddata->cd_type) { 532913413c3SShawn Guo case ESDHC_CD_GPIO: 5337e29c306SWolfram Sang err = gpio_request_one(boarddata->cd_gpio, GPIOF_IN, "ESDHC_CD"); 5347e29c306SWolfram Sang if (err) { 535913413c3SShawn Guo dev_err(mmc_dev(host->mmc), 5367e29c306SWolfram Sang "no card-detect pin available!\n"); 5377e29c306SWolfram Sang goto no_card_detect_pin; 5380c6d49ceSWolfram Sang } 53916a790bcSEric Bénard 5407e29c306SWolfram Sang err = request_irq(gpio_to_irq(boarddata->cd_gpio), cd_irq, 5417e29c306SWolfram Sang IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 5427e29c306SWolfram Sang mmc_hostname(host->mmc), host); 5437e29c306SWolfram Sang if (err) { 544913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "request irq error\n"); 5457e29c306SWolfram Sang goto no_card_detect_irq; 5467e29c306SWolfram Sang } 547913413c3SShawn Guo /* fall through */ 5487e29c306SWolfram Sang 549913413c3SShawn Guo case ESDHC_CD_CONTROLLER: 550913413c3SShawn Guo /* we have a working card_detect back */ 5517e29c306SWolfram Sang host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 552913413c3SShawn Guo break; 553913413c3SShawn Guo 554913413c3SShawn Guo case ESDHC_CD_PERMANENT: 555913413c3SShawn Guo host->mmc->caps = MMC_CAP_NONREMOVABLE; 556913413c3SShawn Guo break; 557913413c3SShawn Guo 558913413c3SShawn Guo case ESDHC_CD_NONE: 559913413c3SShawn Guo break; 5607e29c306SWolfram Sang } 5617e29c306SWolfram Sang 56285d6509dSShawn Guo err = sdhci_add_host(host); 56385d6509dSShawn Guo if (err) 56485d6509dSShawn Guo goto err_add_host; 56585d6509dSShawn Guo 5667e29c306SWolfram Sang return 0; 5677e29c306SWolfram Sang 56885d6509dSShawn Guo err_add_host: 569913413c3SShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 570913413c3SShawn Guo free_irq(gpio_to_irq(boarddata->cd_gpio), host); 571913413c3SShawn Guo no_card_detect_irq: 572913413c3SShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 573913413c3SShawn Guo gpio_free(boarddata->cd_gpio); 574913413c3SShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 575913413c3SShawn Guo gpio_free(boarddata->wp_gpio); 576913413c3SShawn Guo no_card_detect_pin: 577913413c3SShawn Guo no_board_data: 57852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 57952dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 58052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 58185d6509dSShawn Guo err_clk_get: 582913413c3SShawn Guo kfree(imx_data); 583abfafc2dSShawn Guo err_imx_data: 58485d6509dSShawn Guo sdhci_pltfm_free(pdev); 58585d6509dSShawn Guo return err; 58695f25efeSWolfram Sang } 58795f25efeSWolfram Sang 58885d6509dSShawn Guo static int __devexit sdhci_esdhc_imx_remove(struct platform_device *pdev) 58995f25efeSWolfram Sang { 59085d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 59195f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 592e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 593842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 59485d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 59585d6509dSShawn Guo 59685d6509dSShawn Guo sdhci_remove_host(host, dead); 5970c6d49ceSWolfram Sang 598913413c3SShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 5990c6d49ceSWolfram Sang gpio_free(boarddata->wp_gpio); 60095f25efeSWolfram Sang 601913413c3SShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) { 6027e29c306SWolfram Sang free_irq(gpio_to_irq(boarddata->cd_gpio), host); 603913413c3SShawn Guo gpio_free(boarddata->cd_gpio); 6047e29c306SWolfram Sang } 6057e29c306SWolfram Sang 60652dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 60752dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 60852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 60952dac615SSascha Hauer 610e149860dSRichard Zhu kfree(imx_data); 61185d6509dSShawn Guo 61285d6509dSShawn Guo sdhci_pltfm_free(pdev); 61385d6509dSShawn Guo 61485d6509dSShawn Guo return 0; 61595f25efeSWolfram Sang } 61695f25efeSWolfram Sang 61785d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 61885d6509dSShawn Guo .driver = { 61985d6509dSShawn Guo .name = "sdhci-esdhc-imx", 62085d6509dSShawn Guo .owner = THIS_MODULE, 621abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 62229495aa0SManuel Lauss .pm = SDHCI_PLTFM_PMOPS, 62385d6509dSShawn Guo }, 62457ed3314SShawn Guo .id_table = imx_esdhc_devtype, 62585d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 62685d6509dSShawn Guo .remove = __devexit_p(sdhci_esdhc_imx_remove), 62795f25efeSWolfram Sang }; 62885d6509dSShawn Guo 629d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 63085d6509dSShawn Guo 63185d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 63285d6509dSShawn Guo MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 63385d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 634