195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 7035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3089d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 3195f25efeSWolfram Sang #include "sdhci-pltfm.h" 3295f25efeSWolfram Sang #include "sdhci-esdhc.h" 3395f25efeSWolfram Sang 34a215186dSHaibo Chen #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 3560bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 36fd44954eSHaibo Chen #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 3758ac8177SRichard Zhu /* VENDOR SPEC register */ 3860bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3960bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 400322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 41fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 4260bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 43cc17e129SDong Aisheng #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 4460bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 45de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 462a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 470322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 480322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 490b330e38SDong Aisheng #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 500322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 5128b07674SHaibo Chen #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 522a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 532a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 54d131a71cSDong Aisheng /* Tuning bits */ 55d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 5658ac8177SRichard Zhu 57602519b2SDong Aisheng /* dll control register */ 58602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 59602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 60602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 61602519b2SDong Aisheng 620322191eSDong Aisheng /* tune control register */ 630322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 640322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 650322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 660322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 670322191eSDong Aisheng 6828b07674SHaibo Chen /* strobe dll register */ 6928b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL 0x70 7028b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 7128b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 7228b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 7328b07674SHaibo Chen 7428b07674SHaibo Chen #define ESDHC_STROBE_DLL_STATUS 0x74 7528b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 7628b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 7728b07674SHaibo Chen 786e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 796e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 806e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 81d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 82d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_MASK 0xff 83260ecb3cSHaibo Chen #define ESDHC_TUNING_STEP_MASK 0x00070000 84d407e30bSHaibo Chen #define ESDHC_TUNING_STEP_SHIFT 16 856e9fd28eSDong Aisheng 86ad93220dSDong Aisheng /* pinctrl state */ 87ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 88ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 89ad93220dSDong Aisheng 9058ac8177SRichard Zhu /* 91af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 92af51079eSSascha Hauer */ 93af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 94af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 95af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 96af51079eSSascha Hauer 97af51079eSSascha Hauer /* 98d04f8d5bSBenoît Thébaudeau * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 9997e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 10097e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 10197e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 10297e4ba6aSRichard Zhu */ 10360bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 10497e4ba6aSRichard Zhu 10597e4ba6aSRichard Zhu /* 10658ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 10758ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 10858ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 10958ac8177SRichard Zhu * be generated. 11058ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 11158ac8177SRichard Zhu * operations automatically as required at the end of the 11258ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 11358ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 114d04f8d5bSBenoît Thébaudeau * exception. Bit1 of Vendor Spec register is used to fix it. 11558ac8177SRichard Zhu */ 11631fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 11731fbb301SShawn Guo /* 1189d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1199d61c009SShawn Guo * integrated on the i.MX6 series. 1209d61c009SShawn Guo */ 1219d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1226e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1236e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1246e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1256e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1266e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1276e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 12818094430SDong Aisheng /* 129d04f8d5bSBenoît Thébaudeau * The IP has erratum ERR004536 13018094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 13118094430SDong Aisheng * when reading data from the card 132667123f6SBenoît Thébaudeau * This flag is also set for i.MX25 and i.MX35 in order to get 133667123f6SBenoît Thébaudeau * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 13418094430SDong Aisheng */ 13518094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 1364245afffSDong Aisheng /* The IP supports HS200 mode */ 1374245afffSDong Aisheng #define ESDHC_FLAG_HS200 BIT(8) 13828b07674SHaibo Chen /* The IP supports HS400 mode */ 13928b07674SHaibo Chen #define ESDHC_FLAG_HS400 BIT(9) 14028b07674SHaibo Chen 141d04f8d5bSBenoît Thébaudeau /* A clock frequency higher than this rate requires strobe dll control */ 14228b07674SHaibo Chen #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 143e149860dSRichard Zhu 144f47c4bbfSShawn Guo struct esdhc_soc_data { 145f47c4bbfSShawn Guo u32 flags; 146f47c4bbfSShawn Guo }; 147f47c4bbfSShawn Guo 148f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx25_data = { 149667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 150f47c4bbfSShawn Guo }; 151f47c4bbfSShawn Guo 152f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx35_data = { 153667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 154f47c4bbfSShawn Guo }; 155f47c4bbfSShawn Guo 156f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx51_data = { 157f47c4bbfSShawn Guo .flags = 0, 158f47c4bbfSShawn Guo }; 159f47c4bbfSShawn Guo 160f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx53_data = { 161f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 162f47c4bbfSShawn Guo }; 163f47c4bbfSShawn Guo 164f47c4bbfSShawn Guo static struct esdhc_soc_data usdhc_imx6q_data = { 1656e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1666e9fd28eSDong Aisheng }; 1676e9fd28eSDong Aisheng 1686e9fd28eSDong Aisheng static struct esdhc_soc_data usdhc_imx6sl_data = { 1696e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1704245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 1714245afffSDong Aisheng | ESDHC_FLAG_HS200, 17257ed3314SShawn Guo }; 17357ed3314SShawn Guo 174913d4951SDong Aisheng static struct esdhc_soc_data usdhc_imx6sx_data = { 175913d4951SDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1764245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 177913d4951SDong Aisheng }; 178913d4951SDong Aisheng 17928b07674SHaibo Chen static struct esdhc_soc_data usdhc_imx7d_data = { 18028b07674SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 18128b07674SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 18228b07674SHaibo Chen | ESDHC_FLAG_HS400, 18328b07674SHaibo Chen }; 18428b07674SHaibo Chen 185e149860dSRichard Zhu struct pltfm_imx_data { 186e149860dSRichard Zhu u32 scratchpad; 187e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 188ad93220dSDong Aisheng struct pinctrl_state *pins_default; 189ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 190ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 191f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 192842afc02SShawn Guo struct esdhc_platform_data boarddata; 19352dac615SSascha Hauer struct clk *clk_ipg; 19452dac615SSascha Hauer struct clk *clk_ahb; 19552dac615SSascha Hauer struct clk *clk_per; 1963602785bSMichael Trimarchi unsigned int actual_clock; 197361b8482SLucas Stach enum { 198361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending */ 199361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 200361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 201361b8482SLucas Stach } multiblock_status; 202de5bdbffSDong Aisheng u32 is_ddr; 203e149860dSRichard Zhu }; 204e149860dSRichard Zhu 205f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 20657ed3314SShawn Guo { 20757ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 208f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 20957ed3314SShawn Guo }, { 21057ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 211f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 21257ed3314SShawn Guo }, { 21357ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 214f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 21557ed3314SShawn Guo }, { 21657ed3314SShawn Guo /* sentinel */ 21757ed3314SShawn Guo } 21857ed3314SShawn Guo }; 21957ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 22057ed3314SShawn Guo 221abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 222f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 223f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 224f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 225f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 226913d4951SDong Aisheng { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 2276e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 228f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 22928b07674SHaibo Chen { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 230abfafc2dSShawn Guo { /* sentinel */ } 231abfafc2dSShawn Guo }; 232abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 233abfafc2dSShawn Guo 23457ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 23557ed3314SShawn Guo { 236f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 23757ed3314SShawn Guo } 23857ed3314SShawn Guo 23957ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 24057ed3314SShawn Guo { 241f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 24257ed3314SShawn Guo } 24357ed3314SShawn Guo 24495a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 24595a2482aSShawn Guo { 246f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 24795a2482aSShawn Guo } 24895a2482aSShawn Guo 2499d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2509d61c009SShawn Guo { 251f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2529d61c009SShawn Guo } 2539d61c009SShawn Guo 25495f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 25595f25efeSWolfram Sang { 25695f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 25795f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 25895f25efeSWolfram Sang 25995f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 26095f25efeSWolfram Sang } 26195f25efeSWolfram Sang 2627e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 2637e29c306SWolfram Sang { 264361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 265070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 266913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 267913413c3SShawn Guo 2680322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 2690322191eSDong Aisheng u32 fsl_prss = val; 2700322191eSDong Aisheng /* save the least 20 bits */ 2710322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 2720322191eSDong Aisheng /* move dat[0-3] bits */ 2730322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 2740322191eSDong Aisheng /* move cmd line bit */ 2750322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 2760322191eSDong Aisheng } 2770322191eSDong Aisheng 27897e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 2796b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 2806b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2816b4fb671SDong Aisheng val &= 0xffff0000; 2826b4fb671SDong Aisheng 28397e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 28497e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 28597e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 28697e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 287d04f8d5bSBenoît Thébaudeau * quirk on MX25/35 platforms. 28897e4ba6aSRichard Zhu */ 28997e4ba6aSRichard Zhu 29097e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 29197e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 29297e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 29397e4ba6aSRichard Zhu } 29497e4ba6aSRichard Zhu } 29597e4ba6aSRichard Zhu 2966e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 2976e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 2986e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2996e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 3006e9fd28eSDong Aisheng else 3016e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 3020322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 303888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 304da0295ffSDong Aisheng | SDHCI_USE_SDR50_TUNING 305da0295ffSDong Aisheng | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); 30628b07674SHaibo Chen 30728b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 30828b07674SHaibo Chen val |= SDHCI_SUPPORT_HS400; 3096e9fd28eSDong Aisheng } 3106e9fd28eSDong Aisheng } 3110322191eSDong Aisheng 3129d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 3130322191eSDong Aisheng val = 0; 3140322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 3150322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 3160322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 3170322191eSDong Aisheng } 3180322191eSDong Aisheng 31997e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 32060bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 32160bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 32297e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 32397e4ba6aSRichard Zhu } 324361b8482SLucas Stach 325361b8482SLucas Stach /* 326361b8482SLucas Stach * mask off the interrupt we get in response to the manually 327361b8482SLucas Stach * sent CMD12 328361b8482SLucas Stach */ 329361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 330361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 331361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 332361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 333361b8482SLucas Stach SDHCI_INT_STATUS); 334361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 335361b8482SLucas Stach } 33697e4ba6aSRichard Zhu } 33797e4ba6aSRichard Zhu 3387e29c306SWolfram Sang return val; 3397e29c306SWolfram Sang } 3407e29c306SWolfram Sang 3417e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 3427e29c306SWolfram Sang { 343e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 344070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 3450d58864bSTony Lin u32 data; 346e149860dSRichard Zhu 34777da3da0SAaron Brice if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 34877da3da0SAaron Brice reg == SDHCI_INT_STATUS)) { 349b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 3500d58864bSTony Lin /* 3510d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 352d04f8d5bSBenoît Thébaudeau * card interrupt. This is an eSDHC controller problem 3530d58864bSTony Lin * so we need to apply the following workaround: clear 3540d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 3550d58864bSTony Lin * interrupt. In case a card interrupt was lost, 3560d58864bSTony Lin * re-sample it by the following steps. 3570d58864bSTony Lin */ 3580d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 35960bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 3600d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 36160bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 3620d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 3630d58864bSTony Lin } 364915be485SDong Aisheng 365915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 366915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 367915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 368915be485SDong Aisheng } 3690d58864bSTony Lin } 3700d58864bSTony Lin 371f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 37258ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 37358ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 37458ac8177SRichard Zhu u32 v; 37560bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 37660bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 37760bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 378361b8482SLucas Stach 379361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 380361b8482SLucas Stach { 381361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 382361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 383361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 384361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 385361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 386361b8482SLucas Stach } 38758ac8177SRichard Zhu } 38858ac8177SRichard Zhu 3897e29c306SWolfram Sang writel(val, host->ioaddr + reg); 3907e29c306SWolfram Sang } 3917e29c306SWolfram Sang 39295f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 39395f25efeSWolfram Sang { 394ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 395070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 3960322191eSDong Aisheng u16 ret = 0; 3970322191eSDong Aisheng u32 val; 398ef4d0888SShawn Guo 39995a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 400ef4d0888SShawn Guo reg ^= 2; 4019d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 40295a2482aSShawn Guo /* 403ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 404ef4d0888SShawn Guo * Correct it here. 40595a2482aSShawn Guo */ 406ef4d0888SShawn Guo return SDHCI_SPEC_300; 407ef4d0888SShawn Guo } 40895a2482aSShawn Guo } 40995f25efeSWolfram Sang 4100322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 4110322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4120322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 4130322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 4140322191eSDong Aisheng 4159d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 4166e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 4170322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4186e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 4196e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 4206e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4216e9fd28eSDong Aisheng } 4226e9fd28eSDong Aisheng 4230322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 4240322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 4250322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 4260322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 4270322191eSDong Aisheng 4280322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 4290322191eSDong Aisheng 4300322191eSDong Aisheng return ret; 4310322191eSDong Aisheng } 4320322191eSDong Aisheng 4337dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 4347dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 4357dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4367dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 4377dd109efSDong Aisheng /* Swap AC23 bit */ 4387dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 4397dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 4407dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 4417dd109efSDong Aisheng } 4427dd109efSDong Aisheng } else { 4437dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 4447dd109efSDong Aisheng } 4457dd109efSDong Aisheng 4467dd109efSDong Aisheng return ret; 4477dd109efSDong Aisheng } 4487dd109efSDong Aisheng 44995f25efeSWolfram Sang return readw(host->ioaddr + reg); 45095f25efeSWolfram Sang } 45195f25efeSWolfram Sang 45295f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 45395f25efeSWolfram Sang { 45495f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 455070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 4560322191eSDong Aisheng u32 new_val = 0; 45795f25efeSWolfram Sang 45895f25efeSWolfram Sang switch (reg) { 4590322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 4600322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4610322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 4620322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4630322191eSDong Aisheng else 4640322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4650322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4660322191eSDong Aisheng return; 4670322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 4680322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4690322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 4700322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 4710322191eSDong Aisheng else 4720322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 4730322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4746e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 4750322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 476da0295ffSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4770322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 478da0295ffSDong Aisheng new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 479da0295ffSDong Aisheng } else { 4800322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 481da0295ffSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 482da0295ffSDong Aisheng } 4830322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 4846e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 4856e9fd28eSDong Aisheng u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4866e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4878b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4888b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4896e9fd28eSDong Aisheng } else { 4908b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4916e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 4920b330e38SDong Aisheng m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 4936e9fd28eSDong Aisheng } 4946e9fd28eSDong Aisheng 4958b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 4968b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 4978b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 4980b330e38SDong Aisheng m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 4998b2bb0adSDong Aisheng } else { 5008b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 5018b2bb0adSDong Aisheng } 5026e9fd28eSDong Aisheng 5036e9fd28eSDong Aisheng writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 5046e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5056e9fd28eSDong Aisheng } 5060322191eSDong Aisheng return; 50795f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 508f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 50958ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 51058ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 51158ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 51258ac8177SRichard Zhu u32 v; 51360bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 51460bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 51560bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 51658ac8177SRichard Zhu } 51769f54698SShawn Guo 5189d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 51969f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5202a15f981SShawn Guo /* Swap AC23 bit */ 5212a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 5222a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 5232a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 5242a15f981SShawn Guo } 5252a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 52669f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 52769f54698SShawn Guo } else { 52869f54698SShawn Guo /* 52969f54698SShawn Guo * Postpone this write, we must do it together with a 53069f54698SShawn Guo * command write that is down below. 53169f54698SShawn Guo */ 532e149860dSRichard Zhu imx_data->scratchpad = val; 53369f54698SShawn Guo } 53495f25efeSWolfram Sang return; 53595f25efeSWolfram Sang case SDHCI_COMMAND: 536361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 53758ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 53895a2482aSShawn Guo 539361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 540f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 541361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 542361b8482SLucas Stach 5439d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 54495a2482aSShawn Guo writel(val << 16, 54595a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 54669f54698SShawn Guo else 547e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 54895f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 54995f25efeSWolfram Sang return; 55095f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 55195f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 55295f25efeSWolfram Sang break; 55395f25efeSWolfram Sang } 55495f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 55595f25efeSWolfram Sang } 55695f25efeSWolfram Sang 55777da3da0SAaron Brice static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 55877da3da0SAaron Brice { 55977da3da0SAaron Brice u8 ret; 56077da3da0SAaron Brice u32 val; 56177da3da0SAaron Brice 56277da3da0SAaron Brice switch (reg) { 56377da3da0SAaron Brice case SDHCI_HOST_CONTROL: 56477da3da0SAaron Brice val = readl(host->ioaddr + reg); 56577da3da0SAaron Brice 56677da3da0SAaron Brice ret = val & SDHCI_CTRL_LED; 56777da3da0SAaron Brice ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 56877da3da0SAaron Brice ret |= (val & ESDHC_CTRL_4BITBUS); 56977da3da0SAaron Brice ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 57077da3da0SAaron Brice return ret; 57177da3da0SAaron Brice } 57277da3da0SAaron Brice 57377da3da0SAaron Brice return readb(host->ioaddr + reg); 57477da3da0SAaron Brice } 57577da3da0SAaron Brice 57695f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 57795f25efeSWolfram Sang { 5789a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 579070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 58081a0a8bcSBenoît Thébaudeau u32 new_val = 0; 581af51079eSSascha Hauer u32 mask; 58295f25efeSWolfram Sang 58395f25efeSWolfram Sang switch (reg) { 58495f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 58595f25efeSWolfram Sang /* 58695f25efeSWolfram Sang * FSL put some DMA bits here 58795f25efeSWolfram Sang * If your board has a regulator, code should be here 58895f25efeSWolfram Sang */ 58995f25efeSWolfram Sang return; 59095f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 5916b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 592af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 5937122bbb0SMasanari Iida /* ensure the endianness */ 59495f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 5959a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 5969a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 59795f25efeSWolfram Sang /* DMA mode bits are shifted */ 59895f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 5999a0985b7SWilson Callan } 60095f25efeSWolfram Sang 601af51079eSSascha Hauer /* 602af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 603af51079eSSascha Hauer * esdhc_pltfm_bus_width. 604f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 605d04f8d5bSBenoît Thébaudeau * SDIO interrupt erratum workaround. 606af51079eSSascha Hauer */ 607f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 608af51079eSSascha Hauer 609af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 61095f25efeSWolfram Sang return; 61181a0a8bcSBenoît Thébaudeau case SDHCI_SOFTWARE_RESET: 61281a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_DATA) 61381a0a8bcSBenoît Thébaudeau new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 61481a0a8bcSBenoît Thébaudeau break; 61595f25efeSWolfram Sang } 61695f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 617913413c3SShawn Guo 61881a0a8bcSBenoît Thébaudeau if (reg == SDHCI_SOFTWARE_RESET) { 61981a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_ALL) { 620913413c3SShawn Guo /* 62181a0a8bcSBenoît Thébaudeau * The esdhc has a design violation to SDHC spec which 62281a0a8bcSBenoît Thébaudeau * tells that software reset should not affect card 62381a0a8bcSBenoît Thébaudeau * detection circuit. But esdhc clears its SYSCTL 62481a0a8bcSBenoît Thébaudeau * register bits [0..2] during the software reset. This 62581a0a8bcSBenoît Thébaudeau * will stop those clocks that card detection circuit 62681a0a8bcSBenoît Thébaudeau * relies on. To work around it, we turn the clocks on 62781a0a8bcSBenoît Thébaudeau * back to keep card detection circuit functional. 628913413c3SShawn Guo */ 629913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 63058c8c4fbSShawn Guo /* 63158c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 63258c8c4fbSShawn Guo * Do it manually here. 63358c8c4fbSShawn Guo */ 634de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 63581a0a8bcSBenoît Thébaudeau /* 63681a0a8bcSBenoît Thébaudeau * the tuning bits should be kept during reset 63781a0a8bcSBenoît Thébaudeau */ 638d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 639d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 640d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 641de5bdbffSDong Aisheng imx_data->is_ddr = 0; 642de5bdbffSDong Aisheng } 64381a0a8bcSBenoît Thébaudeau } else if (val & SDHCI_RESET_DATA) { 64481a0a8bcSBenoît Thébaudeau /* 64581a0a8bcSBenoît Thébaudeau * The eSDHC DAT line software reset clears at least the 64681a0a8bcSBenoît Thébaudeau * data transfer width on i.MX25, so make sure that the 64781a0a8bcSBenoît Thébaudeau * Host Control register is unaffected. 64881a0a8bcSBenoît Thébaudeau */ 64981a0a8bcSBenoît Thébaudeau esdhc_clrset_le(host, 0xff, new_val, 65081a0a8bcSBenoît Thébaudeau SDHCI_HOST_CONTROL); 65181a0a8bcSBenoît Thébaudeau } 65258c8c4fbSShawn Guo } 65395f25efeSWolfram Sang } 65495f25efeSWolfram Sang 6550ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 6560ddf03c9SLucas Stach { 6570ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 6580ddf03c9SLucas Stach 659a974862fSDong Aisheng return pltfm_host->clock; 6600ddf03c9SLucas Stach } 6610ddf03c9SLucas Stach 66295f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 66395f25efeSWolfram Sang { 66495f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 66595f25efeSWolfram Sang 666a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 66795f25efeSWolfram Sang } 66895f25efeSWolfram Sang 6698ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 6708ba9580aSLucas Stach unsigned int clock) 6718ba9580aSLucas Stach { 6728ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 673070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 674a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 6755143c953SBenoît Thébaudeau int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 6765143c953SBenoît Thébaudeau int pre_div = 1; 677d31fc00aSDong Aisheng int div = 1; 678fed2f6e2SDong Aisheng u32 temp, val; 6798ba9580aSLucas Stach 680fed2f6e2SDong Aisheng if (clock == 0) { 6811650d0c7SRussell King host->mmc->actual_clock = 0; 6821650d0c7SRussell King 6839d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 684fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 685fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 686fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 687fed2f6e2SDong Aisheng } 688373073efSRussell King return; 689fed2f6e2SDong Aisheng } 690d31fc00aSDong Aisheng 691d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 692d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 693d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 694d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 695d31fc00aSDong Aisheng 6965143c953SBenoît Thébaudeau while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 6975143c953SBenoît Thébaudeau pre_div < 256) 698d31fc00aSDong Aisheng pre_div *= 2; 699d31fc00aSDong Aisheng 7005143c953SBenoît Thébaudeau while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 701d31fc00aSDong Aisheng div++; 702d31fc00aSDong Aisheng 7035143c953SBenoît Thébaudeau host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 704d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 705e76b8559SDong Aisheng clock, host->mmc->actual_clock); 706d31fc00aSDong Aisheng 707d31fc00aSDong Aisheng pre_div >>= 1; 708d31fc00aSDong Aisheng div--; 709d31fc00aSDong Aisheng 710d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 711d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 712d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 713d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 714d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 715fed2f6e2SDong Aisheng 7169d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 717fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 718fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 719fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 720fed2f6e2SDong Aisheng } 721fed2f6e2SDong Aisheng 722d31fc00aSDong Aisheng mdelay(1); 7238ba9580aSLucas Stach } 7248ba9580aSLucas Stach 725913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 726913413c3SShawn Guo { 727842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 728070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 729842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 730913413c3SShawn Guo 731913413c3SShawn Guo switch (boarddata->wp_type) { 732913413c3SShawn Guo case ESDHC_WP_GPIO: 733fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 734913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 735913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 736913413c3SShawn Guo SDHCI_WRITE_PROTECT); 737913413c3SShawn Guo case ESDHC_WP_NONE: 738913413c3SShawn Guo break; 739913413c3SShawn Guo } 740913413c3SShawn Guo 741913413c3SShawn Guo return -ENOSYS; 742913413c3SShawn Guo } 743913413c3SShawn Guo 7442317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 745af51079eSSascha Hauer { 746af51079eSSascha Hauer u32 ctrl; 747af51079eSSascha Hauer 748af51079eSSascha Hauer switch (width) { 749af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 750af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 751af51079eSSascha Hauer break; 752af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 753af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 754af51079eSSascha Hauer break; 755af51079eSSascha Hauer default: 756af51079eSSascha Hauer ctrl = 0; 757af51079eSSascha Hauer break; 758af51079eSSascha Hauer } 759af51079eSSascha Hauer 760af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 761af51079eSSascha Hauer SDHCI_HOST_CONTROL); 762af51079eSSascha Hauer } 763af51079eSSascha Hauer 7640322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 7650322191eSDong Aisheng { 7660322191eSDong Aisheng u32 reg; 7670322191eSDong Aisheng 7680322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 7690322191eSDong Aisheng mdelay(1); 7700322191eSDong Aisheng 7710322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7720322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 7730322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 7740322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7750322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 7760322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 777d04f8d5bSBenoît Thébaudeau "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 7780322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 7790322191eSDong Aisheng } 7800322191eSDong Aisheng 7810322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 7820322191eSDong Aisheng { 7830322191eSDong Aisheng u32 reg; 7840322191eSDong Aisheng 7850322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7860322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 787da0295ffSDong Aisheng reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 7880322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7890322191eSDong Aisheng } 7900322191eSDong Aisheng 7910322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 7920322191eSDong Aisheng { 7930322191eSDong Aisheng int min, max, avg, ret; 7940322191eSDong Aisheng 7950322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 7960322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 7970322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 7980322191eSDong Aisheng esdhc_prepare_tuning(host, min); 7999979dbe5SChaotian Jing if (!mmc_send_tuning(host->mmc, opcode, NULL)) 8000322191eSDong Aisheng break; 8010322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 8020322191eSDong Aisheng } 8030322191eSDong Aisheng 8040322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 8050322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 8060322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 8070322191eSDong Aisheng esdhc_prepare_tuning(host, max); 8089979dbe5SChaotian Jing if (mmc_send_tuning(host->mmc, opcode, NULL)) { 8090322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 8100322191eSDong Aisheng break; 8110322191eSDong Aisheng } 8120322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 8130322191eSDong Aisheng } 8140322191eSDong Aisheng 8150322191eSDong Aisheng /* use average delay to get the best timing */ 8160322191eSDong Aisheng avg = (min + max) / 2; 8170322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 8189979dbe5SChaotian Jing ret = mmc_send_tuning(host->mmc, opcode, NULL); 8190322191eSDong Aisheng esdhc_post_tuning(host); 8200322191eSDong Aisheng 821d04f8d5bSBenoît Thébaudeau dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 8220322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 8230322191eSDong Aisheng 8240322191eSDong Aisheng return ret; 8250322191eSDong Aisheng } 8260322191eSDong Aisheng 827ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 828ad93220dSDong Aisheng unsigned int uhs) 829ad93220dSDong Aisheng { 830ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 831070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 832ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 833ad93220dSDong Aisheng 834ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 835ad93220dSDong Aisheng 836ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 837ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 838ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 839ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 840ad93220dSDong Aisheng return -EINVAL; 841ad93220dSDong Aisheng 842ad93220dSDong Aisheng switch (uhs) { 843ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 8449f327845SHaibo Chen case MMC_TIMING_UHS_DDR50: 845ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 846ad93220dSDong Aisheng break; 847ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 848429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 84928b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 850ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 851ad93220dSDong Aisheng break; 852ad93220dSDong Aisheng default: 853ad93220dSDong Aisheng /* back to default state for other legacy timing */ 854ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 855ad93220dSDong Aisheng } 856ad93220dSDong Aisheng 857ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 858ad93220dSDong Aisheng } 859ad93220dSDong Aisheng 86028b07674SHaibo Chen /* 861d04f8d5bSBenoît Thébaudeau * For HS400 eMMC, there is a data_strobe line. This signal is generated 86228b07674SHaibo Chen * by the device and used for data output and CRC status response output 86328b07674SHaibo Chen * in HS400 mode. The frequency of this signal follows the frequency of 864d04f8d5bSBenoît Thébaudeau * CLK generated by host. The host receives the data which is aligned to the 86528b07674SHaibo Chen * edge of data_strobe line. Due to the time delay between CLK line and 86628b07674SHaibo Chen * data_strobe line, if the delay time is larger than one clock cycle, 867d04f8d5bSBenoît Thébaudeau * then CLK and data_strobe line will be misaligned, read error shows up. 86828b07674SHaibo Chen * So when the CLK is higher than 100MHz, each clock cycle is short enough, 869d04f8d5bSBenoît Thébaudeau * host should configure the delay target. 87028b07674SHaibo Chen */ 87128b07674SHaibo Chen static void esdhc_set_strobe_dll(struct sdhci_host *host) 87228b07674SHaibo Chen { 87328b07674SHaibo Chen u32 v; 87428b07674SHaibo Chen 87528b07674SHaibo Chen if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { 8767ac6da26SDong Aisheng /* disable clock before enabling strobe dll */ 8777ac6da26SDong Aisheng writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 8787ac6da26SDong Aisheng ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 8797ac6da26SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 8807ac6da26SDong Aisheng 88128b07674SHaibo Chen /* force a reset on strobe dll */ 88228b07674SHaibo Chen writel(ESDHC_STROBE_DLL_CTRL_RESET, 88328b07674SHaibo Chen host->ioaddr + ESDHC_STROBE_DLL_CTRL); 88428b07674SHaibo Chen /* 88528b07674SHaibo Chen * enable strobe dll ctrl and adjust the delay target 88628b07674SHaibo Chen * for the uSDHC loopback read clock 88728b07674SHaibo Chen */ 88828b07674SHaibo Chen v = ESDHC_STROBE_DLL_CTRL_ENABLE | 88928b07674SHaibo Chen (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 89028b07674SHaibo Chen writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 89128b07674SHaibo Chen /* wait 1us to make sure strobe dll status register stable */ 89228b07674SHaibo Chen udelay(1); 89328b07674SHaibo Chen v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); 89428b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) 89528b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 89628b07674SHaibo Chen "warning! HS400 strobe DLL status REF not lock!\n"); 89728b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 89828b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 89928b07674SHaibo Chen "warning! HS400 strobe DLL status SLV not lock!\n"); 90028b07674SHaibo Chen } 90128b07674SHaibo Chen } 90228b07674SHaibo Chen 903d9370424SHaibo Chen static void esdhc_reset_tuning(struct sdhci_host *host) 904d9370424SHaibo Chen { 905d9370424SHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 906d9370424SHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 907d9370424SHaibo Chen u32 ctrl; 908d9370424SHaibo Chen 909d04f8d5bSBenoît Thébaudeau /* Reset the tuning circuit */ 910d9370424SHaibo Chen if (esdhc_is_usdhc(imx_data)) { 911d9370424SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 912d9370424SHaibo Chen ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 913d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 914d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 915d9370424SHaibo Chen writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 916d9370424SHaibo Chen writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 917d9370424SHaibo Chen } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 918d9370424SHaibo Chen ctrl = readl(host->ioaddr + SDHCI_ACMD12_ERR); 919d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 920d9370424SHaibo Chen writel(ctrl, host->ioaddr + SDHCI_ACMD12_ERR); 921d9370424SHaibo Chen } 922d9370424SHaibo Chen } 923d9370424SHaibo Chen } 924d9370424SHaibo Chen 925850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 926ad93220dSDong Aisheng { 92728b07674SHaibo Chen u32 m; 928ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 929070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 930602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 931ad93220dSDong Aisheng 93228b07674SHaibo Chen /* disable ddr mode and disable HS400 mode */ 93328b07674SHaibo Chen m = readl(host->ioaddr + ESDHC_MIX_CTRL); 93428b07674SHaibo Chen m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 93528b07674SHaibo Chen imx_data->is_ddr = 0; 93628b07674SHaibo Chen 937850a29b8SRussell King switch (timing) { 938ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 939ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 940ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 941ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 942429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 94328b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 944ad93220dSDong Aisheng break; 945ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 94669f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 94728b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN; 94828b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 949de5bdbffSDong Aisheng imx_data->is_ddr = 1; 950602519b2SDong Aisheng if (boarddata->delay_line) { 951602519b2SDong Aisheng u32 v; 952602519b2SDong Aisheng v = boarddata->delay_line << 953602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 954602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 955602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 956602519b2SDong Aisheng v <<= 1; 957602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 958602519b2SDong Aisheng } 959ad93220dSDong Aisheng break; 96028b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 96128b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 96228b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 96328b07674SHaibo Chen imx_data->is_ddr = 1; 9647ac6da26SDong Aisheng /* update clock after enable DDR for strobe DLL lock */ 9657ac6da26SDong Aisheng host->ops->set_clock(host, host->clock); 96628b07674SHaibo Chen esdhc_set_strobe_dll(host); 96728b07674SHaibo Chen break; 968d9370424SHaibo Chen case MMC_TIMING_LEGACY: 969d9370424SHaibo Chen default: 970d9370424SHaibo Chen esdhc_reset_tuning(host); 971d9370424SHaibo Chen break; 972ad93220dSDong Aisheng } 973ad93220dSDong Aisheng 974850a29b8SRussell King esdhc_change_pinstate(host, timing); 975ad93220dSDong Aisheng } 976ad93220dSDong Aisheng 9770718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 9780718e59aSRussell King { 9790718e59aSRussell King sdhci_reset(host, mask); 9800718e59aSRussell King 9810718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 9820718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 9830718e59aSRussell King } 9840718e59aSRussell King 98510fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 98610fd0ad9SAisheng Dong { 98710fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 988070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 98910fd0ad9SAisheng Dong 990d04f8d5bSBenoît Thébaudeau /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 9912fb0b02bSHaibo Chen return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 99210fd0ad9SAisheng Dong } 99310fd0ad9SAisheng Dong 994e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 995e33eb8e2SAisheng Dong { 996e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 997070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 998e33eb8e2SAisheng Dong 999e33eb8e2SAisheng Dong /* use maximum timeout counter */ 1000a215186dSHaibo Chen esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1001a215186dSHaibo Chen esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1002e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 1003e33eb8e2SAisheng Dong } 1004e33eb8e2SAisheng Dong 10056e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 1006e149860dSRichard Zhu .read_l = esdhc_readl_le, 10070c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 100877da3da0SAaron Brice .read_b = esdhc_readb_le, 1009e149860dSRichard Zhu .write_l = esdhc_writel_le, 10100c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 10110c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 10128ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 10130ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 10140c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 101510fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 1016913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 1017e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 10182317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 1019ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 10200718e59aSRussell King .reset = esdhc_reset, 10210c6d49ceSWolfram Sang }; 10220c6d49ceSWolfram Sang 10231db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 102497e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 102597e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 102697e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 102785d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 102885d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 102985d6509dSShawn Guo }; 103085d6509dSShawn Guo 1031f3f5cf3dSDong Aisheng static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1032f3f5cf3dSDong Aisheng { 1033f3f5cf3dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1034f3f5cf3dSDong Aisheng struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 10352b16cf32SDong Aisheng int tmp; 1036f3f5cf3dSDong Aisheng 1037f3f5cf3dSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 1038f3f5cf3dSDong Aisheng /* 1039f3f5cf3dSDong Aisheng * The imx6q ROM code will change the default watermark 1040f3f5cf3dSDong Aisheng * level setting to something insane. Change it back here. 1041f3f5cf3dSDong Aisheng */ 1042f3f5cf3dSDong Aisheng writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1043f3f5cf3dSDong Aisheng 1044f3f5cf3dSDong Aisheng /* 1045f3f5cf3dSDong Aisheng * ROM code will change the bit burst_length_enable setting 1046d04f8d5bSBenoît Thébaudeau * to zero if this usdhc is chosen to boot system. Change 1047f3f5cf3dSDong Aisheng * it back here, otherwise it will impact the performance a 1048f3f5cf3dSDong Aisheng * lot. This bit is used to enable/disable the burst length 1049d04f8d5bSBenoît Thébaudeau * for the external AHB2AXI bridge. It's useful especially 1050f3f5cf3dSDong Aisheng * for INCR transfer because without burst length indicator, 1051f3f5cf3dSDong Aisheng * the AHB2AXI bridge does not know the burst length in 1052f3f5cf3dSDong Aisheng * advance. And without burst length indicator, AHB INCR 1053f3f5cf3dSDong Aisheng * transfer can only be converted to singles on the AXI side. 1054f3f5cf3dSDong Aisheng */ 1055f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1056f3f5cf3dSDong Aisheng | ESDHC_BURST_LEN_EN_INCR, 1057f3f5cf3dSDong Aisheng host->ioaddr + SDHCI_HOST_CONTROL); 1058f3f5cf3dSDong Aisheng /* 1059d04f8d5bSBenoît Thébaudeau * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1060f3f5cf3dSDong Aisheng * TO1.1, it's harmless for MX6SL 1061f3f5cf3dSDong Aisheng */ 1062f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + 0x6c) | BIT(7), 1063f3f5cf3dSDong Aisheng host->ioaddr + 0x6c); 1064f3f5cf3dSDong Aisheng 1065f3f5cf3dSDong Aisheng /* disable DLL_CTRL delay line settings */ 1066f3f5cf3dSDong Aisheng writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 10672b16cf32SDong Aisheng 10682b16cf32SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 10692b16cf32SDong Aisheng tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 10702b16cf32SDong Aisheng tmp |= ESDHC_STD_TUNING_EN | 10712b16cf32SDong Aisheng ESDHC_TUNING_START_TAP_DEFAULT; 10722b16cf32SDong Aisheng if (imx_data->boarddata.tuning_start_tap) { 10732b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_START_TAP_MASK; 10742b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_start_tap; 10752b16cf32SDong Aisheng } 10762b16cf32SDong Aisheng 10772b16cf32SDong Aisheng if (imx_data->boarddata.tuning_step) { 10782b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_STEP_MASK; 10792b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_step 10802b16cf32SDong Aisheng << ESDHC_TUNING_STEP_SHIFT; 10812b16cf32SDong Aisheng } 10822b16cf32SDong Aisheng writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 10832b16cf32SDong Aisheng } 1084f3f5cf3dSDong Aisheng } 1085f3f5cf3dSDong Aisheng } 1086f3f5cf3dSDong Aisheng 1087abfafc2dSShawn Guo #ifdef CONFIG_OF 1088c3be1efdSBill Pemberton static int 1089abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 109007bf2b54SSascha Hauer struct sdhci_host *host, 109191fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1092abfafc2dSShawn Guo { 1093abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 109491fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 10954800e87aSDong Aisheng int ret; 1096abfafc2dSShawn Guo 1097abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 1098abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 1099abfafc2dSShawn Guo 1100abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1101abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 1102abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 1103abfafc2dSShawn Guo 1104d407e30bSHaibo Chen of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1105d87fc966SDong Aisheng of_property_read_u32(np, "fsl,tuning-start-tap", 1106d87fc966SDong Aisheng &boarddata->tuning_start_tap); 1107d407e30bSHaibo Chen 1108ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 1109ad93220dSDong Aisheng boarddata->support_vsel = false; 1110ad93220dSDong Aisheng else 1111ad93220dSDong Aisheng boarddata->support_vsel = true; 1112ad93220dSDong Aisheng 1113602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1114602519b2SDong Aisheng boarddata->delay_line = 0; 1115602519b2SDong Aisheng 111607bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 111707bf2b54SSascha Hauer 1118d04f8d5bSBenoît Thébaudeau /* sdr50 and sdr104 need work on 1.8v signal voltage */ 111991fa4252SDong Aisheng if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && 112091fa4252SDong Aisheng !IS_ERR(imx_data->pins_default)) { 112191fa4252SDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 112291fa4252SDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 112391fa4252SDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 112491fa4252SDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 112591fa4252SDong Aisheng if (IS_ERR(imx_data->pins_100mhz) || 112691fa4252SDong Aisheng IS_ERR(imx_data->pins_200mhz)) { 112791fa4252SDong Aisheng dev_warn(mmc_dev(host->mmc), 112891fa4252SDong Aisheng "could not get ultra high speed state, work on normal mode\n"); 112991fa4252SDong Aisheng /* 1130d04f8d5bSBenoît Thébaudeau * fall back to not supporting uhs by specifying no 1131d04f8d5bSBenoît Thébaudeau * 1.8v quirk 113291fa4252SDong Aisheng */ 113391fa4252SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 113491fa4252SDong Aisheng } 113591fa4252SDong Aisheng } else { 113691fa4252SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 113791fa4252SDong Aisheng } 113891fa4252SDong Aisheng 113915064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 11404800e87aSDong Aisheng ret = mmc_of_parse(host->mmc); 11414800e87aSDong Aisheng if (ret) 11424800e87aSDong Aisheng return ret; 11434800e87aSDong Aisheng 1144287980e4SArnd Bergmann if (mmc_gpio_get_cd(host->mmc) >= 0) 11454800e87aSDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 11464800e87aSDong Aisheng 11474800e87aSDong Aisheng return 0; 1148abfafc2dSShawn Guo } 1149abfafc2dSShawn Guo #else 1150abfafc2dSShawn Guo static inline int 1151abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 115207bf2b54SSascha Hauer struct sdhci_host *host, 115391fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1154abfafc2dSShawn Guo { 1155abfafc2dSShawn Guo return -ENODEV; 1156abfafc2dSShawn Guo } 1157abfafc2dSShawn Guo #endif 1158abfafc2dSShawn Guo 115991fa4252SDong Aisheng static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 116091fa4252SDong Aisheng struct sdhci_host *host, 116191fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 116291fa4252SDong Aisheng { 116391fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 116491fa4252SDong Aisheng int err; 116591fa4252SDong Aisheng 116691fa4252SDong Aisheng if (!host->mmc->parent->platform_data) { 116791fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), "no board data!\n"); 116891fa4252SDong Aisheng return -EINVAL; 116991fa4252SDong Aisheng } 117091fa4252SDong Aisheng 117191fa4252SDong Aisheng imx_data->boarddata = *((struct esdhc_platform_data *) 117291fa4252SDong Aisheng host->mmc->parent->platform_data); 117391fa4252SDong Aisheng /* write_protect */ 117491fa4252SDong Aisheng if (boarddata->wp_type == ESDHC_WP_GPIO) { 117591fa4252SDong Aisheng err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 117691fa4252SDong Aisheng if (err) { 117791fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 117891fa4252SDong Aisheng "failed to request write-protect gpio!\n"); 117991fa4252SDong Aisheng return err; 118091fa4252SDong Aisheng } 118191fa4252SDong Aisheng host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 118291fa4252SDong Aisheng } 118391fa4252SDong Aisheng 118491fa4252SDong Aisheng /* card_detect */ 118591fa4252SDong Aisheng switch (boarddata->cd_type) { 118691fa4252SDong Aisheng case ESDHC_CD_GPIO: 118791fa4252SDong Aisheng err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 118891fa4252SDong Aisheng if (err) { 118991fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 119091fa4252SDong Aisheng "failed to request card-detect gpio!\n"); 119191fa4252SDong Aisheng return err; 119291fa4252SDong Aisheng } 119391fa4252SDong Aisheng /* fall through */ 119491fa4252SDong Aisheng 119591fa4252SDong Aisheng case ESDHC_CD_CONTROLLER: 119691fa4252SDong Aisheng /* we have a working card_detect back */ 119791fa4252SDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 119891fa4252SDong Aisheng break; 119991fa4252SDong Aisheng 120091fa4252SDong Aisheng case ESDHC_CD_PERMANENT: 120191fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 120291fa4252SDong Aisheng break; 120391fa4252SDong Aisheng 120491fa4252SDong Aisheng case ESDHC_CD_NONE: 120591fa4252SDong Aisheng break; 120691fa4252SDong Aisheng } 120791fa4252SDong Aisheng 120891fa4252SDong Aisheng switch (boarddata->max_bus_width) { 120991fa4252SDong Aisheng case 8: 121091fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 121191fa4252SDong Aisheng break; 121291fa4252SDong Aisheng case 4: 121391fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_4_BIT_DATA; 121491fa4252SDong Aisheng break; 121591fa4252SDong Aisheng case 1: 121691fa4252SDong Aisheng default: 121791fa4252SDong Aisheng host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 121891fa4252SDong Aisheng break; 121991fa4252SDong Aisheng } 122091fa4252SDong Aisheng 122191fa4252SDong Aisheng return 0; 122291fa4252SDong Aisheng } 122391fa4252SDong Aisheng 1224c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 122595f25efeSWolfram Sang { 1226abfafc2dSShawn Guo const struct of_device_id *of_id = 1227abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 122885d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 122985d6509dSShawn Guo struct sdhci_host *host; 12300c6d49ceSWolfram Sang int err; 1231e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 123295f25efeSWolfram Sang 1233070e6d3fSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1234070e6d3fSJisheng Zhang sizeof(*imx_data)); 123585d6509dSShawn Guo if (IS_ERR(host)) 123685d6509dSShawn Guo return PTR_ERR(host); 123785d6509dSShawn Guo 123885d6509dSShawn Guo pltfm_host = sdhci_priv(host); 123985d6509dSShawn Guo 1240070e6d3fSJisheng Zhang imx_data = sdhci_pltfm_priv(pltfm_host); 124157ed3314SShawn Guo 1242f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 12433770ee8fSShawn Guo pdev->id_entry->driver_data; 124485d6509dSShawn Guo 124552dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 124652dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 124752dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 1248e3af31c6SShawn Guo goto free_sdhci; 124995f25efeSWolfram Sang } 125052dac615SSascha Hauer 125152dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 125252dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 125352dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 1254e3af31c6SShawn Guo goto free_sdhci; 125552dac615SSascha Hauer } 125652dac615SSascha Hauer 125752dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 125852dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 125952dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 1260e3af31c6SShawn Guo goto free_sdhci; 126152dac615SSascha Hauer } 126252dac615SSascha Hauer 126352dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 1264a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 126517b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 126617b1eb7fSFabio Estevam if (err) 126717b1eb7fSFabio Estevam goto free_sdhci; 126817b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 126917b1eb7fSFabio Estevam if (err) 127017b1eb7fSFabio Estevam goto disable_per_clk; 127117b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ahb); 127217b1eb7fSFabio Estevam if (err) 127317b1eb7fSFabio Estevam goto disable_ipg_clk; 127495f25efeSWolfram Sang 1275ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1276e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1277e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 127817b1eb7fSFabio Estevam goto disable_ahb_clk; 1279e62d8b8fSDong Aisheng } 1280e62d8b8fSDong Aisheng 1281ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 1282ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 1283cd529af7SDirk Behme if (IS_ERR(imx_data->pins_default)) 1284cd529af7SDirk Behme dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 1285ad93220dSDong Aisheng 128669ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 128769ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1288e2997c94SDong Aisheng host->mmc->caps |= MMC_CAP_1_8V_DDR; 12894245afffSDong Aisheng if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 12904245afffSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1291a75dcbf4SDong Aisheng 1292a75dcbf4SDong Aisheng /* clear tuning bits in case ROM has set it already */ 1293a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1294a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR); 1295a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 129669ed60e0SDong Aisheng } 1297f750ba9bSShawn Guo 12986e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 12996e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 13006e9fd28eSDong Aisheng esdhc_executing_tuning; 13018b2bb0adSDong Aisheng 130218094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 130318094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 130418094430SDong Aisheng 130528b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 130628b07674SHaibo Chen host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 130728b07674SHaibo Chen 130891fa4252SDong Aisheng if (of_id) 130991fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 131091fa4252SDong Aisheng else 131191fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 131291fa4252SDong Aisheng if (err) 131317b1eb7fSFabio Estevam goto disable_ahb_clk; 1314ad93220dSDong Aisheng 1315f3f5cf3dSDong Aisheng sdhci_esdhc_imx_hwinit(host); 1316f3f5cf3dSDong Aisheng 131785d6509dSShawn Guo err = sdhci_add_host(host); 131885d6509dSShawn Guo if (err) 131917b1eb7fSFabio Estevam goto disable_ahb_clk; 132085d6509dSShawn Guo 132189d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 132289d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 132389d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 132489d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 132577903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 132689d7e5c1SDong Aisheng 13277e29c306SWolfram Sang return 0; 13287e29c306SWolfram Sang 132917b1eb7fSFabio Estevam disable_ahb_clk: 133052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 133117b1eb7fSFabio Estevam disable_ipg_clk: 133217b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 133317b1eb7fSFabio Estevam disable_per_clk: 133417b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1335e3af31c6SShawn Guo free_sdhci: 133685d6509dSShawn Guo sdhci_pltfm_free(pdev); 133785d6509dSShawn Guo return err; 133895f25efeSWolfram Sang } 133995f25efeSWolfram Sang 13406e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 134195f25efeSWolfram Sang { 134285d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 134395f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1344070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 134585d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 134685d6509dSShawn Guo 13470b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 13480b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 13490b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 13500b414368SUlf Hansson 135185d6509dSShawn Guo sdhci_remove_host(host, dead); 13520c6d49ceSWolfram Sang 135352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 135452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 135552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 135652dac615SSascha Hauer 135785d6509dSShawn Guo sdhci_pltfm_free(pdev); 135885d6509dSShawn Guo 135985d6509dSShawn Guo return 0; 136095f25efeSWolfram Sang } 136195f25efeSWolfram Sang 13622788ed42SUlf Hansson #ifdef CONFIG_PM_SLEEP 136304143fbaSDong Aisheng static int sdhci_esdhc_suspend(struct device *dev) 136404143fbaSDong Aisheng { 13653e3274abSUlf Hansson struct sdhci_host *host = dev_get_drvdata(dev); 13663e3274abSUlf Hansson 1367d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1368d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1369d38dcad4SAdrian Hunter 13703e3274abSUlf Hansson return sdhci_suspend_host(host); 137104143fbaSDong Aisheng } 137204143fbaSDong Aisheng 137304143fbaSDong Aisheng static int sdhci_esdhc_resume(struct device *dev) 137404143fbaSDong Aisheng { 1375cc17e129SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 1376cc17e129SDong Aisheng 137719dbfdd3SDong Aisheng /* re-initialize hw state in case it's lost in low power mode */ 137819dbfdd3SDong Aisheng sdhci_esdhc_imx_hwinit(host); 1379cc17e129SDong Aisheng 13803e3274abSUlf Hansson return sdhci_resume_host(host); 138104143fbaSDong Aisheng } 13822788ed42SUlf Hansson #endif 138304143fbaSDong Aisheng 13842788ed42SUlf Hansson #ifdef CONFIG_PM 138589d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 138689d7e5c1SDong Aisheng { 138789d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 138889d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1389070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 139089d7e5c1SDong Aisheng int ret; 139189d7e5c1SDong Aisheng 139289d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 1393371d39faSMichael Trimarchi if (ret) 1394371d39faSMichael Trimarchi return ret; 139589d7e5c1SDong Aisheng 1396d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1397d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1398d38dcad4SAdrian Hunter 1399be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 14003602785bSMichael Trimarchi imx_data->actual_clock = host->mmc->actual_clock; 14013602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, 0); 140289d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 140389d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 1404be138554SRussell King } 140589d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 140689d7e5c1SDong Aisheng 140789d7e5c1SDong Aisheng return ret; 140889d7e5c1SDong Aisheng } 140989d7e5c1SDong Aisheng 141089d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 141189d7e5c1SDong Aisheng { 141289d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 141389d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1414070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 141517b1eb7fSFabio Estevam int err; 141689d7e5c1SDong Aisheng 1417a0ad3087SMichael Trimarchi err = clk_prepare_enable(imx_data->clk_ahb); 1418a0ad3087SMichael Trimarchi if (err) 1419a0ad3087SMichael Trimarchi return err; 1420a0ad3087SMichael Trimarchi 1421be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 142217b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 142317b1eb7fSFabio Estevam if (err) 1424a0ad3087SMichael Trimarchi goto disable_ahb_clk; 142517b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 142617b1eb7fSFabio Estevam if (err) 142717b1eb7fSFabio Estevam goto disable_per_clk; 14283602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1429be138554SRussell King } 1430a0ad3087SMichael Trimarchi 143117b1eb7fSFabio Estevam err = sdhci_runtime_resume_host(host); 143217b1eb7fSFabio Estevam if (err) 1433a0ad3087SMichael Trimarchi goto disable_ipg_clk; 143489d7e5c1SDong Aisheng 143517b1eb7fSFabio Estevam return 0; 143617b1eb7fSFabio Estevam 143717b1eb7fSFabio Estevam disable_ipg_clk: 143817b1eb7fSFabio Estevam if (!sdhci_sdio_irq_enabled(host)) 143917b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 144017b1eb7fSFabio Estevam disable_per_clk: 144117b1eb7fSFabio Estevam if (!sdhci_sdio_irq_enabled(host)) 144217b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1443a0ad3087SMichael Trimarchi disable_ahb_clk: 1444a0ad3087SMichael Trimarchi clk_disable_unprepare(imx_data->clk_ahb); 144517b1eb7fSFabio Estevam return err; 144689d7e5c1SDong Aisheng } 144789d7e5c1SDong Aisheng #endif 144889d7e5c1SDong Aisheng 144989d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 145004143fbaSDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 145189d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 145289d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 145389d7e5c1SDong Aisheng }; 145489d7e5c1SDong Aisheng 145585d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 145685d6509dSShawn Guo .driver = { 145785d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1458abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 145989d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 146085d6509dSShawn Guo }, 146157ed3314SShawn Guo .id_table = imx_esdhc_devtype, 146285d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 14630433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 146495f25efeSWolfram Sang }; 146585d6509dSShawn Guo 1466d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 146785d6509dSShawn Guo 146885d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1469035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 147085d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1471