1a6e7e407SFabio Estevam // SPDX-License-Identifier: GPL-2.0 295f25efeSWolfram Sang /* 395f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 495f25efeSWolfram Sang * 595f25efeSWolfram Sang * derived from the OF-version. 695f25efeSWolfram Sang * 795f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 8035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 995f25efeSWolfram Sang */ 1095f25efeSWolfram Sang 1195f25efeSWolfram Sang #include <linux/io.h> 1295f25efeSWolfram Sang #include <linux/delay.h> 1395f25efeSWolfram Sang #include <linux/err.h> 1495f25efeSWolfram Sang #include <linux/clk.h> 1566506f76SShawn Guo #include <linux/module.h> 16e149860dSRichard Zhu #include <linux/slab.h> 171c4989b0SBOUGH CHEN #include <linux/pm_qos.h> 1895f25efeSWolfram Sang #include <linux/mmc/host.h> 1958ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2058ac8177SRichard Zhu #include <linux/mmc/sdio.h> 21fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 22abfafc2dSShawn Guo #include <linux/of.h> 23abfafc2dSShawn Guo #include <linux/of_device.h> 24e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2582906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 2689d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 2795f25efeSWolfram Sang #include "sdhci-pltfm.h" 2895f25efeSWolfram Sang #include "sdhci-esdhc.h" 29bb6e3581SBOUGH CHEN #include "cqhci.h" 3095f25efeSWolfram Sang 31a215186dSHaibo Chen #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 3260bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 33fd44954eSHaibo Chen #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 3458ac8177SRichard Zhu /* VENDOR SPEC register */ 3560bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 370322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 38fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 3960bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 40cc17e129SDong Aisheng #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 413fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 423fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 433fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 443fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 453fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 463fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 4760bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 48de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 492a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 500322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 510322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 520b330e38SDong Aisheng #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 530322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 5428b07674SHaibo Chen #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 55029e2476SBOUGH CHEN #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27) 562a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 572a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 58d131a71cSDong Aisheng /* Tuning bits */ 59d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 6058ac8177SRichard Zhu 61602519b2SDong Aisheng /* dll control register */ 62602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 63602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 64602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 65602519b2SDong Aisheng 660322191eSDong Aisheng /* tune control register */ 670322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 680322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 690322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 700322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 710322191eSDong Aisheng 7228b07674SHaibo Chen /* strobe dll register */ 7328b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL 0x70 7428b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 7528b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 7628b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 772eaf5a53SBOUGH CHEN #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) 7828b07674SHaibo Chen 7928b07674SHaibo Chen #define ESDHC_STROBE_DLL_STATUS 0x74 8028b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 8128b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 8228b07674SHaibo Chen 83bcdb5301SBOUGH CHEN #define ESDHC_VEND_SPEC2 0xc8 84bcdb5301SBOUGH CHEN #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8) 85bcdb5301SBOUGH CHEN 866e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 876e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 886e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 89d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 90d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_MASK 0xff 91260ecb3cSHaibo Chen #define ESDHC_TUNING_STEP_MASK 0x00070000 92d407e30bSHaibo Chen #define ESDHC_TUNING_STEP_SHIFT 16 936e9fd28eSDong Aisheng 94ad93220dSDong Aisheng /* pinctrl state */ 95ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 96ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 97ad93220dSDong Aisheng 9858ac8177SRichard Zhu /* 99af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 100af51079eSSascha Hauer */ 101af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 102af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 103af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 104af51079eSSascha Hauer 105af51079eSSascha Hauer /* 106d04f8d5bSBenoît Thébaudeau * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 10797e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 10897e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 10997e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 11097e4ba6aSRichard Zhu */ 11160bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 11297e4ba6aSRichard Zhu 113bb6e3581SBOUGH CHEN /* the address offset of CQHCI */ 114bb6e3581SBOUGH CHEN #define ESDHC_CQHCI_ADDR_OFFSET 0x100 115bb6e3581SBOUGH CHEN 11697e4ba6aSRichard Zhu /* 11758ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 11858ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 11958ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 12058ac8177SRichard Zhu * be generated. 12158ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 12258ac8177SRichard Zhu * operations automatically as required at the end of the 12358ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 12458ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 125d04f8d5bSBenoît Thébaudeau * exception. Bit1 of Vendor Spec register is used to fix it. 12658ac8177SRichard Zhu */ 12731fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 12831fbb301SShawn Guo /* 1299d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1309d61c009SShawn Guo * integrated on the i.MX6 series. 1319d61c009SShawn Guo */ 1329d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1336e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1346e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1356e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1366e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1376e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1386e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 13918094430SDong Aisheng /* 140d04f8d5bSBenoît Thébaudeau * The IP has erratum ERR004536 14118094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 14218094430SDong Aisheng * when reading data from the card 143667123f6SBenoît Thébaudeau * This flag is also set for i.MX25 and i.MX35 in order to get 144667123f6SBenoît Thébaudeau * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 14518094430SDong Aisheng */ 14618094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 1474245afffSDong Aisheng /* The IP supports HS200 mode */ 1484245afffSDong Aisheng #define ESDHC_FLAG_HS200 BIT(8) 14928b07674SHaibo Chen /* The IP supports HS400 mode */ 15028b07674SHaibo Chen #define ESDHC_FLAG_HS400 BIT(9) 151af6a50d4SBOUGH CHEN /* 152af6a50d4SBOUGH CHEN * The IP has errata ERR010450 153af6a50d4SBOUGH CHEN * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't 154af6a50d4SBOUGH CHEN * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. 155af6a50d4SBOUGH CHEN */ 156af6a50d4SBOUGH CHEN #define ESDHC_FLAG_ERR010450 BIT(10) 157029e2476SBOUGH CHEN /* The IP supports HS400ES mode */ 158029e2476SBOUGH CHEN #define ESDHC_FLAG_HS400_ES BIT(11) 159bb6e3581SBOUGH CHEN /* The IP has Host Controller Interface for Command Queuing */ 160bb6e3581SBOUGH CHEN #define ESDHC_FLAG_CQHCI BIT(12) 1611c4989b0SBOUGH CHEN /* need request pmqos during low power */ 1621c4989b0SBOUGH CHEN #define ESDHC_FLAG_PMQOS BIT(13) 163e149860dSRichard Zhu 164f47c4bbfSShawn Guo struct esdhc_soc_data { 165f47c4bbfSShawn Guo u32 flags; 166f47c4bbfSShawn Guo }; 167f47c4bbfSShawn Guo 1684f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx25_data = { 169667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 170f47c4bbfSShawn Guo }; 171f47c4bbfSShawn Guo 1724f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx35_data = { 173667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 174f47c4bbfSShawn Guo }; 175f47c4bbfSShawn Guo 1764f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx51_data = { 177f47c4bbfSShawn Guo .flags = 0, 178f47c4bbfSShawn Guo }; 179f47c4bbfSShawn Guo 1804f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx53_data = { 181f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 182f47c4bbfSShawn Guo }; 183f47c4bbfSShawn Guo 1844f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6q_data = { 1856e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1866e9fd28eSDong Aisheng }; 1876e9fd28eSDong Aisheng 1884f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sl_data = { 1896e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1904245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 1914245afffSDong Aisheng | ESDHC_FLAG_HS200, 19257ed3314SShawn Guo }; 19357ed3314SShawn Guo 1944f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sx_data = { 195913d4951SDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1964245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 197913d4951SDong Aisheng }; 198913d4951SDong Aisheng 199af6a50d4SBOUGH CHEN static const struct esdhc_soc_data usdhc_imx6ull_data = { 200af6a50d4SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 201af6a50d4SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 202af6a50d4SBOUGH CHEN | ESDHC_FLAG_ERR010450, 203af6a50d4SBOUGH CHEN }; 204af6a50d4SBOUGH CHEN 2054f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx7d_data = { 20628b07674SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 20728b07674SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 20828b07674SHaibo Chen | ESDHC_FLAG_HS400, 20928b07674SHaibo Chen }; 21028b07674SHaibo Chen 2111c4989b0SBOUGH CHEN static struct esdhc_soc_data usdhc_imx7ulp_data = { 2121c4989b0SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 2131c4989b0SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 2142eaf5a53SBOUGH CHEN | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400, 2151c4989b0SBOUGH CHEN }; 2161c4989b0SBOUGH CHEN 217029e2476SBOUGH CHEN static struct esdhc_soc_data usdhc_imx8qxp_data = { 218029e2476SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 219029e2476SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 220bb6e3581SBOUGH CHEN | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 221bb6e3581SBOUGH CHEN | ESDHC_FLAG_CQHCI, 222029e2476SBOUGH CHEN }; 223029e2476SBOUGH CHEN 224e149860dSRichard Zhu struct pltfm_imx_data { 225e149860dSRichard Zhu u32 scratchpad; 226e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 227ad93220dSDong Aisheng struct pinctrl_state *pins_default; 228ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 229ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 230f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 231842afc02SShawn Guo struct esdhc_platform_data boarddata; 23252dac615SSascha Hauer struct clk *clk_ipg; 23352dac615SSascha Hauer struct clk *clk_ahb; 23452dac615SSascha Hauer struct clk *clk_per; 2353602785bSMichael Trimarchi unsigned int actual_clock; 236361b8482SLucas Stach enum { 237361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending */ 238361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 239361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 240361b8482SLucas Stach } multiblock_status; 241de5bdbffSDong Aisheng u32 is_ddr; 2421c4989b0SBOUGH CHEN struct pm_qos_request pm_qos_req; 243e149860dSRichard Zhu }; 244e149860dSRichard Zhu 245f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 24657ed3314SShawn Guo { 24757ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 248f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 24957ed3314SShawn Guo }, { 25057ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 251f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 25257ed3314SShawn Guo }, { 25357ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 254f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 25557ed3314SShawn Guo }, { 25657ed3314SShawn Guo /* sentinel */ 25757ed3314SShawn Guo } 25857ed3314SShawn Guo }; 25957ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 26057ed3314SShawn Guo 261abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 262f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 263f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 264f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 265f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 266913d4951SDong Aisheng { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 2676e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 268f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 269af6a50d4SBOUGH CHEN { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, 27028b07674SHaibo Chen { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 2711c4989b0SBOUGH CHEN { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, }, 272029e2476SBOUGH CHEN { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, }, 273abfafc2dSShawn Guo { /* sentinel */ } 274abfafc2dSShawn Guo }; 275abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 276abfafc2dSShawn Guo 27757ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 27857ed3314SShawn Guo { 279f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 28057ed3314SShawn Guo } 28157ed3314SShawn Guo 28257ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 28357ed3314SShawn Guo { 284f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 28557ed3314SShawn Guo } 28657ed3314SShawn Guo 28795a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 28895a2482aSShawn Guo { 289f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 29095a2482aSShawn Guo } 29195a2482aSShawn Guo 2929d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2939d61c009SShawn Guo { 294f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2959d61c009SShawn Guo } 2969d61c009SShawn Guo 29795f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 29895f25efeSWolfram Sang { 29995f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 30095f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 30195f25efeSWolfram Sang 30295f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 30395f25efeSWolfram Sang } 30495f25efeSWolfram Sang 3057e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 3067e29c306SWolfram Sang { 307361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 308070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 309913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 310913413c3SShawn Guo 3110322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 3120322191eSDong Aisheng u32 fsl_prss = val; 3130322191eSDong Aisheng /* save the least 20 bits */ 3140322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 3150322191eSDong Aisheng /* move dat[0-3] bits */ 3160322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 3170322191eSDong Aisheng /* move cmd line bit */ 3180322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 3190322191eSDong Aisheng } 3200322191eSDong Aisheng 32197e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 3226b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 3236b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3246b4fb671SDong Aisheng val &= 0xffff0000; 3256b4fb671SDong Aisheng 32697e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 32797e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 32897e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 32997e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 330d04f8d5bSBenoît Thébaudeau * quirk on MX25/35 platforms. 33197e4ba6aSRichard Zhu */ 33297e4ba6aSRichard Zhu 33397e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 33497e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 33597e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 33697e4ba6aSRichard Zhu } 33797e4ba6aSRichard Zhu } 33897e4ba6aSRichard Zhu 3396e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 3406e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 3416e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3426e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 3436e9fd28eSDong Aisheng else 3446e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 3450322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 346888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 347da0295ffSDong Aisheng | SDHCI_USE_SDR50_TUNING 348da0295ffSDong Aisheng | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); 34928b07674SHaibo Chen 35028b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 35128b07674SHaibo Chen val |= SDHCI_SUPPORT_HS400; 35292748beaSStefan Agner 35392748beaSStefan Agner /* 35492748beaSStefan Agner * Do not advertise faster UHS modes if there are no 35592748beaSStefan Agner * pinctrl states for 100MHz/200MHz. 35692748beaSStefan Agner */ 35792748beaSStefan Agner if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || 35892748beaSStefan Agner IS_ERR_OR_NULL(imx_data->pins_200mhz)) 35992748beaSStefan Agner val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50 36092748beaSStefan Agner | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 3616e9fd28eSDong Aisheng } 3626e9fd28eSDong Aisheng } 3630322191eSDong Aisheng 3649d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 3650322191eSDong Aisheng val = 0; 3660322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 3670322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 3680322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 3690322191eSDong Aisheng } 3700322191eSDong Aisheng 37197e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 37260bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 37360bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 37497e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 37597e4ba6aSRichard Zhu } 376361b8482SLucas Stach 377361b8482SLucas Stach /* 378361b8482SLucas Stach * mask off the interrupt we get in response to the manually 379361b8482SLucas Stach * sent CMD12 380361b8482SLucas Stach */ 381361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 382361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 383361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 384361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 385361b8482SLucas Stach SDHCI_INT_STATUS); 386361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 387361b8482SLucas Stach } 38897e4ba6aSRichard Zhu } 38997e4ba6aSRichard Zhu 3907e29c306SWolfram Sang return val; 3917e29c306SWolfram Sang } 3927e29c306SWolfram Sang 3937e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 3947e29c306SWolfram Sang { 395e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 396070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 3970d58864bSTony Lin u32 data; 398e149860dSRichard Zhu 39977da3da0SAaron Brice if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 40077da3da0SAaron Brice reg == SDHCI_INT_STATUS)) { 401b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 4020d58864bSTony Lin /* 4030d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 404d04f8d5bSBenoît Thébaudeau * card interrupt. This is an eSDHC controller problem 4050d58864bSTony Lin * so we need to apply the following workaround: clear 4060d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 4070d58864bSTony Lin * interrupt. In case a card interrupt was lost, 4080d58864bSTony Lin * re-sample it by the following steps. 4090d58864bSTony Lin */ 4100d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 41160bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 4120d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 41360bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 4140d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 4150d58864bSTony Lin } 416915be485SDong Aisheng 417915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 418915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 419915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 420915be485SDong Aisheng } 4210d58864bSTony Lin } 4220d58864bSTony Lin 423f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 42458ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 42558ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 42658ac8177SRichard Zhu u32 v; 42760bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 42860bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 42960bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 430361b8482SLucas Stach 431361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 432361b8482SLucas Stach { 433361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 434361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 435361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 436361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 437361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 438361b8482SLucas Stach } 43958ac8177SRichard Zhu } 44058ac8177SRichard Zhu 4417e29c306SWolfram Sang writel(val, host->ioaddr + reg); 4427e29c306SWolfram Sang } 4437e29c306SWolfram Sang 44495f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 44595f25efeSWolfram Sang { 446ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 447070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 4480322191eSDong Aisheng u16 ret = 0; 4490322191eSDong Aisheng u32 val; 450ef4d0888SShawn Guo 45195a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 452ef4d0888SShawn Guo reg ^= 2; 4539d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 45495a2482aSShawn Guo /* 455ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 456ef4d0888SShawn Guo * Correct it here. 45795a2482aSShawn Guo */ 458ef4d0888SShawn Guo return SDHCI_SPEC_300; 459ef4d0888SShawn Guo } 46095a2482aSShawn Guo } 46195f25efeSWolfram Sang 4620322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 4630322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4640322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 4650322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 4660322191eSDong Aisheng 4679d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 4686e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 4690322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4706e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 4716e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 472869f8a69SAdrian Hunter val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 4736e9fd28eSDong Aisheng } 4746e9fd28eSDong Aisheng 4750322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 4760322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 4770322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 4780322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 4790322191eSDong Aisheng 4800322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 4810322191eSDong Aisheng 4820322191eSDong Aisheng return ret; 4830322191eSDong Aisheng } 4840322191eSDong Aisheng 4857dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 4867dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 4877dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4887dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 4897dd109efSDong Aisheng /* Swap AC23 bit */ 4907dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 4917dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 4927dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 4937dd109efSDong Aisheng } 4947dd109efSDong Aisheng } else { 4957dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 4967dd109efSDong Aisheng } 4977dd109efSDong Aisheng 4987dd109efSDong Aisheng return ret; 4997dd109efSDong Aisheng } 5007dd109efSDong Aisheng 50195f25efeSWolfram Sang return readw(host->ioaddr + reg); 50295f25efeSWolfram Sang } 50395f25efeSWolfram Sang 50495f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 50595f25efeSWolfram Sang { 50695f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 507070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 5080322191eSDong Aisheng u32 new_val = 0; 50995f25efeSWolfram Sang 51095f25efeSWolfram Sang switch (reg) { 5110322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 5120322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5130322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 5140322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 5150322191eSDong Aisheng else 5160322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 5170322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 5180322191eSDong Aisheng return; 5190322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 5200322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5210322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 5220322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 5230322191eSDong Aisheng else 5240322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 5250322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 5266e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 5270322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 528da0295ffSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 5290322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 530da0295ffSDong Aisheng new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 531da0295ffSDong Aisheng } else { 5320322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 533da0295ffSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 534da0295ffSDong Aisheng } 5350322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 5366e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 537869f8a69SAdrian Hunter u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 5386e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5398b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 5408b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 5416e9fd28eSDong Aisheng } else { 5428b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 5436e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 5440b330e38SDong Aisheng m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 5456e9fd28eSDong Aisheng } 5466e9fd28eSDong Aisheng 5478b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 5488b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 5498b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 5500b330e38SDong Aisheng m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 5518b2bb0adSDong Aisheng } else { 5528b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 5538b2bb0adSDong Aisheng } 5546e9fd28eSDong Aisheng 555869f8a69SAdrian Hunter writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 5566e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5576e9fd28eSDong Aisheng } 5580322191eSDong Aisheng return; 55995f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 560f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 56158ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 56258ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 56358ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 56458ac8177SRichard Zhu u32 v; 56560bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 56660bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 56760bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 56858ac8177SRichard Zhu } 56969f54698SShawn Guo 5709d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 5713fbd4322SAndrew Gabbasov u32 wml; 57269f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5732a15f981SShawn Guo /* Swap AC23 bit */ 5742a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 5752a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 5762a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 5772a15f981SShawn Guo } 5782a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 57969f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5803fbd4322SAndrew Gabbasov 5813fbd4322SAndrew Gabbasov /* Set watermark levels for PIO access to maximum value 5823fbd4322SAndrew Gabbasov * (128 words) to accommodate full 512 bytes buffer. 5833fbd4322SAndrew Gabbasov * For DMA access restore the levels to default value. 5843fbd4322SAndrew Gabbasov */ 5853fbd4322SAndrew Gabbasov m = readl(host->ioaddr + ESDHC_WTMK_LVL); 5863fbd4322SAndrew Gabbasov if (val & SDHCI_TRNS_DMA) 5873fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 5883fbd4322SAndrew Gabbasov else 5893fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 5903fbd4322SAndrew Gabbasov m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 5913fbd4322SAndrew Gabbasov ESDHC_WTMK_LVL_WR_WML_MASK); 5923fbd4322SAndrew Gabbasov m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 5933fbd4322SAndrew Gabbasov (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 5943fbd4322SAndrew Gabbasov writel(m, host->ioaddr + ESDHC_WTMK_LVL); 59569f54698SShawn Guo } else { 59669f54698SShawn Guo /* 59769f54698SShawn Guo * Postpone this write, we must do it together with a 59869f54698SShawn Guo * command write that is down below. 59969f54698SShawn Guo */ 600e149860dSRichard Zhu imx_data->scratchpad = val; 60169f54698SShawn Guo } 60295f25efeSWolfram Sang return; 60395f25efeSWolfram Sang case SDHCI_COMMAND: 604361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 60558ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 60695a2482aSShawn Guo 607361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 608f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 609361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 610361b8482SLucas Stach 6119d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 61295a2482aSShawn Guo writel(val << 16, 61395a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 61469f54698SShawn Guo else 615e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 61695f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 61795f25efeSWolfram Sang return; 61895f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 61995f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 62095f25efeSWolfram Sang break; 62195f25efeSWolfram Sang } 62295f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 62395f25efeSWolfram Sang } 62495f25efeSWolfram Sang 62577da3da0SAaron Brice static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 62677da3da0SAaron Brice { 62777da3da0SAaron Brice u8 ret; 62877da3da0SAaron Brice u32 val; 62977da3da0SAaron Brice 63077da3da0SAaron Brice switch (reg) { 63177da3da0SAaron Brice case SDHCI_HOST_CONTROL: 63277da3da0SAaron Brice val = readl(host->ioaddr + reg); 63377da3da0SAaron Brice 63477da3da0SAaron Brice ret = val & SDHCI_CTRL_LED; 63577da3da0SAaron Brice ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 63677da3da0SAaron Brice ret |= (val & ESDHC_CTRL_4BITBUS); 63777da3da0SAaron Brice ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 63877da3da0SAaron Brice return ret; 63977da3da0SAaron Brice } 64077da3da0SAaron Brice 64177da3da0SAaron Brice return readb(host->ioaddr + reg); 64277da3da0SAaron Brice } 64377da3da0SAaron Brice 64495f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 64595f25efeSWolfram Sang { 6469a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 647070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 64881a0a8bcSBenoît Thébaudeau u32 new_val = 0; 649af51079eSSascha Hauer u32 mask; 65095f25efeSWolfram Sang 65195f25efeSWolfram Sang switch (reg) { 65295f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 65395f25efeSWolfram Sang /* 65495f25efeSWolfram Sang * FSL put some DMA bits here 65595f25efeSWolfram Sang * If your board has a regulator, code should be here 65695f25efeSWolfram Sang */ 65795f25efeSWolfram Sang return; 65895f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 6596b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 660af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 6617122bbb0SMasanari Iida /* ensure the endianness */ 66295f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 6639a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 6649a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 66595f25efeSWolfram Sang /* DMA mode bits are shifted */ 66695f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 6679a0985b7SWilson Callan } 66895f25efeSWolfram Sang 669af51079eSSascha Hauer /* 670af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 671af51079eSSascha Hauer * esdhc_pltfm_bus_width. 672f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 673d04f8d5bSBenoît Thébaudeau * SDIO interrupt erratum workaround. 674af51079eSSascha Hauer */ 675f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 676af51079eSSascha Hauer 677af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 67895f25efeSWolfram Sang return; 67981a0a8bcSBenoît Thébaudeau case SDHCI_SOFTWARE_RESET: 68081a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_DATA) 68181a0a8bcSBenoît Thébaudeau new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 68281a0a8bcSBenoît Thébaudeau break; 68395f25efeSWolfram Sang } 68495f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 685913413c3SShawn Guo 68681a0a8bcSBenoît Thébaudeau if (reg == SDHCI_SOFTWARE_RESET) { 68781a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_ALL) { 688913413c3SShawn Guo /* 68981a0a8bcSBenoît Thébaudeau * The esdhc has a design violation to SDHC spec which 69081a0a8bcSBenoît Thébaudeau * tells that software reset should not affect card 69181a0a8bcSBenoît Thébaudeau * detection circuit. But esdhc clears its SYSCTL 69281a0a8bcSBenoît Thébaudeau * register bits [0..2] during the software reset. This 69381a0a8bcSBenoît Thébaudeau * will stop those clocks that card detection circuit 69481a0a8bcSBenoît Thébaudeau * relies on. To work around it, we turn the clocks on 69581a0a8bcSBenoît Thébaudeau * back to keep card detection circuit functional. 696913413c3SShawn Guo */ 697913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 69858c8c4fbSShawn Guo /* 69958c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 70058c8c4fbSShawn Guo * Do it manually here. 70158c8c4fbSShawn Guo */ 702de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 70381a0a8bcSBenoît Thébaudeau /* 70481a0a8bcSBenoît Thébaudeau * the tuning bits should be kept during reset 70581a0a8bcSBenoît Thébaudeau */ 706d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 707d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 708d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 709de5bdbffSDong Aisheng imx_data->is_ddr = 0; 710de5bdbffSDong Aisheng } 71181a0a8bcSBenoît Thébaudeau } else if (val & SDHCI_RESET_DATA) { 71281a0a8bcSBenoît Thébaudeau /* 71381a0a8bcSBenoît Thébaudeau * The eSDHC DAT line software reset clears at least the 71481a0a8bcSBenoît Thébaudeau * data transfer width on i.MX25, so make sure that the 71581a0a8bcSBenoît Thébaudeau * Host Control register is unaffected. 71681a0a8bcSBenoît Thébaudeau */ 71781a0a8bcSBenoît Thébaudeau esdhc_clrset_le(host, 0xff, new_val, 71881a0a8bcSBenoît Thébaudeau SDHCI_HOST_CONTROL); 71981a0a8bcSBenoît Thébaudeau } 72058c8c4fbSShawn Guo } 72195f25efeSWolfram Sang } 72295f25efeSWolfram Sang 7230ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 7240ddf03c9SLucas Stach { 7250ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 7260ddf03c9SLucas Stach 727a974862fSDong Aisheng return pltfm_host->clock; 7280ddf03c9SLucas Stach } 7290ddf03c9SLucas Stach 73095f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 73195f25efeSWolfram Sang { 73295f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 73395f25efeSWolfram Sang 734a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 73595f25efeSWolfram Sang } 73695f25efeSWolfram Sang 7378ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 7388ba9580aSLucas Stach unsigned int clock) 7398ba9580aSLucas Stach { 7408ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 741070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 742a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 7435143c953SBenoît Thébaudeau int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 7445143c953SBenoît Thébaudeau int pre_div = 1; 745d31fc00aSDong Aisheng int div = 1; 746fed2f6e2SDong Aisheng u32 temp, val; 7478ba9580aSLucas Stach 7489d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 749fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 750fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 751fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 752fed2f6e2SDong Aisheng } 75373e736f8SStefan Agner 75473e736f8SStefan Agner if (clock == 0) { 75573e736f8SStefan Agner host->mmc->actual_clock = 0; 756373073efSRussell King return; 757fed2f6e2SDong Aisheng } 758d31fc00aSDong Aisheng 759499ed50fSBenoît Thébaudeau /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 760499ed50fSBenoît Thébaudeau if (is_imx53_esdhc(imx_data)) { 761499ed50fSBenoît Thébaudeau /* 762499ed50fSBenoît Thébaudeau * According to the i.MX53 reference manual, if DLLCTRL[10] can 763499ed50fSBenoît Thébaudeau * be set, then the controller is eSDHCv3, else it is eSDHCv2. 764499ed50fSBenoît Thébaudeau */ 765499ed50fSBenoît Thébaudeau val = readl(host->ioaddr + ESDHC_DLL_CTRL); 766499ed50fSBenoît Thébaudeau writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 767499ed50fSBenoît Thébaudeau temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 768499ed50fSBenoît Thébaudeau writel(val, host->ioaddr + ESDHC_DLL_CTRL); 769499ed50fSBenoît Thébaudeau if (temp & BIT(10)) 770499ed50fSBenoît Thébaudeau pre_div = 2; 771499ed50fSBenoît Thébaudeau } 772499ed50fSBenoît Thébaudeau 773d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 774d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 775d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 776d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 777d31fc00aSDong Aisheng 778af6a50d4SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { 779af6a50d4SBOUGH CHEN unsigned int max_clock; 780af6a50d4SBOUGH CHEN 781af6a50d4SBOUGH CHEN max_clock = imx_data->is_ddr ? 45000000 : 150000000; 782af6a50d4SBOUGH CHEN 783af6a50d4SBOUGH CHEN clock = min(clock, max_clock); 784af6a50d4SBOUGH CHEN } 785af6a50d4SBOUGH CHEN 7865143c953SBenoît Thébaudeau while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 7875143c953SBenoît Thébaudeau pre_div < 256) 788d31fc00aSDong Aisheng pre_div *= 2; 789d31fc00aSDong Aisheng 7905143c953SBenoît Thébaudeau while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 791d31fc00aSDong Aisheng div++; 792d31fc00aSDong Aisheng 7935143c953SBenoît Thébaudeau host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 794d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 795e76b8559SDong Aisheng clock, host->mmc->actual_clock); 796d31fc00aSDong Aisheng 797d31fc00aSDong Aisheng pre_div >>= 1; 798d31fc00aSDong Aisheng div--; 799d31fc00aSDong Aisheng 800d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 801d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 802d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 803d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 804d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 805fed2f6e2SDong Aisheng 8069d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 807fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 808fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 809fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 810fed2f6e2SDong Aisheng } 811fed2f6e2SDong Aisheng 812d31fc00aSDong Aisheng mdelay(1); 8138ba9580aSLucas Stach } 8148ba9580aSLucas Stach 815913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 816913413c3SShawn Guo { 817842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 818070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 819842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 820913413c3SShawn Guo 821913413c3SShawn Guo switch (boarddata->wp_type) { 822913413c3SShawn Guo case ESDHC_WP_GPIO: 823fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 824913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 825913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 826913413c3SShawn Guo SDHCI_WRITE_PROTECT); 827913413c3SShawn Guo case ESDHC_WP_NONE: 828913413c3SShawn Guo break; 829913413c3SShawn Guo } 830913413c3SShawn Guo 831913413c3SShawn Guo return -ENOSYS; 832913413c3SShawn Guo } 833913413c3SShawn Guo 8342317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 835af51079eSSascha Hauer { 836af51079eSSascha Hauer u32 ctrl; 837af51079eSSascha Hauer 838af51079eSSascha Hauer switch (width) { 839af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 840af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 841af51079eSSascha Hauer break; 842af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 843af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 844af51079eSSascha Hauer break; 845af51079eSSascha Hauer default: 846af51079eSSascha Hauer ctrl = 0; 847af51079eSSascha Hauer break; 848af51079eSSascha Hauer } 849af51079eSSascha Hauer 850af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 851af51079eSSascha Hauer SDHCI_HOST_CONTROL); 852af51079eSSascha Hauer } 853af51079eSSascha Hauer 854de3e1dd0SBOUGH CHEN static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 855de3e1dd0SBOUGH CHEN { 856de3e1dd0SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 857de3e1dd0SBOUGH CHEN 858de3e1dd0SBOUGH CHEN /* 859de3e1dd0SBOUGH CHEN * i.MX uSDHC internally already uses a fixed optimized timing for 860de3e1dd0SBOUGH CHEN * DDR50, normally does not require tuning for DDR50 mode. 861de3e1dd0SBOUGH CHEN */ 862de3e1dd0SBOUGH CHEN if (host->timing == MMC_TIMING_UHS_DDR50) 863de3e1dd0SBOUGH CHEN return 0; 864de3e1dd0SBOUGH CHEN 865de3e1dd0SBOUGH CHEN return sdhci_execute_tuning(mmc, opcode); 866de3e1dd0SBOUGH CHEN } 867de3e1dd0SBOUGH CHEN 8680322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 8690322191eSDong Aisheng { 8700322191eSDong Aisheng u32 reg; 8710322191eSDong Aisheng 8720322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 8730322191eSDong Aisheng mdelay(1); 8740322191eSDong Aisheng 8750322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 8760322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 8770322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 8780322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 8790322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 8800322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 881d04f8d5bSBenoît Thébaudeau "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 8820322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 8830322191eSDong Aisheng } 8840322191eSDong Aisheng 8850322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 8860322191eSDong Aisheng { 8870322191eSDong Aisheng u32 reg; 8880322191eSDong Aisheng 8890322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 8900322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 891da0295ffSDong Aisheng reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 8920322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 8930322191eSDong Aisheng } 8940322191eSDong Aisheng 8950322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 8960322191eSDong Aisheng { 8970322191eSDong Aisheng int min, max, avg, ret; 8980322191eSDong Aisheng 8990322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 9000322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 9010322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 9020322191eSDong Aisheng esdhc_prepare_tuning(host, min); 9039979dbe5SChaotian Jing if (!mmc_send_tuning(host->mmc, opcode, NULL)) 9040322191eSDong Aisheng break; 9050322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 9060322191eSDong Aisheng } 9070322191eSDong Aisheng 9080322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 9090322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 9100322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 9110322191eSDong Aisheng esdhc_prepare_tuning(host, max); 9129979dbe5SChaotian Jing if (mmc_send_tuning(host->mmc, opcode, NULL)) { 9130322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 9140322191eSDong Aisheng break; 9150322191eSDong Aisheng } 9160322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 9170322191eSDong Aisheng } 9180322191eSDong Aisheng 9190322191eSDong Aisheng /* use average delay to get the best timing */ 9200322191eSDong Aisheng avg = (min + max) / 2; 9210322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 9229979dbe5SChaotian Jing ret = mmc_send_tuning(host->mmc, opcode, NULL); 9230322191eSDong Aisheng esdhc_post_tuning(host); 9240322191eSDong Aisheng 925d04f8d5bSBenoît Thébaudeau dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 9260322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 9270322191eSDong Aisheng 9280322191eSDong Aisheng return ret; 9290322191eSDong Aisheng } 9300322191eSDong Aisheng 931029e2476SBOUGH CHEN static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) 932029e2476SBOUGH CHEN { 933029e2476SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 934029e2476SBOUGH CHEN u32 m; 935029e2476SBOUGH CHEN 936029e2476SBOUGH CHEN m = readl(host->ioaddr + ESDHC_MIX_CTRL); 937029e2476SBOUGH CHEN if (ios->enhanced_strobe) 938029e2476SBOUGH CHEN m |= ESDHC_MIX_CTRL_HS400_ES_EN; 939029e2476SBOUGH CHEN else 940029e2476SBOUGH CHEN m &= ~ESDHC_MIX_CTRL_HS400_ES_EN; 941029e2476SBOUGH CHEN writel(m, host->ioaddr + ESDHC_MIX_CTRL); 942029e2476SBOUGH CHEN } 943029e2476SBOUGH CHEN 944ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 945ad93220dSDong Aisheng unsigned int uhs) 946ad93220dSDong Aisheng { 947ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 948070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 949ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 950ad93220dSDong Aisheng 951ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 952ad93220dSDong Aisheng 953ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 954ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 955ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 956ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 957ad93220dSDong Aisheng return -EINVAL; 958ad93220dSDong Aisheng 959ad93220dSDong Aisheng switch (uhs) { 960ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 9619f327845SHaibo Chen case MMC_TIMING_UHS_DDR50: 962ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 963ad93220dSDong Aisheng break; 964ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 965429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 96628b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 967ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 968ad93220dSDong Aisheng break; 969ad93220dSDong Aisheng default: 970ad93220dSDong Aisheng /* back to default state for other legacy timing */ 971ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 972ad93220dSDong Aisheng } 973ad93220dSDong Aisheng 974ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 975ad93220dSDong Aisheng } 976ad93220dSDong Aisheng 97728b07674SHaibo Chen /* 978d04f8d5bSBenoît Thébaudeau * For HS400 eMMC, there is a data_strobe line. This signal is generated 97928b07674SHaibo Chen * by the device and used for data output and CRC status response output 98028b07674SHaibo Chen * in HS400 mode. The frequency of this signal follows the frequency of 981d04f8d5bSBenoît Thébaudeau * CLK generated by host. The host receives the data which is aligned to the 98228b07674SHaibo Chen * edge of data_strobe line. Due to the time delay between CLK line and 98328b07674SHaibo Chen * data_strobe line, if the delay time is larger than one clock cycle, 984d04f8d5bSBenoît Thébaudeau * then CLK and data_strobe line will be misaligned, read error shows up. 98528b07674SHaibo Chen */ 98628b07674SHaibo Chen static void esdhc_set_strobe_dll(struct sdhci_host *host) 98728b07674SHaibo Chen { 98828b07674SHaibo Chen u32 v; 98928b07674SHaibo Chen 9907ac6da26SDong Aisheng /* disable clock before enabling strobe dll */ 9917ac6da26SDong Aisheng writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 9927ac6da26SDong Aisheng ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 9937ac6da26SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 9947ac6da26SDong Aisheng 99528b07674SHaibo Chen /* force a reset on strobe dll */ 99628b07674SHaibo Chen writel(ESDHC_STROBE_DLL_CTRL_RESET, 99728b07674SHaibo Chen host->ioaddr + ESDHC_STROBE_DLL_CTRL); 9982eaf5a53SBOUGH CHEN /* clear the reset bit on strobe dll before any setting */ 9992eaf5a53SBOUGH CHEN writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 10002eaf5a53SBOUGH CHEN 100128b07674SHaibo Chen /* 100228b07674SHaibo Chen * enable strobe dll ctrl and adjust the delay target 100328b07674SHaibo Chen * for the uSDHC loopback read clock 100428b07674SHaibo Chen */ 100528b07674SHaibo Chen v = ESDHC_STROBE_DLL_CTRL_ENABLE | 10062eaf5a53SBOUGH CHEN ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | 100728b07674SHaibo Chen (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 100828b07674SHaibo Chen writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 10092eaf5a53SBOUGH CHEN /* wait 5us to make sure strobe dll status register stable */ 10102eaf5a53SBOUGH CHEN udelay(5); 101128b07674SHaibo Chen v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); 101228b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) 101328b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 101428b07674SHaibo Chen "warning! HS400 strobe DLL status REF not lock!\n"); 101528b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 101628b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 101728b07674SHaibo Chen "warning! HS400 strobe DLL status SLV not lock!\n"); 101828b07674SHaibo Chen } 101928b07674SHaibo Chen 1020d9370424SHaibo Chen static void esdhc_reset_tuning(struct sdhci_host *host) 1021d9370424SHaibo Chen { 1022d9370424SHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1023d9370424SHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1024d9370424SHaibo Chen u32 ctrl; 1025d9370424SHaibo Chen 1026d04f8d5bSBenoît Thébaudeau /* Reset the tuning circuit */ 1027d9370424SHaibo Chen if (esdhc_is_usdhc(imx_data)) { 1028d9370424SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1029d9370424SHaibo Chen ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1030d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1031d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1032d9370424SHaibo Chen writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1033d9370424SHaibo Chen writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1034d9370424SHaibo Chen } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1035869f8a69SAdrian Hunter ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1036d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1037869f8a69SAdrian Hunter writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1038d9370424SHaibo Chen } 1039d9370424SHaibo Chen } 1040d9370424SHaibo Chen } 1041d9370424SHaibo Chen 1042850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1043ad93220dSDong Aisheng { 104428b07674SHaibo Chen u32 m; 1045ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1046070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1047602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1048ad93220dSDong Aisheng 104928b07674SHaibo Chen /* disable ddr mode and disable HS400 mode */ 105028b07674SHaibo Chen m = readl(host->ioaddr + ESDHC_MIX_CTRL); 105128b07674SHaibo Chen m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 105228b07674SHaibo Chen imx_data->is_ddr = 0; 105328b07674SHaibo Chen 1054850a29b8SRussell King switch (timing) { 1055ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 1056ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 1057ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 1058ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 1059de0a0decSBOUGH CHEN case MMC_TIMING_MMC_HS: 1060429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 106128b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1062ad93220dSDong Aisheng break; 1063ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 106469f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 106528b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN; 106628b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1067de5bdbffSDong Aisheng imx_data->is_ddr = 1; 1068602519b2SDong Aisheng if (boarddata->delay_line) { 1069602519b2SDong Aisheng u32 v; 1070602519b2SDong Aisheng v = boarddata->delay_line << 1071602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 1072602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 1073602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 1074602519b2SDong Aisheng v <<= 1; 1075602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 1076602519b2SDong Aisheng } 1077ad93220dSDong Aisheng break; 107828b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 107928b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 108028b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 108128b07674SHaibo Chen imx_data->is_ddr = 1; 10827ac6da26SDong Aisheng /* update clock after enable DDR for strobe DLL lock */ 10837ac6da26SDong Aisheng host->ops->set_clock(host, host->clock); 108428b07674SHaibo Chen esdhc_set_strobe_dll(host); 108528b07674SHaibo Chen break; 1086d9370424SHaibo Chen case MMC_TIMING_LEGACY: 1087d9370424SHaibo Chen default: 1088d9370424SHaibo Chen esdhc_reset_tuning(host); 1089d9370424SHaibo Chen break; 1090ad93220dSDong Aisheng } 1091ad93220dSDong Aisheng 1092850a29b8SRussell King esdhc_change_pinstate(host, timing); 1093ad93220dSDong Aisheng } 1094ad93220dSDong Aisheng 10950718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 10960718e59aSRussell King { 10970718e59aSRussell King sdhci_reset(host, mask); 10980718e59aSRussell King 10990718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 11000718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 11010718e59aSRussell King } 11020718e59aSRussell King 110310fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 110410fd0ad9SAisheng Dong { 110510fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1106070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 110710fd0ad9SAisheng Dong 1108d04f8d5bSBenoît Thébaudeau /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 11092fb0b02bSHaibo Chen return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 111010fd0ad9SAisheng Dong } 111110fd0ad9SAisheng Dong 1112e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1113e33eb8e2SAisheng Dong { 1114e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1115070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1116e33eb8e2SAisheng Dong 1117e33eb8e2SAisheng Dong /* use maximum timeout counter */ 1118a215186dSHaibo Chen esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1119a215186dSHaibo Chen esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1120e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 1121e33eb8e2SAisheng Dong } 1122e33eb8e2SAisheng Dong 1123bb6e3581SBOUGH CHEN static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) 1124bb6e3581SBOUGH CHEN { 1125bb6e3581SBOUGH CHEN int cmd_error = 0; 1126bb6e3581SBOUGH CHEN int data_error = 0; 1127bb6e3581SBOUGH CHEN 1128bb6e3581SBOUGH CHEN if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1129bb6e3581SBOUGH CHEN return intmask; 1130bb6e3581SBOUGH CHEN 1131bb6e3581SBOUGH CHEN cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1132bb6e3581SBOUGH CHEN 1133bb6e3581SBOUGH CHEN return 0; 1134bb6e3581SBOUGH CHEN } 1135bb6e3581SBOUGH CHEN 11366e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 1137e149860dSRichard Zhu .read_l = esdhc_readl_le, 11380c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 113977da3da0SAaron Brice .read_b = esdhc_readb_le, 1140e149860dSRichard Zhu .write_l = esdhc_writel_le, 11410c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 11420c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 11438ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 11440ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 11450c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 114610fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 1147913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 1148e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 11492317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 1150ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 11510718e59aSRussell King .reset = esdhc_reset, 1152bb6e3581SBOUGH CHEN .irq = esdhc_cqhci_irq, 11530c6d49ceSWolfram Sang }; 11540c6d49ceSWolfram Sang 11551db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 115697e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 115797e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 115897e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 115985d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 116085d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 116185d6509dSShawn Guo }; 116285d6509dSShawn Guo 1163f3f5cf3dSDong Aisheng static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1164f3f5cf3dSDong Aisheng { 1165f3f5cf3dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1166f3f5cf3dSDong Aisheng struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 11672b16cf32SDong Aisheng int tmp; 1168f3f5cf3dSDong Aisheng 1169f3f5cf3dSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 1170f3f5cf3dSDong Aisheng /* 1171f3f5cf3dSDong Aisheng * The imx6q ROM code will change the default watermark 1172f3f5cf3dSDong Aisheng * level setting to something insane. Change it back here. 1173f3f5cf3dSDong Aisheng */ 1174f3f5cf3dSDong Aisheng writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1175f3f5cf3dSDong Aisheng 1176f3f5cf3dSDong Aisheng /* 1177f3f5cf3dSDong Aisheng * ROM code will change the bit burst_length_enable setting 1178d04f8d5bSBenoît Thébaudeau * to zero if this usdhc is chosen to boot system. Change 1179f3f5cf3dSDong Aisheng * it back here, otherwise it will impact the performance a 1180f3f5cf3dSDong Aisheng * lot. This bit is used to enable/disable the burst length 1181d04f8d5bSBenoît Thébaudeau * for the external AHB2AXI bridge. It's useful especially 1182f3f5cf3dSDong Aisheng * for INCR transfer because without burst length indicator, 1183f3f5cf3dSDong Aisheng * the AHB2AXI bridge does not know the burst length in 1184f3f5cf3dSDong Aisheng * advance. And without burst length indicator, AHB INCR 1185f3f5cf3dSDong Aisheng * transfer can only be converted to singles on the AXI side. 1186f3f5cf3dSDong Aisheng */ 1187f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1188f3f5cf3dSDong Aisheng | ESDHC_BURST_LEN_EN_INCR, 1189f3f5cf3dSDong Aisheng host->ioaddr + SDHCI_HOST_CONTROL); 1190e30be063SBOUGH CHEN 1191f3f5cf3dSDong Aisheng /* 1192d04f8d5bSBenoît Thébaudeau * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1193f3f5cf3dSDong Aisheng * TO1.1, it's harmless for MX6SL 1194f3f5cf3dSDong Aisheng */ 1195e30be063SBOUGH CHEN writel(readl(host->ioaddr + 0x6c) & ~BIT(7), 1196f3f5cf3dSDong Aisheng host->ioaddr + 0x6c); 1197f3f5cf3dSDong Aisheng 1198f3f5cf3dSDong Aisheng /* disable DLL_CTRL delay line settings */ 1199f3f5cf3dSDong Aisheng writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 12002b16cf32SDong Aisheng 1201bcdb5301SBOUGH CHEN /* 1202bcdb5301SBOUGH CHEN * For the case of command with busy, if set the bit 1203bcdb5301SBOUGH CHEN * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a 1204bcdb5301SBOUGH CHEN * transfer complete interrupt when busy is deasserted. 1205bcdb5301SBOUGH CHEN * When CQHCI use DCMD to send a CMD need R1b respons, 1206bcdb5301SBOUGH CHEN * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ, 1207bcdb5301SBOUGH CHEN * otherwise DCMD will always meet timeout waiting for 1208bcdb5301SBOUGH CHEN * hardware interrupt issue. 1209bcdb5301SBOUGH CHEN */ 1210bcdb5301SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1211bcdb5301SBOUGH CHEN tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); 1212bcdb5301SBOUGH CHEN tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ; 1213bcdb5301SBOUGH CHEN writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); 1214bcdb5301SBOUGH CHEN 1215bcdb5301SBOUGH CHEN host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1216bcdb5301SBOUGH CHEN } 1217bcdb5301SBOUGH CHEN 12182b16cf32SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 12192b16cf32SDong Aisheng tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 12202b16cf32SDong Aisheng tmp |= ESDHC_STD_TUNING_EN | 12212b16cf32SDong Aisheng ESDHC_TUNING_START_TAP_DEFAULT; 12222b16cf32SDong Aisheng if (imx_data->boarddata.tuning_start_tap) { 12232b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_START_TAP_MASK; 12242b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_start_tap; 12252b16cf32SDong Aisheng } 12262b16cf32SDong Aisheng 12272b16cf32SDong Aisheng if (imx_data->boarddata.tuning_step) { 12282b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_STEP_MASK; 12292b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_step 12302b16cf32SDong Aisheng << ESDHC_TUNING_STEP_SHIFT; 12312b16cf32SDong Aisheng } 12322b16cf32SDong Aisheng writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1233a98c557eSBOUGH CHEN } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1234a98c557eSBOUGH CHEN /* 1235a98c557eSBOUGH CHEN * ESDHC_STD_TUNING_EN may be configed in bootloader 1236a98c557eSBOUGH CHEN * or ROM code, so clear this bit here to make sure 1237a98c557eSBOUGH CHEN * the manual tuning can work. 1238a98c557eSBOUGH CHEN */ 1239a98c557eSBOUGH CHEN tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1240a98c557eSBOUGH CHEN tmp &= ~ESDHC_STD_TUNING_EN; 1241a98c557eSBOUGH CHEN writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 12422b16cf32SDong Aisheng } 1243f3f5cf3dSDong Aisheng } 1244f3f5cf3dSDong Aisheng } 1245f3f5cf3dSDong Aisheng 1246bb6e3581SBOUGH CHEN static void esdhc_cqe_enable(struct mmc_host *mmc) 1247bb6e3581SBOUGH CHEN { 1248bb6e3581SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 124985236d2bSBOUGH CHEN struct cqhci_host *cq_host = mmc->cqe_private; 1250bb6e3581SBOUGH CHEN u32 reg; 1251bb6e3581SBOUGH CHEN u16 mode; 1252bb6e3581SBOUGH CHEN int count = 10; 1253bb6e3581SBOUGH CHEN 1254bb6e3581SBOUGH CHEN /* 1255bb6e3581SBOUGH CHEN * CQE gets stuck if it sees Buffer Read Enable bit set, which can be 1256bb6e3581SBOUGH CHEN * the case after tuning, so ensure the buffer is drained. 1257bb6e3581SBOUGH CHEN */ 1258bb6e3581SBOUGH CHEN reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1259bb6e3581SBOUGH CHEN while (reg & SDHCI_DATA_AVAILABLE) { 1260bb6e3581SBOUGH CHEN sdhci_readl(host, SDHCI_BUFFER); 1261bb6e3581SBOUGH CHEN reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1262bb6e3581SBOUGH CHEN if (count-- == 0) { 1263bb6e3581SBOUGH CHEN dev_warn(mmc_dev(host->mmc), 1264bb6e3581SBOUGH CHEN "CQE may get stuck because the Buffer Read Enable bit is set\n"); 1265bb6e3581SBOUGH CHEN break; 1266bb6e3581SBOUGH CHEN } 1267bb6e3581SBOUGH CHEN mdelay(1); 1268bb6e3581SBOUGH CHEN } 1269bb6e3581SBOUGH CHEN 1270bb6e3581SBOUGH CHEN /* 1271bb6e3581SBOUGH CHEN * Runtime resume will reset the entire host controller, which 1272bb6e3581SBOUGH CHEN * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL. 1273bb6e3581SBOUGH CHEN * Here set DMAEN and BCEN when enable CMDQ. 1274bb6e3581SBOUGH CHEN */ 1275bb6e3581SBOUGH CHEN mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 1276bb6e3581SBOUGH CHEN if (host->flags & SDHCI_REQ_USE_DMA) 1277bb6e3581SBOUGH CHEN mode |= SDHCI_TRNS_DMA; 1278bb6e3581SBOUGH CHEN if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 1279bb6e3581SBOUGH CHEN mode |= SDHCI_TRNS_BLK_CNT_EN; 1280bb6e3581SBOUGH CHEN sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 1281bb6e3581SBOUGH CHEN 128285236d2bSBOUGH CHEN /* 128385236d2bSBOUGH CHEN * Though Runtime resume reset the entire host controller, 128485236d2bSBOUGH CHEN * but do not impact the CQHCI side, need to clear the 128585236d2bSBOUGH CHEN * HALT bit, avoid CQHCI stuck in the first request when 128685236d2bSBOUGH CHEN * system resume back. 128785236d2bSBOUGH CHEN */ 128885236d2bSBOUGH CHEN cqhci_writel(cq_host, 0, CQHCI_CTL); 128985236d2bSBOUGH CHEN if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT) 129085236d2bSBOUGH CHEN dev_err(mmc_dev(host->mmc), 129185236d2bSBOUGH CHEN "failed to exit halt state when enable CQE\n"); 129285236d2bSBOUGH CHEN 129385236d2bSBOUGH CHEN 1294bb6e3581SBOUGH CHEN sdhci_cqe_enable(mmc); 1295bb6e3581SBOUGH CHEN } 1296bb6e3581SBOUGH CHEN 1297bb6e3581SBOUGH CHEN static void esdhc_sdhci_dumpregs(struct mmc_host *mmc) 1298bb6e3581SBOUGH CHEN { 1299bb6e3581SBOUGH CHEN sdhci_dumpregs(mmc_priv(mmc)); 1300bb6e3581SBOUGH CHEN } 1301bb6e3581SBOUGH CHEN 1302bb6e3581SBOUGH CHEN static const struct cqhci_host_ops esdhc_cqhci_ops = { 1303bb6e3581SBOUGH CHEN .enable = esdhc_cqe_enable, 1304bb6e3581SBOUGH CHEN .disable = sdhci_cqe_disable, 1305bb6e3581SBOUGH CHEN .dumpregs = esdhc_sdhci_dumpregs, 1306bb6e3581SBOUGH CHEN }; 1307bb6e3581SBOUGH CHEN 1308abfafc2dSShawn Guo #ifdef CONFIG_OF 1309c3be1efdSBill Pemberton static int 1310abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 131107bf2b54SSascha Hauer struct sdhci_host *host, 131291fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1313abfafc2dSShawn Guo { 1314abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 131591fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 13164800e87aSDong Aisheng int ret; 1317abfafc2dSShawn Guo 1318abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 1319abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 1320abfafc2dSShawn Guo 132174ff81e1SLinus Walleij /* 132274ff81e1SLinus Walleij * If we have this property, then activate WP check. 132374ff81e1SLinus Walleij * Retrieveing and requesting the actual WP GPIO will happen 132474ff81e1SLinus Walleij * in the call to mmc_of_parse(). 132574ff81e1SLinus Walleij */ 132674ff81e1SLinus Walleij if (of_property_read_bool(np, "wp-gpios")) 1327abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 1328abfafc2dSShawn Guo 1329d407e30bSHaibo Chen of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1330d87fc966SDong Aisheng of_property_read_u32(np, "fsl,tuning-start-tap", 1331d87fc966SDong Aisheng &boarddata->tuning_start_tap); 1332d407e30bSHaibo Chen 1333ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 133486f495c5SStefan Agner host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1335ad93220dSDong Aisheng 1336602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1337602519b2SDong Aisheng boarddata->delay_line = 0; 1338602519b2SDong Aisheng 133907bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 134007bf2b54SSascha Hauer 134186f495c5SStefan Agner if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pins_default)) { 134291fa4252SDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 134391fa4252SDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 134491fa4252SDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 134591fa4252SDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 134691fa4252SDong Aisheng } 134791fa4252SDong Aisheng 134815064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 13494800e87aSDong Aisheng ret = mmc_of_parse(host->mmc); 13504800e87aSDong Aisheng if (ret) 13514800e87aSDong Aisheng return ret; 13524800e87aSDong Aisheng 1353287980e4SArnd Bergmann if (mmc_gpio_get_cd(host->mmc) >= 0) 13544800e87aSDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 13554800e87aSDong Aisheng 13564800e87aSDong Aisheng return 0; 1357abfafc2dSShawn Guo } 1358abfafc2dSShawn Guo #else 1359abfafc2dSShawn Guo static inline int 1360abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 136107bf2b54SSascha Hauer struct sdhci_host *host, 136291fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1363abfafc2dSShawn Guo { 1364abfafc2dSShawn Guo return -ENODEV; 1365abfafc2dSShawn Guo } 1366abfafc2dSShawn Guo #endif 1367abfafc2dSShawn Guo 136891fa4252SDong Aisheng static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 136991fa4252SDong Aisheng struct sdhci_host *host, 137091fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 137191fa4252SDong Aisheng { 137291fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 137391fa4252SDong Aisheng int err; 137491fa4252SDong Aisheng 137591fa4252SDong Aisheng if (!host->mmc->parent->platform_data) { 137691fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), "no board data!\n"); 137791fa4252SDong Aisheng return -EINVAL; 137891fa4252SDong Aisheng } 137991fa4252SDong Aisheng 138091fa4252SDong Aisheng imx_data->boarddata = *((struct esdhc_platform_data *) 138191fa4252SDong Aisheng host->mmc->parent->platform_data); 138291fa4252SDong Aisheng /* write_protect */ 138391fa4252SDong Aisheng if (boarddata->wp_type == ESDHC_WP_GPIO) { 1384a2b760a6SLinus Walleij err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0, NULL); 138591fa4252SDong Aisheng if (err) { 138691fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 138791fa4252SDong Aisheng "failed to request write-protect gpio!\n"); 138891fa4252SDong Aisheng return err; 138991fa4252SDong Aisheng } 139091fa4252SDong Aisheng host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 139191fa4252SDong Aisheng } 139291fa4252SDong Aisheng 139391fa4252SDong Aisheng /* card_detect */ 139491fa4252SDong Aisheng switch (boarddata->cd_type) { 139591fa4252SDong Aisheng case ESDHC_CD_GPIO: 139674ff81e1SLinus Walleij err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0, NULL); 139791fa4252SDong Aisheng if (err) { 139891fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 139991fa4252SDong Aisheng "failed to request card-detect gpio!\n"); 140091fa4252SDong Aisheng return err; 140191fa4252SDong Aisheng } 140291fa4252SDong Aisheng /* fall through */ 140391fa4252SDong Aisheng 140491fa4252SDong Aisheng case ESDHC_CD_CONTROLLER: 140591fa4252SDong Aisheng /* we have a working card_detect back */ 140691fa4252SDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 140791fa4252SDong Aisheng break; 140891fa4252SDong Aisheng 140991fa4252SDong Aisheng case ESDHC_CD_PERMANENT: 141091fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 141191fa4252SDong Aisheng break; 141291fa4252SDong Aisheng 141391fa4252SDong Aisheng case ESDHC_CD_NONE: 141491fa4252SDong Aisheng break; 141591fa4252SDong Aisheng } 141691fa4252SDong Aisheng 141791fa4252SDong Aisheng switch (boarddata->max_bus_width) { 141891fa4252SDong Aisheng case 8: 141991fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 142091fa4252SDong Aisheng break; 142191fa4252SDong Aisheng case 4: 142291fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_4_BIT_DATA; 142391fa4252SDong Aisheng break; 142491fa4252SDong Aisheng case 1: 142591fa4252SDong Aisheng default: 142691fa4252SDong Aisheng host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 142791fa4252SDong Aisheng break; 142891fa4252SDong Aisheng } 142991fa4252SDong Aisheng 143091fa4252SDong Aisheng return 0; 143191fa4252SDong Aisheng } 143291fa4252SDong Aisheng 1433c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 143495f25efeSWolfram Sang { 1435abfafc2dSShawn Guo const struct of_device_id *of_id = 1436abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 143785d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 143885d6509dSShawn Guo struct sdhci_host *host; 1439bb6e3581SBOUGH CHEN struct cqhci_host *cq_host; 14400c6d49ceSWolfram Sang int err; 1441e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 144295f25efeSWolfram Sang 1443070e6d3fSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1444070e6d3fSJisheng Zhang sizeof(*imx_data)); 144585d6509dSShawn Guo if (IS_ERR(host)) 144685d6509dSShawn Guo return PTR_ERR(host); 144785d6509dSShawn Guo 144885d6509dSShawn Guo pltfm_host = sdhci_priv(host); 144985d6509dSShawn Guo 1450070e6d3fSJisheng Zhang imx_data = sdhci_pltfm_priv(pltfm_host); 145157ed3314SShawn Guo 1452f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 14533770ee8fSShawn Guo pdev->id_entry->driver_data; 145485d6509dSShawn Guo 14551c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 14561c4989b0SBOUGH CHEN pm_qos_add_request(&imx_data->pm_qos_req, 14571c4989b0SBOUGH CHEN PM_QOS_CPU_DMA_LATENCY, 0); 14581c4989b0SBOUGH CHEN 145952dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 146052dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 146152dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 1462e3af31c6SShawn Guo goto free_sdhci; 146395f25efeSWolfram Sang } 146452dac615SSascha Hauer 146552dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 146652dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 146752dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 1468e3af31c6SShawn Guo goto free_sdhci; 146952dac615SSascha Hauer } 147052dac615SSascha Hauer 147152dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 147252dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 147352dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 1474e3af31c6SShawn Guo goto free_sdhci; 147552dac615SSascha Hauer } 147652dac615SSascha Hauer 147752dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 1478a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 147917b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 148017b1eb7fSFabio Estevam if (err) 148117b1eb7fSFabio Estevam goto free_sdhci; 148217b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 148317b1eb7fSFabio Estevam if (err) 148417b1eb7fSFabio Estevam goto disable_per_clk; 148517b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ahb); 148617b1eb7fSFabio Estevam if (err) 148717b1eb7fSFabio Estevam goto disable_ipg_clk; 148895f25efeSWolfram Sang 1489ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1490e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1491e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 149217b1eb7fSFabio Estevam goto disable_ahb_clk; 1493e62d8b8fSDong Aisheng } 1494e62d8b8fSDong Aisheng 1495ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 1496ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 1497cd529af7SDirk Behme if (IS_ERR(imx_data->pins_default)) 1498cd529af7SDirk Behme dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 1499ad93220dSDong Aisheng 150069ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 150169ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 150209c8192bSStefan Agner host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 15034245afffSDong Aisheng if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 15044245afffSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1505a75dcbf4SDong Aisheng 1506a75dcbf4SDong Aisheng /* clear tuning bits in case ROM has set it already */ 1507a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1508869f8a69SAdrian Hunter writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1509a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1510de3e1dd0SBOUGH CHEN 1511de3e1dd0SBOUGH CHEN /* 1512de3e1dd0SBOUGH CHEN * Link usdhc specific mmc_host_ops execute_tuning function, 1513de3e1dd0SBOUGH CHEN * to replace the standard one in sdhci_ops. 1514de3e1dd0SBOUGH CHEN */ 1515de3e1dd0SBOUGH CHEN host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; 151669ed60e0SDong Aisheng } 1517f750ba9bSShawn Guo 15186e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 15196e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 15206e9fd28eSDong Aisheng esdhc_executing_tuning; 15218b2bb0adSDong Aisheng 152218094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 152318094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 152418094430SDong Aisheng 152528b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 152628b07674SHaibo Chen host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 152728b07674SHaibo Chen 1528029e2476SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { 1529029e2476SBOUGH CHEN host->mmc->caps2 |= MMC_CAP2_HS400_ES; 1530029e2476SBOUGH CHEN host->mmc_host_ops.hs400_enhanced_strobe = 1531029e2476SBOUGH CHEN esdhc_hs400_enhanced_strobe; 1532029e2476SBOUGH CHEN } 1533029e2476SBOUGH CHEN 1534bb6e3581SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1535bcdb5301SBOUGH CHEN host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1536bb6e3581SBOUGH CHEN cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 15379a633f3bSWei Yongjun if (!cq_host) { 15389a633f3bSWei Yongjun err = -ENOMEM; 1539bb6e3581SBOUGH CHEN goto disable_ahb_clk; 1540bb6e3581SBOUGH CHEN } 1541bb6e3581SBOUGH CHEN 1542bb6e3581SBOUGH CHEN cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; 1543bb6e3581SBOUGH CHEN cq_host->ops = &esdhc_cqhci_ops; 1544bb6e3581SBOUGH CHEN 1545bb6e3581SBOUGH CHEN err = cqhci_init(cq_host, host->mmc, false); 1546bb6e3581SBOUGH CHEN if (err) 1547bb6e3581SBOUGH CHEN goto disable_ahb_clk; 1548bb6e3581SBOUGH CHEN } 1549bb6e3581SBOUGH CHEN 155091fa4252SDong Aisheng if (of_id) 155191fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 155291fa4252SDong Aisheng else 155391fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 155491fa4252SDong Aisheng if (err) 155517b1eb7fSFabio Estevam goto disable_ahb_clk; 1556ad93220dSDong Aisheng 1557d00ab101SBOUGH CHEN host->tuning_delay = 1; 1558d00ab101SBOUGH CHEN 1559f3f5cf3dSDong Aisheng sdhci_esdhc_imx_hwinit(host); 1560f3f5cf3dSDong Aisheng 156185d6509dSShawn Guo err = sdhci_add_host(host); 156285d6509dSShawn Guo if (err) 156317b1eb7fSFabio Estevam goto disable_ahb_clk; 156485d6509dSShawn Guo 156589d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 156689d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 156789d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 156889d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 156977903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 157089d7e5c1SDong Aisheng 15717e29c306SWolfram Sang return 0; 15727e29c306SWolfram Sang 157317b1eb7fSFabio Estevam disable_ahb_clk: 157452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 157517b1eb7fSFabio Estevam disable_ipg_clk: 157617b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 157717b1eb7fSFabio Estevam disable_per_clk: 157817b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1579e3af31c6SShawn Guo free_sdhci: 15801c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 15811c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 158285d6509dSShawn Guo sdhci_pltfm_free(pdev); 158385d6509dSShawn Guo return err; 158495f25efeSWolfram Sang } 158595f25efeSWolfram Sang 15866e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 158795f25efeSWolfram Sang { 158885d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 158995f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1590070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 159185d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 159285d6509dSShawn Guo 15930b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 15940b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 15950b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 15960b414368SUlf Hansson 159785d6509dSShawn Guo sdhci_remove_host(host, dead); 15980c6d49ceSWolfram Sang 159952dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 160052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 160152dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 160252dac615SSascha Hauer 16031c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 16041c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 16051c4989b0SBOUGH CHEN 160685d6509dSShawn Guo sdhci_pltfm_free(pdev); 160785d6509dSShawn Guo 160885d6509dSShawn Guo return 0; 160995f25efeSWolfram Sang } 161095f25efeSWolfram Sang 16112788ed42SUlf Hansson #ifdef CONFIG_PM_SLEEP 161204143fbaSDong Aisheng static int sdhci_esdhc_suspend(struct device *dev) 161304143fbaSDong Aisheng { 16143e3274abSUlf Hansson struct sdhci_host *host = dev_get_drvdata(dev); 1615bb6e3581SBOUGH CHEN int ret; 1616bb6e3581SBOUGH CHEN 1617bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) { 1618bb6e3581SBOUGH CHEN ret = cqhci_suspend(host->mmc); 1619bb6e3581SBOUGH CHEN if (ret) 1620bb6e3581SBOUGH CHEN return ret; 1621bb6e3581SBOUGH CHEN } 16223e3274abSUlf Hansson 1623d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1624d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1625d38dcad4SAdrian Hunter 16263e3274abSUlf Hansson return sdhci_suspend_host(host); 162704143fbaSDong Aisheng } 162804143fbaSDong Aisheng 162904143fbaSDong Aisheng static int sdhci_esdhc_resume(struct device *dev) 163004143fbaSDong Aisheng { 1631cc17e129SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 1632bb6e3581SBOUGH CHEN int ret; 1633cc17e129SDong Aisheng 163419dbfdd3SDong Aisheng /* re-initialize hw state in case it's lost in low power mode */ 163519dbfdd3SDong Aisheng sdhci_esdhc_imx_hwinit(host); 1636cc17e129SDong Aisheng 1637bb6e3581SBOUGH CHEN ret = sdhci_resume_host(host); 1638bb6e3581SBOUGH CHEN if (ret) 1639bb6e3581SBOUGH CHEN return ret; 1640bb6e3581SBOUGH CHEN 1641bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) 1642bb6e3581SBOUGH CHEN ret = cqhci_resume(host->mmc); 1643bb6e3581SBOUGH CHEN 1644bb6e3581SBOUGH CHEN return ret; 164504143fbaSDong Aisheng } 16462788ed42SUlf Hansson #endif 164704143fbaSDong Aisheng 16482788ed42SUlf Hansson #ifdef CONFIG_PM 164989d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 165089d7e5c1SDong Aisheng { 165189d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 165289d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1653070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 165489d7e5c1SDong Aisheng int ret; 165589d7e5c1SDong Aisheng 1656bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) { 1657bb6e3581SBOUGH CHEN ret = cqhci_suspend(host->mmc); 1658bb6e3581SBOUGH CHEN if (ret) 1659bb6e3581SBOUGH CHEN return ret; 1660bb6e3581SBOUGH CHEN } 1661bb6e3581SBOUGH CHEN 166289d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 1663371d39faSMichael Trimarchi if (ret) 1664371d39faSMichael Trimarchi return ret; 166589d7e5c1SDong Aisheng 1666d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1667d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1668d38dcad4SAdrian Hunter 1669be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 16703602785bSMichael Trimarchi imx_data->actual_clock = host->mmc->actual_clock; 16713602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, 0); 167289d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 167389d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 1674be138554SRussell King } 167589d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 167689d7e5c1SDong Aisheng 16771c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 16781c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 16791c4989b0SBOUGH CHEN 168089d7e5c1SDong Aisheng return ret; 168189d7e5c1SDong Aisheng } 168289d7e5c1SDong Aisheng 168389d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 168489d7e5c1SDong Aisheng { 168589d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 168689d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1687070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 168817b1eb7fSFabio Estevam int err; 168989d7e5c1SDong Aisheng 16901c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 16911c4989b0SBOUGH CHEN pm_qos_add_request(&imx_data->pm_qos_req, 16921c4989b0SBOUGH CHEN PM_QOS_CPU_DMA_LATENCY, 0); 16931c4989b0SBOUGH CHEN 1694a0ad3087SMichael Trimarchi err = clk_prepare_enable(imx_data->clk_ahb); 1695a0ad3087SMichael Trimarchi if (err) 16961c4989b0SBOUGH CHEN goto remove_pm_qos_request; 1697a0ad3087SMichael Trimarchi 1698be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 169917b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 170017b1eb7fSFabio Estevam if (err) 1701a0ad3087SMichael Trimarchi goto disable_ahb_clk; 170217b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 170317b1eb7fSFabio Estevam if (err) 170417b1eb7fSFabio Estevam goto disable_per_clk; 17053602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1706be138554SRussell King } 1707a0ad3087SMichael Trimarchi 170817b1eb7fSFabio Estevam err = sdhci_runtime_resume_host(host); 170917b1eb7fSFabio Estevam if (err) 1710a0ad3087SMichael Trimarchi goto disable_ipg_clk; 171189d7e5c1SDong Aisheng 1712bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) 1713bb6e3581SBOUGH CHEN err = cqhci_resume(host->mmc); 1714bb6e3581SBOUGH CHEN 1715bb6e3581SBOUGH CHEN return err; 171617b1eb7fSFabio Estevam 171717b1eb7fSFabio Estevam disable_ipg_clk: 171817b1eb7fSFabio Estevam if (!sdhci_sdio_irq_enabled(host)) 171917b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 172017b1eb7fSFabio Estevam disable_per_clk: 172117b1eb7fSFabio Estevam if (!sdhci_sdio_irq_enabled(host)) 172217b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1723a0ad3087SMichael Trimarchi disable_ahb_clk: 1724a0ad3087SMichael Trimarchi clk_disable_unprepare(imx_data->clk_ahb); 17251c4989b0SBOUGH CHEN remove_pm_qos_request: 17261c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 17271c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 172817b1eb7fSFabio Estevam return err; 172989d7e5c1SDong Aisheng } 173089d7e5c1SDong Aisheng #endif 173189d7e5c1SDong Aisheng 173289d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 173304143fbaSDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 173489d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 173589d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 173689d7e5c1SDong Aisheng }; 173789d7e5c1SDong Aisheng 173885d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 173985d6509dSShawn Guo .driver = { 174085d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1741abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 174289d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 174385d6509dSShawn Guo }, 174457ed3314SShawn Guo .id_table = imx_esdhc_devtype, 174585d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 17460433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 174795f25efeSWolfram Sang }; 174885d6509dSShawn Guo 1749d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 175085d6509dSShawn Guo 175185d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1752035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 175385d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1754