195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 7035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3089d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 3195f25efeSWolfram Sang #include "sdhci-pltfm.h" 3295f25efeSWolfram Sang #include "sdhci-esdhc.h" 3395f25efeSWolfram Sang 3460bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 35fd44954eSHaibo Chen #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 3658ac8177SRichard Zhu /* VENDOR SPEC register */ 3760bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3860bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 390322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 40fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 4160bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 42cc17e129SDong Aisheng #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 4360bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 44de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 452a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 460322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 470322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 480b330e38SDong Aisheng #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 490322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 5028b07674SHaibo Chen #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 512a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 522a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 53d131a71cSDong Aisheng /* Tuning bits */ 54d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 5558ac8177SRichard Zhu 56602519b2SDong Aisheng /* dll control register */ 57602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 58602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 59602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 60602519b2SDong Aisheng 610322191eSDong Aisheng /* tune control register */ 620322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 630322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 640322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 650322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 660322191eSDong Aisheng 6728b07674SHaibo Chen /* strobe dll register */ 6828b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL 0x70 6928b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 7028b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 7128b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 7228b07674SHaibo Chen 7328b07674SHaibo Chen #define ESDHC_STROBE_DLL_STATUS 0x74 7428b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 7528b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 7628b07674SHaibo Chen 776e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 786e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 796e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 80d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 81d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_MASK 0xff 82260ecb3cSHaibo Chen #define ESDHC_TUNING_STEP_MASK 0x00070000 83d407e30bSHaibo Chen #define ESDHC_TUNING_STEP_SHIFT 16 846e9fd28eSDong Aisheng 85ad93220dSDong Aisheng /* pinctrl state */ 86ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 87ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 88ad93220dSDong Aisheng 8958ac8177SRichard Zhu /* 90af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 91af51079eSSascha Hauer */ 92af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 93af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 94af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 95af51079eSSascha Hauer 96af51079eSSascha Hauer /* 9797e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 9897e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 9997e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 10097e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 10197e4ba6aSRichard Zhu */ 10260bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 10397e4ba6aSRichard Zhu 10497e4ba6aSRichard Zhu /* 10558ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 10658ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 10758ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 10858ac8177SRichard Zhu * be generated. 10958ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 11058ac8177SRichard Zhu * operations automatically as required at the end of the 11158ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 11258ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 11358ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 11458ac8177SRichard Zhu */ 11531fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 11631fbb301SShawn Guo /* 11731fbb301SShawn Guo * The flag enables the workaround for ESDHC errata ENGcm07207 which 11831fbb301SShawn Guo * affects i.MX25 and i.MX35. 11931fbb301SShawn Guo */ 12031fbb301SShawn Guo #define ESDHC_FLAG_ENGCM07207 BIT(2) 1219d61c009SShawn Guo /* 1229d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1239d61c009SShawn Guo * integrated on the i.MX6 series. 1249d61c009SShawn Guo */ 1259d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1266e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1276e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1286e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1296e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1306e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1316e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 13218094430SDong Aisheng /* 13318094430SDong Aisheng * The IP has errata ERR004536 13418094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 13518094430SDong Aisheng * when reading data from the card 13618094430SDong Aisheng */ 13718094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 1384245afffSDong Aisheng /* The IP supports HS200 mode */ 1394245afffSDong Aisheng #define ESDHC_FLAG_HS200 BIT(8) 14028b07674SHaibo Chen /* The IP supports HS400 mode */ 14128b07674SHaibo Chen #define ESDHC_FLAG_HS400 BIT(9) 14228b07674SHaibo Chen 14328b07674SHaibo Chen /* A higher clock ferquency than this rate requires strobell dll control */ 14428b07674SHaibo Chen #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 145e149860dSRichard Zhu 146f47c4bbfSShawn Guo struct esdhc_soc_data { 147f47c4bbfSShawn Guo u32 flags; 148f47c4bbfSShawn Guo }; 149f47c4bbfSShawn Guo 150f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx25_data = { 151f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 152f47c4bbfSShawn Guo }; 153f47c4bbfSShawn Guo 154f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx35_data = { 155f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 156f47c4bbfSShawn Guo }; 157f47c4bbfSShawn Guo 158f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx51_data = { 159f47c4bbfSShawn Guo .flags = 0, 160f47c4bbfSShawn Guo }; 161f47c4bbfSShawn Guo 162f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx53_data = { 163f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 164f47c4bbfSShawn Guo }; 165f47c4bbfSShawn Guo 166f47c4bbfSShawn Guo static struct esdhc_soc_data usdhc_imx6q_data = { 1676e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1686e9fd28eSDong Aisheng }; 1696e9fd28eSDong Aisheng 1706e9fd28eSDong Aisheng static struct esdhc_soc_data usdhc_imx6sl_data = { 1716e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1724245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 1734245afffSDong Aisheng | ESDHC_FLAG_HS200, 17457ed3314SShawn Guo }; 17557ed3314SShawn Guo 176913d4951SDong Aisheng static struct esdhc_soc_data usdhc_imx6sx_data = { 177913d4951SDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1784245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 179913d4951SDong Aisheng }; 180913d4951SDong Aisheng 18128b07674SHaibo Chen static struct esdhc_soc_data usdhc_imx7d_data = { 18228b07674SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 18328b07674SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 18428b07674SHaibo Chen | ESDHC_FLAG_HS400, 18528b07674SHaibo Chen }; 18628b07674SHaibo Chen 187e149860dSRichard Zhu struct pltfm_imx_data { 188e149860dSRichard Zhu u32 scratchpad; 189e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 190ad93220dSDong Aisheng struct pinctrl_state *pins_default; 191ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 192ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 193f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 194842afc02SShawn Guo struct esdhc_platform_data boarddata; 19552dac615SSascha Hauer struct clk *clk_ipg; 19652dac615SSascha Hauer struct clk *clk_ahb; 19752dac615SSascha Hauer struct clk *clk_per; 198361b8482SLucas Stach enum { 199361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending*/ 200361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 201361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 202361b8482SLucas Stach } multiblock_status; 203de5bdbffSDong Aisheng u32 is_ddr; 204e149860dSRichard Zhu }; 205e149860dSRichard Zhu 206f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 20757ed3314SShawn Guo { 20857ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 209f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 21057ed3314SShawn Guo }, { 21157ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 212f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 21357ed3314SShawn Guo }, { 21457ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 215f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 21657ed3314SShawn Guo }, { 21757ed3314SShawn Guo /* sentinel */ 21857ed3314SShawn Guo } 21957ed3314SShawn Guo }; 22057ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 22157ed3314SShawn Guo 222abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 223f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 224f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 225f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 226f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 227913d4951SDong Aisheng { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 2286e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 229f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 23028b07674SHaibo Chen { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 231abfafc2dSShawn Guo { /* sentinel */ } 232abfafc2dSShawn Guo }; 233abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 234abfafc2dSShawn Guo 23557ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 23657ed3314SShawn Guo { 237f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 23857ed3314SShawn Guo } 23957ed3314SShawn Guo 24057ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 24157ed3314SShawn Guo { 242f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 24357ed3314SShawn Guo } 24457ed3314SShawn Guo 24595a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 24695a2482aSShawn Guo { 247f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 24895a2482aSShawn Guo } 24995a2482aSShawn Guo 2509d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2519d61c009SShawn Guo { 252f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2539d61c009SShawn Guo } 2549d61c009SShawn Guo 25595f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 25695f25efeSWolfram Sang { 25795f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 25895f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 25995f25efeSWolfram Sang 26095f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 26195f25efeSWolfram Sang } 26295f25efeSWolfram Sang 2637e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 2647e29c306SWolfram Sang { 265361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 266070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 267913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 268913413c3SShawn Guo 2690322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 2700322191eSDong Aisheng u32 fsl_prss = val; 2710322191eSDong Aisheng /* save the least 20 bits */ 2720322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 2730322191eSDong Aisheng /* move dat[0-3] bits */ 2740322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 2750322191eSDong Aisheng /* move cmd line bit */ 2760322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 2770322191eSDong Aisheng } 2780322191eSDong Aisheng 27997e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 2806b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 2816b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2826b4fb671SDong Aisheng val &= 0xffff0000; 2836b4fb671SDong Aisheng 28497e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 28597e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 28697e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 28797e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 28897e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 28997e4ba6aSRichard Zhu */ 29097e4ba6aSRichard Zhu 29197e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 29297e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 29397e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 29497e4ba6aSRichard Zhu } 29597e4ba6aSRichard Zhu } 29697e4ba6aSRichard Zhu 2976e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 2986e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 2996e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3006e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 3016e9fd28eSDong Aisheng else 3026e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 3030322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 304888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 305da0295ffSDong Aisheng | SDHCI_USE_SDR50_TUNING 306da0295ffSDong Aisheng | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); 30728b07674SHaibo Chen 30828b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 30928b07674SHaibo Chen val |= SDHCI_SUPPORT_HS400; 3106e9fd28eSDong Aisheng } 3116e9fd28eSDong Aisheng } 3120322191eSDong Aisheng 3139d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 3140322191eSDong Aisheng val = 0; 3150322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 3160322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 3170322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 3180322191eSDong Aisheng } 3190322191eSDong Aisheng 32097e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 32160bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 32260bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 32397e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 32497e4ba6aSRichard Zhu } 325361b8482SLucas Stach 326361b8482SLucas Stach /* 327361b8482SLucas Stach * mask off the interrupt we get in response to the manually 328361b8482SLucas Stach * sent CMD12 329361b8482SLucas Stach */ 330361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 331361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 332361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 333361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 334361b8482SLucas Stach SDHCI_INT_STATUS); 335361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 336361b8482SLucas Stach } 33797e4ba6aSRichard Zhu } 33897e4ba6aSRichard Zhu 3397e29c306SWolfram Sang return val; 3407e29c306SWolfram Sang } 3417e29c306SWolfram Sang 3427e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 3437e29c306SWolfram Sang { 344e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 345070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 3460d58864bSTony Lin u32 data; 347e149860dSRichard Zhu 3480d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 349b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 3500d58864bSTony Lin /* 3510d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 3520d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 3530d58864bSTony Lin * so we need to apply the following workaround: clear 3540d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 3550d58864bSTony Lin * interrupt. In case a card interrupt was lost, 3560d58864bSTony Lin * re-sample it by the following steps. 3570d58864bSTony Lin */ 3580d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 35960bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 3600d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 36160bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 3620d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 3630d58864bSTony Lin } 364915be485SDong Aisheng 365915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 366915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 367915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 368915be485SDong Aisheng } 3690d58864bSTony Lin } 3700d58864bSTony Lin 371f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 37258ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 37358ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 37458ac8177SRichard Zhu u32 v; 37560bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 37660bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 37760bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 378361b8482SLucas Stach 379361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 380361b8482SLucas Stach { 381361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 382361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 383361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 384361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 385361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 386361b8482SLucas Stach } 38758ac8177SRichard Zhu } 38858ac8177SRichard Zhu 3897e29c306SWolfram Sang writel(val, host->ioaddr + reg); 3907e29c306SWolfram Sang } 3917e29c306SWolfram Sang 39295f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 39395f25efeSWolfram Sang { 394ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 395070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 3960322191eSDong Aisheng u16 ret = 0; 3970322191eSDong Aisheng u32 val; 398ef4d0888SShawn Guo 39995a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 400ef4d0888SShawn Guo reg ^= 2; 4019d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 40295a2482aSShawn Guo /* 403ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 404ef4d0888SShawn Guo * Correct it here. 40595a2482aSShawn Guo */ 406ef4d0888SShawn Guo return SDHCI_SPEC_300; 407ef4d0888SShawn Guo } 40895a2482aSShawn Guo } 40995f25efeSWolfram Sang 4100322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 4110322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4120322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 4130322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 4140322191eSDong Aisheng 4159d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 4166e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 4170322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4186e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 4196e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 4206e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4216e9fd28eSDong Aisheng } 4226e9fd28eSDong Aisheng 4230322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 4240322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 4250322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 4260322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 4270322191eSDong Aisheng 4280322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 4290322191eSDong Aisheng 4300322191eSDong Aisheng return ret; 4310322191eSDong Aisheng } 4320322191eSDong Aisheng 4337dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 4347dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 4357dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4367dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 4377dd109efSDong Aisheng /* Swap AC23 bit */ 4387dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 4397dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 4407dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 4417dd109efSDong Aisheng } 4427dd109efSDong Aisheng } else { 4437dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 4447dd109efSDong Aisheng } 4457dd109efSDong Aisheng 4467dd109efSDong Aisheng return ret; 4477dd109efSDong Aisheng } 4487dd109efSDong Aisheng 44995f25efeSWolfram Sang return readw(host->ioaddr + reg); 45095f25efeSWolfram Sang } 45195f25efeSWolfram Sang 45295f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 45395f25efeSWolfram Sang { 45495f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 455070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 4560322191eSDong Aisheng u32 new_val = 0; 45795f25efeSWolfram Sang 45895f25efeSWolfram Sang switch (reg) { 4590322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 4600322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4610322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 4620322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4630322191eSDong Aisheng else 4640322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4650322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4660322191eSDong Aisheng return; 4670322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 4680322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4690322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 4700322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 4710322191eSDong Aisheng else 4720322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 4730322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4746e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 4750322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 476da0295ffSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4770322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 478da0295ffSDong Aisheng new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 479da0295ffSDong Aisheng } else { 4800322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 481da0295ffSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 482da0295ffSDong Aisheng } 4830322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 4846e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 4856e9fd28eSDong Aisheng u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4866e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4878b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4888b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4896e9fd28eSDong Aisheng } else { 4908b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4916e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 4920b330e38SDong Aisheng m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 4936e9fd28eSDong Aisheng } 4946e9fd28eSDong Aisheng 4958b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 4968b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 4978b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 4980b330e38SDong Aisheng m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 4998b2bb0adSDong Aisheng } else { 5008b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 5018b2bb0adSDong Aisheng } 5026e9fd28eSDong Aisheng 5036e9fd28eSDong Aisheng writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 5046e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5056e9fd28eSDong Aisheng } 5060322191eSDong Aisheng return; 50795f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 508f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 50958ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 51058ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 51158ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 51258ac8177SRichard Zhu u32 v; 51360bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 51460bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 51560bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 51658ac8177SRichard Zhu } 51769f54698SShawn Guo 5189d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 51969f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5202a15f981SShawn Guo /* Swap AC23 bit */ 5212a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 5222a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 5232a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 5242a15f981SShawn Guo } 5252a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 52669f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 52769f54698SShawn Guo } else { 52869f54698SShawn Guo /* 52969f54698SShawn Guo * Postpone this write, we must do it together with a 53069f54698SShawn Guo * command write that is down below. 53169f54698SShawn Guo */ 532e149860dSRichard Zhu imx_data->scratchpad = val; 53369f54698SShawn Guo } 53495f25efeSWolfram Sang return; 53595f25efeSWolfram Sang case SDHCI_COMMAND: 536361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 53758ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 53895a2482aSShawn Guo 539361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 540f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 541361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 542361b8482SLucas Stach 5439d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 54495a2482aSShawn Guo writel(val << 16, 54595a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 54669f54698SShawn Guo else 547e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 54895f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 54995f25efeSWolfram Sang return; 55095f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 55195f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 55295f25efeSWolfram Sang break; 55395f25efeSWolfram Sang } 55495f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 55595f25efeSWolfram Sang } 55695f25efeSWolfram Sang 55795f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 55895f25efeSWolfram Sang { 5599a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 560070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 56195f25efeSWolfram Sang u32 new_val; 562af51079eSSascha Hauer u32 mask; 56395f25efeSWolfram Sang 56495f25efeSWolfram Sang switch (reg) { 56595f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 56695f25efeSWolfram Sang /* 56795f25efeSWolfram Sang * FSL put some DMA bits here 56895f25efeSWolfram Sang * If your board has a regulator, code should be here 56995f25efeSWolfram Sang */ 57095f25efeSWolfram Sang return; 57195f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 5726b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 573af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 5747122bbb0SMasanari Iida /* ensure the endianness */ 57595f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 5769a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 5779a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 57895f25efeSWolfram Sang /* DMA mode bits are shifted */ 57995f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 5809a0985b7SWilson Callan } 58195f25efeSWolfram Sang 582af51079eSSascha Hauer /* 583af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 584af51079eSSascha Hauer * esdhc_pltfm_bus_width. 585f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 586f6825748SMartin Fuzzey * SDIO interrupt errata workaround. 587af51079eSSascha Hauer */ 588f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 589af51079eSSascha Hauer 590af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 59195f25efeSWolfram Sang return; 59295f25efeSWolfram Sang } 59395f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 594913413c3SShawn Guo 595913413c3SShawn Guo /* 596913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 597913413c3SShawn Guo * that software reset should not affect card detection circuit. 598913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 599913413c3SShawn Guo * software reset. This will stop those clocks that card detection 600913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 601913413c3SShawn Guo * to keep card detection circuit functional. 602913413c3SShawn Guo */ 60358c8c4fbSShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 604913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 60558c8c4fbSShawn Guo /* 60658c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 60758c8c4fbSShawn Guo * Do it manually here. 60858c8c4fbSShawn Guo */ 609de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 610d131a71cSDong Aisheng /* the tuning bits should be kept during reset */ 611d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 612d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 613d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 614de5bdbffSDong Aisheng imx_data->is_ddr = 0; 615de5bdbffSDong Aisheng } 61658c8c4fbSShawn Guo } 61795f25efeSWolfram Sang } 61895f25efeSWolfram Sang 6190ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 6200ddf03c9SLucas Stach { 6210ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 6220ddf03c9SLucas Stach 623a974862fSDong Aisheng return pltfm_host->clock; 6240ddf03c9SLucas Stach } 6250ddf03c9SLucas Stach 62695f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 62795f25efeSWolfram Sang { 62895f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 62995f25efeSWolfram Sang 630a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 63195f25efeSWolfram Sang } 63295f25efeSWolfram Sang 6338ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 6348ba9580aSLucas Stach unsigned int clock) 6358ba9580aSLucas Stach { 6368ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 637070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 638a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 639d31fc00aSDong Aisheng int pre_div = 2; 640d31fc00aSDong Aisheng int div = 1; 641fed2f6e2SDong Aisheng u32 temp, val; 6428ba9580aSLucas Stach 643fed2f6e2SDong Aisheng if (clock == 0) { 6441650d0c7SRussell King host->mmc->actual_clock = 0; 6451650d0c7SRussell King 6469d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 647fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 648fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 649fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 650fed2f6e2SDong Aisheng } 651373073efSRussell King return; 652fed2f6e2SDong Aisheng } 653d31fc00aSDong Aisheng 654de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) 6555f7886c5SDong Aisheng pre_div = 1; 6565f7886c5SDong Aisheng 657d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 658d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 659d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 660d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 661d31fc00aSDong Aisheng 662d31fc00aSDong Aisheng while (host_clock / pre_div / 16 > clock && pre_div < 256) 663d31fc00aSDong Aisheng pre_div *= 2; 664d31fc00aSDong Aisheng 665d31fc00aSDong Aisheng while (host_clock / pre_div / div > clock && div < 16) 666d31fc00aSDong Aisheng div++; 667d31fc00aSDong Aisheng 668e76b8559SDong Aisheng host->mmc->actual_clock = host_clock / pre_div / div; 669d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 670e76b8559SDong Aisheng clock, host->mmc->actual_clock); 671d31fc00aSDong Aisheng 672de5bdbffSDong Aisheng if (imx_data->is_ddr) 673de5bdbffSDong Aisheng pre_div >>= 2; 674de5bdbffSDong Aisheng else 675d31fc00aSDong Aisheng pre_div >>= 1; 676d31fc00aSDong Aisheng div--; 677d31fc00aSDong Aisheng 678d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 679d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 680d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 681d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 682d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 683fed2f6e2SDong Aisheng 6849d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 685fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 686fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 687fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 688fed2f6e2SDong Aisheng } 689fed2f6e2SDong Aisheng 690d31fc00aSDong Aisheng mdelay(1); 6918ba9580aSLucas Stach } 6928ba9580aSLucas Stach 693913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 694913413c3SShawn Guo { 695842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 696070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 697842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 698913413c3SShawn Guo 699913413c3SShawn Guo switch (boarddata->wp_type) { 700913413c3SShawn Guo case ESDHC_WP_GPIO: 701fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 702913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 703913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 704913413c3SShawn Guo SDHCI_WRITE_PROTECT); 705913413c3SShawn Guo case ESDHC_WP_NONE: 706913413c3SShawn Guo break; 707913413c3SShawn Guo } 708913413c3SShawn Guo 709913413c3SShawn Guo return -ENOSYS; 710913413c3SShawn Guo } 711913413c3SShawn Guo 7122317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 713af51079eSSascha Hauer { 714af51079eSSascha Hauer u32 ctrl; 715af51079eSSascha Hauer 716af51079eSSascha Hauer switch (width) { 717af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 718af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 719af51079eSSascha Hauer break; 720af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 721af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 722af51079eSSascha Hauer break; 723af51079eSSascha Hauer default: 724af51079eSSascha Hauer ctrl = 0; 725af51079eSSascha Hauer break; 726af51079eSSascha Hauer } 727af51079eSSascha Hauer 728af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 729af51079eSSascha Hauer SDHCI_HOST_CONTROL); 730af51079eSSascha Hauer } 731af51079eSSascha Hauer 7320322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 7330322191eSDong Aisheng { 7340322191eSDong Aisheng u32 reg; 7350322191eSDong Aisheng 7360322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 7370322191eSDong Aisheng mdelay(1); 7380322191eSDong Aisheng 7390322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7400322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 7410322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 7420322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7430322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 7440322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 7450322191eSDong Aisheng "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 7460322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 7470322191eSDong Aisheng } 7480322191eSDong Aisheng 7490322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 7500322191eSDong Aisheng { 7510322191eSDong Aisheng u32 reg; 7520322191eSDong Aisheng 7530322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7540322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 755da0295ffSDong Aisheng reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 7560322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7570322191eSDong Aisheng } 7580322191eSDong Aisheng 7590322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 7600322191eSDong Aisheng { 7610322191eSDong Aisheng int min, max, avg, ret; 7620322191eSDong Aisheng 7630322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 7640322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 7650322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 7660322191eSDong Aisheng esdhc_prepare_tuning(host, min); 7679979dbe5SChaotian Jing if (!mmc_send_tuning(host->mmc, opcode, NULL)) 7680322191eSDong Aisheng break; 7690322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 7700322191eSDong Aisheng } 7710322191eSDong Aisheng 7720322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 7730322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 7740322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 7750322191eSDong Aisheng esdhc_prepare_tuning(host, max); 7769979dbe5SChaotian Jing if (mmc_send_tuning(host->mmc, opcode, NULL)) { 7770322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 7780322191eSDong Aisheng break; 7790322191eSDong Aisheng } 7800322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 7810322191eSDong Aisheng } 7820322191eSDong Aisheng 7830322191eSDong Aisheng /* use average delay to get the best timing */ 7840322191eSDong Aisheng avg = (min + max) / 2; 7850322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 7869979dbe5SChaotian Jing ret = mmc_send_tuning(host->mmc, opcode, NULL); 7870322191eSDong Aisheng esdhc_post_tuning(host); 7880322191eSDong Aisheng 7890322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 7900322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 7910322191eSDong Aisheng 7920322191eSDong Aisheng return ret; 7930322191eSDong Aisheng } 7940322191eSDong Aisheng 795ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 796ad93220dSDong Aisheng unsigned int uhs) 797ad93220dSDong Aisheng { 798ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 799070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 800ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 801ad93220dSDong Aisheng 802ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 803ad93220dSDong Aisheng 804ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 805ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 806ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 807ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 808ad93220dSDong Aisheng return -EINVAL; 809ad93220dSDong Aisheng 810ad93220dSDong Aisheng switch (uhs) { 811ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 812ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 813ad93220dSDong Aisheng break; 814ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 815429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 81628b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 817ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 818ad93220dSDong Aisheng break; 819ad93220dSDong Aisheng default: 820ad93220dSDong Aisheng /* back to default state for other legacy timing */ 821ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 822ad93220dSDong Aisheng } 823ad93220dSDong Aisheng 824ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 825ad93220dSDong Aisheng } 826ad93220dSDong Aisheng 82728b07674SHaibo Chen /* 82828b07674SHaibo Chen * For HS400 eMMC, there is a data_strobe line, this signal is generated 82928b07674SHaibo Chen * by the device and used for data output and CRC status response output 83028b07674SHaibo Chen * in HS400 mode. The frequency of this signal follows the frequency of 83128b07674SHaibo Chen * CLK generated by host. Host receive the data which is aligned to the 83228b07674SHaibo Chen * edge of data_strobe line. Due to the time delay between CLK line and 83328b07674SHaibo Chen * data_strobe line, if the delay time is larger than one clock cycle, 83428b07674SHaibo Chen * then CLK and data_strobe line will misaligned, read error shows up. 83528b07674SHaibo Chen * So when the CLK is higher than 100MHz, each clock cycle is short enough, 83628b07674SHaibo Chen * host should config the delay target. 83728b07674SHaibo Chen */ 83828b07674SHaibo Chen static void esdhc_set_strobe_dll(struct sdhci_host *host) 83928b07674SHaibo Chen { 84028b07674SHaibo Chen u32 v; 84128b07674SHaibo Chen 84228b07674SHaibo Chen if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { 8437ac6da26SDong Aisheng /* disable clock before enabling strobe dll */ 8447ac6da26SDong Aisheng writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 8457ac6da26SDong Aisheng ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 8467ac6da26SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 8477ac6da26SDong Aisheng 84828b07674SHaibo Chen /* force a reset on strobe dll */ 84928b07674SHaibo Chen writel(ESDHC_STROBE_DLL_CTRL_RESET, 85028b07674SHaibo Chen host->ioaddr + ESDHC_STROBE_DLL_CTRL); 85128b07674SHaibo Chen /* 85228b07674SHaibo Chen * enable strobe dll ctrl and adjust the delay target 85328b07674SHaibo Chen * for the uSDHC loopback read clock 85428b07674SHaibo Chen */ 85528b07674SHaibo Chen v = ESDHC_STROBE_DLL_CTRL_ENABLE | 85628b07674SHaibo Chen (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 85728b07674SHaibo Chen writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 85828b07674SHaibo Chen /* wait 1us to make sure strobe dll status register stable */ 85928b07674SHaibo Chen udelay(1); 86028b07674SHaibo Chen v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); 86128b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) 86228b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 86328b07674SHaibo Chen "warning! HS400 strobe DLL status REF not lock!\n"); 86428b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 86528b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 86628b07674SHaibo Chen "warning! HS400 strobe DLL status SLV not lock!\n"); 86728b07674SHaibo Chen } 86828b07674SHaibo Chen } 86928b07674SHaibo Chen 870850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 871ad93220dSDong Aisheng { 87228b07674SHaibo Chen u32 m; 873ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 874070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 875602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 876ad93220dSDong Aisheng 87728b07674SHaibo Chen /* disable ddr mode and disable HS400 mode */ 87828b07674SHaibo Chen m = readl(host->ioaddr + ESDHC_MIX_CTRL); 87928b07674SHaibo Chen m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 88028b07674SHaibo Chen imx_data->is_ddr = 0; 88128b07674SHaibo Chen 882850a29b8SRussell King switch (timing) { 883ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 884ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 885ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 886ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 887429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 88828b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 889ad93220dSDong Aisheng break; 890ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 89169f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 89228b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN; 89328b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 894de5bdbffSDong Aisheng imx_data->is_ddr = 1; 895602519b2SDong Aisheng if (boarddata->delay_line) { 896602519b2SDong Aisheng u32 v; 897602519b2SDong Aisheng v = boarddata->delay_line << 898602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 899602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 900602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 901602519b2SDong Aisheng v <<= 1; 902602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 903602519b2SDong Aisheng } 904ad93220dSDong Aisheng break; 90528b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 90628b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 90728b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 90828b07674SHaibo Chen imx_data->is_ddr = 1; 9097ac6da26SDong Aisheng /* update clock after enable DDR for strobe DLL lock */ 9107ac6da26SDong Aisheng host->ops->set_clock(host, host->clock); 91128b07674SHaibo Chen esdhc_set_strobe_dll(host); 91228b07674SHaibo Chen break; 913ad93220dSDong Aisheng } 914ad93220dSDong Aisheng 915850a29b8SRussell King esdhc_change_pinstate(host, timing); 916ad93220dSDong Aisheng } 917ad93220dSDong Aisheng 9180718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 9190718e59aSRussell King { 9200718e59aSRussell King sdhci_reset(host, mask); 9210718e59aSRussell King 9220718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 9230718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 9240718e59aSRussell King } 9250718e59aSRussell King 92610fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 92710fd0ad9SAisheng Dong { 92810fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 929070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 93010fd0ad9SAisheng Dong 93110fd0ad9SAisheng Dong return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; 93210fd0ad9SAisheng Dong } 93310fd0ad9SAisheng Dong 934e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 935e33eb8e2SAisheng Dong { 936e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 937070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 938e33eb8e2SAisheng Dong 939e33eb8e2SAisheng Dong /* use maximum timeout counter */ 940e33eb8e2SAisheng Dong sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 941e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 942e33eb8e2SAisheng Dong } 943e33eb8e2SAisheng Dong 9446e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 945e149860dSRichard Zhu .read_l = esdhc_readl_le, 9460c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 947e149860dSRichard Zhu .write_l = esdhc_writel_le, 9480c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 9490c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 9508ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 9510ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 9520c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 95310fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 954913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 955e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 9562317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 957ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 9580718e59aSRussell King .reset = esdhc_reset, 9590c6d49ceSWolfram Sang }; 9600c6d49ceSWolfram Sang 9611db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 96297e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 96397e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 96497e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 96585d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 96685d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 96785d6509dSShawn Guo }; 96885d6509dSShawn Guo 969f3f5cf3dSDong Aisheng static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 970f3f5cf3dSDong Aisheng { 971f3f5cf3dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 972f3f5cf3dSDong Aisheng struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 9732b16cf32SDong Aisheng int tmp; 974f3f5cf3dSDong Aisheng 975f3f5cf3dSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 976f3f5cf3dSDong Aisheng /* 977f3f5cf3dSDong Aisheng * The imx6q ROM code will change the default watermark 978f3f5cf3dSDong Aisheng * level setting to something insane. Change it back here. 979f3f5cf3dSDong Aisheng */ 980f3f5cf3dSDong Aisheng writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 981f3f5cf3dSDong Aisheng 982f3f5cf3dSDong Aisheng /* 983f3f5cf3dSDong Aisheng * ROM code will change the bit burst_length_enable setting 984f3f5cf3dSDong Aisheng * to zero if this usdhc is choosed to boot system. Change 985f3f5cf3dSDong Aisheng * it back here, otherwise it will impact the performance a 986f3f5cf3dSDong Aisheng * lot. This bit is used to enable/disable the burst length 987f3f5cf3dSDong Aisheng * for the external AHB2AXI bridge, it's usefully especially 988f3f5cf3dSDong Aisheng * for INCR transfer because without burst length indicator, 989f3f5cf3dSDong Aisheng * the AHB2AXI bridge does not know the burst length in 990f3f5cf3dSDong Aisheng * advance. And without burst length indicator, AHB INCR 991f3f5cf3dSDong Aisheng * transfer can only be converted to singles on the AXI side. 992f3f5cf3dSDong Aisheng */ 993f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 994f3f5cf3dSDong Aisheng | ESDHC_BURST_LEN_EN_INCR, 995f3f5cf3dSDong Aisheng host->ioaddr + SDHCI_HOST_CONTROL); 996f3f5cf3dSDong Aisheng /* 997f3f5cf3dSDong Aisheng * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 998f3f5cf3dSDong Aisheng * TO1.1, it's harmless for MX6SL 999f3f5cf3dSDong Aisheng */ 1000f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + 0x6c) | BIT(7), 1001f3f5cf3dSDong Aisheng host->ioaddr + 0x6c); 1002f3f5cf3dSDong Aisheng 1003f3f5cf3dSDong Aisheng /* disable DLL_CTRL delay line settings */ 1004f3f5cf3dSDong Aisheng writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 10052b16cf32SDong Aisheng 10062b16cf32SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 10072b16cf32SDong Aisheng tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 10082b16cf32SDong Aisheng tmp |= ESDHC_STD_TUNING_EN | 10092b16cf32SDong Aisheng ESDHC_TUNING_START_TAP_DEFAULT; 10102b16cf32SDong Aisheng if (imx_data->boarddata.tuning_start_tap) { 10112b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_START_TAP_MASK; 10122b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_start_tap; 10132b16cf32SDong Aisheng } 10142b16cf32SDong Aisheng 10152b16cf32SDong Aisheng if (imx_data->boarddata.tuning_step) { 10162b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_STEP_MASK; 10172b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_step 10182b16cf32SDong Aisheng << ESDHC_TUNING_STEP_SHIFT; 10192b16cf32SDong Aisheng } 10202b16cf32SDong Aisheng writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 10212b16cf32SDong Aisheng } 1022f3f5cf3dSDong Aisheng } 1023f3f5cf3dSDong Aisheng } 1024f3f5cf3dSDong Aisheng 1025abfafc2dSShawn Guo #ifdef CONFIG_OF 1026c3be1efdSBill Pemberton static int 1027abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 102807bf2b54SSascha Hauer struct sdhci_host *host, 102991fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1030abfafc2dSShawn Guo { 1031abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 103291fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 10334800e87aSDong Aisheng int ret; 1034abfafc2dSShawn Guo 1035abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 1036abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 1037abfafc2dSShawn Guo 1038abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1039abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 1040abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 1041abfafc2dSShawn Guo 1042d407e30bSHaibo Chen of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1043d87fc966SDong Aisheng of_property_read_u32(np, "fsl,tuning-start-tap", 1044d87fc966SDong Aisheng &boarddata->tuning_start_tap); 1045d407e30bSHaibo Chen 1046ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 1047ad93220dSDong Aisheng boarddata->support_vsel = false; 1048ad93220dSDong Aisheng else 1049ad93220dSDong Aisheng boarddata->support_vsel = true; 1050ad93220dSDong Aisheng 1051602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1052602519b2SDong Aisheng boarddata->delay_line = 0; 1053602519b2SDong Aisheng 105407bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 105507bf2b54SSascha Hauer 105691fa4252SDong Aisheng /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 105791fa4252SDong Aisheng if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && 105891fa4252SDong Aisheng !IS_ERR(imx_data->pins_default)) { 105991fa4252SDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 106091fa4252SDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 106191fa4252SDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 106291fa4252SDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 106391fa4252SDong Aisheng if (IS_ERR(imx_data->pins_100mhz) || 106491fa4252SDong Aisheng IS_ERR(imx_data->pins_200mhz)) { 106591fa4252SDong Aisheng dev_warn(mmc_dev(host->mmc), 106691fa4252SDong Aisheng "could not get ultra high speed state, work on normal mode\n"); 106791fa4252SDong Aisheng /* 106891fa4252SDong Aisheng * fall back to not support uhs by specify no 1.8v quirk 106991fa4252SDong Aisheng */ 107091fa4252SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 107191fa4252SDong Aisheng } 107291fa4252SDong Aisheng } else { 107391fa4252SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 107491fa4252SDong Aisheng } 107591fa4252SDong Aisheng 107615064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 10774800e87aSDong Aisheng ret = mmc_of_parse(host->mmc); 10784800e87aSDong Aisheng if (ret) 10794800e87aSDong Aisheng return ret; 10804800e87aSDong Aisheng 1081287980e4SArnd Bergmann if (mmc_gpio_get_cd(host->mmc) >= 0) 10824800e87aSDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 10834800e87aSDong Aisheng 10844800e87aSDong Aisheng return 0; 1085abfafc2dSShawn Guo } 1086abfafc2dSShawn Guo #else 1087abfafc2dSShawn Guo static inline int 1088abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 108907bf2b54SSascha Hauer struct sdhci_host *host, 109091fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1091abfafc2dSShawn Guo { 1092abfafc2dSShawn Guo return -ENODEV; 1093abfafc2dSShawn Guo } 1094abfafc2dSShawn Guo #endif 1095abfafc2dSShawn Guo 109691fa4252SDong Aisheng static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 109791fa4252SDong Aisheng struct sdhci_host *host, 109891fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 109991fa4252SDong Aisheng { 110091fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 110191fa4252SDong Aisheng int err; 110291fa4252SDong Aisheng 110391fa4252SDong Aisheng if (!host->mmc->parent->platform_data) { 110491fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), "no board data!\n"); 110591fa4252SDong Aisheng return -EINVAL; 110691fa4252SDong Aisheng } 110791fa4252SDong Aisheng 110891fa4252SDong Aisheng imx_data->boarddata = *((struct esdhc_platform_data *) 110991fa4252SDong Aisheng host->mmc->parent->platform_data); 111091fa4252SDong Aisheng /* write_protect */ 111191fa4252SDong Aisheng if (boarddata->wp_type == ESDHC_WP_GPIO) { 111291fa4252SDong Aisheng err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 111391fa4252SDong Aisheng if (err) { 111491fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 111591fa4252SDong Aisheng "failed to request write-protect gpio!\n"); 111691fa4252SDong Aisheng return err; 111791fa4252SDong Aisheng } 111891fa4252SDong Aisheng host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 111991fa4252SDong Aisheng } 112091fa4252SDong Aisheng 112191fa4252SDong Aisheng /* card_detect */ 112291fa4252SDong Aisheng switch (boarddata->cd_type) { 112391fa4252SDong Aisheng case ESDHC_CD_GPIO: 112491fa4252SDong Aisheng err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 112591fa4252SDong Aisheng if (err) { 112691fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 112791fa4252SDong Aisheng "failed to request card-detect gpio!\n"); 112891fa4252SDong Aisheng return err; 112991fa4252SDong Aisheng } 113091fa4252SDong Aisheng /* fall through */ 113191fa4252SDong Aisheng 113291fa4252SDong Aisheng case ESDHC_CD_CONTROLLER: 113391fa4252SDong Aisheng /* we have a working card_detect back */ 113491fa4252SDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 113591fa4252SDong Aisheng break; 113691fa4252SDong Aisheng 113791fa4252SDong Aisheng case ESDHC_CD_PERMANENT: 113891fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 113991fa4252SDong Aisheng break; 114091fa4252SDong Aisheng 114191fa4252SDong Aisheng case ESDHC_CD_NONE: 114291fa4252SDong Aisheng break; 114391fa4252SDong Aisheng } 114491fa4252SDong Aisheng 114591fa4252SDong Aisheng switch (boarddata->max_bus_width) { 114691fa4252SDong Aisheng case 8: 114791fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 114891fa4252SDong Aisheng break; 114991fa4252SDong Aisheng case 4: 115091fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_4_BIT_DATA; 115191fa4252SDong Aisheng break; 115291fa4252SDong Aisheng case 1: 115391fa4252SDong Aisheng default: 115491fa4252SDong Aisheng host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 115591fa4252SDong Aisheng break; 115691fa4252SDong Aisheng } 115791fa4252SDong Aisheng 115891fa4252SDong Aisheng return 0; 115991fa4252SDong Aisheng } 116091fa4252SDong Aisheng 1161c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 116295f25efeSWolfram Sang { 1163abfafc2dSShawn Guo const struct of_device_id *of_id = 1164abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 116585d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 116685d6509dSShawn Guo struct sdhci_host *host; 11670c6d49ceSWolfram Sang int err; 1168e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 116995f25efeSWolfram Sang 1170070e6d3fSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1171070e6d3fSJisheng Zhang sizeof(*imx_data)); 117285d6509dSShawn Guo if (IS_ERR(host)) 117385d6509dSShawn Guo return PTR_ERR(host); 117485d6509dSShawn Guo 117585d6509dSShawn Guo pltfm_host = sdhci_priv(host); 117685d6509dSShawn Guo 1177070e6d3fSJisheng Zhang imx_data = sdhci_pltfm_priv(pltfm_host); 117857ed3314SShawn Guo 1179f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 11803770ee8fSShawn Guo pdev->id_entry->driver_data; 118185d6509dSShawn Guo 118252dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 118352dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 118452dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 1185e3af31c6SShawn Guo goto free_sdhci; 118695f25efeSWolfram Sang } 118752dac615SSascha Hauer 118852dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 118952dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 119052dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 1191e3af31c6SShawn Guo goto free_sdhci; 119252dac615SSascha Hauer } 119352dac615SSascha Hauer 119452dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 119552dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 119652dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 1197e3af31c6SShawn Guo goto free_sdhci; 119852dac615SSascha Hauer } 119952dac615SSascha Hauer 120052dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 1201a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 120252dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 120352dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 120452dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 120595f25efeSWolfram Sang 1206ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1207e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1208e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 1209e3af31c6SShawn Guo goto disable_clk; 1210e62d8b8fSDong Aisheng } 1211e62d8b8fSDong Aisheng 1212ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 1213ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 1214cd529af7SDirk Behme if (IS_ERR(imx_data->pins_default)) 1215cd529af7SDirk Behme dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 1216ad93220dSDong Aisheng 1217f47c4bbfSShawn Guo if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 12180c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 121997e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 122097e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 12210c6d49ceSWolfram Sang 122269ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 122369ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1224e2997c94SDong Aisheng host->mmc->caps |= MMC_CAP_1_8V_DDR; 12254245afffSDong Aisheng if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 12264245afffSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 122769ed60e0SDong Aisheng } 1228f750ba9bSShawn Guo 12296e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 12306e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 12316e9fd28eSDong Aisheng esdhc_executing_tuning; 12328b2bb0adSDong Aisheng 123318094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 123418094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 123518094430SDong Aisheng 123628b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 123728b07674SHaibo Chen host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 123828b07674SHaibo Chen 123991fa4252SDong Aisheng if (of_id) 124091fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 124191fa4252SDong Aisheng else 124291fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 124391fa4252SDong Aisheng if (err) 1244e3af31c6SShawn Guo goto disable_clk; 1245ad93220dSDong Aisheng 1246f3f5cf3dSDong Aisheng sdhci_esdhc_imx_hwinit(host); 1247f3f5cf3dSDong Aisheng 124885d6509dSShawn Guo err = sdhci_add_host(host); 124985d6509dSShawn Guo if (err) 1250e3af31c6SShawn Guo goto disable_clk; 125185d6509dSShawn Guo 125289d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 125389d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 125489d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 125589d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 125677903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 125789d7e5c1SDong Aisheng 12587e29c306SWolfram Sang return 0; 12597e29c306SWolfram Sang 1260e3af31c6SShawn Guo disable_clk: 126152dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 126252dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 126352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 1264e3af31c6SShawn Guo free_sdhci: 126585d6509dSShawn Guo sdhci_pltfm_free(pdev); 126685d6509dSShawn Guo return err; 126795f25efeSWolfram Sang } 126895f25efeSWolfram Sang 12696e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 127095f25efeSWolfram Sang { 127185d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 127295f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1273070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 127485d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 127585d6509dSShawn Guo 12760b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 12770b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 12780b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 12790b414368SUlf Hansson 128085d6509dSShawn Guo sdhci_remove_host(host, dead); 12810c6d49ceSWolfram Sang 128252dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 128352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 128452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 128552dac615SSascha Hauer 128685d6509dSShawn Guo sdhci_pltfm_free(pdev); 128785d6509dSShawn Guo 128885d6509dSShawn Guo return 0; 128995f25efeSWolfram Sang } 129095f25efeSWolfram Sang 1291162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 129204143fbaSDong Aisheng static int sdhci_esdhc_suspend(struct device *dev) 129304143fbaSDong Aisheng { 129404143fbaSDong Aisheng return sdhci_pltfm_suspend(dev); 129504143fbaSDong Aisheng } 129604143fbaSDong Aisheng 129704143fbaSDong Aisheng static int sdhci_esdhc_resume(struct device *dev) 129804143fbaSDong Aisheng { 1299cc17e129SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 1300cc17e129SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1301cc17e129SDong Aisheng struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1302cc17e129SDong Aisheng 1303cc17e129SDong Aisheng /* restore watermark setting in case it's lost in low power mode */ 1304cc17e129SDong Aisheng if (esdhc_is_usdhc(imx_data)) 1305cc17e129SDong Aisheng writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1306cc17e129SDong Aisheng 130704143fbaSDong Aisheng return sdhci_pltfm_resume(dev); 130804143fbaSDong Aisheng } 130904143fbaSDong Aisheng 131089d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 131189d7e5c1SDong Aisheng { 131289d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 131389d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1314070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 131589d7e5c1SDong Aisheng int ret; 131689d7e5c1SDong Aisheng 131789d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 131889d7e5c1SDong Aisheng 1319be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 132089d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 132189d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 1322be138554SRussell King } 132389d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 132489d7e5c1SDong Aisheng 132589d7e5c1SDong Aisheng return ret; 132689d7e5c1SDong Aisheng } 132789d7e5c1SDong Aisheng 132889d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 132989d7e5c1SDong Aisheng { 133089d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 133189d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1332070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 133389d7e5c1SDong Aisheng 1334be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 133589d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_per); 133689d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ipg); 1337be138554SRussell King } 133889d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ahb); 133989d7e5c1SDong Aisheng 134089d7e5c1SDong Aisheng return sdhci_runtime_resume_host(host); 134189d7e5c1SDong Aisheng } 134289d7e5c1SDong Aisheng #endif 134389d7e5c1SDong Aisheng 134489d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 134504143fbaSDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 134689d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 134789d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 134889d7e5c1SDong Aisheng }; 134989d7e5c1SDong Aisheng 135085d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 135185d6509dSShawn Guo .driver = { 135285d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1353abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 135489d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 135585d6509dSShawn Guo }, 135657ed3314SShawn Guo .id_table = imx_esdhc_devtype, 135785d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 13580433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 135995f25efeSWolfram Sang }; 136085d6509dSShawn Guo 1361d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 136285d6509dSShawn Guo 136385d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1364035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 136585d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1366