195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 795f25efeSWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3095f25efeSWolfram Sang #include "sdhci-pltfm.h" 3195f25efeSWolfram Sang #include "sdhci-esdhc.h" 3295f25efeSWolfram Sang 3360bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 3458ac8177SRichard Zhu /* VENDOR SPEC register */ 3560bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 3760bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 3860bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 392a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 402a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 412a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 4258ac8177SRichard Zhu 4358ac8177SRichard Zhu /* 44af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 45af51079eSSascha Hauer */ 46af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 47af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 48af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 49af51079eSSascha Hauer 50af51079eSSascha Hauer /* 5197e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 5297e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 5397e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 5497e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 5597e4ba6aSRichard Zhu */ 5660bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 5797e4ba6aSRichard Zhu 5897e4ba6aSRichard Zhu /* 5958ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 6058ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 6158ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 6258ac8177SRichard Zhu * be generated. 6358ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 6458ac8177SRichard Zhu * operations automatically as required at the end of the 6558ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 6658ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 6758ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 6858ac8177SRichard Zhu */ 6958ac8177SRichard Zhu #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1) 70e149860dSRichard Zhu 7157ed3314SShawn Guo enum imx_esdhc_type { 7257ed3314SShawn Guo IMX25_ESDHC, 7357ed3314SShawn Guo IMX35_ESDHC, 7457ed3314SShawn Guo IMX51_ESDHC, 7557ed3314SShawn Guo IMX53_ESDHC, 7695a2482aSShawn Guo IMX6Q_USDHC, 7757ed3314SShawn Guo }; 7857ed3314SShawn Guo 79e149860dSRichard Zhu struct pltfm_imx_data { 80e149860dSRichard Zhu int flags; 81e149860dSRichard Zhu u32 scratchpad; 8257ed3314SShawn Guo enum imx_esdhc_type devtype; 83e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 84842afc02SShawn Guo struct esdhc_platform_data boarddata; 8552dac615SSascha Hauer struct clk *clk_ipg; 8652dac615SSascha Hauer struct clk *clk_ahb; 8752dac615SSascha Hauer struct clk *clk_per; 88e149860dSRichard Zhu }; 89e149860dSRichard Zhu 9057ed3314SShawn Guo static struct platform_device_id imx_esdhc_devtype[] = { 9157ed3314SShawn Guo { 9257ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 9357ed3314SShawn Guo .driver_data = IMX25_ESDHC, 9457ed3314SShawn Guo }, { 9557ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 9657ed3314SShawn Guo .driver_data = IMX35_ESDHC, 9757ed3314SShawn Guo }, { 9857ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 9957ed3314SShawn Guo .driver_data = IMX51_ESDHC, 10057ed3314SShawn Guo }, { 10157ed3314SShawn Guo .name = "sdhci-esdhc-imx53", 10257ed3314SShawn Guo .driver_data = IMX53_ESDHC, 10357ed3314SShawn Guo }, { 10495a2482aSShawn Guo .name = "sdhci-usdhc-imx6q", 10595a2482aSShawn Guo .driver_data = IMX6Q_USDHC, 10695a2482aSShawn Guo }, { 10757ed3314SShawn Guo /* sentinel */ 10857ed3314SShawn Guo } 10957ed3314SShawn Guo }; 11057ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 11157ed3314SShawn Guo 112abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 113abfafc2dSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], }, 114abfafc2dSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], }, 115abfafc2dSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], }, 116abfafc2dSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], }, 11795a2482aSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], }, 118abfafc2dSShawn Guo { /* sentinel */ } 119abfafc2dSShawn Guo }; 120abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 121abfafc2dSShawn Guo 12257ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 12357ed3314SShawn Guo { 12457ed3314SShawn Guo return data->devtype == IMX25_ESDHC; 12557ed3314SShawn Guo } 12657ed3314SShawn Guo 12757ed3314SShawn Guo static inline int is_imx35_esdhc(struct pltfm_imx_data *data) 12857ed3314SShawn Guo { 12957ed3314SShawn Guo return data->devtype == IMX35_ESDHC; 13057ed3314SShawn Guo } 13157ed3314SShawn Guo 13257ed3314SShawn Guo static inline int is_imx51_esdhc(struct pltfm_imx_data *data) 13357ed3314SShawn Guo { 13457ed3314SShawn Guo return data->devtype == IMX51_ESDHC; 13557ed3314SShawn Guo } 13657ed3314SShawn Guo 13757ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 13857ed3314SShawn Guo { 13957ed3314SShawn Guo return data->devtype == IMX53_ESDHC; 14057ed3314SShawn Guo } 14157ed3314SShawn Guo 14295a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 14395a2482aSShawn Guo { 14495a2482aSShawn Guo return data->devtype == IMX6Q_USDHC; 14595a2482aSShawn Guo } 14695a2482aSShawn Guo 14795f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 14895f25efeSWolfram Sang { 14995f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 15095f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 15195f25efeSWolfram Sang 15295f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 15395f25efeSWolfram Sang } 15495f25efeSWolfram Sang 1557e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 1567e29c306SWolfram Sang { 157913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 158913413c3SShawn Guo 15997e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 16097e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 16197e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 16297e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 16397e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 16497e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 16597e4ba6aSRichard Zhu */ 16697e4ba6aSRichard Zhu 16797e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 16897e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 16997e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 17097e4ba6aSRichard Zhu } 17197e4ba6aSRichard Zhu } 17297e4ba6aSRichard Zhu 17397e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 17460bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 17560bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 17697e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 17797e4ba6aSRichard Zhu } 17897e4ba6aSRichard Zhu } 17997e4ba6aSRichard Zhu 1807e29c306SWolfram Sang return val; 1817e29c306SWolfram Sang } 1827e29c306SWolfram Sang 1837e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 1847e29c306SWolfram Sang { 185e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 186e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 1870d58864bSTony Lin u32 data; 188e149860dSRichard Zhu 1890d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 1900d58864bSTony Lin if (val & SDHCI_INT_CARD_INT) { 1910d58864bSTony Lin /* 1920d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 1930d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 1940d58864bSTony Lin * so we need to apply the following workaround: clear 1950d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 1960d58864bSTony Lin * interrupt. In case a card interrupt was lost, 1970d58864bSTony Lin * re-sample it by the following steps. 1980d58864bSTony Lin */ 1990d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 20060bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 2010d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 20260bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 2030d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 2040d58864bSTony Lin } 2050d58864bSTony Lin } 2060d58864bSTony Lin 20758ac8177SRichard Zhu if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 20858ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 20958ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 21058ac8177SRichard Zhu u32 v; 21160bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 21260bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 21360bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 21458ac8177SRichard Zhu } 21558ac8177SRichard Zhu 21697e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 21797e4ba6aSRichard Zhu if (val & SDHCI_INT_ADMA_ERROR) { 21897e4ba6aSRichard Zhu val &= ~SDHCI_INT_ADMA_ERROR; 21960bf6396SShawn Guo val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 22097e4ba6aSRichard Zhu } 22197e4ba6aSRichard Zhu } 22297e4ba6aSRichard Zhu 2237e29c306SWolfram Sang writel(val, host->ioaddr + reg); 2247e29c306SWolfram Sang } 2257e29c306SWolfram Sang 22695f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 22795f25efeSWolfram Sang { 228ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 229ef4d0888SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 230ef4d0888SShawn Guo 23195a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 232ef4d0888SShawn Guo reg ^= 2; 233ef4d0888SShawn Guo if (is_imx6q_usdhc(imx_data)) { 23495a2482aSShawn Guo /* 235ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 236ef4d0888SShawn Guo * Correct it here. 23795a2482aSShawn Guo */ 238ef4d0888SShawn Guo return SDHCI_SPEC_300; 239ef4d0888SShawn Guo } 24095a2482aSShawn Guo } 24195f25efeSWolfram Sang 24295f25efeSWolfram Sang return readw(host->ioaddr + reg); 24395f25efeSWolfram Sang } 24495f25efeSWolfram Sang 24595f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 24695f25efeSWolfram Sang { 24795f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 248e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 24995f25efeSWolfram Sang 25095f25efeSWolfram Sang switch (reg) { 25195f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 25258ac8177SRichard Zhu if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 25358ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 25458ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 25558ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 25658ac8177SRichard Zhu u32 v; 25760bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 25860bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 25960bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 26058ac8177SRichard Zhu } 26169f54698SShawn Guo 26269f54698SShawn Guo if (is_imx6q_usdhc(imx_data)) { 26369f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 2642a15f981SShawn Guo /* Swap AC23 bit */ 2652a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 2662a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 2672a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 2682a15f981SShawn Guo } 2692a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 27069f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 27169f54698SShawn Guo } else { 27269f54698SShawn Guo /* 27369f54698SShawn Guo * Postpone this write, we must do it together with a 27469f54698SShawn Guo * command write that is down below. 27569f54698SShawn Guo */ 276e149860dSRichard Zhu imx_data->scratchpad = val; 27769f54698SShawn Guo } 27895f25efeSWolfram Sang return; 27995f25efeSWolfram Sang case SDHCI_COMMAND: 2805b6b0ad6SSascha Hauer if ((host->cmd->opcode == MMC_STOP_TRANSMISSION || 2815b6b0ad6SSascha Hauer host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 2825b6b0ad6SSascha Hauer (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 28358ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 28495a2482aSShawn Guo 28569f54698SShawn Guo if (is_imx6q_usdhc(imx_data)) 28695a2482aSShawn Guo writel(val << 16, 28795a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 28869f54698SShawn Guo else 289e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 29095f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 29195f25efeSWolfram Sang return; 29295f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 29395f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 29495f25efeSWolfram Sang break; 29595f25efeSWolfram Sang } 29695f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 29795f25efeSWolfram Sang } 29895f25efeSWolfram Sang 29995f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 30095f25efeSWolfram Sang { 3019a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3029a0985b7SWilson Callan struct pltfm_imx_data *imx_data = pltfm_host->priv; 30395f25efeSWolfram Sang u32 new_val; 304af51079eSSascha Hauer u32 mask; 30595f25efeSWolfram Sang 30695f25efeSWolfram Sang switch (reg) { 30795f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 30895f25efeSWolfram Sang /* 30995f25efeSWolfram Sang * FSL put some DMA bits here 31095f25efeSWolfram Sang * If your board has a regulator, code should be here 31195f25efeSWolfram Sang */ 31295f25efeSWolfram Sang return; 31395f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 3146b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 315af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 3167122bbb0SMasanari Iida /* ensure the endianness */ 31795f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 3189a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 3199a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 32095f25efeSWolfram Sang /* DMA mode bits are shifted */ 32195f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 3229a0985b7SWilson Callan } 32395f25efeSWolfram Sang 324af51079eSSascha Hauer /* 325af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 326af51079eSSascha Hauer * esdhc_pltfm_bus_width. 327af51079eSSascha Hauer */ 328af51079eSSascha Hauer mask = 0xffff & ~ESDHC_CTRL_BUSWIDTH_MASK; 329af51079eSSascha Hauer 330af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 33195f25efeSWolfram Sang return; 33295f25efeSWolfram Sang } 33395f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 334913413c3SShawn Guo 335913413c3SShawn Guo /* 336913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 337913413c3SShawn Guo * that software reset should not affect card detection circuit. 338913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 339913413c3SShawn Guo * software reset. This will stop those clocks that card detection 340913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 341913413c3SShawn Guo * to keep card detection circuit functional. 342913413c3SShawn Guo */ 34358c8c4fbSShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 344913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 34558c8c4fbSShawn Guo /* 34658c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 34758c8c4fbSShawn Guo * Do it manually here. 34858c8c4fbSShawn Guo */ 34958c8c4fbSShawn Guo if (is_imx6q_usdhc(imx_data)) 35058c8c4fbSShawn Guo writel(0, host->ioaddr + ESDHC_MIX_CTRL); 35158c8c4fbSShawn Guo } 35295f25efeSWolfram Sang } 35395f25efeSWolfram Sang 35495f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 35595f25efeSWolfram Sang { 35695f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 35795f25efeSWolfram Sang 35895f25efeSWolfram Sang return clk_get_rate(pltfm_host->clk) / 256 / 16; 35995f25efeSWolfram Sang } 36095f25efeSWolfram Sang 361913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 362913413c3SShawn Guo { 363842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 364842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 365842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 366913413c3SShawn Guo 367913413c3SShawn Guo switch (boarddata->wp_type) { 368913413c3SShawn Guo case ESDHC_WP_GPIO: 369fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 370913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 371913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 372913413c3SShawn Guo SDHCI_WRITE_PROTECT); 373913413c3SShawn Guo case ESDHC_WP_NONE: 374913413c3SShawn Guo break; 375913413c3SShawn Guo } 376913413c3SShawn Guo 377913413c3SShawn Guo return -ENOSYS; 378913413c3SShawn Guo } 379913413c3SShawn Guo 380af51079eSSascha Hauer static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) 381af51079eSSascha Hauer { 382af51079eSSascha Hauer u32 ctrl; 383af51079eSSascha Hauer 384af51079eSSascha Hauer switch (width) { 385af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 386af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 387af51079eSSascha Hauer break; 388af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 389af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 390af51079eSSascha Hauer break; 391af51079eSSascha Hauer default: 392af51079eSSascha Hauer ctrl = 0; 393af51079eSSascha Hauer break; 394af51079eSSascha Hauer } 395af51079eSSascha Hauer 396af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 397af51079eSSascha Hauer SDHCI_HOST_CONTROL); 398af51079eSSascha Hauer 399af51079eSSascha Hauer return 0; 400af51079eSSascha Hauer } 401af51079eSSascha Hauer 4020c6d49ceSWolfram Sang static struct sdhci_ops sdhci_esdhc_ops = { 403e149860dSRichard Zhu .read_l = esdhc_readl_le, 4040c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 405e149860dSRichard Zhu .write_l = esdhc_writel_le, 4060c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 4070c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 4080c6d49ceSWolfram Sang .set_clock = esdhc_set_clock, 409d005d943SLars-Peter Clausen .get_max_clock = sdhci_pltfm_clk_get_max_clock, 4100c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 411913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 412af51079eSSascha Hauer .platform_bus_width = esdhc_pltfm_bus_width, 4130c6d49ceSWolfram Sang }; 4140c6d49ceSWolfram Sang 4151db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 41697e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 41797e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 41897e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 41985d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 42085d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 42185d6509dSShawn Guo }; 42285d6509dSShawn Guo 423abfafc2dSShawn Guo #ifdef CONFIG_OF 424c3be1efdSBill Pemberton static int 425abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 426abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 427abfafc2dSShawn Guo { 428abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 429abfafc2dSShawn Guo 430abfafc2dSShawn Guo if (!np) 431abfafc2dSShawn Guo return -ENODEV; 432abfafc2dSShawn Guo 4337f217794SArnd Bergmann if (of_get_property(np, "non-removable", NULL)) 434abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_PERMANENT; 435abfafc2dSShawn Guo 436abfafc2dSShawn Guo if (of_get_property(np, "fsl,cd-controller", NULL)) 437abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_CONTROLLER; 438abfafc2dSShawn Guo 439abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 440abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 441abfafc2dSShawn Guo 442abfafc2dSShawn Guo boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 443abfafc2dSShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 444abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_GPIO; 445abfafc2dSShawn Guo 446abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 447abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 448abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 449abfafc2dSShawn Guo 450af51079eSSascha Hauer of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); 451af51079eSSascha Hauer 452abfafc2dSShawn Guo return 0; 453abfafc2dSShawn Guo } 454abfafc2dSShawn Guo #else 455abfafc2dSShawn Guo static inline int 456abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 457abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 458abfafc2dSShawn Guo { 459abfafc2dSShawn Guo return -ENODEV; 460abfafc2dSShawn Guo } 461abfafc2dSShawn Guo #endif 462abfafc2dSShawn Guo 463c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 46495f25efeSWolfram Sang { 465abfafc2dSShawn Guo const struct of_device_id *of_id = 466abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 46785d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 46885d6509dSShawn Guo struct sdhci_host *host; 46985d6509dSShawn Guo struct esdhc_platform_data *boarddata; 4700c6d49ceSWolfram Sang int err; 471e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 47295f25efeSWolfram Sang 47385d6509dSShawn Guo host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata); 47485d6509dSShawn Guo if (IS_ERR(host)) 47585d6509dSShawn Guo return PTR_ERR(host); 47685d6509dSShawn Guo 47785d6509dSShawn Guo pltfm_host = sdhci_priv(host); 47885d6509dSShawn Guo 479e3af31c6SShawn Guo imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 480abfafc2dSShawn Guo if (!imx_data) { 481abfafc2dSShawn Guo err = -ENOMEM; 482e3af31c6SShawn Guo goto free_sdhci; 483abfafc2dSShawn Guo } 48457ed3314SShawn Guo 485abfafc2dSShawn Guo if (of_id) 486abfafc2dSShawn Guo pdev->id_entry = of_id->data; 48757ed3314SShawn Guo imx_data->devtype = pdev->id_entry->driver_data; 48885d6509dSShawn Guo pltfm_host->priv = imx_data; 48985d6509dSShawn Guo 49052dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 49152dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 49252dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 493e3af31c6SShawn Guo goto free_sdhci; 49495f25efeSWolfram Sang } 49552dac615SSascha Hauer 49652dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 49752dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 49852dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 499e3af31c6SShawn Guo goto free_sdhci; 50052dac615SSascha Hauer } 50152dac615SSascha Hauer 50252dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 50352dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 50452dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 505e3af31c6SShawn Guo goto free_sdhci; 50652dac615SSascha Hauer } 50752dac615SSascha Hauer 50852dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 50952dac615SSascha Hauer 51052dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 51152dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 51252dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 51395f25efeSWolfram Sang 514e62d8b8fSDong Aisheng imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 515e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 516e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 517e3af31c6SShawn Guo goto disable_clk; 518e62d8b8fSDong Aisheng } 519e62d8b8fSDong Aisheng 52037865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 52137865fe9SEric Bénard 52257ed3314SShawn Guo if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) 5230c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 52497e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 52597e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 5260c6d49ceSWolfram Sang 52757ed3314SShawn Guo if (is_imx53_esdhc(imx_data)) 52858ac8177SRichard Zhu imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT; 52958ac8177SRichard Zhu 530f750ba9bSShawn Guo /* 531f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 532f750ba9bSShawn Guo * to something insane. Change it back here. 533f750ba9bSShawn Guo */ 534f750ba9bSShawn Guo if (is_imx6q_usdhc(imx_data)) 53560bf6396SShawn Guo writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 536f750ba9bSShawn Guo 537abfafc2dSShawn Guo boarddata = &imx_data->boarddata; 538abfafc2dSShawn Guo if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { 539842afc02SShawn Guo if (!host->mmc->parent->platform_data) { 540913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "no board data!\n"); 541913413c3SShawn Guo err = -EINVAL; 542e3af31c6SShawn Guo goto disable_clk; 543913413c3SShawn Guo } 544842afc02SShawn Guo imx_data->boarddata = *((struct esdhc_platform_data *) 545842afc02SShawn Guo host->mmc->parent->platform_data); 546abfafc2dSShawn Guo } 547913413c3SShawn Guo 548913413c3SShawn Guo /* write_protect */ 549913413c3SShawn Guo if (boarddata->wp_type == ESDHC_WP_GPIO) { 550fbe5fdd1SShawn Guo err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 5510c6d49ceSWolfram Sang if (err) { 552fbe5fdd1SShawn Guo dev_err(mmc_dev(host->mmc), 553fbe5fdd1SShawn Guo "failed to request write-protect gpio!\n"); 554fbe5fdd1SShawn Guo goto disable_clk; 555913413c3SShawn Guo } 556fbe5fdd1SShawn Guo host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 5570c6d49ceSWolfram Sang } 5587e29c306SWolfram Sang 559913413c3SShawn Guo /* card_detect */ 560913413c3SShawn Guo switch (boarddata->cd_type) { 561913413c3SShawn Guo case ESDHC_CD_GPIO: 562fbe5fdd1SShawn Guo err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio); 5637e29c306SWolfram Sang if (err) { 564913413c3SShawn Guo dev_err(mmc_dev(host->mmc), 565fbe5fdd1SShawn Guo "failed to request card-detect gpio!\n"); 566e3af31c6SShawn Guo goto disable_clk; 5677e29c306SWolfram Sang } 568913413c3SShawn Guo /* fall through */ 5697e29c306SWolfram Sang 570913413c3SShawn Guo case ESDHC_CD_CONTROLLER: 571913413c3SShawn Guo /* we have a working card_detect back */ 5727e29c306SWolfram Sang host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 573913413c3SShawn Guo break; 574913413c3SShawn Guo 575913413c3SShawn Guo case ESDHC_CD_PERMANENT: 576913413c3SShawn Guo host->mmc->caps = MMC_CAP_NONREMOVABLE; 577913413c3SShawn Guo break; 578913413c3SShawn Guo 579913413c3SShawn Guo case ESDHC_CD_NONE: 580913413c3SShawn Guo break; 5817e29c306SWolfram Sang } 5827e29c306SWolfram Sang 583af51079eSSascha Hauer switch (boarddata->max_bus_width) { 584af51079eSSascha Hauer case 8: 585af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 586af51079eSSascha Hauer break; 587af51079eSSascha Hauer case 4: 588af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_4_BIT_DATA; 589af51079eSSascha Hauer break; 590af51079eSSascha Hauer case 1: 591af51079eSSascha Hauer default: 592af51079eSSascha Hauer host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 593af51079eSSascha Hauer break; 594af51079eSSascha Hauer } 595af51079eSSascha Hauer 59685d6509dSShawn Guo err = sdhci_add_host(host); 59785d6509dSShawn Guo if (err) 598e3af31c6SShawn Guo goto disable_clk; 59985d6509dSShawn Guo 6007e29c306SWolfram Sang return 0; 6017e29c306SWolfram Sang 602e3af31c6SShawn Guo disable_clk: 60352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 60452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 60552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 606e3af31c6SShawn Guo free_sdhci: 60785d6509dSShawn Guo sdhci_pltfm_free(pdev); 60885d6509dSShawn Guo return err; 60995f25efeSWolfram Sang } 61095f25efeSWolfram Sang 6116e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 61295f25efeSWolfram Sang { 61385d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 61495f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 615e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 61685d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 61785d6509dSShawn Guo 61885d6509dSShawn Guo sdhci_remove_host(host, dead); 6190c6d49ceSWolfram Sang 62052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 62152dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 62252dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 62352dac615SSascha Hauer 62485d6509dSShawn Guo sdhci_pltfm_free(pdev); 62585d6509dSShawn Guo 62685d6509dSShawn Guo return 0; 62795f25efeSWolfram Sang } 62895f25efeSWolfram Sang 62985d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 63085d6509dSShawn Guo .driver = { 63185d6509dSShawn Guo .name = "sdhci-esdhc-imx", 63285d6509dSShawn Guo .owner = THIS_MODULE, 633abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 63429495aa0SManuel Lauss .pm = SDHCI_PLTFM_PMOPS, 63585d6509dSShawn Guo }, 63657ed3314SShawn Guo .id_table = imx_esdhc_devtype, 63785d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 6380433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 63995f25efeSWolfram Sang }; 64085d6509dSShawn Guo 641d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 64285d6509dSShawn Guo 64385d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 64485d6509dSShawn Guo MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 64585d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 646