195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 7035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3089d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 3195f25efeSWolfram Sang #include "sdhci-pltfm.h" 3295f25efeSWolfram Sang #include "sdhci-esdhc.h" 3395f25efeSWolfram Sang 3460bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 3558ac8177SRichard Zhu /* VENDOR SPEC register */ 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3760bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 380322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 39fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 4060bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 4160bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 42de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 432a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 440322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 450322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 460322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 472a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 482a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 49d131a71cSDong Aisheng /* Tuning bits */ 50d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 5158ac8177SRichard Zhu 52602519b2SDong Aisheng /* dll control register */ 53602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 54602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 55602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 56602519b2SDong Aisheng 570322191eSDong Aisheng /* tune control register */ 580322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 590322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 600322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 610322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 620322191eSDong Aisheng 636e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 646e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 656e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 666e9fd28eSDong Aisheng #define ESDHC_TUNING_START_TAP 0x1 676e9fd28eSDong Aisheng 68ad93220dSDong Aisheng /* pinctrl state */ 69ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 70ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 71ad93220dSDong Aisheng 7258ac8177SRichard Zhu /* 73af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 74af51079eSSascha Hauer */ 75af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 76af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 77af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 78af51079eSSascha Hauer 79af51079eSSascha Hauer /* 8097e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 8197e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 8297e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 8397e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 8497e4ba6aSRichard Zhu */ 8560bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 8697e4ba6aSRichard Zhu 8797e4ba6aSRichard Zhu /* 8858ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 8958ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 9058ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 9158ac8177SRichard Zhu * be generated. 9258ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 9358ac8177SRichard Zhu * operations automatically as required at the end of the 9458ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 9558ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 9658ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 9758ac8177SRichard Zhu */ 9831fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 9931fbb301SShawn Guo /* 10031fbb301SShawn Guo * The flag enables the workaround for ESDHC errata ENGcm07207 which 10131fbb301SShawn Guo * affects i.MX25 and i.MX35. 10231fbb301SShawn Guo */ 10331fbb301SShawn Guo #define ESDHC_FLAG_ENGCM07207 BIT(2) 1049d61c009SShawn Guo /* 1059d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1069d61c009SShawn Guo * integrated on the i.MX6 series. 1079d61c009SShawn Guo */ 1089d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1096e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1106e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1116e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1126e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1136e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1146e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 11518094430SDong Aisheng /* 11618094430SDong Aisheng * The IP has errata ERR004536 11718094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 11818094430SDong Aisheng * when reading data from the card 11918094430SDong Aisheng */ 12018094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 121e149860dSRichard Zhu 122f47c4bbfSShawn Guo struct esdhc_soc_data { 123f47c4bbfSShawn Guo u32 flags; 124f47c4bbfSShawn Guo }; 125f47c4bbfSShawn Guo 126f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx25_data = { 127f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 128f47c4bbfSShawn Guo }; 129f47c4bbfSShawn Guo 130f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx35_data = { 131f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 132f47c4bbfSShawn Guo }; 133f47c4bbfSShawn Guo 134f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx51_data = { 135f47c4bbfSShawn Guo .flags = 0, 136f47c4bbfSShawn Guo }; 137f47c4bbfSShawn Guo 138f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx53_data = { 139f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 140f47c4bbfSShawn Guo }; 141f47c4bbfSShawn Guo 142f47c4bbfSShawn Guo static struct esdhc_soc_data usdhc_imx6q_data = { 1436e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1446e9fd28eSDong Aisheng }; 1456e9fd28eSDong Aisheng 1466e9fd28eSDong Aisheng static struct esdhc_soc_data usdhc_imx6sl_data = { 1476e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 14818094430SDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536, 14957ed3314SShawn Guo }; 15057ed3314SShawn Guo 151e149860dSRichard Zhu struct pltfm_imx_data { 152e149860dSRichard Zhu u32 scratchpad; 153e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 154ad93220dSDong Aisheng struct pinctrl_state *pins_default; 155ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 156ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 157f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 158842afc02SShawn Guo struct esdhc_platform_data boarddata; 15952dac615SSascha Hauer struct clk *clk_ipg; 16052dac615SSascha Hauer struct clk *clk_ahb; 16152dac615SSascha Hauer struct clk *clk_per; 162361b8482SLucas Stach enum { 163361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending*/ 164361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 165361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 166361b8482SLucas Stach } multiblock_status; 167de5bdbffSDong Aisheng u32 is_ddr; 168e149860dSRichard Zhu }; 169e149860dSRichard Zhu 170f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 17157ed3314SShawn Guo { 17257ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 173f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 17457ed3314SShawn Guo }, { 17557ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 176f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 17757ed3314SShawn Guo }, { 17857ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 179f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 18057ed3314SShawn Guo }, { 18157ed3314SShawn Guo /* sentinel */ 18257ed3314SShawn Guo } 18357ed3314SShawn Guo }; 18457ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 18557ed3314SShawn Guo 186abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 187f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 188f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 189f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 190f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 1916e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 192f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 193abfafc2dSShawn Guo { /* sentinel */ } 194abfafc2dSShawn Guo }; 195abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 196abfafc2dSShawn Guo 19757ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 19857ed3314SShawn Guo { 199f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 20057ed3314SShawn Guo } 20157ed3314SShawn Guo 20257ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 20357ed3314SShawn Guo { 204f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 20557ed3314SShawn Guo } 20657ed3314SShawn Guo 20795a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 20895a2482aSShawn Guo { 209f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 21095a2482aSShawn Guo } 21195a2482aSShawn Guo 2129d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2139d61c009SShawn Guo { 214f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2159d61c009SShawn Guo } 2169d61c009SShawn Guo 21795f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 21895f25efeSWolfram Sang { 21995f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 22095f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 22195f25efeSWolfram Sang 22295f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 22395f25efeSWolfram Sang } 22495f25efeSWolfram Sang 2257e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 2267e29c306SWolfram Sang { 227361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 228361b8482SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 229913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 230913413c3SShawn Guo 2310322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 2320322191eSDong Aisheng u32 fsl_prss = val; 2330322191eSDong Aisheng /* save the least 20 bits */ 2340322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 2350322191eSDong Aisheng /* move dat[0-3] bits */ 2360322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 2370322191eSDong Aisheng /* move cmd line bit */ 2380322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 2390322191eSDong Aisheng } 2400322191eSDong Aisheng 24197e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 2426b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 2436b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2446b4fb671SDong Aisheng val &= 0xffff0000; 2456b4fb671SDong Aisheng 24697e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 24797e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 24897e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 24997e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 25097e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 25197e4ba6aSRichard Zhu */ 25297e4ba6aSRichard Zhu 25397e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 25497e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 25597e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 25697e4ba6aSRichard Zhu } 25797e4ba6aSRichard Zhu } 25897e4ba6aSRichard Zhu 2596e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 2606e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 2616e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2626e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 2636e9fd28eSDong Aisheng else 2646e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 2650322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 266888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 267888824bbSDong Aisheng | SDHCI_USE_SDR50_TUNING; 2686e9fd28eSDong Aisheng } 2696e9fd28eSDong Aisheng } 2700322191eSDong Aisheng 2719d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 2720322191eSDong Aisheng val = 0; 2730322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 2740322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 2750322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 2760322191eSDong Aisheng } 2770322191eSDong Aisheng 27897e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 27960bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 28060bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 28197e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 28297e4ba6aSRichard Zhu } 283361b8482SLucas Stach 284361b8482SLucas Stach /* 285361b8482SLucas Stach * mask off the interrupt we get in response to the manually 286361b8482SLucas Stach * sent CMD12 287361b8482SLucas Stach */ 288361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 289361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 290361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 291361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 292361b8482SLucas Stach SDHCI_INT_STATUS); 293361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 294361b8482SLucas Stach } 29597e4ba6aSRichard Zhu } 29697e4ba6aSRichard Zhu 2977e29c306SWolfram Sang return val; 2987e29c306SWolfram Sang } 2997e29c306SWolfram Sang 3007e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 3017e29c306SWolfram Sang { 302e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 303e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 3040d58864bSTony Lin u32 data; 305e149860dSRichard Zhu 3060d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 307b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 3080d58864bSTony Lin /* 3090d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 3100d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 3110d58864bSTony Lin * so we need to apply the following workaround: clear 3120d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 3130d58864bSTony Lin * interrupt. In case a card interrupt was lost, 3140d58864bSTony Lin * re-sample it by the following steps. 3150d58864bSTony Lin */ 3160d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 31760bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 3180d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 31960bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 3200d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 3210d58864bSTony Lin } 322915be485SDong Aisheng 323915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 324915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 325915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 326915be485SDong Aisheng } 3270d58864bSTony Lin } 3280d58864bSTony Lin 329f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 33058ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 33158ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 33258ac8177SRichard Zhu u32 v; 33360bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 33460bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 33560bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 336361b8482SLucas Stach 337361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 338361b8482SLucas Stach { 339361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 340361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 341361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 342361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 343361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 344361b8482SLucas Stach } 34558ac8177SRichard Zhu } 34658ac8177SRichard Zhu 3477e29c306SWolfram Sang writel(val, host->ioaddr + reg); 3487e29c306SWolfram Sang } 3497e29c306SWolfram Sang 35095f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 35195f25efeSWolfram Sang { 352ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 353ef4d0888SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 3540322191eSDong Aisheng u16 ret = 0; 3550322191eSDong Aisheng u32 val; 356ef4d0888SShawn Guo 35795a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 358ef4d0888SShawn Guo reg ^= 2; 3599d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 36095a2482aSShawn Guo /* 361ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 362ef4d0888SShawn Guo * Correct it here. 36395a2482aSShawn Guo */ 364ef4d0888SShawn Guo return SDHCI_SPEC_300; 365ef4d0888SShawn Guo } 36695a2482aSShawn Guo } 36795f25efeSWolfram Sang 3680322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 3690322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 3700322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 3710322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 3720322191eSDong Aisheng 3739d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 3746e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 3750322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 3766e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 3776e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 3786e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 3796e9fd28eSDong Aisheng } 3806e9fd28eSDong Aisheng 3810322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 3820322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 3830322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 3840322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 3850322191eSDong Aisheng 3860322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 3870322191eSDong Aisheng 3880322191eSDong Aisheng return ret; 3890322191eSDong Aisheng } 3900322191eSDong Aisheng 3917dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 3927dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 3937dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 3947dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 3957dd109efSDong Aisheng /* Swap AC23 bit */ 3967dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 3977dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 3987dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 3997dd109efSDong Aisheng } 4007dd109efSDong Aisheng } else { 4017dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 4027dd109efSDong Aisheng } 4037dd109efSDong Aisheng 4047dd109efSDong Aisheng return ret; 4057dd109efSDong Aisheng } 4067dd109efSDong Aisheng 40795f25efeSWolfram Sang return readw(host->ioaddr + reg); 40895f25efeSWolfram Sang } 40995f25efeSWolfram Sang 41095f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 41195f25efeSWolfram Sang { 41295f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 413e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 4140322191eSDong Aisheng u32 new_val = 0; 41595f25efeSWolfram Sang 41695f25efeSWolfram Sang switch (reg) { 4170322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 4180322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4190322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 4200322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4210322191eSDong Aisheng else 4220322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4230322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4240322191eSDong Aisheng return; 4250322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 4260322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4270322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 4280322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 4290322191eSDong Aisheng else 4300322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 4310322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4326e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 4330322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4340322191eSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) 4350322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4360322191eSDong Aisheng else 4370322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4380322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 4396e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 4406e9fd28eSDong Aisheng u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4416e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4428b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4438b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4446e9fd28eSDong Aisheng } else { 4458b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4466e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 4476e9fd28eSDong Aisheng } 4486e9fd28eSDong Aisheng 4498b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 4508b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 4518b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 4528b2bb0adSDong Aisheng } else { 4538b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 4548b2bb0adSDong Aisheng } 4556e9fd28eSDong Aisheng 4566e9fd28eSDong Aisheng writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 4576e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 4586e9fd28eSDong Aisheng } 4590322191eSDong Aisheng return; 46095f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 461f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 46258ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 46358ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 46458ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 46558ac8177SRichard Zhu u32 v; 46660bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 46760bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 46860bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 46958ac8177SRichard Zhu } 47069f54698SShawn Guo 4719d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 47269f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4732a15f981SShawn Guo /* Swap AC23 bit */ 4742a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 4752a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 4762a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 4772a15f981SShawn Guo } 4782a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 47969f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 48069f54698SShawn Guo } else { 48169f54698SShawn Guo /* 48269f54698SShawn Guo * Postpone this write, we must do it together with a 48369f54698SShawn Guo * command write that is down below. 48469f54698SShawn Guo */ 485e149860dSRichard Zhu imx_data->scratchpad = val; 48669f54698SShawn Guo } 48795f25efeSWolfram Sang return; 48895f25efeSWolfram Sang case SDHCI_COMMAND: 489361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 49058ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 49195a2482aSShawn Guo 492361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 493f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 494361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 495361b8482SLucas Stach 4969d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 49795a2482aSShawn Guo writel(val << 16, 49895a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 49969f54698SShawn Guo else 500e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 50195f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 50295f25efeSWolfram Sang return; 50395f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 50495f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 50595f25efeSWolfram Sang break; 50695f25efeSWolfram Sang } 50795f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 50895f25efeSWolfram Sang } 50995f25efeSWolfram Sang 51095f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 51195f25efeSWolfram Sang { 5129a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5139a0985b7SWilson Callan struct pltfm_imx_data *imx_data = pltfm_host->priv; 51495f25efeSWolfram Sang u32 new_val; 515af51079eSSascha Hauer u32 mask; 51695f25efeSWolfram Sang 51795f25efeSWolfram Sang switch (reg) { 51895f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 51995f25efeSWolfram Sang /* 52095f25efeSWolfram Sang * FSL put some DMA bits here 52195f25efeSWolfram Sang * If your board has a regulator, code should be here 52295f25efeSWolfram Sang */ 52395f25efeSWolfram Sang return; 52495f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 5256b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 526af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 5277122bbb0SMasanari Iida /* ensure the endianness */ 52895f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 5299a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 5309a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 53195f25efeSWolfram Sang /* DMA mode bits are shifted */ 53295f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 5339a0985b7SWilson Callan } 53495f25efeSWolfram Sang 535af51079eSSascha Hauer /* 536af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 537af51079eSSascha Hauer * esdhc_pltfm_bus_width. 538f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 539f6825748SMartin Fuzzey * SDIO interrupt errata workaround. 540af51079eSSascha Hauer */ 541f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 542af51079eSSascha Hauer 543af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 54495f25efeSWolfram Sang return; 54595f25efeSWolfram Sang } 54695f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 547913413c3SShawn Guo 548913413c3SShawn Guo /* 549913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 550913413c3SShawn Guo * that software reset should not affect card detection circuit. 551913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 552913413c3SShawn Guo * software reset. This will stop those clocks that card detection 553913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 554913413c3SShawn Guo * to keep card detection circuit functional. 555913413c3SShawn Guo */ 55658c8c4fbSShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 557913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 55858c8c4fbSShawn Guo /* 55958c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 56058c8c4fbSShawn Guo * Do it manually here. 56158c8c4fbSShawn Guo */ 562de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 563d131a71cSDong Aisheng /* the tuning bits should be kept during reset */ 564d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 565d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 566d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 567de5bdbffSDong Aisheng imx_data->is_ddr = 0; 568de5bdbffSDong Aisheng } 56958c8c4fbSShawn Guo } 57095f25efeSWolfram Sang } 57195f25efeSWolfram Sang 5720ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 5730ddf03c9SLucas Stach { 5740ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5750ddf03c9SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 5760ddf03c9SLucas Stach struct esdhc_platform_data *boarddata = &imx_data->boarddata; 5770ddf03c9SLucas Stach 578a974862fSDong Aisheng if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock)) 5790ddf03c9SLucas Stach return boarddata->f_max; 5800ddf03c9SLucas Stach else 581a974862fSDong Aisheng return pltfm_host->clock; 5820ddf03c9SLucas Stach } 5830ddf03c9SLucas Stach 58495f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 58595f25efeSWolfram Sang { 58695f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 58795f25efeSWolfram Sang 588a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 58995f25efeSWolfram Sang } 59095f25efeSWolfram Sang 5918ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 5928ba9580aSLucas Stach unsigned int clock) 5938ba9580aSLucas Stach { 5948ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 595fed2f6e2SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 596a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 597d31fc00aSDong Aisheng int pre_div = 2; 598d31fc00aSDong Aisheng int div = 1; 599fed2f6e2SDong Aisheng u32 temp, val; 6008ba9580aSLucas Stach 601fed2f6e2SDong Aisheng if (clock == 0) { 6021650d0c7SRussell King host->mmc->actual_clock = 0; 6031650d0c7SRussell King 6049d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 605fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 606fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 607fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 608fed2f6e2SDong Aisheng } 609373073efSRussell King return; 610fed2f6e2SDong Aisheng } 611d31fc00aSDong Aisheng 612de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) 6135f7886c5SDong Aisheng pre_div = 1; 6145f7886c5SDong Aisheng 615d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 616d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 617d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 618d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 619d31fc00aSDong Aisheng 620d31fc00aSDong Aisheng while (host_clock / pre_div / 16 > clock && pre_div < 256) 621d31fc00aSDong Aisheng pre_div *= 2; 622d31fc00aSDong Aisheng 623d31fc00aSDong Aisheng while (host_clock / pre_div / div > clock && div < 16) 624d31fc00aSDong Aisheng div++; 625d31fc00aSDong Aisheng 626e76b8559SDong Aisheng host->mmc->actual_clock = host_clock / pre_div / div; 627d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 628e76b8559SDong Aisheng clock, host->mmc->actual_clock); 629d31fc00aSDong Aisheng 630de5bdbffSDong Aisheng if (imx_data->is_ddr) 631de5bdbffSDong Aisheng pre_div >>= 2; 632de5bdbffSDong Aisheng else 633d31fc00aSDong Aisheng pre_div >>= 1; 634d31fc00aSDong Aisheng div--; 635d31fc00aSDong Aisheng 636d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 637d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 638d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 639d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 640d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 641fed2f6e2SDong Aisheng 6429d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 643fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 644fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 645fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 646fed2f6e2SDong Aisheng } 647fed2f6e2SDong Aisheng 648d31fc00aSDong Aisheng mdelay(1); 6498ba9580aSLucas Stach } 6508ba9580aSLucas Stach 651913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 652913413c3SShawn Guo { 653842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 654842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 655842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 656913413c3SShawn Guo 657913413c3SShawn Guo switch (boarddata->wp_type) { 658913413c3SShawn Guo case ESDHC_WP_GPIO: 659fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 660913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 661913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 662913413c3SShawn Guo SDHCI_WRITE_PROTECT); 663913413c3SShawn Guo case ESDHC_WP_NONE: 664913413c3SShawn Guo break; 665913413c3SShawn Guo } 666913413c3SShawn Guo 667913413c3SShawn Guo return -ENOSYS; 668913413c3SShawn Guo } 669913413c3SShawn Guo 6702317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 671af51079eSSascha Hauer { 672af51079eSSascha Hauer u32 ctrl; 673af51079eSSascha Hauer 674af51079eSSascha Hauer switch (width) { 675af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 676af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 677af51079eSSascha Hauer break; 678af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 679af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 680af51079eSSascha Hauer break; 681af51079eSSascha Hauer default: 682af51079eSSascha Hauer ctrl = 0; 683af51079eSSascha Hauer break; 684af51079eSSascha Hauer } 685af51079eSSascha Hauer 686af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 687af51079eSSascha Hauer SDHCI_HOST_CONTROL); 688af51079eSSascha Hauer } 689af51079eSSascha Hauer 6900322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 6910322191eSDong Aisheng { 6920322191eSDong Aisheng u32 reg; 6930322191eSDong Aisheng 6940322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 6950322191eSDong Aisheng mdelay(1); 6960322191eSDong Aisheng 6970322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 6980322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 6990322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 7000322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7010322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 7020322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 7030322191eSDong Aisheng "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 7040322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 7050322191eSDong Aisheng } 7060322191eSDong Aisheng 7070322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 7080322191eSDong Aisheng { 7090322191eSDong Aisheng u32 reg; 7100322191eSDong Aisheng 7110322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7120322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 7130322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7140322191eSDong Aisheng } 7150322191eSDong Aisheng 7160322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 7170322191eSDong Aisheng { 7180322191eSDong Aisheng int min, max, avg, ret; 7190322191eSDong Aisheng 7200322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 7210322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 7220322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 7230322191eSDong Aisheng esdhc_prepare_tuning(host, min); 724d1785326SUlf Hansson if (!mmc_send_tuning(host->mmc)) 7250322191eSDong Aisheng break; 7260322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 7270322191eSDong Aisheng } 7280322191eSDong Aisheng 7290322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 7300322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 7310322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 7320322191eSDong Aisheng esdhc_prepare_tuning(host, max); 733d1785326SUlf Hansson if (mmc_send_tuning(host->mmc)) { 7340322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 7350322191eSDong Aisheng break; 7360322191eSDong Aisheng } 7370322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 7380322191eSDong Aisheng } 7390322191eSDong Aisheng 7400322191eSDong Aisheng /* use average delay to get the best timing */ 7410322191eSDong Aisheng avg = (min + max) / 2; 7420322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 743d1785326SUlf Hansson ret = mmc_send_tuning(host->mmc); 7440322191eSDong Aisheng esdhc_post_tuning(host); 7450322191eSDong Aisheng 7460322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 7470322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 7480322191eSDong Aisheng 7490322191eSDong Aisheng return ret; 7500322191eSDong Aisheng } 7510322191eSDong Aisheng 752ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 753ad93220dSDong Aisheng unsigned int uhs) 754ad93220dSDong Aisheng { 755ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 756ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 757ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 758ad93220dSDong Aisheng 759ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 760ad93220dSDong Aisheng 761ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 762ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 763ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 764ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 765ad93220dSDong Aisheng return -EINVAL; 766ad93220dSDong Aisheng 767ad93220dSDong Aisheng switch (uhs) { 768ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 769ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 770ad93220dSDong Aisheng break; 771ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 772429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 773ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 774ad93220dSDong Aisheng break; 775ad93220dSDong Aisheng default: 776ad93220dSDong Aisheng /* back to default state for other legacy timing */ 777ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 778ad93220dSDong Aisheng } 779ad93220dSDong Aisheng 780ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 781ad93220dSDong Aisheng } 782ad93220dSDong Aisheng 783850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 784ad93220dSDong Aisheng { 785ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 786ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 787602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 788ad93220dSDong Aisheng 789850a29b8SRussell King switch (timing) { 790ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 791ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 792ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 793ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 794429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 795ad93220dSDong Aisheng break; 796ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 79769f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 798de5bdbffSDong Aisheng writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | 799de5bdbffSDong Aisheng ESDHC_MIX_CTRL_DDREN, 800de5bdbffSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 801de5bdbffSDong Aisheng imx_data->is_ddr = 1; 802602519b2SDong Aisheng if (boarddata->delay_line) { 803602519b2SDong Aisheng u32 v; 804602519b2SDong Aisheng v = boarddata->delay_line << 805602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 806602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 807602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 808602519b2SDong Aisheng v <<= 1; 809602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 810602519b2SDong Aisheng } 811ad93220dSDong Aisheng break; 812ad93220dSDong Aisheng } 813ad93220dSDong Aisheng 814850a29b8SRussell King esdhc_change_pinstate(host, timing); 815ad93220dSDong Aisheng } 816ad93220dSDong Aisheng 8170718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 8180718e59aSRussell King { 8190718e59aSRussell King sdhci_reset(host, mask); 8200718e59aSRussell King 8210718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 8220718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 8230718e59aSRussell King } 8240718e59aSRussell King 82510fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 82610fd0ad9SAisheng Dong { 82710fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 82810fd0ad9SAisheng Dong struct pltfm_imx_data *imx_data = pltfm_host->priv; 82910fd0ad9SAisheng Dong 83010fd0ad9SAisheng Dong return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; 83110fd0ad9SAisheng Dong } 83210fd0ad9SAisheng Dong 833e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 834e33eb8e2SAisheng Dong { 835e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 836e33eb8e2SAisheng Dong struct pltfm_imx_data *imx_data = pltfm_host->priv; 837e33eb8e2SAisheng Dong 838e33eb8e2SAisheng Dong /* use maximum timeout counter */ 839e33eb8e2SAisheng Dong sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 840e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 841e33eb8e2SAisheng Dong } 842e33eb8e2SAisheng Dong 8436e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 844e149860dSRichard Zhu .read_l = esdhc_readl_le, 8450c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 846e149860dSRichard Zhu .write_l = esdhc_writel_le, 8470c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 8480c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 8498ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 8500ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 8510c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 85210fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 853913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 854e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 8552317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 856ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 8570718e59aSRussell King .reset = esdhc_reset, 8580c6d49ceSWolfram Sang }; 8590c6d49ceSWolfram Sang 8601db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 86197e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 86297e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 86397e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 86485d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 86585d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 86685d6509dSShawn Guo }; 86785d6509dSShawn Guo 868abfafc2dSShawn Guo #ifdef CONFIG_OF 869c3be1efdSBill Pemberton static int 870abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 87107bf2b54SSascha Hauer struct sdhci_host *host, 872abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 873abfafc2dSShawn Guo { 874abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 875abfafc2dSShawn Guo 876abfafc2dSShawn Guo if (!np) 877abfafc2dSShawn Guo return -ENODEV; 878abfafc2dSShawn Guo 8797f217794SArnd Bergmann if (of_get_property(np, "non-removable", NULL)) 880abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_PERMANENT; 881abfafc2dSShawn Guo 882abfafc2dSShawn Guo if (of_get_property(np, "fsl,cd-controller", NULL)) 883abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_CONTROLLER; 884abfafc2dSShawn Guo 885abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 886abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 887abfafc2dSShawn Guo 888abfafc2dSShawn Guo boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 889abfafc2dSShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 890abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_GPIO; 891abfafc2dSShawn Guo 892abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 893abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 894abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 895abfafc2dSShawn Guo 896af51079eSSascha Hauer of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); 897af51079eSSascha Hauer 8980ddf03c9SLucas Stach of_property_read_u32(np, "max-frequency", &boarddata->f_max); 8990ddf03c9SLucas Stach 900ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 901ad93220dSDong Aisheng boarddata->support_vsel = false; 902ad93220dSDong Aisheng else 903ad93220dSDong Aisheng boarddata->support_vsel = true; 904ad93220dSDong Aisheng 905602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 906602519b2SDong Aisheng boarddata->delay_line = 0; 907602519b2SDong Aisheng 90807bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 90907bf2b54SSascha Hauer 91015064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 91115064119SFabio Estevam return mmc_of_parse(host->mmc); 912abfafc2dSShawn Guo } 913abfafc2dSShawn Guo #else 914abfafc2dSShawn Guo static inline int 915abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 91607bf2b54SSascha Hauer struct sdhci_host *host, 917abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 918abfafc2dSShawn Guo { 919abfafc2dSShawn Guo return -ENODEV; 920abfafc2dSShawn Guo } 921abfafc2dSShawn Guo #endif 922abfafc2dSShawn Guo 923c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 92495f25efeSWolfram Sang { 925abfafc2dSShawn Guo const struct of_device_id *of_id = 926abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 92785d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 92885d6509dSShawn Guo struct sdhci_host *host; 92985d6509dSShawn Guo struct esdhc_platform_data *boarddata; 9300c6d49ceSWolfram Sang int err; 931e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 9327ccddeb0SFabio Estevam bool dt = true; 93395f25efeSWolfram Sang 9340e748234SChristian Daudt host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); 93585d6509dSShawn Guo if (IS_ERR(host)) 93685d6509dSShawn Guo return PTR_ERR(host); 93785d6509dSShawn Guo 93885d6509dSShawn Guo pltfm_host = sdhci_priv(host); 93985d6509dSShawn Guo 940e3af31c6SShawn Guo imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 941abfafc2dSShawn Guo if (!imx_data) { 942abfafc2dSShawn Guo err = -ENOMEM; 943e3af31c6SShawn Guo goto free_sdhci; 944abfafc2dSShawn Guo } 94557ed3314SShawn Guo 946f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 9473770ee8fSShawn Guo pdev->id_entry->driver_data; 94885d6509dSShawn Guo pltfm_host->priv = imx_data; 94985d6509dSShawn Guo 95052dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 95152dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 95252dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 953e3af31c6SShawn Guo goto free_sdhci; 95495f25efeSWolfram Sang } 95552dac615SSascha Hauer 95652dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 95752dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 95852dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 959e3af31c6SShawn Guo goto free_sdhci; 96052dac615SSascha Hauer } 96152dac615SSascha Hauer 96252dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 96352dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 96452dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 965e3af31c6SShawn Guo goto free_sdhci; 96652dac615SSascha Hauer } 96752dac615SSascha Hauer 96852dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 969a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 97052dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 97152dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 97252dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 97395f25efeSWolfram Sang 974ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 975e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 976e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 977e3af31c6SShawn Guo goto disable_clk; 978e62d8b8fSDong Aisheng } 979e62d8b8fSDong Aisheng 980ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 981ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 982cd529af7SDirk Behme if (IS_ERR(imx_data->pins_default)) 983cd529af7SDirk Behme dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 984ad93220dSDong Aisheng 98537865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 98637865fe9SEric Bénard 987f47c4bbfSShawn Guo if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 9880c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 98997e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 99097e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 9910c6d49ceSWolfram Sang 992f750ba9bSShawn Guo /* 993f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 994f750ba9bSShawn Guo * to something insane. Change it back here. 995f750ba9bSShawn Guo */ 99669ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 99760bf6396SShawn Guo writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 99869ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 999e2997c94SDong Aisheng host->mmc->caps |= MMC_CAP_1_8V_DDR; 100018094430SDong Aisheng 100118094430SDong Aisheng /* 100218094430SDong Aisheng * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 100318094430SDong Aisheng * TO1.1, it's harmless for MX6SL 100418094430SDong Aisheng */ 100518094430SDong Aisheng writel(readl(host->ioaddr + 0x6c) | BIT(7), 100618094430SDong Aisheng host->ioaddr + 0x6c); 100769ed60e0SDong Aisheng } 1008f750ba9bSShawn Guo 10096e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 10106e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 10116e9fd28eSDong Aisheng esdhc_executing_tuning; 10128b2bb0adSDong Aisheng 10138b2bb0adSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 10148b2bb0adSDong Aisheng writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | 10158b2bb0adSDong Aisheng ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, 10168b2bb0adSDong Aisheng host->ioaddr + ESDHC_TUNING_CTRL); 10178b2bb0adSDong Aisheng 101818094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 101918094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 102018094430SDong Aisheng 1021abfafc2dSShawn Guo boarddata = &imx_data->boarddata; 102207bf2b54SSascha Hauer if (sdhci_esdhc_imx_probe_dt(pdev, host, boarddata) < 0) { 1023842afc02SShawn Guo if (!host->mmc->parent->platform_data) { 1024913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "no board data!\n"); 1025913413c3SShawn Guo err = -EINVAL; 1026e3af31c6SShawn Guo goto disable_clk; 1027913413c3SShawn Guo } 1028842afc02SShawn Guo imx_data->boarddata = *((struct esdhc_platform_data *) 1029842afc02SShawn Guo host->mmc->parent->platform_data); 10307ccddeb0SFabio Estevam dt = false; 10317ccddeb0SFabio Estevam } 10327ccddeb0SFabio Estevam /* write_protect */ 10337ccddeb0SFabio Estevam if (boarddata->wp_type == ESDHC_WP_GPIO && !dt) { 10347ccddeb0SFabio Estevam err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 10357ccddeb0SFabio Estevam if (err) { 10367ccddeb0SFabio Estevam dev_err(mmc_dev(host->mmc), 10377ccddeb0SFabio Estevam "failed to request write-protect gpio!\n"); 10387ccddeb0SFabio Estevam goto disable_clk; 10397ccddeb0SFabio Estevam } 10407ccddeb0SFabio Estevam host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1041abfafc2dSShawn Guo } 1042913413c3SShawn Guo 1043913413c3SShawn Guo /* card_detect */ 10447ccddeb0SFabio Estevam switch (boarddata->cd_type) { 10457ccddeb0SFabio Estevam case ESDHC_CD_GPIO: 10467ccddeb0SFabio Estevam if (dt) 10477ccddeb0SFabio Estevam break; 10487ccddeb0SFabio Estevam err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 10497ccddeb0SFabio Estevam if (err) { 10507ccddeb0SFabio Estevam dev_err(mmc_dev(host->mmc), 10517ccddeb0SFabio Estevam "failed to request card-detect gpio!\n"); 10527ccddeb0SFabio Estevam goto disable_clk; 10537ccddeb0SFabio Estevam } 10547ccddeb0SFabio Estevam /* fall through */ 10557ccddeb0SFabio Estevam 10567ccddeb0SFabio Estevam case ESDHC_CD_CONTROLLER: 10577ccddeb0SFabio Estevam /* we have a working card_detect back */ 10587e29c306SWolfram Sang host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 10597ccddeb0SFabio Estevam break; 10607ccddeb0SFabio Estevam 10617ccddeb0SFabio Estevam case ESDHC_CD_PERMANENT: 10627ccddeb0SFabio Estevam host->mmc->caps |= MMC_CAP_NONREMOVABLE; 10637ccddeb0SFabio Estevam break; 10647ccddeb0SFabio Estevam 10657ccddeb0SFabio Estevam case ESDHC_CD_NONE: 10667ccddeb0SFabio Estevam break; 10677ccddeb0SFabio Estevam } 10687e29c306SWolfram Sang 1069af51079eSSascha Hauer switch (boarddata->max_bus_width) { 1070af51079eSSascha Hauer case 8: 1071af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 1072af51079eSSascha Hauer break; 1073af51079eSSascha Hauer case 4: 1074af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_4_BIT_DATA; 1075af51079eSSascha Hauer break; 1076af51079eSSascha Hauer case 1: 1077af51079eSSascha Hauer default: 1078af51079eSSascha Hauer host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 1079af51079eSSascha Hauer break; 1080af51079eSSascha Hauer } 1081af51079eSSascha Hauer 1082ad93220dSDong Aisheng /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 1083cd529af7SDirk Behme if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && 1084cd529af7SDirk Behme !IS_ERR(imx_data->pins_default)) { 1085ad93220dSDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1086ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 1087ad93220dSDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1088ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 1089ad93220dSDong Aisheng if (IS_ERR(imx_data->pins_100mhz) || 1090ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) { 1091ad93220dSDong Aisheng dev_warn(mmc_dev(host->mmc), 1092ad93220dSDong Aisheng "could not get ultra high speed state, work on normal mode\n"); 1093ad93220dSDong Aisheng /* fall back to not support uhs by specify no 1.8v quirk */ 1094ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1095ad93220dSDong Aisheng } 1096ad93220dSDong Aisheng } else { 1097ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1098ad93220dSDong Aisheng } 1099ad93220dSDong Aisheng 110085d6509dSShawn Guo err = sdhci_add_host(host); 110185d6509dSShawn Guo if (err) 1102e3af31c6SShawn Guo goto disable_clk; 110385d6509dSShawn Guo 110489d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 110589d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 110689d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 110789d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 110877903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 110989d7e5c1SDong Aisheng 11107e29c306SWolfram Sang return 0; 11117e29c306SWolfram Sang 1112e3af31c6SShawn Guo disable_clk: 111352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 111452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 111552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 1116e3af31c6SShawn Guo free_sdhci: 111785d6509dSShawn Guo sdhci_pltfm_free(pdev); 111885d6509dSShawn Guo return err; 111995f25efeSWolfram Sang } 112095f25efeSWolfram Sang 11216e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 112295f25efeSWolfram Sang { 112385d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 112495f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1125e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 112685d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 112785d6509dSShawn Guo 11280b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 11290b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 11300b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 11310b414368SUlf Hansson 113285d6509dSShawn Guo sdhci_remove_host(host, dead); 11330c6d49ceSWolfram Sang 113452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 113552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 113652dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 113752dac615SSascha Hauer 113885d6509dSShawn Guo sdhci_pltfm_free(pdev); 113985d6509dSShawn Guo 114085d6509dSShawn Guo return 0; 114195f25efeSWolfram Sang } 114295f25efeSWolfram Sang 1143162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 114489d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 114589d7e5c1SDong Aisheng { 114689d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 114789d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 114889d7e5c1SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 114989d7e5c1SDong Aisheng int ret; 115089d7e5c1SDong Aisheng 115189d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 115289d7e5c1SDong Aisheng 1153be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 115489d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 115589d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 1156be138554SRussell King } 115789d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 115889d7e5c1SDong Aisheng 115989d7e5c1SDong Aisheng return ret; 116089d7e5c1SDong Aisheng } 116189d7e5c1SDong Aisheng 116289d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 116389d7e5c1SDong Aisheng { 116489d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 116589d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 116689d7e5c1SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 116789d7e5c1SDong Aisheng 1168be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 116989d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_per); 117089d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ipg); 1171be138554SRussell King } 117289d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ahb); 117389d7e5c1SDong Aisheng 117489d7e5c1SDong Aisheng return sdhci_runtime_resume_host(host); 117589d7e5c1SDong Aisheng } 117689d7e5c1SDong Aisheng #endif 117789d7e5c1SDong Aisheng 117889d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 117989d7e5c1SDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) 118089d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 118189d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 118289d7e5c1SDong Aisheng }; 118389d7e5c1SDong Aisheng 118485d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 118585d6509dSShawn Guo .driver = { 118685d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1187abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 118889d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 118985d6509dSShawn Guo }, 119057ed3314SShawn Guo .id_table = imx_esdhc_devtype, 119185d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 11920433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 119395f25efeSWolfram Sang }; 119485d6509dSShawn Guo 1195d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 119685d6509dSShawn Guo 119785d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1198035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 119985d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1200