195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 7035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3089d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 3195f25efeSWolfram Sang #include "sdhci-pltfm.h" 3295f25efeSWolfram Sang #include "sdhci-esdhc.h" 3395f25efeSWolfram Sang 3460bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 3558ac8177SRichard Zhu /* VENDOR SPEC register */ 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3760bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 380322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 39fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 4060bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 4160bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 42de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 432a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 440322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 450322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 460322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 472a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 482a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 49d131a71cSDong Aisheng /* Tuning bits */ 50d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 5158ac8177SRichard Zhu 52602519b2SDong Aisheng /* dll control register */ 53602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 54602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 55602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 56602519b2SDong Aisheng 570322191eSDong Aisheng /* tune control register */ 580322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 590322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 600322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 610322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 620322191eSDong Aisheng 636e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 646e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 656e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 666e9fd28eSDong Aisheng #define ESDHC_TUNING_START_TAP 0x1 676e9fd28eSDong Aisheng 68ad93220dSDong Aisheng /* pinctrl state */ 69ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 70ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 71ad93220dSDong Aisheng 7258ac8177SRichard Zhu /* 73af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 74af51079eSSascha Hauer */ 75af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 76af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 77af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 78af51079eSSascha Hauer 79af51079eSSascha Hauer /* 8097e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 8197e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 8297e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 8397e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 8497e4ba6aSRichard Zhu */ 8560bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 8697e4ba6aSRichard Zhu 8797e4ba6aSRichard Zhu /* 8858ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 8958ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 9058ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 9158ac8177SRichard Zhu * be generated. 9258ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 9358ac8177SRichard Zhu * operations automatically as required at the end of the 9458ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 9558ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 9658ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 9758ac8177SRichard Zhu */ 9831fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 9931fbb301SShawn Guo /* 10031fbb301SShawn Guo * The flag enables the workaround for ESDHC errata ENGcm07207 which 10131fbb301SShawn Guo * affects i.MX25 and i.MX35. 10231fbb301SShawn Guo */ 10331fbb301SShawn Guo #define ESDHC_FLAG_ENGCM07207 BIT(2) 1049d61c009SShawn Guo /* 1059d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1069d61c009SShawn Guo * integrated on the i.MX6 series. 1079d61c009SShawn Guo */ 1089d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1096e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1106e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1116e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1126e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1136e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1146e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 115e149860dSRichard Zhu 116f47c4bbfSShawn Guo struct esdhc_soc_data { 117f47c4bbfSShawn Guo u32 flags; 118f47c4bbfSShawn Guo }; 119f47c4bbfSShawn Guo 120f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx25_data = { 121f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 122f47c4bbfSShawn Guo }; 123f47c4bbfSShawn Guo 124f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx35_data = { 125f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 126f47c4bbfSShawn Guo }; 127f47c4bbfSShawn Guo 128f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx51_data = { 129f47c4bbfSShawn Guo .flags = 0, 130f47c4bbfSShawn Guo }; 131f47c4bbfSShawn Guo 132f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx53_data = { 133f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 134f47c4bbfSShawn Guo }; 135f47c4bbfSShawn Guo 136f47c4bbfSShawn Guo static struct esdhc_soc_data usdhc_imx6q_data = { 1376e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1386e9fd28eSDong Aisheng }; 1396e9fd28eSDong Aisheng 1406e9fd28eSDong Aisheng static struct esdhc_soc_data usdhc_imx6sl_data = { 1416e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1426e9fd28eSDong Aisheng | ESDHC_FLAG_HAVE_CAP1, 14357ed3314SShawn Guo }; 14457ed3314SShawn Guo 145e149860dSRichard Zhu struct pltfm_imx_data { 146e149860dSRichard Zhu u32 scratchpad; 147e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 148ad93220dSDong Aisheng struct pinctrl_state *pins_default; 149ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 150ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 151f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 152842afc02SShawn Guo struct esdhc_platform_data boarddata; 15352dac615SSascha Hauer struct clk *clk_ipg; 15452dac615SSascha Hauer struct clk *clk_ahb; 15552dac615SSascha Hauer struct clk *clk_per; 156361b8482SLucas Stach enum { 157361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending*/ 158361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 159361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 160361b8482SLucas Stach } multiblock_status; 161de5bdbffSDong Aisheng u32 is_ddr; 162e149860dSRichard Zhu }; 163e149860dSRichard Zhu 164f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 16557ed3314SShawn Guo { 16657ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 167f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 16857ed3314SShawn Guo }, { 16957ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 170f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 17157ed3314SShawn Guo }, { 17257ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 173f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 17457ed3314SShawn Guo }, { 17557ed3314SShawn Guo /* sentinel */ 17657ed3314SShawn Guo } 17757ed3314SShawn Guo }; 17857ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 17957ed3314SShawn Guo 180abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 181f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 182f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 183f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 184f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 1856e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 186f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 187abfafc2dSShawn Guo { /* sentinel */ } 188abfafc2dSShawn Guo }; 189abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 190abfafc2dSShawn Guo 19157ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 19257ed3314SShawn Guo { 193f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 19457ed3314SShawn Guo } 19557ed3314SShawn Guo 19657ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 19757ed3314SShawn Guo { 198f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 19957ed3314SShawn Guo } 20057ed3314SShawn Guo 20195a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 20295a2482aSShawn Guo { 203f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 20495a2482aSShawn Guo } 20595a2482aSShawn Guo 2069d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2079d61c009SShawn Guo { 208f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2099d61c009SShawn Guo } 2109d61c009SShawn Guo 21195f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 21295f25efeSWolfram Sang { 21395f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 21495f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 21595f25efeSWolfram Sang 21695f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 21795f25efeSWolfram Sang } 21895f25efeSWolfram Sang 2197e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 2207e29c306SWolfram Sang { 221361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 222361b8482SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 223913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 224913413c3SShawn Guo 2250322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 2260322191eSDong Aisheng u32 fsl_prss = val; 2270322191eSDong Aisheng /* save the least 20 bits */ 2280322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 2290322191eSDong Aisheng /* move dat[0-3] bits */ 2300322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 2310322191eSDong Aisheng /* move cmd line bit */ 2320322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 2330322191eSDong Aisheng } 2340322191eSDong Aisheng 23597e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 2366b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 2376b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2386b4fb671SDong Aisheng val &= 0xffff0000; 2396b4fb671SDong Aisheng 24097e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 24197e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 24297e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 24397e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 24497e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 24597e4ba6aSRichard Zhu */ 24697e4ba6aSRichard Zhu 24797e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 24897e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 24997e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 25097e4ba6aSRichard Zhu } 25197e4ba6aSRichard Zhu } 25297e4ba6aSRichard Zhu 2536e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 2546e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 2556e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2566e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 2576e9fd28eSDong Aisheng else 2586e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 2590322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 260888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 261888824bbSDong Aisheng | SDHCI_USE_SDR50_TUNING; 2626e9fd28eSDong Aisheng } 2636e9fd28eSDong Aisheng } 2640322191eSDong Aisheng 2659d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 2660322191eSDong Aisheng val = 0; 2670322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 2680322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 2690322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 2700322191eSDong Aisheng } 2710322191eSDong Aisheng 27297e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 27360bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 27460bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 27597e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 27697e4ba6aSRichard Zhu } 277361b8482SLucas Stach 278361b8482SLucas Stach /* 279361b8482SLucas Stach * mask off the interrupt we get in response to the manually 280361b8482SLucas Stach * sent CMD12 281361b8482SLucas Stach */ 282361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 283361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 284361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 285361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 286361b8482SLucas Stach SDHCI_INT_STATUS); 287361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 288361b8482SLucas Stach } 28997e4ba6aSRichard Zhu } 29097e4ba6aSRichard Zhu 2917e29c306SWolfram Sang return val; 2927e29c306SWolfram Sang } 2937e29c306SWolfram Sang 2947e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 2957e29c306SWolfram Sang { 296e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 297e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 2980d58864bSTony Lin u32 data; 299e149860dSRichard Zhu 3000d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 3010d58864bSTony Lin if (val & SDHCI_INT_CARD_INT) { 3020d58864bSTony Lin /* 3030d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 3040d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 3050d58864bSTony Lin * so we need to apply the following workaround: clear 3060d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 3070d58864bSTony Lin * interrupt. In case a card interrupt was lost, 3080d58864bSTony Lin * re-sample it by the following steps. 3090d58864bSTony Lin */ 3100d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 31160bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 3120d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 31360bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 3140d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 3150d58864bSTony Lin } 3160d58864bSTony Lin } 3170d58864bSTony Lin 318f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 31958ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 32058ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 32158ac8177SRichard Zhu u32 v; 32260bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 32360bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 32460bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 325361b8482SLucas Stach 326361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 327361b8482SLucas Stach { 328361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 329361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 330361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 331361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 332361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 333361b8482SLucas Stach } 33458ac8177SRichard Zhu } 33558ac8177SRichard Zhu 33697e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 33797e4ba6aSRichard Zhu if (val & SDHCI_INT_ADMA_ERROR) { 33897e4ba6aSRichard Zhu val &= ~SDHCI_INT_ADMA_ERROR; 33960bf6396SShawn Guo val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 34097e4ba6aSRichard Zhu } 34197e4ba6aSRichard Zhu } 34297e4ba6aSRichard Zhu 3437e29c306SWolfram Sang writel(val, host->ioaddr + reg); 3447e29c306SWolfram Sang } 3457e29c306SWolfram Sang 34695f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 34795f25efeSWolfram Sang { 348ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 349ef4d0888SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 3500322191eSDong Aisheng u16 ret = 0; 3510322191eSDong Aisheng u32 val; 352ef4d0888SShawn Guo 35395a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 354ef4d0888SShawn Guo reg ^= 2; 3559d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 35695a2482aSShawn Guo /* 357ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 358ef4d0888SShawn Guo * Correct it here. 35995a2482aSShawn Guo */ 360ef4d0888SShawn Guo return SDHCI_SPEC_300; 361ef4d0888SShawn Guo } 36295a2482aSShawn Guo } 36395f25efeSWolfram Sang 3640322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 3650322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 3660322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 3670322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 3680322191eSDong Aisheng 3699d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 3706e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 3710322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 3726e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 3736e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 3746e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 3756e9fd28eSDong Aisheng } 3766e9fd28eSDong Aisheng 3770322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 3780322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 3790322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 3800322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 3810322191eSDong Aisheng 3820322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 3830322191eSDong Aisheng 3840322191eSDong Aisheng return ret; 3850322191eSDong Aisheng } 3860322191eSDong Aisheng 3877dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 3887dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 3897dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 3907dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 3917dd109efSDong Aisheng /* Swap AC23 bit */ 3927dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 3937dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 3947dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 3957dd109efSDong Aisheng } 3967dd109efSDong Aisheng } else { 3977dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 3987dd109efSDong Aisheng } 3997dd109efSDong Aisheng 4007dd109efSDong Aisheng return ret; 4017dd109efSDong Aisheng } 4027dd109efSDong Aisheng 40395f25efeSWolfram Sang return readw(host->ioaddr + reg); 40495f25efeSWolfram Sang } 40595f25efeSWolfram Sang 40695f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 40795f25efeSWolfram Sang { 40895f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 409e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 4100322191eSDong Aisheng u32 new_val = 0; 41195f25efeSWolfram Sang 41295f25efeSWolfram Sang switch (reg) { 4130322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 4140322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4150322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 4160322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4170322191eSDong Aisheng else 4180322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4190322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4200322191eSDong Aisheng return; 4210322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 4220322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4230322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 4240322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 4250322191eSDong Aisheng else 4260322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 4270322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4286e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 4290322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4300322191eSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) 4310322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4320322191eSDong Aisheng else 4330322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4340322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 4356e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 4366e9fd28eSDong Aisheng u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4376e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4388b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4398b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4406e9fd28eSDong Aisheng } else { 4418b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4426e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 4436e9fd28eSDong Aisheng } 4446e9fd28eSDong Aisheng 4458b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 4468b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 4478b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 4488b2bb0adSDong Aisheng } else { 4498b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 4508b2bb0adSDong Aisheng } 4516e9fd28eSDong Aisheng 4526e9fd28eSDong Aisheng writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 4536e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 4546e9fd28eSDong Aisheng } 4550322191eSDong Aisheng return; 45695f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 457f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 45858ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 45958ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 46058ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 46158ac8177SRichard Zhu u32 v; 46260bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 46360bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 46460bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 46558ac8177SRichard Zhu } 46669f54698SShawn Guo 4679d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 46869f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4692a15f981SShawn Guo /* Swap AC23 bit */ 4702a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 4712a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 4722a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 4732a15f981SShawn Guo } 4742a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 47569f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 47669f54698SShawn Guo } else { 47769f54698SShawn Guo /* 47869f54698SShawn Guo * Postpone this write, we must do it together with a 47969f54698SShawn Guo * command write that is down below. 48069f54698SShawn Guo */ 481e149860dSRichard Zhu imx_data->scratchpad = val; 48269f54698SShawn Guo } 48395f25efeSWolfram Sang return; 48495f25efeSWolfram Sang case SDHCI_COMMAND: 485361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 48658ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 48795a2482aSShawn Guo 488361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 489f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 490361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 491361b8482SLucas Stach 4929d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 49395a2482aSShawn Guo writel(val << 16, 49495a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 49569f54698SShawn Guo else 496e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 49795f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 49895f25efeSWolfram Sang return; 49995f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 50095f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 50195f25efeSWolfram Sang break; 50295f25efeSWolfram Sang } 50395f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 50495f25efeSWolfram Sang } 50595f25efeSWolfram Sang 50695f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 50795f25efeSWolfram Sang { 5089a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5099a0985b7SWilson Callan struct pltfm_imx_data *imx_data = pltfm_host->priv; 51095f25efeSWolfram Sang u32 new_val; 511af51079eSSascha Hauer u32 mask; 51295f25efeSWolfram Sang 51395f25efeSWolfram Sang switch (reg) { 51495f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 51595f25efeSWolfram Sang /* 51695f25efeSWolfram Sang * FSL put some DMA bits here 51795f25efeSWolfram Sang * If your board has a regulator, code should be here 51895f25efeSWolfram Sang */ 51995f25efeSWolfram Sang return; 52095f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 5216b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 522af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 5237122bbb0SMasanari Iida /* ensure the endianness */ 52495f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 5259a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 5269a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 52795f25efeSWolfram Sang /* DMA mode bits are shifted */ 52895f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 5299a0985b7SWilson Callan } 53095f25efeSWolfram Sang 531af51079eSSascha Hauer /* 532af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 533af51079eSSascha Hauer * esdhc_pltfm_bus_width. 534f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 535f6825748SMartin Fuzzey * SDIO interrupt errata workaround. 536af51079eSSascha Hauer */ 537f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 538af51079eSSascha Hauer 539af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 54095f25efeSWolfram Sang return; 54195f25efeSWolfram Sang } 54295f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 543913413c3SShawn Guo 544913413c3SShawn Guo /* 545913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 546913413c3SShawn Guo * that software reset should not affect card detection circuit. 547913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 548913413c3SShawn Guo * software reset. This will stop those clocks that card detection 549913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 550913413c3SShawn Guo * to keep card detection circuit functional. 551913413c3SShawn Guo */ 55258c8c4fbSShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 553913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 55458c8c4fbSShawn Guo /* 55558c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 55658c8c4fbSShawn Guo * Do it manually here. 55758c8c4fbSShawn Guo */ 558de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 559d131a71cSDong Aisheng /* the tuning bits should be kept during reset */ 560d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 561d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 562d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 563de5bdbffSDong Aisheng imx_data->is_ddr = 0; 564de5bdbffSDong Aisheng } 56558c8c4fbSShawn Guo } 56695f25efeSWolfram Sang } 56795f25efeSWolfram Sang 5680ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 5690ddf03c9SLucas Stach { 5700ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5710ddf03c9SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 5720ddf03c9SLucas Stach struct esdhc_platform_data *boarddata = &imx_data->boarddata; 5730ddf03c9SLucas Stach 574a974862fSDong Aisheng if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock)) 5750ddf03c9SLucas Stach return boarddata->f_max; 5760ddf03c9SLucas Stach else 577a974862fSDong Aisheng return pltfm_host->clock; 5780ddf03c9SLucas Stach } 5790ddf03c9SLucas Stach 58095f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 58195f25efeSWolfram Sang { 58295f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 58395f25efeSWolfram Sang 584a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 58595f25efeSWolfram Sang } 58695f25efeSWolfram Sang 5878ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 5888ba9580aSLucas Stach unsigned int clock) 5898ba9580aSLucas Stach { 5908ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 591fed2f6e2SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 592a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 593d31fc00aSDong Aisheng int pre_div = 2; 594d31fc00aSDong Aisheng int div = 1; 595fed2f6e2SDong Aisheng u32 temp, val; 5968ba9580aSLucas Stach 597fed2f6e2SDong Aisheng if (clock == 0) { 5981650d0c7SRussell King host->mmc->actual_clock = 0; 5991650d0c7SRussell King 6009d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 601fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 602fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 603fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 604fed2f6e2SDong Aisheng } 605373073efSRussell King return; 606fed2f6e2SDong Aisheng } 607d31fc00aSDong Aisheng 608de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) 6095f7886c5SDong Aisheng pre_div = 1; 6105f7886c5SDong Aisheng 611d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 612d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 613d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 614d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 615d31fc00aSDong Aisheng 616d31fc00aSDong Aisheng while (host_clock / pre_div / 16 > clock && pre_div < 256) 617d31fc00aSDong Aisheng pre_div *= 2; 618d31fc00aSDong Aisheng 619d31fc00aSDong Aisheng while (host_clock / pre_div / div > clock && div < 16) 620d31fc00aSDong Aisheng div++; 621d31fc00aSDong Aisheng 622e76b8559SDong Aisheng host->mmc->actual_clock = host_clock / pre_div / div; 623d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 624e76b8559SDong Aisheng clock, host->mmc->actual_clock); 625d31fc00aSDong Aisheng 626de5bdbffSDong Aisheng if (imx_data->is_ddr) 627de5bdbffSDong Aisheng pre_div >>= 2; 628de5bdbffSDong Aisheng else 629d31fc00aSDong Aisheng pre_div >>= 1; 630d31fc00aSDong Aisheng div--; 631d31fc00aSDong Aisheng 632d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 633d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 634d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 635d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 636d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 637fed2f6e2SDong Aisheng 6389d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 639fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 640fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 641fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 642fed2f6e2SDong Aisheng } 643fed2f6e2SDong Aisheng 644d31fc00aSDong Aisheng mdelay(1); 6458ba9580aSLucas Stach } 6468ba9580aSLucas Stach 647913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 648913413c3SShawn Guo { 649842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 650842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 651842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 652913413c3SShawn Guo 653913413c3SShawn Guo switch (boarddata->wp_type) { 654913413c3SShawn Guo case ESDHC_WP_GPIO: 655fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 656913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 657913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 658913413c3SShawn Guo SDHCI_WRITE_PROTECT); 659913413c3SShawn Guo case ESDHC_WP_NONE: 660913413c3SShawn Guo break; 661913413c3SShawn Guo } 662913413c3SShawn Guo 663913413c3SShawn Guo return -ENOSYS; 664913413c3SShawn Guo } 665913413c3SShawn Guo 6662317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 667af51079eSSascha Hauer { 668af51079eSSascha Hauer u32 ctrl; 669af51079eSSascha Hauer 670af51079eSSascha Hauer switch (width) { 671af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 672af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 673af51079eSSascha Hauer break; 674af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 675af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 676af51079eSSascha Hauer break; 677af51079eSSascha Hauer default: 678af51079eSSascha Hauer ctrl = 0; 679af51079eSSascha Hauer break; 680af51079eSSascha Hauer } 681af51079eSSascha Hauer 682af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 683af51079eSSascha Hauer SDHCI_HOST_CONTROL); 684af51079eSSascha Hauer } 685af51079eSSascha Hauer 6860322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 6870322191eSDong Aisheng { 6880322191eSDong Aisheng u32 reg; 6890322191eSDong Aisheng 6900322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 6910322191eSDong Aisheng mdelay(1); 6920322191eSDong Aisheng 6930322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 6940322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 6950322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 6960322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 6970322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 6980322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 6990322191eSDong Aisheng "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 7000322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 7010322191eSDong Aisheng } 7020322191eSDong Aisheng 7030322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 7040322191eSDong Aisheng { 7050322191eSDong Aisheng u32 reg; 7060322191eSDong Aisheng 7070322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7080322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 7090322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7100322191eSDong Aisheng } 7110322191eSDong Aisheng 7120322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 7130322191eSDong Aisheng { 7140322191eSDong Aisheng int min, max, avg, ret; 7150322191eSDong Aisheng 7160322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 7170322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 7180322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 7190322191eSDong Aisheng esdhc_prepare_tuning(host, min); 720d1785326SUlf Hansson if (!mmc_send_tuning(host->mmc)) 7210322191eSDong Aisheng break; 7220322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 7230322191eSDong Aisheng } 7240322191eSDong Aisheng 7250322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 7260322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 7270322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 7280322191eSDong Aisheng esdhc_prepare_tuning(host, max); 729d1785326SUlf Hansson if (mmc_send_tuning(host->mmc)) { 7300322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 7310322191eSDong Aisheng break; 7320322191eSDong Aisheng } 7330322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 7340322191eSDong Aisheng } 7350322191eSDong Aisheng 7360322191eSDong Aisheng /* use average delay to get the best timing */ 7370322191eSDong Aisheng avg = (min + max) / 2; 7380322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 739d1785326SUlf Hansson ret = mmc_send_tuning(host->mmc); 7400322191eSDong Aisheng esdhc_post_tuning(host); 7410322191eSDong Aisheng 7420322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 7430322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 7440322191eSDong Aisheng 7450322191eSDong Aisheng return ret; 7460322191eSDong Aisheng } 7470322191eSDong Aisheng 748ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 749ad93220dSDong Aisheng unsigned int uhs) 750ad93220dSDong Aisheng { 751ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 752ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 753ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 754ad93220dSDong Aisheng 755ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 756ad93220dSDong Aisheng 757ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 758ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 759ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 760ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 761ad93220dSDong Aisheng return -EINVAL; 762ad93220dSDong Aisheng 763ad93220dSDong Aisheng switch (uhs) { 764ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 765ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 766ad93220dSDong Aisheng break; 767ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 768429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 769ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 770ad93220dSDong Aisheng break; 771ad93220dSDong Aisheng default: 772ad93220dSDong Aisheng /* back to default state for other legacy timing */ 773ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 774ad93220dSDong Aisheng } 775ad93220dSDong Aisheng 776ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 777ad93220dSDong Aisheng } 778ad93220dSDong Aisheng 779850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 780ad93220dSDong Aisheng { 781ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 782ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 783602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 784ad93220dSDong Aisheng 785850a29b8SRussell King switch (timing) { 786ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 787ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 788ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 789ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 790429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 791ad93220dSDong Aisheng break; 792ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 79369f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 794de5bdbffSDong Aisheng writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | 795de5bdbffSDong Aisheng ESDHC_MIX_CTRL_DDREN, 796de5bdbffSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 797de5bdbffSDong Aisheng imx_data->is_ddr = 1; 798602519b2SDong Aisheng if (boarddata->delay_line) { 799602519b2SDong Aisheng u32 v; 800602519b2SDong Aisheng v = boarddata->delay_line << 801602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 802602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 803602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 804602519b2SDong Aisheng v <<= 1; 805602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 806602519b2SDong Aisheng } 807ad93220dSDong Aisheng break; 808ad93220dSDong Aisheng } 809ad93220dSDong Aisheng 810850a29b8SRussell King esdhc_change_pinstate(host, timing); 811ad93220dSDong Aisheng } 812ad93220dSDong Aisheng 8130718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 8140718e59aSRussell King { 8150718e59aSRussell King sdhci_reset(host, mask); 8160718e59aSRussell King 8170718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 8180718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 8190718e59aSRussell King } 8200718e59aSRussell King 82110fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 82210fd0ad9SAisheng Dong { 82310fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 82410fd0ad9SAisheng Dong struct pltfm_imx_data *imx_data = pltfm_host->priv; 82510fd0ad9SAisheng Dong 82610fd0ad9SAisheng Dong return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; 82710fd0ad9SAisheng Dong } 82810fd0ad9SAisheng Dong 829e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 830e33eb8e2SAisheng Dong { 831e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 832e33eb8e2SAisheng Dong struct pltfm_imx_data *imx_data = pltfm_host->priv; 833e33eb8e2SAisheng Dong 834e33eb8e2SAisheng Dong /* use maximum timeout counter */ 835e33eb8e2SAisheng Dong sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 836e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 837e33eb8e2SAisheng Dong } 838e33eb8e2SAisheng Dong 8396e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 840e149860dSRichard Zhu .read_l = esdhc_readl_le, 8410c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 842e149860dSRichard Zhu .write_l = esdhc_writel_le, 8430c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 8440c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 8458ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 8460ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 8470c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 84810fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 849913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 850e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 8512317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 852ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 8530718e59aSRussell King .reset = esdhc_reset, 8540c6d49ceSWolfram Sang }; 8550c6d49ceSWolfram Sang 8561db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 85797e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 85897e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 85997e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 86085d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 86185d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 86285d6509dSShawn Guo }; 86385d6509dSShawn Guo 864abfafc2dSShawn Guo #ifdef CONFIG_OF 865c3be1efdSBill Pemberton static int 866abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 86707bf2b54SSascha Hauer struct sdhci_host *host, 868abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 869abfafc2dSShawn Guo { 870abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 871abfafc2dSShawn Guo 872abfafc2dSShawn Guo if (!np) 873abfafc2dSShawn Guo return -ENODEV; 874abfafc2dSShawn Guo 8757f217794SArnd Bergmann if (of_get_property(np, "non-removable", NULL)) 876abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_PERMANENT; 877abfafc2dSShawn Guo 878abfafc2dSShawn Guo if (of_get_property(np, "fsl,cd-controller", NULL)) 879abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_CONTROLLER; 880abfafc2dSShawn Guo 881abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 882abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 883abfafc2dSShawn Guo 884abfafc2dSShawn Guo boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 885abfafc2dSShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 886abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_GPIO; 887abfafc2dSShawn Guo 888abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 889abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 890abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 891abfafc2dSShawn Guo 892af51079eSSascha Hauer of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); 893af51079eSSascha Hauer 8940ddf03c9SLucas Stach of_property_read_u32(np, "max-frequency", &boarddata->f_max); 8950ddf03c9SLucas Stach 896ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 897ad93220dSDong Aisheng boarddata->support_vsel = false; 898ad93220dSDong Aisheng else 899ad93220dSDong Aisheng boarddata->support_vsel = true; 900ad93220dSDong Aisheng 901602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 902602519b2SDong Aisheng boarddata->delay_line = 0; 903602519b2SDong Aisheng 90407bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 90507bf2b54SSascha Hauer 90615064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 90715064119SFabio Estevam return mmc_of_parse(host->mmc); 908abfafc2dSShawn Guo } 909abfafc2dSShawn Guo #else 910abfafc2dSShawn Guo static inline int 911abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 91207bf2b54SSascha Hauer struct sdhci_host *host, 913abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 914abfafc2dSShawn Guo { 915abfafc2dSShawn Guo return -ENODEV; 916abfafc2dSShawn Guo } 917abfafc2dSShawn Guo #endif 918abfafc2dSShawn Guo 919c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 92095f25efeSWolfram Sang { 921abfafc2dSShawn Guo const struct of_device_id *of_id = 922abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 92385d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 92485d6509dSShawn Guo struct sdhci_host *host; 92585d6509dSShawn Guo struct esdhc_platform_data *boarddata; 9260c6d49ceSWolfram Sang int err; 927e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 92895f25efeSWolfram Sang 9290e748234SChristian Daudt host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); 93085d6509dSShawn Guo if (IS_ERR(host)) 93185d6509dSShawn Guo return PTR_ERR(host); 93285d6509dSShawn Guo 93385d6509dSShawn Guo pltfm_host = sdhci_priv(host); 93485d6509dSShawn Guo 935e3af31c6SShawn Guo imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 936abfafc2dSShawn Guo if (!imx_data) { 937abfafc2dSShawn Guo err = -ENOMEM; 938e3af31c6SShawn Guo goto free_sdhci; 939abfafc2dSShawn Guo } 94057ed3314SShawn Guo 941f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 9423770ee8fSShawn Guo pdev->id_entry->driver_data; 94385d6509dSShawn Guo pltfm_host->priv = imx_data; 94485d6509dSShawn Guo 94552dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 94652dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 94752dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 948e3af31c6SShawn Guo goto free_sdhci; 94995f25efeSWolfram Sang } 95052dac615SSascha Hauer 95152dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 95252dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 95352dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 954e3af31c6SShawn Guo goto free_sdhci; 95552dac615SSascha Hauer } 95652dac615SSascha Hauer 95752dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 95852dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 95952dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 960e3af31c6SShawn Guo goto free_sdhci; 96152dac615SSascha Hauer } 96252dac615SSascha Hauer 96352dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 964a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 96552dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 96652dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 96752dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 96895f25efeSWolfram Sang 969ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 970e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 971e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 972e3af31c6SShawn Guo goto disable_clk; 973e62d8b8fSDong Aisheng } 974e62d8b8fSDong Aisheng 975ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 976ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 977cd529af7SDirk Behme if (IS_ERR(imx_data->pins_default)) 978cd529af7SDirk Behme dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 979ad93220dSDong Aisheng 98037865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 98137865fe9SEric Bénard 982f47c4bbfSShawn Guo if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 9830c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 98497e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 98597e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 9860c6d49ceSWolfram Sang 987f750ba9bSShawn Guo /* 988f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 989f750ba9bSShawn Guo * to something insane. Change it back here. 990f750ba9bSShawn Guo */ 99169ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 99260bf6396SShawn Guo writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 99369ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 994e2997c94SDong Aisheng host->mmc->caps |= MMC_CAP_1_8V_DDR; 99569ed60e0SDong Aisheng } 996f750ba9bSShawn Guo 9976e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 9986e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 9996e9fd28eSDong Aisheng esdhc_executing_tuning; 10008b2bb0adSDong Aisheng 10018b2bb0adSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 10028b2bb0adSDong Aisheng writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | 10038b2bb0adSDong Aisheng ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, 10048b2bb0adSDong Aisheng host->ioaddr + ESDHC_TUNING_CTRL); 10058b2bb0adSDong Aisheng 1006abfafc2dSShawn Guo boarddata = &imx_data->boarddata; 100707bf2b54SSascha Hauer if (sdhci_esdhc_imx_probe_dt(pdev, host, boarddata) < 0) { 1008842afc02SShawn Guo if (!host->mmc->parent->platform_data) { 1009913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "no board data!\n"); 1010913413c3SShawn Guo err = -EINVAL; 1011e3af31c6SShawn Guo goto disable_clk; 1012913413c3SShawn Guo } 1013842afc02SShawn Guo imx_data->boarddata = *((struct esdhc_platform_data *) 1014842afc02SShawn Guo host->mmc->parent->platform_data); 1015abfafc2dSShawn Guo } 1016913413c3SShawn Guo 1017913413c3SShawn Guo /* card_detect */ 10188d86e4fcSFabio Estevam if (boarddata->cd_type == ESDHC_CD_CONTROLLER) 10197e29c306SWolfram Sang host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 10207e29c306SWolfram Sang 1021af51079eSSascha Hauer switch (boarddata->max_bus_width) { 1022af51079eSSascha Hauer case 8: 1023af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 1024af51079eSSascha Hauer break; 1025af51079eSSascha Hauer case 4: 1026af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_4_BIT_DATA; 1027af51079eSSascha Hauer break; 1028af51079eSSascha Hauer case 1: 1029af51079eSSascha Hauer default: 1030af51079eSSascha Hauer host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 1031af51079eSSascha Hauer break; 1032af51079eSSascha Hauer } 1033af51079eSSascha Hauer 1034ad93220dSDong Aisheng /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 1035cd529af7SDirk Behme if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && 1036cd529af7SDirk Behme !IS_ERR(imx_data->pins_default)) { 1037ad93220dSDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1038ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 1039ad93220dSDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1040ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 1041ad93220dSDong Aisheng if (IS_ERR(imx_data->pins_100mhz) || 1042ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) { 1043ad93220dSDong Aisheng dev_warn(mmc_dev(host->mmc), 1044ad93220dSDong Aisheng "could not get ultra high speed state, work on normal mode\n"); 1045ad93220dSDong Aisheng /* fall back to not support uhs by specify no 1.8v quirk */ 1046ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1047ad93220dSDong Aisheng } 1048ad93220dSDong Aisheng } else { 1049ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1050ad93220dSDong Aisheng } 1051ad93220dSDong Aisheng 105285d6509dSShawn Guo err = sdhci_add_host(host); 105385d6509dSShawn Guo if (err) 1054e3af31c6SShawn Guo goto disable_clk; 105585d6509dSShawn Guo 105689d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 105789d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 105889d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 105989d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 106077903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 106189d7e5c1SDong Aisheng 10627e29c306SWolfram Sang return 0; 10637e29c306SWolfram Sang 1064e3af31c6SShawn Guo disable_clk: 106552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 106652dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 106752dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 1068e3af31c6SShawn Guo free_sdhci: 106985d6509dSShawn Guo sdhci_pltfm_free(pdev); 107085d6509dSShawn Guo return err; 107195f25efeSWolfram Sang } 107295f25efeSWolfram Sang 10736e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 107495f25efeSWolfram Sang { 107585d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 107695f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1077e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 107885d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 107985d6509dSShawn Guo 10800b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 10810b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 10820b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 10830b414368SUlf Hansson 108485d6509dSShawn Guo sdhci_remove_host(host, dead); 10850c6d49ceSWolfram Sang 108652dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 108752dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 108852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 108952dac615SSascha Hauer 109085d6509dSShawn Guo sdhci_pltfm_free(pdev); 109185d6509dSShawn Guo 109285d6509dSShawn Guo return 0; 109395f25efeSWolfram Sang } 109495f25efeSWolfram Sang 1095162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 109689d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 109789d7e5c1SDong Aisheng { 109889d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 109989d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 110089d7e5c1SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 110189d7e5c1SDong Aisheng int ret; 110289d7e5c1SDong Aisheng 110389d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 110489d7e5c1SDong Aisheng 1105be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 110689d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 110789d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 1108be138554SRussell King } 110989d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 111089d7e5c1SDong Aisheng 111189d7e5c1SDong Aisheng return ret; 111289d7e5c1SDong Aisheng } 111389d7e5c1SDong Aisheng 111489d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 111589d7e5c1SDong Aisheng { 111689d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 111789d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 111889d7e5c1SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 111989d7e5c1SDong Aisheng 1120be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 112189d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_per); 112289d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ipg); 1123be138554SRussell King } 112489d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ahb); 112589d7e5c1SDong Aisheng 112689d7e5c1SDong Aisheng return sdhci_runtime_resume_host(host); 112789d7e5c1SDong Aisheng } 112889d7e5c1SDong Aisheng #endif 112989d7e5c1SDong Aisheng 113089d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 113189d7e5c1SDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) 113289d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 113389d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 113489d7e5c1SDong Aisheng }; 113589d7e5c1SDong Aisheng 113685d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 113785d6509dSShawn Guo .driver = { 113885d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1139abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 114089d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 114185d6509dSShawn Guo }, 114257ed3314SShawn Guo .id_table = imx_esdhc_devtype, 114385d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 11440433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 114595f25efeSWolfram Sang }; 114685d6509dSShawn Guo 1147d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 114885d6509dSShawn Guo 114985d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1150035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 115185d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1152