1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bits.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/mmc/host.h> 12 #include <linux/mmc/mmc.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 16 #include "sdhci-pltfm.h" 17 18 /* HRS - Host Register Set (specific to Cadence) */ 19 #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ 20 #define SDHCI_CDNS_HRS04_ACK BIT(26) 21 #define SDHCI_CDNS_HRS04_RD BIT(25) 22 #define SDHCI_CDNS_HRS04_WR BIT(24) 23 #define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16) 24 #define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8) 25 #define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0) 26 27 #define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ 28 #define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) 29 #define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8) 30 #define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0) 31 #define SDHCI_CDNS_HRS06_MODE_SD 0x0 32 #define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 33 #define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 34 #define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 35 #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 36 #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 37 38 /* SRS - Slot Register Set (SDHCI-compatible) */ 39 #define SDHCI_CDNS_SRS_BASE 0x200 40 41 /* PHY */ 42 #define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 43 #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 44 #define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 45 #define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 46 #define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 47 #define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 48 #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 49 #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 50 #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 51 #define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b 52 #define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c 53 #define SDHCI_CDNS_PHY_DLY_STROBE 0x0d 54 55 /* 56 * The tuned val register is 6 bit-wide, but not the whole of the range is 57 * available. The range 0-42 seems to be available (then 43 wraps around to 0) 58 * but I am not quite sure if it is official. Use only 0 to 39 for safety. 59 */ 60 #define SDHCI_CDNS_MAX_TUNING_LOOP 40 61 62 struct sdhci_cdns_phy_param { 63 u8 addr; 64 u8 data; 65 }; 66 67 struct sdhci_cdns_priv { 68 void __iomem *hrs_addr; 69 void __iomem *ctl_addr; /* write control */ 70 spinlock_t wrlock; /* write lock */ 71 bool enhanced_strobe; 72 void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); 73 unsigned int nr_phy_params; 74 struct sdhci_cdns_phy_param phy_params[]; 75 }; 76 77 struct sdhci_cdns_phy_cfg { 78 const char *property; 79 u8 addr; 80 }; 81 82 struct sdhci_cdns_drv_data { 83 int (*init)(struct platform_device *pdev); 84 const struct sdhci_pltfm_data pltfm_data; 85 }; 86 87 static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { 88 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, 89 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, 90 { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, }, 91 { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, }, 92 { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, }, 93 { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, }, 94 { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, }, 95 { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, }, 96 { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, }, 97 { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, }, 98 { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, 99 }; 100 101 static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val, 102 void __iomem *reg) 103 { 104 writel(val, reg); 105 } 106 107 static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, 108 u8 addr, u8 data) 109 { 110 void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04; 111 u32 tmp; 112 int ret; 113 114 ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 115 0, 10); 116 if (ret) 117 return ret; 118 119 tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | 120 FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); 121 priv->priv_writel(priv, tmp, reg); 122 123 tmp |= SDHCI_CDNS_HRS04_WR; 124 priv->priv_writel(priv, tmp, reg); 125 126 ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); 127 if (ret) 128 return ret; 129 130 tmp &= ~SDHCI_CDNS_HRS04_WR; 131 priv->priv_writel(priv, tmp, reg); 132 133 ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 134 0, 10); 135 136 return ret; 137 } 138 139 static unsigned int sdhci_cdns_phy_param_count(struct device_node *np) 140 { 141 unsigned int count = 0; 142 int i; 143 144 for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) 145 if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property)) 146 count++; 147 148 return count; 149 } 150 151 static void sdhci_cdns_phy_param_parse(struct device_node *np, 152 struct sdhci_cdns_priv *priv) 153 { 154 struct sdhci_cdns_phy_param *p = priv->phy_params; 155 u32 val; 156 int ret, i; 157 158 for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) { 159 ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property, 160 &val); 161 if (ret) 162 continue; 163 164 p->addr = sdhci_cdns_phy_cfgs[i].addr; 165 p->data = val; 166 p++; 167 } 168 } 169 170 static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv) 171 { 172 int ret, i; 173 174 for (i = 0; i < priv->nr_phy_params; i++) { 175 ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr, 176 priv->phy_params[i].data); 177 if (ret) 178 return ret; 179 } 180 181 return 0; 182 } 183 184 static void *sdhci_cdns_priv(struct sdhci_host *host) 185 { 186 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 187 188 return sdhci_pltfm_priv(pltfm_host); 189 } 190 191 static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host) 192 { 193 /* 194 * Cadence's spec says the Timeout Clock Frequency is the same as the 195 * Base Clock Frequency. 196 */ 197 return host->max_clk; 198 } 199 200 static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) 201 { 202 u32 tmp; 203 204 /* The speed mode for eMMC is selected by HRS06 register */ 205 tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); 206 tmp &= ~SDHCI_CDNS_HRS06_MODE; 207 tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); 208 priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); 209 } 210 211 static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) 212 { 213 u32 tmp; 214 215 tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); 216 return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp); 217 } 218 219 static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) 220 { 221 struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); 222 void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06; 223 u32 tmp; 224 int i, ret; 225 226 if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val))) 227 return -EINVAL; 228 229 tmp = readl(reg); 230 tmp &= ~SDHCI_CDNS_HRS06_TUNE; 231 tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val); 232 233 /* 234 * Workaround for IP errata: 235 * The IP6116 SD/eMMC PHY design has a timing issue on receive data 236 * path. Send tune request twice. 237 */ 238 for (i = 0; i < 2; i++) { 239 tmp |= SDHCI_CDNS_HRS06_TUNE_UP; 240 priv->priv_writel(priv, tmp, reg); 241 242 ret = readl_poll_timeout(reg, tmp, 243 !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), 244 0, 1); 245 if (ret) 246 return ret; 247 } 248 249 return 0; 250 } 251 252 /* 253 * In SD mode, software must not use the hardware tuning and instead perform 254 * an almost identical procedure to eMMC. 255 */ 256 static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode) 257 { 258 int cur_streak = 0; 259 int max_streak = 0; 260 int end_of_streak = 0; 261 int i; 262 263 /* 264 * Do not execute tuning for UHS_SDR50 or UHS_DDR50. 265 * The delay is set by probe, based on the DT properties. 266 */ 267 if (host->timing != MMC_TIMING_MMC_HS200 && 268 host->timing != MMC_TIMING_UHS_SDR104) 269 return 0; 270 271 for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) { 272 if (sdhci_cdns_set_tune_val(host, i) || 273 mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */ 274 cur_streak = 0; 275 } else { /* good */ 276 cur_streak++; 277 if (cur_streak > max_streak) { 278 max_streak = cur_streak; 279 end_of_streak = i; 280 } 281 } 282 } 283 284 if (!max_streak) { 285 dev_err(mmc_dev(host->mmc), "no tuning point found\n"); 286 return -EIO; 287 } 288 289 return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2); 290 } 291 292 static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, 293 unsigned int timing) 294 { 295 struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); 296 u32 mode; 297 298 switch (timing) { 299 case MMC_TIMING_MMC_HS: 300 mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; 301 break; 302 case MMC_TIMING_MMC_DDR52: 303 mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; 304 break; 305 case MMC_TIMING_MMC_HS200: 306 mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200; 307 break; 308 case MMC_TIMING_MMC_HS400: 309 if (priv->enhanced_strobe) 310 mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES; 311 else 312 mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400; 313 break; 314 default: 315 mode = SDHCI_CDNS_HRS06_MODE_SD; 316 break; 317 } 318 319 sdhci_cdns_set_emmc_mode(priv, mode); 320 321 /* For SD, fall back to the default handler */ 322 if (mode == SDHCI_CDNS_HRS06_MODE_SD) 323 sdhci_set_uhs_signaling(host, timing); 324 } 325 326 /* Elba control register bits [6:3] are byte-lane enables */ 327 #define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) 328 329 /* 330 * The Pensando Elba SoC explicitly controls byte-lane enabling on writes 331 * which includes writes to the HRS registers. The write lock (wrlock) 332 * is used to ensure byte-lane enable, using write control (ctl_addr), 333 * occurs before the data write. 334 */ 335 static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val, 336 void __iomem *reg) 337 { 338 unsigned long flags; 339 340 spin_lock_irqsave(&priv->wrlock, flags); 341 writel(GENMASK(7, 3), priv->ctl_addr); 342 writel(val, reg); 343 spin_unlock_irqrestore(&priv->wrlock, flags); 344 } 345 346 static void elba_write_l(struct sdhci_host *host, u32 val, int reg) 347 { 348 elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg); 349 } 350 351 static void elba_write_w(struct sdhci_host *host, u16 val, int reg) 352 { 353 struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); 354 u32 shift = reg & GENMASK(1, 0); 355 unsigned long flags; 356 u32 byte_enables; 357 358 byte_enables = GENMASK(1, 0) << shift; 359 spin_lock_irqsave(&priv->wrlock, flags); 360 writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); 361 writew(val, host->ioaddr + reg); 362 spin_unlock_irqrestore(&priv->wrlock, flags); 363 } 364 365 static void elba_write_b(struct sdhci_host *host, u8 val, int reg) 366 { 367 struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); 368 u32 shift = reg & GENMASK(1, 0); 369 unsigned long flags; 370 u32 byte_enables; 371 372 byte_enables = BIT(0) << shift; 373 spin_lock_irqsave(&priv->wrlock, flags); 374 writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); 375 writeb(val, host->ioaddr + reg); 376 spin_unlock_irqrestore(&priv->wrlock, flags); 377 } 378 379 static const struct sdhci_ops sdhci_elba_ops = { 380 .write_l = elba_write_l, 381 .write_w = elba_write_w, 382 .write_b = elba_write_b, 383 .set_clock = sdhci_set_clock, 384 .get_timeout_clock = sdhci_cdns_get_timeout_clock, 385 .set_bus_width = sdhci_set_bus_width, 386 .reset = sdhci_reset, 387 .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, 388 }; 389 390 static int elba_drv_init(struct platform_device *pdev) 391 { 392 struct sdhci_host *host = platform_get_drvdata(pdev); 393 struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); 394 void __iomem *ioaddr; 395 396 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA; 397 spin_lock_init(&priv->wrlock); 398 399 /* Byte-lane control register */ 400 ioaddr = devm_platform_ioremap_resource(pdev, 1); 401 if (IS_ERR(ioaddr)) 402 return PTR_ERR(ioaddr); 403 404 priv->ctl_addr = ioaddr; 405 priv->priv_writel = elba_priv_writel; 406 writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); 407 408 return 0; 409 } 410 411 static const struct sdhci_ops sdhci_cdns_ops = { 412 .set_clock = sdhci_set_clock, 413 .get_timeout_clock = sdhci_cdns_get_timeout_clock, 414 .set_bus_width = sdhci_set_bus_width, 415 .reset = sdhci_reset, 416 .platform_execute_tuning = sdhci_cdns_execute_tuning, 417 .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, 418 }; 419 420 static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { 421 .pltfm_data = { 422 .ops = &sdhci_cdns_ops, 423 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 424 }, 425 }; 426 427 static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = { 428 .init = elba_drv_init, 429 .pltfm_data = { 430 .ops = &sdhci_elba_ops, 431 }, 432 }; 433 434 static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { 435 .pltfm_data = { 436 .ops = &sdhci_cdns_ops, 437 }, 438 }; 439 440 static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, 441 struct mmc_ios *ios) 442 { 443 struct sdhci_host *host = mmc_priv(mmc); 444 struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); 445 u32 mode; 446 447 priv->enhanced_strobe = ios->enhanced_strobe; 448 449 mode = sdhci_cdns_get_emmc_mode(priv); 450 451 if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe) 452 sdhci_cdns_set_emmc_mode(priv, 453 SDHCI_CDNS_HRS06_MODE_MMC_HS400ES); 454 455 if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe) 456 sdhci_cdns_set_emmc_mode(priv, 457 SDHCI_CDNS_HRS06_MODE_MMC_HS400); 458 } 459 460 static int sdhci_cdns_probe(struct platform_device *pdev) 461 { 462 struct sdhci_host *host; 463 const struct sdhci_cdns_drv_data *data; 464 struct sdhci_pltfm_host *pltfm_host; 465 struct sdhci_cdns_priv *priv; 466 struct clk *clk; 467 unsigned int nr_phy_params; 468 int ret; 469 struct device *dev = &pdev->dev; 470 static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT; 471 472 clk = devm_clk_get(dev, NULL); 473 if (IS_ERR(clk)) 474 return PTR_ERR(clk); 475 476 ret = clk_prepare_enable(clk); 477 if (ret) 478 return ret; 479 480 data = of_device_get_match_data(dev); 481 if (!data) 482 data = &sdhci_cdns_drv_data; 483 484 nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node); 485 host = sdhci_pltfm_init(pdev, &data->pltfm_data, 486 struct_size(priv, phy_params, nr_phy_params)); 487 if (IS_ERR(host)) { 488 ret = PTR_ERR(host); 489 goto disable_clk; 490 } 491 492 pltfm_host = sdhci_priv(host); 493 pltfm_host->clk = clk; 494 495 priv = sdhci_pltfm_priv(pltfm_host); 496 priv->nr_phy_params = nr_phy_params; 497 priv->hrs_addr = host->ioaddr; 498 priv->enhanced_strobe = false; 499 priv->priv_writel = cdns_writel; 500 host->ioaddr += SDHCI_CDNS_SRS_BASE; 501 host->mmc_host_ops.hs400_enhanced_strobe = 502 sdhci_cdns_hs400_enhanced_strobe; 503 if (data->init) { 504 ret = data->init(pdev); 505 if (ret) 506 goto free; 507 } 508 sdhci_enable_v4_mode(host); 509 __sdhci_read_caps(host, &version, NULL, NULL); 510 511 sdhci_get_of_property(pdev); 512 513 ret = mmc_of_parse(host->mmc); 514 if (ret) 515 goto free; 516 517 sdhci_cdns_phy_param_parse(dev->of_node, priv); 518 519 ret = sdhci_cdns_phy_init(priv); 520 if (ret) 521 goto free; 522 523 ret = sdhci_add_host(host); 524 if (ret) 525 goto free; 526 527 return 0; 528 free: 529 sdhci_pltfm_free(pdev); 530 disable_clk: 531 clk_disable_unprepare(clk); 532 533 return ret; 534 } 535 536 #ifdef CONFIG_PM_SLEEP 537 static int sdhci_cdns_resume(struct device *dev) 538 { 539 struct sdhci_host *host = dev_get_drvdata(dev); 540 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 541 struct sdhci_cdns_priv *priv = sdhci_pltfm_priv(pltfm_host); 542 int ret; 543 544 ret = clk_prepare_enable(pltfm_host->clk); 545 if (ret) 546 return ret; 547 548 ret = sdhci_cdns_phy_init(priv); 549 if (ret) 550 goto disable_clk; 551 552 ret = sdhci_resume_host(host); 553 if (ret) 554 goto disable_clk; 555 556 return 0; 557 558 disable_clk: 559 clk_disable_unprepare(pltfm_host->clk); 560 561 return ret; 562 } 563 #endif 564 565 static const struct dev_pm_ops sdhci_cdns_pm_ops = { 566 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_cdns_resume) 567 }; 568 569 static const struct of_device_id sdhci_cdns_match[] = { 570 { 571 .compatible = "socionext,uniphier-sd4hc", 572 .data = &sdhci_cdns_uniphier_drv_data, 573 }, 574 { 575 .compatible = "amd,pensando-elba-sd4hc", 576 .data = &sdhci_elba_drv_data, 577 }, 578 { .compatible = "cdns,sd4hc" }, 579 { /* sentinel */ } 580 }; 581 MODULE_DEVICE_TABLE(of, sdhci_cdns_match); 582 583 static struct platform_driver sdhci_cdns_driver = { 584 .driver = { 585 .name = "sdhci-cdns", 586 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 587 .pm = &sdhci_cdns_pm_ops, 588 .of_match_table = sdhci_cdns_match, 589 }, 590 .probe = sdhci_cdns_probe, 591 .remove = sdhci_pltfm_unregister, 592 }; 593 module_platform_driver(sdhci_cdns_driver); 594 595 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 596 MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver"); 597 MODULE_LICENSE("GPL"); 598