xref: /openbmc/linux/drivers/mmc/host/sdhci-cadence.c (revision 6aa7de05)
1 /*
2  * Copyright (C) 2016 Socionext Inc.
3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 
16 #include <linux/bitops.h>
17 #include <linux/iopoll.h>
18 #include <linux/module.h>
19 #include <linux/mmc/host.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/of.h>
22 
23 #include "sdhci-pltfm.h"
24 
25 /* HRS - Host Register Set (specific to Cadence) */
26 #define SDHCI_CDNS_HRS04		0x10		/* PHY access port */
27 #define   SDHCI_CDNS_HRS04_ACK			BIT(26)
28 #define   SDHCI_CDNS_HRS04_RD			BIT(25)
29 #define   SDHCI_CDNS_HRS04_WR			BIT(24)
30 #define   SDHCI_CDNS_HRS04_RDATA_SHIFT		16
31 #define   SDHCI_CDNS_HRS04_WDATA_SHIFT		8
32 #define   SDHCI_CDNS_HRS04_ADDR_SHIFT		0
33 
34 #define SDHCI_CDNS_HRS06		0x18		/* eMMC control */
35 #define   SDHCI_CDNS_HRS06_TUNE_UP		BIT(15)
36 #define   SDHCI_CDNS_HRS06_TUNE_SHIFT		8
37 #define   SDHCI_CDNS_HRS06_TUNE_MASK		0x3f
38 #define   SDHCI_CDNS_HRS06_MODE_MASK		0x7
39 #define   SDHCI_CDNS_HRS06_MODE_SD		0x0
40 #define   SDHCI_CDNS_HRS06_MODE_MMC_SDR		0x2
41 #define   SDHCI_CDNS_HRS06_MODE_MMC_DDR		0x3
42 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS200	0x4
43 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400	0x5
44 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400ES	0x6
45 
46 /* SRS - Slot Register Set (SDHCI-compatible) */
47 #define SDHCI_CDNS_SRS_BASE		0x200
48 
49 /* PHY */
50 #define SDHCI_CDNS_PHY_DLY_SD_HS	0x00
51 #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT	0x01
52 #define SDHCI_CDNS_PHY_DLY_UHS_SDR12	0x02
53 #define SDHCI_CDNS_PHY_DLY_UHS_SDR25	0x03
54 #define SDHCI_CDNS_PHY_DLY_UHS_SDR50	0x04
55 #define SDHCI_CDNS_PHY_DLY_UHS_DDR50	0x05
56 #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY	0x06
57 #define SDHCI_CDNS_PHY_DLY_EMMC_SDR	0x07
58 #define SDHCI_CDNS_PHY_DLY_EMMC_DDR	0x08
59 #define SDHCI_CDNS_PHY_DLY_SDCLK	0x0b
60 #define SDHCI_CDNS_PHY_DLY_HSMMC	0x0c
61 #define SDHCI_CDNS_PHY_DLY_STROBE	0x0d
62 
63 /*
64  * The tuned val register is 6 bit-wide, but not the whole of the range is
65  * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
66  * but I am not quite sure if it is official.  Use only 0 to 39 for safety.
67  */
68 #define SDHCI_CDNS_MAX_TUNING_LOOP	40
69 
70 struct sdhci_cdns_phy_param {
71 	u8 addr;
72 	u8 data;
73 };
74 
75 struct sdhci_cdns_priv {
76 	void __iomem *hrs_addr;
77 	bool enhanced_strobe;
78 	unsigned int nr_phy_params;
79 	struct sdhci_cdns_phy_param phy_params[0];
80 };
81 
82 struct sdhci_cdns_phy_cfg {
83 	const char *property;
84 	u8 addr;
85 };
86 
87 static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
88 	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
89 	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
90 	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
91 	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
92 	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
93 	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
94 	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
95 	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
96 	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
97 	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
98 	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
99 };
100 
101 static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
102 				    u8 addr, u8 data)
103 {
104 	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
105 	u32 tmp;
106 	int ret;
107 
108 	tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
109 	      (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
110 	writel(tmp, reg);
111 
112 	tmp |= SDHCI_CDNS_HRS04_WR;
113 	writel(tmp, reg);
114 
115 	ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
116 	if (ret)
117 		return ret;
118 
119 	tmp &= ~SDHCI_CDNS_HRS04_WR;
120 	writel(tmp, reg);
121 
122 	return 0;
123 }
124 
125 static unsigned int sdhci_cdns_phy_param_count(struct device_node *np)
126 {
127 	unsigned int count = 0;
128 	int i;
129 
130 	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++)
131 		if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property))
132 			count++;
133 
134 	return count;
135 }
136 
137 static void sdhci_cdns_phy_param_parse(struct device_node *np,
138 				       struct sdhci_cdns_priv *priv)
139 {
140 	struct sdhci_cdns_phy_param *p = priv->phy_params;
141 	u32 val;
142 	int ret, i;
143 
144 	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
145 		ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property,
146 					   &val);
147 		if (ret)
148 			continue;
149 
150 		p->addr = sdhci_cdns_phy_cfgs[i].addr;
151 		p->data = val;
152 		p++;
153 	}
154 }
155 
156 static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
157 {
158 	int ret, i;
159 
160 	for (i = 0; i < priv->nr_phy_params; i++) {
161 		ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,
162 					       priv->phy_params[i].data);
163 		if (ret)
164 			return ret;
165 	}
166 
167 	return 0;
168 }
169 
170 static inline void *sdhci_cdns_priv(struct sdhci_host *host)
171 {
172 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
173 
174 	return sdhci_pltfm_priv(pltfm_host);
175 }
176 
177 static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
178 {
179 	/*
180 	 * Cadence's spec says the Timeout Clock Frequency is the same as the
181 	 * Base Clock Frequency.
182 	 */
183 	return host->max_clk;
184 }
185 
186 static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
187 {
188 	u32 tmp;
189 
190 	/* The speed mode for eMMC is selected by HRS06 register */
191 	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
192 	tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK;
193 	tmp |= mode;
194 	writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
195 }
196 
197 static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
198 {
199 	u32 tmp;
200 
201 	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
202 	return tmp & SDHCI_CDNS_HRS06_MODE_MASK;
203 }
204 
205 static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
206 					 unsigned int timing)
207 {
208 	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
209 	u32 mode;
210 
211 	switch (timing) {
212 	case MMC_TIMING_MMC_HS:
213 		mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
214 		break;
215 	case MMC_TIMING_MMC_DDR52:
216 		mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
217 		break;
218 	case MMC_TIMING_MMC_HS200:
219 		mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
220 		break;
221 	case MMC_TIMING_MMC_HS400:
222 		if (priv->enhanced_strobe)
223 			mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES;
224 		else
225 			mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
226 		break;
227 	default:
228 		mode = SDHCI_CDNS_HRS06_MODE_SD;
229 		break;
230 	}
231 
232 	sdhci_cdns_set_emmc_mode(priv, mode);
233 
234 	/* For SD, fall back to the default handler */
235 	if (mode == SDHCI_CDNS_HRS06_MODE_SD)
236 		sdhci_set_uhs_signaling(host, timing);
237 }
238 
239 static const struct sdhci_ops sdhci_cdns_ops = {
240 	.set_clock = sdhci_set_clock,
241 	.get_timeout_clock = sdhci_cdns_get_timeout_clock,
242 	.set_bus_width = sdhci_set_bus_width,
243 	.reset = sdhci_reset,
244 	.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
245 };
246 
247 static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
248 	.ops = &sdhci_cdns_ops,
249 };
250 
251 static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
252 {
253 	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
254 	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
255 	u32 tmp;
256 
257 	if (WARN_ON(val > SDHCI_CDNS_HRS06_TUNE_MASK))
258 		return -EINVAL;
259 
260 	tmp = readl(reg);
261 	tmp &= ~(SDHCI_CDNS_HRS06_TUNE_MASK << SDHCI_CDNS_HRS06_TUNE_SHIFT);
262 	tmp |= val << SDHCI_CDNS_HRS06_TUNE_SHIFT;
263 	tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
264 	writel(tmp, reg);
265 
266 	return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
267 				  0, 1);
268 }
269 
270 static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode)
271 {
272 	struct sdhci_host *host = mmc_priv(mmc);
273 	int cur_streak = 0;
274 	int max_streak = 0;
275 	int end_of_streak = 0;
276 	int i;
277 
278 	/*
279 	 * This handler only implements the eMMC tuning that is specific to
280 	 * this controller.  Fall back to the standard method for SD timing.
281 	 */
282 	if (host->timing != MMC_TIMING_MMC_HS200)
283 		return sdhci_execute_tuning(mmc, opcode);
284 
285 	if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
286 		return -EINVAL;
287 
288 	for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
289 		if (sdhci_cdns_set_tune_val(host, i) ||
290 		    mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
291 			cur_streak = 0;
292 		} else { /* good */
293 			cur_streak++;
294 			if (cur_streak > max_streak) {
295 				max_streak = cur_streak;
296 				end_of_streak = i;
297 			}
298 		}
299 	}
300 
301 	if (!max_streak) {
302 		dev_err(mmc_dev(host->mmc), "no tuning point found\n");
303 		return -EIO;
304 	}
305 
306 	return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
307 }
308 
309 static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
310 					     struct mmc_ios *ios)
311 {
312 	struct sdhci_host *host = mmc_priv(mmc);
313 	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
314 	u32 mode;
315 
316 	priv->enhanced_strobe = ios->enhanced_strobe;
317 
318 	mode = sdhci_cdns_get_emmc_mode(priv);
319 
320 	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe)
321 		sdhci_cdns_set_emmc_mode(priv,
322 					 SDHCI_CDNS_HRS06_MODE_MMC_HS400ES);
323 
324 	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe)
325 		sdhci_cdns_set_emmc_mode(priv,
326 					 SDHCI_CDNS_HRS06_MODE_MMC_HS400);
327 }
328 
329 static int sdhci_cdns_probe(struct platform_device *pdev)
330 {
331 	struct sdhci_host *host;
332 	struct sdhci_pltfm_host *pltfm_host;
333 	struct sdhci_cdns_priv *priv;
334 	struct clk *clk;
335 	size_t priv_size;
336 	unsigned int nr_phy_params;
337 	int ret;
338 	struct device *dev = &pdev->dev;
339 
340 	clk = devm_clk_get(dev, NULL);
341 	if (IS_ERR(clk))
342 		return PTR_ERR(clk);
343 
344 	ret = clk_prepare_enable(clk);
345 	if (ret)
346 		return ret;
347 
348 	nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
349 	priv_size = sizeof(*priv) + sizeof(priv->phy_params[0]) * nr_phy_params;
350 	host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, priv_size);
351 	if (IS_ERR(host)) {
352 		ret = PTR_ERR(host);
353 		goto disable_clk;
354 	}
355 
356 	pltfm_host = sdhci_priv(host);
357 	pltfm_host->clk = clk;
358 
359 	priv = sdhci_pltfm_priv(pltfm_host);
360 	priv->nr_phy_params = nr_phy_params;
361 	priv->hrs_addr = host->ioaddr;
362 	priv->enhanced_strobe = false;
363 	host->ioaddr += SDHCI_CDNS_SRS_BASE;
364 	host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning;
365 	host->mmc_host_ops.hs400_enhanced_strobe =
366 				sdhci_cdns_hs400_enhanced_strobe;
367 
368 	sdhci_get_of_property(pdev);
369 
370 	ret = mmc_of_parse(host->mmc);
371 	if (ret)
372 		goto free;
373 
374 	sdhci_cdns_phy_param_parse(dev->of_node, priv);
375 
376 	ret = sdhci_cdns_phy_init(priv);
377 	if (ret)
378 		goto free;
379 
380 	ret = sdhci_add_host(host);
381 	if (ret)
382 		goto free;
383 
384 	return 0;
385 free:
386 	sdhci_pltfm_free(pdev);
387 disable_clk:
388 	clk_disable_unprepare(clk);
389 
390 	return ret;
391 }
392 
393 #ifdef CONFIG_PM_SLEEP
394 static int sdhci_cdns_resume(struct device *dev)
395 {
396 	struct sdhci_host *host = dev_get_drvdata(dev);
397 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
398 	struct sdhci_cdns_priv *priv = sdhci_pltfm_priv(pltfm_host);
399 	int ret;
400 
401 	ret = clk_prepare_enable(pltfm_host->clk);
402 	if (ret)
403 		return ret;
404 
405 	ret = sdhci_cdns_phy_init(priv);
406 	if (ret)
407 		goto disable_clk;
408 
409 	ret = sdhci_resume_host(host);
410 	if (ret)
411 		goto disable_clk;
412 
413 	return 0;
414 
415 disable_clk:
416 	clk_disable_unprepare(pltfm_host->clk);
417 
418 	return ret;
419 }
420 #endif
421 
422 static const struct dev_pm_ops sdhci_cdns_pm_ops = {
423 	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_cdns_resume)
424 };
425 
426 static const struct of_device_id sdhci_cdns_match[] = {
427 	{ .compatible = "socionext,uniphier-sd4hc" },
428 	{ .compatible = "cdns,sd4hc" },
429 	{ /* sentinel */ }
430 };
431 MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
432 
433 static struct platform_driver sdhci_cdns_driver = {
434 	.driver = {
435 		.name = "sdhci-cdns",
436 		.pm = &sdhci_cdns_pm_ops,
437 		.of_match_table = sdhci_cdns_match,
438 	},
439 	.probe = sdhci_cdns_probe,
440 	.remove = sdhci_pltfm_unregister,
441 };
442 module_platform_driver(sdhci_cdns_driver);
443 
444 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
445 MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
446 MODULE_LICENSE("GPL");
447