1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's 4 * 5 * Copyright (C) 2015 Broadcom Corporation 6 */ 7 8 #include <linux/io.h> 9 #include <linux/mmc/host.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/bitops.h> 13 #include <linux/delay.h> 14 15 #include "sdhci-pltfm.h" 16 #include "cqhci.h" 17 18 #define SDHCI_VENDOR 0x78 19 #define SDHCI_VENDOR_ENHANCED_STRB 0x1 20 #define SDHCI_VENDOR_GATE_SDCLK_EN 0x2 21 22 #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) 23 #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) 24 #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2) 25 26 #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) 27 #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1) 28 29 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 30 31 struct sdhci_brcmstb_priv { 32 void __iomem *cfg_regs; 33 unsigned int flags; 34 struct clk *base_clk; 35 u32 base_freq_hz; 36 }; 37 38 struct brcmstb_match_priv { 39 void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); 40 struct sdhci_ops *ops; 41 const unsigned int flags; 42 }; 43 44 static inline void enable_clock_gating(struct sdhci_host *host) 45 { 46 u32 reg; 47 48 reg = sdhci_readl(host, SDHCI_VENDOR); 49 reg |= SDHCI_VENDOR_GATE_SDCLK_EN; 50 sdhci_writel(host, reg, SDHCI_VENDOR); 51 } 52 53 static void brcmstb_reset(struct sdhci_host *host, u8 mask) 54 { 55 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 56 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 57 58 sdhci_reset(host, mask); 59 60 /* Reset will clear this, so re-enable it */ 61 if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK) 62 enable_clock_gating(host); 63 } 64 65 static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) 66 { 67 struct sdhci_host *host = mmc_priv(mmc); 68 69 u32 reg; 70 71 dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n", 72 __func__); 73 reg = readl(host->ioaddr + SDHCI_VENDOR); 74 if (ios->enhanced_strobe) 75 reg |= SDHCI_VENDOR_ENHANCED_STRB; 76 else 77 reg &= ~SDHCI_VENDOR_ENHANCED_STRB; 78 writel(reg, host->ioaddr + SDHCI_VENDOR); 79 } 80 81 static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) 82 { 83 u16 clk; 84 85 host->mmc->actual_clock = 0; 86 87 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 88 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 89 90 if (clock == 0) 91 return; 92 93 sdhci_enable_clk(host, clk); 94 } 95 96 static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, 97 unsigned int timing) 98 { 99 u16 ctrl_2; 100 101 dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n", 102 __func__, timing); 103 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 104 /* Select Bus Speed Mode for host */ 105 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 106 if ((timing == MMC_TIMING_MMC_HS200) || 107 (timing == MMC_TIMING_UHS_SDR104)) 108 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 109 else if (timing == MMC_TIMING_UHS_SDR12) 110 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 111 else if (timing == MMC_TIMING_SD_HS || 112 timing == MMC_TIMING_MMC_HS || 113 timing == MMC_TIMING_UHS_SDR25) 114 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 115 else if (timing == MMC_TIMING_UHS_SDR50) 116 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 117 else if ((timing == MMC_TIMING_UHS_DDR50) || 118 (timing == MMC_TIMING_MMC_DDR52)) 119 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 120 else if (timing == MMC_TIMING_MMC_HS400) 121 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 122 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 123 } 124 125 static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) 126 { 127 sdhci_dumpregs(mmc_priv(mmc)); 128 } 129 130 static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc) 131 { 132 struct sdhci_host *host = mmc_priv(mmc); 133 u32 reg; 134 135 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 136 while (reg & SDHCI_DATA_AVAILABLE) { 137 sdhci_readl(host, SDHCI_BUFFER); 138 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 139 } 140 141 sdhci_cqe_enable(mmc); 142 } 143 144 static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = { 145 .enable = sdhci_brcmstb_cqe_enable, 146 .disable = sdhci_cqe_disable, 147 .dumpregs = sdhci_brcmstb_dumpregs, 148 }; 149 150 static struct sdhci_ops sdhci_brcmstb_ops = { 151 .set_clock = sdhci_set_clock, 152 .set_bus_width = sdhci_set_bus_width, 153 .reset = sdhci_reset, 154 .set_uhs_signaling = sdhci_set_uhs_signaling, 155 }; 156 157 static struct sdhci_ops sdhci_brcmstb_ops_7216 = { 158 .set_clock = sdhci_brcmstb_set_clock, 159 .set_bus_width = sdhci_set_bus_width, 160 .reset = brcmstb_reset, 161 .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, 162 }; 163 164 static struct brcmstb_match_priv match_priv_7425 = { 165 .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | 166 BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 167 .ops = &sdhci_brcmstb_ops, 168 }; 169 170 static struct brcmstb_match_priv match_priv_7445 = { 171 .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 172 .ops = &sdhci_brcmstb_ops, 173 }; 174 175 static const struct brcmstb_match_priv match_priv_7216 = { 176 .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, 177 .hs400es = sdhci_brcmstb_hs400es, 178 .ops = &sdhci_brcmstb_ops_7216, 179 }; 180 181 static const struct of_device_id sdhci_brcm_of_match[] = { 182 { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, 183 { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, 184 { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, 185 {}, 186 }; 187 188 static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask) 189 { 190 int cmd_error = 0; 191 int data_error = 0; 192 193 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 194 return intmask; 195 196 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 197 198 return 0; 199 } 200 201 static int sdhci_brcmstb_add_host(struct sdhci_host *host, 202 struct sdhci_brcmstb_priv *priv) 203 { 204 struct cqhci_host *cq_host; 205 bool dma64; 206 int ret; 207 208 if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0) 209 return sdhci_add_host(host); 210 211 dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); 212 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 213 ret = sdhci_setup_host(host); 214 if (ret) 215 return ret; 216 217 cq_host = devm_kzalloc(mmc_dev(host->mmc), 218 sizeof(*cq_host), GFP_KERNEL); 219 if (!cq_host) { 220 ret = -ENOMEM; 221 goto cleanup; 222 } 223 224 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 225 cq_host->ops = &sdhci_brcmstb_cqhci_ops; 226 227 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 228 if (dma64) { 229 dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n"); 230 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 231 } 232 233 ret = cqhci_init(cq_host, host->mmc, dma64); 234 if (ret) 235 goto cleanup; 236 237 ret = __sdhci_add_host(host); 238 if (ret) 239 goto cleanup; 240 241 return 0; 242 243 cleanup: 244 sdhci_cleanup_host(host); 245 return ret; 246 } 247 248 static int sdhci_brcmstb_probe(struct platform_device *pdev) 249 { 250 const struct brcmstb_match_priv *match_priv; 251 struct sdhci_pltfm_data brcmstb_pdata; 252 struct sdhci_pltfm_host *pltfm_host; 253 const struct of_device_id *match; 254 struct sdhci_brcmstb_priv *priv; 255 u32 actual_clock_mhz; 256 struct sdhci_host *host; 257 struct resource *iomem; 258 struct clk *clk; 259 struct clk *base_clk = NULL; 260 int res; 261 262 match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); 263 match_priv = match->data; 264 265 dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible); 266 267 clk = devm_clk_get_optional(&pdev->dev, NULL); 268 if (IS_ERR(clk)) 269 return dev_err_probe(&pdev->dev, PTR_ERR(clk), 270 "Failed to get clock from Device Tree\n"); 271 272 res = clk_prepare_enable(clk); 273 if (res) 274 return res; 275 276 memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); 277 brcmstb_pdata.ops = match_priv->ops; 278 host = sdhci_pltfm_init(pdev, &brcmstb_pdata, 279 sizeof(struct sdhci_brcmstb_priv)); 280 if (IS_ERR(host)) { 281 res = PTR_ERR(host); 282 goto err_clk; 283 } 284 285 pltfm_host = sdhci_priv(host); 286 priv = sdhci_pltfm_priv(pltfm_host); 287 if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 288 priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE; 289 match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; 290 } 291 292 /* Map in the non-standard CFG registers */ 293 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 294 priv->cfg_regs = devm_ioremap_resource(&pdev->dev, iomem); 295 if (IS_ERR(priv->cfg_regs)) { 296 res = PTR_ERR(priv->cfg_regs); 297 goto err; 298 } 299 300 sdhci_get_of_property(pdev); 301 res = mmc_of_parse(host->mmc); 302 if (res) 303 goto err; 304 305 /* 306 * Automatic clock gating does not work for SD cards that may 307 * voltage switch so only enable it for non-removable devices. 308 */ 309 if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) && 310 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 311 priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK; 312 313 /* 314 * If the chip has enhanced strobe and it's enabled, add 315 * callback 316 */ 317 if (match_priv->hs400es && 318 (host->mmc->caps2 & MMC_CAP2_HS400_ES)) 319 host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; 320 321 /* 322 * Supply the existing CAPS, but clear the UHS modes. This 323 * will allow these modes to be specified by device tree 324 * properties through mmc_of_parse(). 325 */ 326 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); 327 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT) 328 host->caps &= ~SDHCI_CAN_64BIT; 329 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 330 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 331 SDHCI_SUPPORT_DDR50); 332 host->quirks |= SDHCI_QUIRK_MISSING_CAPS; 333 334 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) 335 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 336 337 /* Change the base clock frequency if the DT property exists */ 338 if (device_property_read_u32(&pdev->dev, "clock-frequency", 339 &priv->base_freq_hz) != 0) 340 goto add_host; 341 342 base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq"); 343 if (IS_ERR(base_clk)) { 344 dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n"); 345 goto add_host; 346 } 347 348 res = clk_prepare_enable(base_clk); 349 if (res) 350 goto err; 351 352 /* set improved clock rate */ 353 clk_set_rate(base_clk, priv->base_freq_hz); 354 actual_clock_mhz = clk_get_rate(base_clk) / 1000000; 355 356 host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; 357 host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT); 358 /* Disable presets because they are now incorrect */ 359 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 360 361 dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n", 362 actual_clock_mhz); 363 priv->base_clk = base_clk; 364 365 add_host: 366 res = sdhci_brcmstb_add_host(host, priv); 367 if (res) 368 goto err; 369 370 pltfm_host->clk = clk; 371 return res; 372 373 err: 374 sdhci_pltfm_free(pdev); 375 err_clk: 376 clk_disable_unprepare(base_clk); 377 clk_disable_unprepare(clk); 378 return res; 379 } 380 381 static void sdhci_brcmstb_shutdown(struct platform_device *pdev) 382 { 383 sdhci_pltfm_suspend(&pdev->dev); 384 } 385 386 MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match); 387 388 #ifdef CONFIG_PM_SLEEP 389 static int sdhci_brcmstb_suspend(struct device *dev) 390 { 391 struct sdhci_host *host = dev_get_drvdata(dev); 392 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 393 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 394 395 clk_disable_unprepare(priv->base_clk); 396 return sdhci_pltfm_suspend(dev); 397 } 398 399 static int sdhci_brcmstb_resume(struct device *dev) 400 { 401 struct sdhci_host *host = dev_get_drvdata(dev); 402 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 403 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 404 int ret; 405 406 ret = sdhci_pltfm_resume(dev); 407 if (!ret && priv->base_freq_hz) { 408 ret = clk_prepare_enable(priv->base_clk); 409 /* 410 * Note: using clk_get_rate() below as clk_get_rate() 411 * honors CLK_GET_RATE_NOCACHE attribute, but clk_set_rate() 412 * may do implicit get_rate() calls that do not honor 413 * CLK_GET_RATE_NOCACHE. 414 */ 415 if (!ret && 416 (clk_get_rate(priv->base_clk) != priv->base_freq_hz)) 417 ret = clk_set_rate(priv->base_clk, priv->base_freq_hz); 418 } 419 420 return ret; 421 } 422 #endif 423 424 static const struct dev_pm_ops sdhci_brcmstb_pmops = { 425 SET_SYSTEM_SLEEP_PM_OPS(sdhci_brcmstb_suspend, sdhci_brcmstb_resume) 426 }; 427 428 static struct platform_driver sdhci_brcmstb_driver = { 429 .driver = { 430 .name = "sdhci-brcmstb", 431 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 432 .pm = &sdhci_brcmstb_pmops, 433 .of_match_table = of_match_ptr(sdhci_brcm_of_match), 434 }, 435 .probe = sdhci_brcmstb_probe, 436 .remove = sdhci_pltfm_unregister, 437 .shutdown = sdhci_brcmstb_shutdown, 438 }; 439 440 module_platform_driver(sdhci_brcmstb_driver); 441 442 MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs"); 443 MODULE_AUTHOR("Broadcom"); 444 MODULE_LICENSE("GPL v2"); 445