1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's 4 * 5 * Copyright (C) 2015 Broadcom Corporation 6 */ 7 8 #include <linux/io.h> 9 #include <linux/mmc/host.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/bitops.h> 13 #include <linux/delay.h> 14 15 #include "sdhci-cqhci.h" 16 #include "sdhci-pltfm.h" 17 #include "cqhci.h" 18 19 #define SDHCI_VENDOR 0x78 20 #define SDHCI_VENDOR_ENHANCED_STRB 0x1 21 #define SDHCI_VENDOR_GATE_SDCLK_EN 0x2 22 23 #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) 24 #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) 25 #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2) 26 #define BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY BIT(4) 27 28 #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) 29 #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1) 30 31 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 32 33 struct sdhci_brcmstb_priv { 34 void __iomem *cfg_regs; 35 unsigned int flags; 36 struct clk *base_clk; 37 u32 base_freq_hz; 38 }; 39 40 struct brcmstb_match_priv { 41 void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); 42 struct sdhci_ops *ops; 43 const unsigned int flags; 44 }; 45 46 static inline void enable_clock_gating(struct sdhci_host *host) 47 { 48 u32 reg; 49 50 reg = sdhci_readl(host, SDHCI_VENDOR); 51 reg |= SDHCI_VENDOR_GATE_SDCLK_EN; 52 sdhci_writel(host, reg, SDHCI_VENDOR); 53 } 54 55 static void brcmstb_reset(struct sdhci_host *host, u8 mask) 56 { 57 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 58 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 59 60 sdhci_and_cqhci_reset(host, mask); 61 62 /* Reset will clear this, so re-enable it */ 63 if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK) 64 enable_clock_gating(host); 65 } 66 67 static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) 68 { 69 struct sdhci_host *host = mmc_priv(mmc); 70 71 u32 reg; 72 73 dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n", 74 __func__); 75 reg = readl(host->ioaddr + SDHCI_VENDOR); 76 if (ios->enhanced_strobe) 77 reg |= SDHCI_VENDOR_ENHANCED_STRB; 78 else 79 reg &= ~SDHCI_VENDOR_ENHANCED_STRB; 80 writel(reg, host->ioaddr + SDHCI_VENDOR); 81 } 82 83 static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) 84 { 85 u16 clk; 86 87 host->mmc->actual_clock = 0; 88 89 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 90 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 91 92 if (clock == 0) 93 return; 94 95 sdhci_enable_clk(host, clk); 96 } 97 98 static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, 99 unsigned int timing) 100 { 101 u16 ctrl_2; 102 103 dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n", 104 __func__, timing); 105 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 106 /* Select Bus Speed Mode for host */ 107 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 108 if ((timing == MMC_TIMING_MMC_HS200) || 109 (timing == MMC_TIMING_UHS_SDR104)) 110 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 111 else if (timing == MMC_TIMING_UHS_SDR12) 112 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 113 else if (timing == MMC_TIMING_SD_HS || 114 timing == MMC_TIMING_MMC_HS || 115 timing == MMC_TIMING_UHS_SDR25) 116 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 117 else if (timing == MMC_TIMING_UHS_SDR50) 118 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 119 else if ((timing == MMC_TIMING_UHS_DDR50) || 120 (timing == MMC_TIMING_MMC_DDR52)) 121 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 122 else if (timing == MMC_TIMING_MMC_HS400) 123 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 124 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 125 } 126 127 static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) 128 { 129 sdhci_dumpregs(mmc_priv(mmc)); 130 } 131 132 static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc) 133 { 134 struct sdhci_host *host = mmc_priv(mmc); 135 u32 reg; 136 137 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 138 while (reg & SDHCI_DATA_AVAILABLE) { 139 sdhci_readl(host, SDHCI_BUFFER); 140 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 141 } 142 143 sdhci_cqe_enable(mmc); 144 } 145 146 static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = { 147 .enable = sdhci_brcmstb_cqe_enable, 148 .disable = sdhci_cqe_disable, 149 .dumpregs = sdhci_brcmstb_dumpregs, 150 }; 151 152 static struct sdhci_ops sdhci_brcmstb_ops = { 153 .set_clock = sdhci_set_clock, 154 .set_bus_width = sdhci_set_bus_width, 155 .reset = sdhci_reset, 156 .set_uhs_signaling = sdhci_set_uhs_signaling, 157 }; 158 159 static struct sdhci_ops sdhci_brcmstb_ops_7216 = { 160 .set_clock = sdhci_brcmstb_set_clock, 161 .set_bus_width = sdhci_set_bus_width, 162 .reset = brcmstb_reset, 163 .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, 164 }; 165 166 static struct brcmstb_match_priv match_priv_7425 = { 167 .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | 168 BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 169 .ops = &sdhci_brcmstb_ops, 170 }; 171 172 static struct brcmstb_match_priv match_priv_7445 = { 173 .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 174 .ops = &sdhci_brcmstb_ops, 175 }; 176 177 static const struct brcmstb_match_priv match_priv_7216 = { 178 .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, 179 .hs400es = sdhci_brcmstb_hs400es, 180 .ops = &sdhci_brcmstb_ops_7216, 181 }; 182 183 static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { 184 { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, 185 { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, 186 { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, 187 {}, 188 }; 189 190 static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask) 191 { 192 int cmd_error = 0; 193 int data_error = 0; 194 195 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 196 return intmask; 197 198 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 199 200 return 0; 201 } 202 203 static int sdhci_brcmstb_add_host(struct sdhci_host *host, 204 struct sdhci_brcmstb_priv *priv) 205 { 206 struct cqhci_host *cq_host; 207 bool dma64; 208 int ret; 209 210 if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0) 211 return sdhci_add_host(host); 212 213 dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); 214 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 215 ret = sdhci_setup_host(host); 216 if (ret) 217 return ret; 218 219 cq_host = devm_kzalloc(mmc_dev(host->mmc), 220 sizeof(*cq_host), GFP_KERNEL); 221 if (!cq_host) { 222 ret = -ENOMEM; 223 goto cleanup; 224 } 225 226 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 227 cq_host->ops = &sdhci_brcmstb_cqhci_ops; 228 229 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 230 if (dma64) { 231 dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n"); 232 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 233 } 234 235 ret = cqhci_init(cq_host, host->mmc, dma64); 236 if (ret) 237 goto cleanup; 238 239 ret = __sdhci_add_host(host); 240 if (ret) 241 goto cleanup; 242 243 return 0; 244 245 cleanup: 246 sdhci_cleanup_host(host); 247 return ret; 248 } 249 250 static int sdhci_brcmstb_probe(struct platform_device *pdev) 251 { 252 const struct brcmstb_match_priv *match_priv; 253 struct sdhci_pltfm_data brcmstb_pdata; 254 struct sdhci_pltfm_host *pltfm_host; 255 const struct of_device_id *match; 256 struct sdhci_brcmstb_priv *priv; 257 u32 actual_clock_mhz; 258 struct sdhci_host *host; 259 struct clk *clk; 260 struct clk *base_clk = NULL; 261 int res; 262 263 match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); 264 match_priv = match->data; 265 266 dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible); 267 268 clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 269 if (IS_ERR(clk)) 270 return dev_err_probe(&pdev->dev, PTR_ERR(clk), 271 "Failed to get and enable clock from Device Tree\n"); 272 273 memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); 274 brcmstb_pdata.ops = match_priv->ops; 275 host = sdhci_pltfm_init(pdev, &brcmstb_pdata, 276 sizeof(struct sdhci_brcmstb_priv)); 277 if (IS_ERR(host)) 278 return PTR_ERR(host); 279 280 pltfm_host = sdhci_priv(host); 281 priv = sdhci_pltfm_priv(pltfm_host); 282 if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 283 priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE; 284 match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; 285 } 286 287 /* Map in the non-standard CFG registers */ 288 priv->cfg_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 289 if (IS_ERR(priv->cfg_regs)) { 290 res = PTR_ERR(priv->cfg_regs); 291 goto err; 292 } 293 294 sdhci_get_of_property(pdev); 295 res = mmc_of_parse(host->mmc); 296 if (res) 297 goto err; 298 299 /* 300 * Automatic clock gating does not work for SD cards that may 301 * voltage switch so only enable it for non-removable devices. 302 */ 303 if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) && 304 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 305 priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK; 306 307 /* 308 * If the chip has enhanced strobe and it's enabled, add 309 * callback 310 */ 311 if (match_priv->hs400es && 312 (host->mmc->caps2 & MMC_CAP2_HS400_ES)) 313 host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; 314 315 /* 316 * Supply the existing CAPS, but clear the UHS modes. This 317 * will allow these modes to be specified by device tree 318 * properties through mmc_of_parse(). 319 */ 320 sdhci_read_caps(host); 321 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT) 322 host->caps &= ~SDHCI_CAN_64BIT; 323 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 324 SDHCI_SUPPORT_DDR50); 325 326 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) 327 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 328 329 if (!(match_priv->flags & BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY)) 330 host->mmc_host_ops.card_busy = NULL; 331 332 /* Change the base clock frequency if the DT property exists */ 333 if (device_property_read_u32(&pdev->dev, "clock-frequency", 334 &priv->base_freq_hz) != 0) 335 goto add_host; 336 337 base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq"); 338 if (IS_ERR(base_clk)) { 339 dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n"); 340 goto add_host; 341 } 342 343 res = clk_prepare_enable(base_clk); 344 if (res) 345 goto err; 346 347 /* set improved clock rate */ 348 clk_set_rate(base_clk, priv->base_freq_hz); 349 actual_clock_mhz = clk_get_rate(base_clk) / 1000000; 350 351 host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; 352 host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT); 353 /* Disable presets because they are now incorrect */ 354 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 355 356 dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n", 357 actual_clock_mhz); 358 priv->base_clk = base_clk; 359 360 add_host: 361 res = sdhci_brcmstb_add_host(host, priv); 362 if (res) 363 goto err; 364 365 pltfm_host->clk = clk; 366 return res; 367 368 err: 369 sdhci_pltfm_free(pdev); 370 clk_disable_unprepare(base_clk); 371 return res; 372 } 373 374 static void sdhci_brcmstb_shutdown(struct platform_device *pdev) 375 { 376 sdhci_pltfm_suspend(&pdev->dev); 377 } 378 379 MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match); 380 381 #ifdef CONFIG_PM_SLEEP 382 static int sdhci_brcmstb_suspend(struct device *dev) 383 { 384 struct sdhci_host *host = dev_get_drvdata(dev); 385 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 386 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 387 388 clk_disable_unprepare(priv->base_clk); 389 return sdhci_pltfm_suspend(dev); 390 } 391 392 static int sdhci_brcmstb_resume(struct device *dev) 393 { 394 struct sdhci_host *host = dev_get_drvdata(dev); 395 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 396 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 397 int ret; 398 399 ret = sdhci_pltfm_resume(dev); 400 if (!ret && priv->base_freq_hz) { 401 ret = clk_prepare_enable(priv->base_clk); 402 /* 403 * Note: using clk_get_rate() below as clk_get_rate() 404 * honors CLK_GET_RATE_NOCACHE attribute, but clk_set_rate() 405 * may do implicit get_rate() calls that do not honor 406 * CLK_GET_RATE_NOCACHE. 407 */ 408 if (!ret && 409 (clk_get_rate(priv->base_clk) != priv->base_freq_hz)) 410 ret = clk_set_rate(priv->base_clk, priv->base_freq_hz); 411 } 412 413 return ret; 414 } 415 #endif 416 417 static const struct dev_pm_ops sdhci_brcmstb_pmops = { 418 SET_SYSTEM_SLEEP_PM_OPS(sdhci_brcmstb_suspend, sdhci_brcmstb_resume) 419 }; 420 421 static struct platform_driver sdhci_brcmstb_driver = { 422 .driver = { 423 .name = "sdhci-brcmstb", 424 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 425 .pm = &sdhci_brcmstb_pmops, 426 .of_match_table = of_match_ptr(sdhci_brcm_of_match), 427 }, 428 .probe = sdhci_brcmstb_probe, 429 .remove_new = sdhci_pltfm_remove, 430 .shutdown = sdhci_brcmstb_shutdown, 431 }; 432 433 module_platform_driver(sdhci_brcmstb_driver); 434 435 MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs"); 436 MODULE_AUTHOR("Broadcom"); 437 MODULE_LICENSE("GPL v2"); 438