11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2476bf3d6SAl Cooper /*
3476bf3d6SAl Cooper * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
4476bf3d6SAl Cooper *
5476bf3d6SAl Cooper * Copyright (C) 2015 Broadcom Corporation
6476bf3d6SAl Cooper */
7476bf3d6SAl Cooper
8476bf3d6SAl Cooper #include <linux/io.h>
9476bf3d6SAl Cooper #include <linux/mmc/host.h>
10476bf3d6SAl Cooper #include <linux/module.h>
11476bf3d6SAl Cooper #include <linux/of.h>
1278ab82fdSAl Cooper #include <linux/bitops.h>
13d46ba2d1SAl Cooper #include <linux/delay.h>
14476bf3d6SAl Cooper
1556baa208SBrian Norris #include "sdhci-cqhci.h"
16476bf3d6SAl Cooper #include "sdhci-pltfm.h"
17d46ba2d1SAl Cooper #include "cqhci.h"
18476bf3d6SAl Cooper
1978ab82fdSAl Cooper #define SDHCI_VENDOR 0x78
2078ab82fdSAl Cooper #define SDHCI_VENDOR_ENHANCED_STRB 0x1
216bcc55feSAl Cooper #define SDHCI_VENDOR_GATE_SDCLK_EN 0x2
2278ab82fdSAl Cooper
23f3a70f99SAl Cooper #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0)
24f3a70f99SAl Cooper #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1)
256bcc55feSAl Cooper #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2)
26f3a70f99SAl Cooper
27f3a70f99SAl Cooper #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0)
286bcc55feSAl Cooper #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1)
2978ab82fdSAl Cooper
30d46ba2d1SAl Cooper #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
31d46ba2d1SAl Cooper
3278ab82fdSAl Cooper struct sdhci_brcmstb_priv {
3378ab82fdSAl Cooper void __iomem *cfg_regs;
34f3a70f99SAl Cooper unsigned int flags;
3597904a59SKamal Dasu struct clk *base_clk;
3697904a59SKamal Dasu u32 base_freq_hz;
3778ab82fdSAl Cooper };
3878ab82fdSAl Cooper
3978ab82fdSAl Cooper struct brcmstb_match_priv {
4078ab82fdSAl Cooper void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
41d46ba2d1SAl Cooper struct sdhci_ops *ops;
42f3a70f99SAl Cooper const unsigned int flags;
4378ab82fdSAl Cooper };
4478ab82fdSAl Cooper
enable_clock_gating(struct sdhci_host * host)456bcc55feSAl Cooper static inline void enable_clock_gating(struct sdhci_host *host)
466bcc55feSAl Cooper {
476bcc55feSAl Cooper u32 reg;
486bcc55feSAl Cooper
496bcc55feSAl Cooper reg = sdhci_readl(host, SDHCI_VENDOR);
506bcc55feSAl Cooper reg |= SDHCI_VENDOR_GATE_SDCLK_EN;
516bcc55feSAl Cooper sdhci_writel(host, reg, SDHCI_VENDOR);
526bcc55feSAl Cooper }
536bcc55feSAl Cooper
brcmstb_reset(struct sdhci_host * host,u8 mask)540c9ee5baSUlf Hansson static void brcmstb_reset(struct sdhci_host *host, u8 mask)
556bcc55feSAl Cooper {
566bcc55feSAl Cooper struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
576bcc55feSAl Cooper struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
586bcc55feSAl Cooper
5956baa208SBrian Norris sdhci_and_cqhci_reset(host, mask);
606bcc55feSAl Cooper
616bcc55feSAl Cooper /* Reset will clear this, so re-enable it */
626bcc55feSAl Cooper if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK)
636bcc55feSAl Cooper enable_clock_gating(host);
646bcc55feSAl Cooper }
656bcc55feSAl Cooper
sdhci_brcmstb_hs400es(struct mmc_host * mmc,struct mmc_ios * ios)6678ab82fdSAl Cooper static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios)
6778ab82fdSAl Cooper {
6878ab82fdSAl Cooper struct sdhci_host *host = mmc_priv(mmc);
6978ab82fdSAl Cooper
7078ab82fdSAl Cooper u32 reg;
7178ab82fdSAl Cooper
7278ab82fdSAl Cooper dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n",
7378ab82fdSAl Cooper __func__);
7478ab82fdSAl Cooper reg = readl(host->ioaddr + SDHCI_VENDOR);
7578ab82fdSAl Cooper if (ios->enhanced_strobe)
7678ab82fdSAl Cooper reg |= SDHCI_VENDOR_ENHANCED_STRB;
7778ab82fdSAl Cooper else
7878ab82fdSAl Cooper reg &= ~SDHCI_VENDOR_ENHANCED_STRB;
7978ab82fdSAl Cooper writel(reg, host->ioaddr + SDHCI_VENDOR);
8078ab82fdSAl Cooper }
8178ab82fdSAl Cooper
sdhci_brcmstb_set_clock(struct sdhci_host * host,unsigned int clock)82d46ba2d1SAl Cooper static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock)
83d46ba2d1SAl Cooper {
84d46ba2d1SAl Cooper u16 clk;
85d46ba2d1SAl Cooper
86d46ba2d1SAl Cooper host->mmc->actual_clock = 0;
87d46ba2d1SAl Cooper
88d46ba2d1SAl Cooper clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
89d46ba2d1SAl Cooper sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
90d46ba2d1SAl Cooper
91d46ba2d1SAl Cooper if (clock == 0)
92d46ba2d1SAl Cooper return;
93d46ba2d1SAl Cooper
94d46ba2d1SAl Cooper sdhci_enable_clk(host, clk);
95d46ba2d1SAl Cooper }
96d46ba2d1SAl Cooper
sdhci_brcmstb_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)972fefc7c5SAl Cooper static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host,
982fefc7c5SAl Cooper unsigned int timing)
992fefc7c5SAl Cooper {
1002fefc7c5SAl Cooper u16 ctrl_2;
1012fefc7c5SAl Cooper
1022fefc7c5SAl Cooper dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n",
1032fefc7c5SAl Cooper __func__, timing);
1042fefc7c5SAl Cooper ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1052fefc7c5SAl Cooper /* Select Bus Speed Mode for host */
1062fefc7c5SAl Cooper ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1072fefc7c5SAl Cooper if ((timing == MMC_TIMING_MMC_HS200) ||
1082fefc7c5SAl Cooper (timing == MMC_TIMING_UHS_SDR104))
1092fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1102fefc7c5SAl Cooper else if (timing == MMC_TIMING_UHS_SDR12)
1112fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1122fefc7c5SAl Cooper else if (timing == MMC_TIMING_SD_HS ||
1132fefc7c5SAl Cooper timing == MMC_TIMING_MMC_HS ||
1142fefc7c5SAl Cooper timing == MMC_TIMING_UHS_SDR25)
1152fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1162fefc7c5SAl Cooper else if (timing == MMC_TIMING_UHS_SDR50)
1172fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1182fefc7c5SAl Cooper else if ((timing == MMC_TIMING_UHS_DDR50) ||
1192fefc7c5SAl Cooper (timing == MMC_TIMING_MMC_DDR52))
1202fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1212fefc7c5SAl Cooper else if (timing == MMC_TIMING_MMC_HS400)
1222fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1232fefc7c5SAl Cooper sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1242fefc7c5SAl Cooper }
1252fefc7c5SAl Cooper
sdhci_brcmstb_dumpregs(struct mmc_host * mmc)126d46ba2d1SAl Cooper static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc)
127d46ba2d1SAl Cooper {
128d46ba2d1SAl Cooper sdhci_dumpregs(mmc_priv(mmc));
129d46ba2d1SAl Cooper }
130d46ba2d1SAl Cooper
sdhci_brcmstb_cqe_enable(struct mmc_host * mmc)131d46ba2d1SAl Cooper static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc)
132d46ba2d1SAl Cooper {
133d46ba2d1SAl Cooper struct sdhci_host *host = mmc_priv(mmc);
134d46ba2d1SAl Cooper u32 reg;
135d46ba2d1SAl Cooper
136d46ba2d1SAl Cooper reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
137d46ba2d1SAl Cooper while (reg & SDHCI_DATA_AVAILABLE) {
138d46ba2d1SAl Cooper sdhci_readl(host, SDHCI_BUFFER);
139d46ba2d1SAl Cooper reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
140d46ba2d1SAl Cooper }
141d46ba2d1SAl Cooper
142d46ba2d1SAl Cooper sdhci_cqe_enable(mmc);
143d46ba2d1SAl Cooper }
144d46ba2d1SAl Cooper
145d46ba2d1SAl Cooper static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = {
146d46ba2d1SAl Cooper .enable = sdhci_brcmstb_cqe_enable,
147d46ba2d1SAl Cooper .disable = sdhci_cqe_disable,
148d46ba2d1SAl Cooper .dumpregs = sdhci_brcmstb_dumpregs,
149d46ba2d1SAl Cooper };
150d46ba2d1SAl Cooper
151d46ba2d1SAl Cooper static struct sdhci_ops sdhci_brcmstb_ops = {
152476bf3d6SAl Cooper .set_clock = sdhci_set_clock,
153476bf3d6SAl Cooper .set_bus_width = sdhci_set_bus_width,
154476bf3d6SAl Cooper .reset = sdhci_reset,
155476bf3d6SAl Cooper .set_uhs_signaling = sdhci_set_uhs_signaling,
156476bf3d6SAl Cooper };
157476bf3d6SAl Cooper
158d46ba2d1SAl Cooper static struct sdhci_ops sdhci_brcmstb_ops_7216 = {
159d46ba2d1SAl Cooper .set_clock = sdhci_brcmstb_set_clock,
160d46ba2d1SAl Cooper .set_bus_width = sdhci_set_bus_width,
1616bcc55feSAl Cooper .reset = brcmstb_reset,
1622fefc7c5SAl Cooper .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,
163d46ba2d1SAl Cooper };
164d46ba2d1SAl Cooper
165d46ba2d1SAl Cooper static struct brcmstb_match_priv match_priv_7425 = {
166f3a70f99SAl Cooper .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT |
167f3a70f99SAl Cooper BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
168476bf3d6SAl Cooper .ops = &sdhci_brcmstb_ops,
169476bf3d6SAl Cooper };
170476bf3d6SAl Cooper
171d46ba2d1SAl Cooper static struct brcmstb_match_priv match_priv_7445 = {
172f3a70f99SAl Cooper .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
173d46ba2d1SAl Cooper .ops = &sdhci_brcmstb_ops,
17478ab82fdSAl Cooper };
17578ab82fdSAl Cooper
17678ab82fdSAl Cooper static const struct brcmstb_match_priv match_priv_7216 = {
1776bcc55feSAl Cooper .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
17878ab82fdSAl Cooper .hs400es = sdhci_brcmstb_hs400es,
179d46ba2d1SAl Cooper .ops = &sdhci_brcmstb_ops_7216,
18078ab82fdSAl Cooper };
18178ab82fdSAl Cooper
182a234442cSBrian Norris static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = {
18378ab82fdSAl Cooper { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
18478ab82fdSAl Cooper { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
18578ab82fdSAl Cooper { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
18678ab82fdSAl Cooper {},
18778ab82fdSAl Cooper };
18878ab82fdSAl Cooper
sdhci_brcmstb_cqhci_irq(struct sdhci_host * host,u32 intmask)189d46ba2d1SAl Cooper static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask)
190d46ba2d1SAl Cooper {
191d46ba2d1SAl Cooper int cmd_error = 0;
192d46ba2d1SAl Cooper int data_error = 0;
193d46ba2d1SAl Cooper
194d46ba2d1SAl Cooper if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
195d46ba2d1SAl Cooper return intmask;
196d46ba2d1SAl Cooper
197d46ba2d1SAl Cooper cqhci_irq(host->mmc, intmask, cmd_error, data_error);
198d46ba2d1SAl Cooper
199d46ba2d1SAl Cooper return 0;
200d46ba2d1SAl Cooper }
201d46ba2d1SAl Cooper
sdhci_brcmstb_add_host(struct sdhci_host * host,struct sdhci_brcmstb_priv * priv)202d46ba2d1SAl Cooper static int sdhci_brcmstb_add_host(struct sdhci_host *host,
203d46ba2d1SAl Cooper struct sdhci_brcmstb_priv *priv)
204d46ba2d1SAl Cooper {
205d46ba2d1SAl Cooper struct cqhci_host *cq_host;
206d46ba2d1SAl Cooper bool dma64;
207d46ba2d1SAl Cooper int ret;
208d46ba2d1SAl Cooper
209f3a70f99SAl Cooper if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0)
210d46ba2d1SAl Cooper return sdhci_add_host(host);
211d46ba2d1SAl Cooper
212d46ba2d1SAl Cooper dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n");
213d46ba2d1SAl Cooper host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
214d46ba2d1SAl Cooper ret = sdhci_setup_host(host);
215d46ba2d1SAl Cooper if (ret)
216d46ba2d1SAl Cooper return ret;
217d46ba2d1SAl Cooper
218d46ba2d1SAl Cooper cq_host = devm_kzalloc(mmc_dev(host->mmc),
219d46ba2d1SAl Cooper sizeof(*cq_host), GFP_KERNEL);
220d46ba2d1SAl Cooper if (!cq_host) {
221d46ba2d1SAl Cooper ret = -ENOMEM;
222d46ba2d1SAl Cooper goto cleanup;
223d46ba2d1SAl Cooper }
224d46ba2d1SAl Cooper
225d46ba2d1SAl Cooper cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
226d46ba2d1SAl Cooper cq_host->ops = &sdhci_brcmstb_cqhci_ops;
227d46ba2d1SAl Cooper
228d46ba2d1SAl Cooper dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
229d46ba2d1SAl Cooper if (dma64) {
230d46ba2d1SAl Cooper dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n");
231d46ba2d1SAl Cooper cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
232d46ba2d1SAl Cooper }
233d46ba2d1SAl Cooper
234d46ba2d1SAl Cooper ret = cqhci_init(cq_host, host->mmc, dma64);
235d46ba2d1SAl Cooper if (ret)
236d46ba2d1SAl Cooper goto cleanup;
237d46ba2d1SAl Cooper
238d46ba2d1SAl Cooper ret = __sdhci_add_host(host);
239d46ba2d1SAl Cooper if (ret)
240d46ba2d1SAl Cooper goto cleanup;
241d46ba2d1SAl Cooper
242d46ba2d1SAl Cooper return 0;
243d46ba2d1SAl Cooper
244d46ba2d1SAl Cooper cleanup:
245d46ba2d1SAl Cooper sdhci_cleanup_host(host);
246d46ba2d1SAl Cooper return ret;
247d46ba2d1SAl Cooper }
248d46ba2d1SAl Cooper
sdhci_brcmstb_probe(struct platform_device * pdev)249476bf3d6SAl Cooper static int sdhci_brcmstb_probe(struct platform_device *pdev)
250476bf3d6SAl Cooper {
25178ab82fdSAl Cooper const struct brcmstb_match_priv *match_priv;
252d46ba2d1SAl Cooper struct sdhci_pltfm_data brcmstb_pdata;
253476bf3d6SAl Cooper struct sdhci_pltfm_host *pltfm_host;
25478ab82fdSAl Cooper const struct of_device_id *match;
25578ab82fdSAl Cooper struct sdhci_brcmstb_priv *priv;
25697904a59SKamal Dasu u32 actual_clock_mhz;
25778ab82fdSAl Cooper struct sdhci_host *host;
258476bf3d6SAl Cooper struct clk *clk;
259c3c0ed75SNathan Chancellor struct clk *base_clk = NULL;
260476bf3d6SAl Cooper int res;
261476bf3d6SAl Cooper
26278ab82fdSAl Cooper match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node);
26378ab82fdSAl Cooper match_priv = match->data;
26478ab82fdSAl Cooper
265d46ba2d1SAl Cooper dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible);
266d46ba2d1SAl Cooper
267*b6c90da3SAdrian Hunter clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
268b41123f4SKrzysztof Kozlowski if (IS_ERR(clk))
269b41123f4SKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(clk),
270*b6c90da3SAdrian Hunter "Failed to get and enable clock from Device Tree\n");
271476bf3d6SAl Cooper
272d46ba2d1SAl Cooper memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata));
273d46ba2d1SAl Cooper brcmstb_pdata.ops = match_priv->ops;
274d46ba2d1SAl Cooper host = sdhci_pltfm_init(pdev, &brcmstb_pdata,
27578ab82fdSAl Cooper sizeof(struct sdhci_brcmstb_priv));
276*b6c90da3SAdrian Hunter if (IS_ERR(host))
277*b6c90da3SAdrian Hunter return PTR_ERR(host);
278476bf3d6SAl Cooper
27978ab82fdSAl Cooper pltfm_host = sdhci_priv(host);
28078ab82fdSAl Cooper priv = sdhci_pltfm_priv(pltfm_host);
281f3a70f99SAl Cooper if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
282f3a70f99SAl Cooper priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;
283f3a70f99SAl Cooper match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
284f3a70f99SAl Cooper }
28578ab82fdSAl Cooper
28678ab82fdSAl Cooper /* Map in the non-standard CFG registers */
28708623d74SYe Xingchen priv->cfg_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
28878ab82fdSAl Cooper if (IS_ERR(priv->cfg_regs)) {
28978ab82fdSAl Cooper res = PTR_ERR(priv->cfg_regs);
29078ab82fdSAl Cooper goto err;
29178ab82fdSAl Cooper }
29278ab82fdSAl Cooper
293476bf3d6SAl Cooper sdhci_get_of_property(pdev);
2941e20186eSStefan Wahren res = mmc_of_parse(host->mmc);
2951e20186eSStefan Wahren if (res)
2961e20186eSStefan Wahren goto err;
297476bf3d6SAl Cooper
298476bf3d6SAl Cooper /*
2996bcc55feSAl Cooper * Automatic clock gating does not work for SD cards that may
3006bcc55feSAl Cooper * voltage switch so only enable it for non-removable devices.
3016bcc55feSAl Cooper */
3026bcc55feSAl Cooper if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) &&
3036bcc55feSAl Cooper (host->mmc->caps & MMC_CAP_NONREMOVABLE))
3046bcc55feSAl Cooper priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK;
3056bcc55feSAl Cooper
3066bcc55feSAl Cooper /*
30778ab82fdSAl Cooper * If the chip has enhanced strobe and it's enabled, add
30878ab82fdSAl Cooper * callback
30978ab82fdSAl Cooper */
31078ab82fdSAl Cooper if (match_priv->hs400es &&
31178ab82fdSAl Cooper (host->mmc->caps2 & MMC_CAP2_HS400_ES))
31278ab82fdSAl Cooper host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es;
31378ab82fdSAl Cooper
31478ab82fdSAl Cooper /*
315476bf3d6SAl Cooper * Supply the existing CAPS, but clear the UHS modes. This
316476bf3d6SAl Cooper * will allow these modes to be specified by device tree
317476bf3d6SAl Cooper * properties through mmc_of_parse().
318476bf3d6SAl Cooper */
319759329edSAdrian Hunter sdhci_read_caps(host);
320f3a70f99SAl Cooper if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT)
3216a3d8cedSJaedon Shin host->caps &= ~SDHCI_CAN_64BIT;
322476bf3d6SAl Cooper host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
323476bf3d6SAl Cooper SDHCI_SUPPORT_DDR50);
32478ab82fdSAl Cooper
325f3a70f99SAl Cooper if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT)
32678ab82fdSAl Cooper host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
327476bf3d6SAl Cooper
32897904a59SKamal Dasu /* Change the base clock frequency if the DT property exists */
32997904a59SKamal Dasu if (device_property_read_u32(&pdev->dev, "clock-frequency",
33097904a59SKamal Dasu &priv->base_freq_hz) != 0)
33197904a59SKamal Dasu goto add_host;
33297904a59SKamal Dasu
33397904a59SKamal Dasu base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq");
33497904a59SKamal Dasu if (IS_ERR(base_clk)) {
33597904a59SKamal Dasu dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n");
33697904a59SKamal Dasu goto add_host;
33797904a59SKamal Dasu }
33897904a59SKamal Dasu
33997904a59SKamal Dasu res = clk_prepare_enable(base_clk);
34097904a59SKamal Dasu if (res)
34197904a59SKamal Dasu goto err;
34297904a59SKamal Dasu
34397904a59SKamal Dasu /* set improved clock rate */
34497904a59SKamal Dasu clk_set_rate(base_clk, priv->base_freq_hz);
34597904a59SKamal Dasu actual_clock_mhz = clk_get_rate(base_clk) / 1000000;
34697904a59SKamal Dasu
34797904a59SKamal Dasu host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK;
34897904a59SKamal Dasu host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT);
34997904a59SKamal Dasu /* Disable presets because they are now incorrect */
35097904a59SKamal Dasu host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
35197904a59SKamal Dasu
35297904a59SKamal Dasu dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n",
35397904a59SKamal Dasu actual_clock_mhz);
35497904a59SKamal Dasu priv->base_clk = base_clk;
35597904a59SKamal Dasu
35697904a59SKamal Dasu add_host:
357d46ba2d1SAl Cooper res = sdhci_brcmstb_add_host(host, priv);
358476bf3d6SAl Cooper if (res)
359476bf3d6SAl Cooper goto err;
360476bf3d6SAl Cooper
361476bf3d6SAl Cooper pltfm_host->clk = clk;
362476bf3d6SAl Cooper return res;
363476bf3d6SAl Cooper
364476bf3d6SAl Cooper err:
365476bf3d6SAl Cooper sdhci_pltfm_free(pdev);
36697904a59SKamal Dasu clk_disable_unprepare(base_clk);
367476bf3d6SAl Cooper return res;
368476bf3d6SAl Cooper }
369476bf3d6SAl Cooper
sdhci_brcmstb_shutdown(struct platform_device * pdev)370e7b5d63aSAl Cooper static void sdhci_brcmstb_shutdown(struct platform_device *pdev)
371e7b5d63aSAl Cooper {
3725b191dcbSAl Cooper sdhci_pltfm_suspend(&pdev->dev);
373e7b5d63aSAl Cooper }
374e7b5d63aSAl Cooper
375476bf3d6SAl Cooper MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match);
376476bf3d6SAl Cooper
37797904a59SKamal Dasu #ifdef CONFIG_PM_SLEEP
sdhci_brcmstb_suspend(struct device * dev)37897904a59SKamal Dasu static int sdhci_brcmstb_suspend(struct device *dev)
37997904a59SKamal Dasu {
38097904a59SKamal Dasu struct sdhci_host *host = dev_get_drvdata(dev);
38197904a59SKamal Dasu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
38297904a59SKamal Dasu struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
38397904a59SKamal Dasu
38497904a59SKamal Dasu clk_disable_unprepare(priv->base_clk);
38597904a59SKamal Dasu return sdhci_pltfm_suspend(dev);
38697904a59SKamal Dasu }
38797904a59SKamal Dasu
sdhci_brcmstb_resume(struct device * dev)38897904a59SKamal Dasu static int sdhci_brcmstb_resume(struct device *dev)
38997904a59SKamal Dasu {
39097904a59SKamal Dasu struct sdhci_host *host = dev_get_drvdata(dev);
39197904a59SKamal Dasu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
39297904a59SKamal Dasu struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
39397904a59SKamal Dasu int ret;
39497904a59SKamal Dasu
39597904a59SKamal Dasu ret = sdhci_pltfm_resume(dev);
39697904a59SKamal Dasu if (!ret && priv->base_freq_hz) {
39797904a59SKamal Dasu ret = clk_prepare_enable(priv->base_clk);
398886201c7SKamal Dasu /*
399886201c7SKamal Dasu * Note: using clk_get_rate() below as clk_get_rate()
400886201c7SKamal Dasu * honors CLK_GET_RATE_NOCACHE attribute, but clk_set_rate()
401886201c7SKamal Dasu * may do implicit get_rate() calls that do not honor
402886201c7SKamal Dasu * CLK_GET_RATE_NOCACHE.
403886201c7SKamal Dasu */
404886201c7SKamal Dasu if (!ret &&
405886201c7SKamal Dasu (clk_get_rate(priv->base_clk) != priv->base_freq_hz))
40697904a59SKamal Dasu ret = clk_set_rate(priv->base_clk, priv->base_freq_hz);
40797904a59SKamal Dasu }
40897904a59SKamal Dasu
40997904a59SKamal Dasu return ret;
41097904a59SKamal Dasu }
41197904a59SKamal Dasu #endif
41297904a59SKamal Dasu
41397904a59SKamal Dasu static const struct dev_pm_ops sdhci_brcmstb_pmops = {
41497904a59SKamal Dasu SET_SYSTEM_SLEEP_PM_OPS(sdhci_brcmstb_suspend, sdhci_brcmstb_resume)
41597904a59SKamal Dasu };
41697904a59SKamal Dasu
417476bf3d6SAl Cooper static struct platform_driver sdhci_brcmstb_driver = {
418476bf3d6SAl Cooper .driver = {
419476bf3d6SAl Cooper .name = "sdhci-brcmstb",
4202a99f3faSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
42197904a59SKamal Dasu .pm = &sdhci_brcmstb_pmops,
422476bf3d6SAl Cooper .of_match_table = of_match_ptr(sdhci_brcm_of_match),
423476bf3d6SAl Cooper },
424476bf3d6SAl Cooper .probe = sdhci_brcmstb_probe,
425*b6c90da3SAdrian Hunter .remove_new = sdhci_pltfm_remove,
426e7b5d63aSAl Cooper .shutdown = sdhci_brcmstb_shutdown,
427476bf3d6SAl Cooper };
428476bf3d6SAl Cooper
429476bf3d6SAl Cooper module_platform_driver(sdhci_brcmstb_driver);
430476bf3d6SAl Cooper
431476bf3d6SAl Cooper MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs");
432476bf3d6SAl Cooper MODULE_AUTHOR("Broadcom");
433476bf3d6SAl Cooper MODULE_LICENSE("GPL v2");
434