11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2476bf3d6SAl Cooper /* 3476bf3d6SAl Cooper * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's 4476bf3d6SAl Cooper * 5476bf3d6SAl Cooper * Copyright (C) 2015 Broadcom Corporation 6476bf3d6SAl Cooper */ 7476bf3d6SAl Cooper 8476bf3d6SAl Cooper #include <linux/io.h> 9476bf3d6SAl Cooper #include <linux/mmc/host.h> 10476bf3d6SAl Cooper #include <linux/module.h> 11476bf3d6SAl Cooper #include <linux/of.h> 1278ab82fdSAl Cooper #include <linux/bitops.h> 13d46ba2d1SAl Cooper #include <linux/delay.h> 14476bf3d6SAl Cooper 15476bf3d6SAl Cooper #include "sdhci-pltfm.h" 16d46ba2d1SAl Cooper #include "cqhci.h" 17476bf3d6SAl Cooper 1878ab82fdSAl Cooper #define SDHCI_VENDOR 0x78 1978ab82fdSAl Cooper #define SDHCI_VENDOR_ENHANCED_STRB 0x1 2078ab82fdSAl Cooper 2178ab82fdSAl Cooper #define BRCMSTB_PRIV_FLAGS_NO_64BIT BIT(0) 2278ab82fdSAl Cooper #define BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT BIT(1) 2378ab82fdSAl Cooper 24d46ba2d1SAl Cooper #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 25d46ba2d1SAl Cooper 2678ab82fdSAl Cooper struct sdhci_brcmstb_priv { 2778ab82fdSAl Cooper void __iomem *cfg_regs; 28d46ba2d1SAl Cooper bool has_cqe; 2978ab82fdSAl Cooper }; 3078ab82fdSAl Cooper 3178ab82fdSAl Cooper struct brcmstb_match_priv { 3278ab82fdSAl Cooper void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); 33d46ba2d1SAl Cooper struct sdhci_ops *ops; 3478ab82fdSAl Cooper unsigned int flags; 3578ab82fdSAl Cooper }; 3678ab82fdSAl Cooper 3778ab82fdSAl Cooper static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) 3878ab82fdSAl Cooper { 3978ab82fdSAl Cooper struct sdhci_host *host = mmc_priv(mmc); 4078ab82fdSAl Cooper 4178ab82fdSAl Cooper u32 reg; 4278ab82fdSAl Cooper 4378ab82fdSAl Cooper dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n", 4478ab82fdSAl Cooper __func__); 4578ab82fdSAl Cooper reg = readl(host->ioaddr + SDHCI_VENDOR); 4678ab82fdSAl Cooper if (ios->enhanced_strobe) 4778ab82fdSAl Cooper reg |= SDHCI_VENDOR_ENHANCED_STRB; 4878ab82fdSAl Cooper else 4978ab82fdSAl Cooper reg &= ~SDHCI_VENDOR_ENHANCED_STRB; 5078ab82fdSAl Cooper writel(reg, host->ioaddr + SDHCI_VENDOR); 5178ab82fdSAl Cooper } 5278ab82fdSAl Cooper 53d46ba2d1SAl Cooper static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) 54d46ba2d1SAl Cooper { 55d46ba2d1SAl Cooper u16 clk; 56d46ba2d1SAl Cooper 57d46ba2d1SAl Cooper host->mmc->actual_clock = 0; 58d46ba2d1SAl Cooper 59d46ba2d1SAl Cooper clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 60d46ba2d1SAl Cooper sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 61d46ba2d1SAl Cooper 62d46ba2d1SAl Cooper if (clock == 0) 63d46ba2d1SAl Cooper return; 64d46ba2d1SAl Cooper 65d46ba2d1SAl Cooper sdhci_enable_clk(host, clk); 66d46ba2d1SAl Cooper } 67d46ba2d1SAl Cooper 682fefc7c5SAl Cooper static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, 692fefc7c5SAl Cooper unsigned int timing) 702fefc7c5SAl Cooper { 712fefc7c5SAl Cooper u16 ctrl_2; 722fefc7c5SAl Cooper 732fefc7c5SAl Cooper dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n", 742fefc7c5SAl Cooper __func__, timing); 752fefc7c5SAl Cooper ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 762fefc7c5SAl Cooper /* Select Bus Speed Mode for host */ 772fefc7c5SAl Cooper ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 782fefc7c5SAl Cooper if ((timing == MMC_TIMING_MMC_HS200) || 792fefc7c5SAl Cooper (timing == MMC_TIMING_UHS_SDR104)) 802fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 812fefc7c5SAl Cooper else if (timing == MMC_TIMING_UHS_SDR12) 822fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 832fefc7c5SAl Cooper else if (timing == MMC_TIMING_SD_HS || 842fefc7c5SAl Cooper timing == MMC_TIMING_MMC_HS || 852fefc7c5SAl Cooper timing == MMC_TIMING_UHS_SDR25) 862fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 872fefc7c5SAl Cooper else if (timing == MMC_TIMING_UHS_SDR50) 882fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 892fefc7c5SAl Cooper else if ((timing == MMC_TIMING_UHS_DDR50) || 902fefc7c5SAl Cooper (timing == MMC_TIMING_MMC_DDR52)) 912fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 922fefc7c5SAl Cooper else if (timing == MMC_TIMING_MMC_HS400) 932fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 942fefc7c5SAl Cooper sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 952fefc7c5SAl Cooper } 962fefc7c5SAl Cooper 97d46ba2d1SAl Cooper static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) 98d46ba2d1SAl Cooper { 99d46ba2d1SAl Cooper sdhci_dumpregs(mmc_priv(mmc)); 100d46ba2d1SAl Cooper } 101d46ba2d1SAl Cooper 102d46ba2d1SAl Cooper static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc) 103d46ba2d1SAl Cooper { 104d46ba2d1SAl Cooper struct sdhci_host *host = mmc_priv(mmc); 105d46ba2d1SAl Cooper u32 reg; 106d46ba2d1SAl Cooper 107d46ba2d1SAl Cooper reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 108d46ba2d1SAl Cooper while (reg & SDHCI_DATA_AVAILABLE) { 109d46ba2d1SAl Cooper sdhci_readl(host, SDHCI_BUFFER); 110d46ba2d1SAl Cooper reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 111d46ba2d1SAl Cooper } 112d46ba2d1SAl Cooper 113d46ba2d1SAl Cooper sdhci_cqe_enable(mmc); 114d46ba2d1SAl Cooper } 115d46ba2d1SAl Cooper 116d46ba2d1SAl Cooper static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = { 117d46ba2d1SAl Cooper .enable = sdhci_brcmstb_cqe_enable, 118d46ba2d1SAl Cooper .disable = sdhci_cqe_disable, 119d46ba2d1SAl Cooper .dumpregs = sdhci_brcmstb_dumpregs, 120d46ba2d1SAl Cooper }; 121d46ba2d1SAl Cooper 122d46ba2d1SAl Cooper static struct sdhci_ops sdhci_brcmstb_ops = { 123476bf3d6SAl Cooper .set_clock = sdhci_set_clock, 124476bf3d6SAl Cooper .set_bus_width = sdhci_set_bus_width, 125476bf3d6SAl Cooper .reset = sdhci_reset, 126476bf3d6SAl Cooper .set_uhs_signaling = sdhci_set_uhs_signaling, 127476bf3d6SAl Cooper }; 128476bf3d6SAl Cooper 129d46ba2d1SAl Cooper static struct sdhci_ops sdhci_brcmstb_ops_7216 = { 130d46ba2d1SAl Cooper .set_clock = sdhci_brcmstb_set_clock, 131d46ba2d1SAl Cooper .set_bus_width = sdhci_set_bus_width, 132d46ba2d1SAl Cooper .reset = sdhci_reset, 1332fefc7c5SAl Cooper .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, 134d46ba2d1SAl Cooper }; 135d46ba2d1SAl Cooper 136d46ba2d1SAl Cooper static struct brcmstb_match_priv match_priv_7425 = { 137d46ba2d1SAl Cooper .flags = BRCMSTB_PRIV_FLAGS_NO_64BIT | 138d46ba2d1SAl Cooper BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, 139476bf3d6SAl Cooper .ops = &sdhci_brcmstb_ops, 140476bf3d6SAl Cooper }; 141476bf3d6SAl Cooper 142d46ba2d1SAl Cooper static struct brcmstb_match_priv match_priv_7445 = { 14378ab82fdSAl Cooper .flags = BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, 144d46ba2d1SAl Cooper .ops = &sdhci_brcmstb_ops, 14578ab82fdSAl Cooper }; 14678ab82fdSAl Cooper 14778ab82fdSAl Cooper static const struct brcmstb_match_priv match_priv_7216 = { 14878ab82fdSAl Cooper .hs400es = sdhci_brcmstb_hs400es, 149d46ba2d1SAl Cooper .ops = &sdhci_brcmstb_ops_7216, 15078ab82fdSAl Cooper }; 15178ab82fdSAl Cooper 15278ab82fdSAl Cooper static const struct of_device_id sdhci_brcm_of_match[] = { 15378ab82fdSAl Cooper { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, 15478ab82fdSAl Cooper { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, 15578ab82fdSAl Cooper { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, 15678ab82fdSAl Cooper {}, 15778ab82fdSAl Cooper }; 15878ab82fdSAl Cooper 159d46ba2d1SAl Cooper static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask) 160d46ba2d1SAl Cooper { 161d46ba2d1SAl Cooper int cmd_error = 0; 162d46ba2d1SAl Cooper int data_error = 0; 163d46ba2d1SAl Cooper 164d46ba2d1SAl Cooper if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 165d46ba2d1SAl Cooper return intmask; 166d46ba2d1SAl Cooper 167d46ba2d1SAl Cooper cqhci_irq(host->mmc, intmask, cmd_error, data_error); 168d46ba2d1SAl Cooper 169d46ba2d1SAl Cooper return 0; 170d46ba2d1SAl Cooper } 171d46ba2d1SAl Cooper 172d46ba2d1SAl Cooper static int sdhci_brcmstb_add_host(struct sdhci_host *host, 173d46ba2d1SAl Cooper struct sdhci_brcmstb_priv *priv) 174d46ba2d1SAl Cooper { 175d46ba2d1SAl Cooper struct cqhci_host *cq_host; 176d46ba2d1SAl Cooper bool dma64; 177d46ba2d1SAl Cooper int ret; 178d46ba2d1SAl Cooper 179d46ba2d1SAl Cooper if (!priv->has_cqe) 180d46ba2d1SAl Cooper return sdhci_add_host(host); 181d46ba2d1SAl Cooper 182d46ba2d1SAl Cooper dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); 183d46ba2d1SAl Cooper host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 184d46ba2d1SAl Cooper ret = sdhci_setup_host(host); 185d46ba2d1SAl Cooper if (ret) 186d46ba2d1SAl Cooper return ret; 187d46ba2d1SAl Cooper 188d46ba2d1SAl Cooper cq_host = devm_kzalloc(mmc_dev(host->mmc), 189d46ba2d1SAl Cooper sizeof(*cq_host), GFP_KERNEL); 190d46ba2d1SAl Cooper if (!cq_host) { 191d46ba2d1SAl Cooper ret = -ENOMEM; 192d46ba2d1SAl Cooper goto cleanup; 193d46ba2d1SAl Cooper } 194d46ba2d1SAl Cooper 195d46ba2d1SAl Cooper cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 196d46ba2d1SAl Cooper cq_host->ops = &sdhci_brcmstb_cqhci_ops; 197d46ba2d1SAl Cooper 198d46ba2d1SAl Cooper dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 199d46ba2d1SAl Cooper if (dma64) { 200d46ba2d1SAl Cooper dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n"); 201d46ba2d1SAl Cooper cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 202d46ba2d1SAl Cooper cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 203d46ba2d1SAl Cooper } 204d46ba2d1SAl Cooper 205d46ba2d1SAl Cooper ret = cqhci_init(cq_host, host->mmc, dma64); 206d46ba2d1SAl Cooper if (ret) 207d46ba2d1SAl Cooper goto cleanup; 208d46ba2d1SAl Cooper 209d46ba2d1SAl Cooper ret = __sdhci_add_host(host); 210d46ba2d1SAl Cooper if (ret) 211d46ba2d1SAl Cooper goto cleanup; 212d46ba2d1SAl Cooper 213d46ba2d1SAl Cooper return 0; 214d46ba2d1SAl Cooper 215d46ba2d1SAl Cooper cleanup: 216d46ba2d1SAl Cooper sdhci_cleanup_host(host); 217d46ba2d1SAl Cooper return ret; 218d46ba2d1SAl Cooper } 219d46ba2d1SAl Cooper 220476bf3d6SAl Cooper static int sdhci_brcmstb_probe(struct platform_device *pdev) 221476bf3d6SAl Cooper { 22278ab82fdSAl Cooper const struct brcmstb_match_priv *match_priv; 223d46ba2d1SAl Cooper struct sdhci_pltfm_data brcmstb_pdata; 224476bf3d6SAl Cooper struct sdhci_pltfm_host *pltfm_host; 22578ab82fdSAl Cooper const struct of_device_id *match; 22678ab82fdSAl Cooper struct sdhci_brcmstb_priv *priv; 22778ab82fdSAl Cooper struct sdhci_host *host; 22878ab82fdSAl Cooper struct resource *iomem; 229d46ba2d1SAl Cooper bool has_cqe = false; 230476bf3d6SAl Cooper struct clk *clk; 231476bf3d6SAl Cooper int res; 232476bf3d6SAl Cooper 23378ab82fdSAl Cooper match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); 23478ab82fdSAl Cooper match_priv = match->data; 23578ab82fdSAl Cooper 236d46ba2d1SAl Cooper dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible); 237d46ba2d1SAl Cooper 238*b41123f4SKrzysztof Kozlowski clk = devm_clk_get_optional(&pdev->dev, NULL); 239*b41123f4SKrzysztof Kozlowski if (IS_ERR(clk)) 240*b41123f4SKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(clk), 241*b41123f4SKrzysztof Kozlowski "Failed to get clock from Device Tree\n"); 242*b41123f4SKrzysztof Kozlowski 243476bf3d6SAl Cooper res = clk_prepare_enable(clk); 244476bf3d6SAl Cooper if (res) 245476bf3d6SAl Cooper return res; 246476bf3d6SAl Cooper 247d46ba2d1SAl Cooper memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); 248d46ba2d1SAl Cooper if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 249d46ba2d1SAl Cooper has_cqe = true; 250d46ba2d1SAl Cooper match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; 251d46ba2d1SAl Cooper } 252d46ba2d1SAl Cooper brcmstb_pdata.ops = match_priv->ops; 253d46ba2d1SAl Cooper host = sdhci_pltfm_init(pdev, &brcmstb_pdata, 25478ab82fdSAl Cooper sizeof(struct sdhci_brcmstb_priv)); 255476bf3d6SAl Cooper if (IS_ERR(host)) { 256476bf3d6SAl Cooper res = PTR_ERR(host); 257476bf3d6SAl Cooper goto err_clk; 258476bf3d6SAl Cooper } 259476bf3d6SAl Cooper 26078ab82fdSAl Cooper pltfm_host = sdhci_priv(host); 26178ab82fdSAl Cooper priv = sdhci_pltfm_priv(pltfm_host); 262d46ba2d1SAl Cooper priv->has_cqe = has_cqe; 26378ab82fdSAl Cooper 26478ab82fdSAl Cooper /* Map in the non-standard CFG registers */ 26578ab82fdSAl Cooper iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 26678ab82fdSAl Cooper priv->cfg_regs = devm_ioremap_resource(&pdev->dev, iomem); 26778ab82fdSAl Cooper if (IS_ERR(priv->cfg_regs)) { 26878ab82fdSAl Cooper res = PTR_ERR(priv->cfg_regs); 26978ab82fdSAl Cooper goto err; 27078ab82fdSAl Cooper } 27178ab82fdSAl Cooper 272476bf3d6SAl Cooper sdhci_get_of_property(pdev); 2731e20186eSStefan Wahren res = mmc_of_parse(host->mmc); 2741e20186eSStefan Wahren if (res) 2751e20186eSStefan Wahren goto err; 276476bf3d6SAl Cooper 277476bf3d6SAl Cooper /* 27878ab82fdSAl Cooper * If the chip has enhanced strobe and it's enabled, add 27978ab82fdSAl Cooper * callback 28078ab82fdSAl Cooper */ 28178ab82fdSAl Cooper if (match_priv->hs400es && 28278ab82fdSAl Cooper (host->mmc->caps2 & MMC_CAP2_HS400_ES)) 28378ab82fdSAl Cooper host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; 28478ab82fdSAl Cooper 28578ab82fdSAl Cooper /* 286476bf3d6SAl Cooper * Supply the existing CAPS, but clear the UHS modes. This 287476bf3d6SAl Cooper * will allow these modes to be specified by device tree 288476bf3d6SAl Cooper * properties through mmc_of_parse(). 289476bf3d6SAl Cooper */ 290476bf3d6SAl Cooper host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); 29178ab82fdSAl Cooper if (match_priv->flags & BRCMSTB_PRIV_FLAGS_NO_64BIT) 2926a3d8cedSJaedon Shin host->caps &= ~SDHCI_CAN_64BIT; 293476bf3d6SAl Cooper host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 294476bf3d6SAl Cooper host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 295476bf3d6SAl Cooper SDHCI_SUPPORT_DDR50); 29678ab82fdSAl Cooper host->quirks |= SDHCI_QUIRK_MISSING_CAPS; 29778ab82fdSAl Cooper 29878ab82fdSAl Cooper if (match_priv->flags & BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT) 29978ab82fdSAl Cooper host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 300476bf3d6SAl Cooper 301d46ba2d1SAl Cooper res = sdhci_brcmstb_add_host(host, priv); 302476bf3d6SAl Cooper if (res) 303476bf3d6SAl Cooper goto err; 304476bf3d6SAl Cooper 305476bf3d6SAl Cooper pltfm_host->clk = clk; 306476bf3d6SAl Cooper return res; 307476bf3d6SAl Cooper 308476bf3d6SAl Cooper err: 309476bf3d6SAl Cooper sdhci_pltfm_free(pdev); 310476bf3d6SAl Cooper err_clk: 311476bf3d6SAl Cooper clk_disable_unprepare(clk); 312476bf3d6SAl Cooper return res; 313476bf3d6SAl Cooper } 314476bf3d6SAl Cooper 315e7b5d63aSAl Cooper static void sdhci_brcmstb_shutdown(struct platform_device *pdev) 316e7b5d63aSAl Cooper { 317e7b5d63aSAl Cooper int ret; 318e7b5d63aSAl Cooper 319e7b5d63aSAl Cooper ret = sdhci_pltfm_unregister(pdev); 320e7b5d63aSAl Cooper if (ret) 321e7b5d63aSAl Cooper dev_err(&pdev->dev, "failed to shutdown\n"); 322e7b5d63aSAl Cooper } 323e7b5d63aSAl Cooper 324476bf3d6SAl Cooper MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match); 325476bf3d6SAl Cooper 326476bf3d6SAl Cooper static struct platform_driver sdhci_brcmstb_driver = { 327476bf3d6SAl Cooper .driver = { 328476bf3d6SAl Cooper .name = "sdhci-brcmstb", 3291ab0d2d7SMasahiro Yamada .pm = &sdhci_pltfm_pmops, 330476bf3d6SAl Cooper .of_match_table = of_match_ptr(sdhci_brcm_of_match), 331476bf3d6SAl Cooper }, 332476bf3d6SAl Cooper .probe = sdhci_brcmstb_probe, 333476bf3d6SAl Cooper .remove = sdhci_pltfm_unregister, 334e7b5d63aSAl Cooper .shutdown = sdhci_brcmstb_shutdown, 335476bf3d6SAl Cooper }; 336476bf3d6SAl Cooper 337476bf3d6SAl Cooper module_platform_driver(sdhci_brcmstb_driver); 338476bf3d6SAl Cooper 339476bf3d6SAl Cooper MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs"); 340476bf3d6SAl Cooper MODULE_AUTHOR("Broadcom"); 341476bf3d6SAl Cooper MODULE_LICENSE("GPL v2"); 342