11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2476bf3d6SAl Cooper /* 3476bf3d6SAl Cooper * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's 4476bf3d6SAl Cooper * 5476bf3d6SAl Cooper * Copyright (C) 2015 Broadcom Corporation 6476bf3d6SAl Cooper */ 7476bf3d6SAl Cooper 8476bf3d6SAl Cooper #include <linux/io.h> 9476bf3d6SAl Cooper #include <linux/mmc/host.h> 10476bf3d6SAl Cooper #include <linux/module.h> 11476bf3d6SAl Cooper #include <linux/of.h> 1278ab82fdSAl Cooper #include <linux/bitops.h> 13d46ba2d1SAl Cooper #include <linux/delay.h> 14476bf3d6SAl Cooper 15476bf3d6SAl Cooper #include "sdhci-pltfm.h" 16d46ba2d1SAl Cooper #include "cqhci.h" 17476bf3d6SAl Cooper 1878ab82fdSAl Cooper #define SDHCI_VENDOR 0x78 1978ab82fdSAl Cooper #define SDHCI_VENDOR_ENHANCED_STRB 0x1 206bcc55feSAl Cooper #define SDHCI_VENDOR_GATE_SDCLK_EN 0x2 2178ab82fdSAl Cooper 22f3a70f99SAl Cooper #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) 23f3a70f99SAl Cooper #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) 246bcc55feSAl Cooper #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2) 25f3a70f99SAl Cooper 26f3a70f99SAl Cooper #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) 276bcc55feSAl Cooper #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1) 2878ab82fdSAl Cooper 29d46ba2d1SAl Cooper #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 30d46ba2d1SAl Cooper 3178ab82fdSAl Cooper struct sdhci_brcmstb_priv { 3278ab82fdSAl Cooper void __iomem *cfg_regs; 33f3a70f99SAl Cooper unsigned int flags; 3497904a59SKamal Dasu struct clk *base_clk; 3597904a59SKamal Dasu u32 base_freq_hz; 3678ab82fdSAl Cooper }; 3778ab82fdSAl Cooper 3878ab82fdSAl Cooper struct brcmstb_match_priv { 3978ab82fdSAl Cooper void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); 40d46ba2d1SAl Cooper struct sdhci_ops *ops; 41f3a70f99SAl Cooper const unsigned int flags; 4278ab82fdSAl Cooper }; 4378ab82fdSAl Cooper 446bcc55feSAl Cooper static inline void enable_clock_gating(struct sdhci_host *host) 456bcc55feSAl Cooper { 466bcc55feSAl Cooper u32 reg; 476bcc55feSAl Cooper 486bcc55feSAl Cooper reg = sdhci_readl(host, SDHCI_VENDOR); 496bcc55feSAl Cooper reg |= SDHCI_VENDOR_GATE_SDCLK_EN; 506bcc55feSAl Cooper sdhci_writel(host, reg, SDHCI_VENDOR); 516bcc55feSAl Cooper } 526bcc55feSAl Cooper 530c9ee5baSUlf Hansson static void brcmstb_reset(struct sdhci_host *host, u8 mask) 546bcc55feSAl Cooper { 556bcc55feSAl Cooper struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 566bcc55feSAl Cooper struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 576bcc55feSAl Cooper 586bcc55feSAl Cooper sdhci_reset(host, mask); 596bcc55feSAl Cooper 606bcc55feSAl Cooper /* Reset will clear this, so re-enable it */ 616bcc55feSAl Cooper if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK) 626bcc55feSAl Cooper enable_clock_gating(host); 636bcc55feSAl Cooper } 646bcc55feSAl Cooper 6578ab82fdSAl Cooper static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) 6678ab82fdSAl Cooper { 6778ab82fdSAl Cooper struct sdhci_host *host = mmc_priv(mmc); 6878ab82fdSAl Cooper 6978ab82fdSAl Cooper u32 reg; 7078ab82fdSAl Cooper 7178ab82fdSAl Cooper dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n", 7278ab82fdSAl Cooper __func__); 7378ab82fdSAl Cooper reg = readl(host->ioaddr + SDHCI_VENDOR); 7478ab82fdSAl Cooper if (ios->enhanced_strobe) 7578ab82fdSAl Cooper reg |= SDHCI_VENDOR_ENHANCED_STRB; 7678ab82fdSAl Cooper else 7778ab82fdSAl Cooper reg &= ~SDHCI_VENDOR_ENHANCED_STRB; 7878ab82fdSAl Cooper writel(reg, host->ioaddr + SDHCI_VENDOR); 7978ab82fdSAl Cooper } 8078ab82fdSAl Cooper 81d46ba2d1SAl Cooper static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) 82d46ba2d1SAl Cooper { 83d46ba2d1SAl Cooper u16 clk; 84d46ba2d1SAl Cooper 85d46ba2d1SAl Cooper host->mmc->actual_clock = 0; 86d46ba2d1SAl Cooper 87d46ba2d1SAl Cooper clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 88d46ba2d1SAl Cooper sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 89d46ba2d1SAl Cooper 90d46ba2d1SAl Cooper if (clock == 0) 91d46ba2d1SAl Cooper return; 92d46ba2d1SAl Cooper 93d46ba2d1SAl Cooper sdhci_enable_clk(host, clk); 94d46ba2d1SAl Cooper } 95d46ba2d1SAl Cooper 962fefc7c5SAl Cooper static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, 972fefc7c5SAl Cooper unsigned int timing) 982fefc7c5SAl Cooper { 992fefc7c5SAl Cooper u16 ctrl_2; 1002fefc7c5SAl Cooper 1012fefc7c5SAl Cooper dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n", 1022fefc7c5SAl Cooper __func__, timing); 1032fefc7c5SAl Cooper ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1042fefc7c5SAl Cooper /* Select Bus Speed Mode for host */ 1052fefc7c5SAl Cooper ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1062fefc7c5SAl Cooper if ((timing == MMC_TIMING_MMC_HS200) || 1072fefc7c5SAl Cooper (timing == MMC_TIMING_UHS_SDR104)) 1082fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1092fefc7c5SAl Cooper else if (timing == MMC_TIMING_UHS_SDR12) 1102fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1112fefc7c5SAl Cooper else if (timing == MMC_TIMING_SD_HS || 1122fefc7c5SAl Cooper timing == MMC_TIMING_MMC_HS || 1132fefc7c5SAl Cooper timing == MMC_TIMING_UHS_SDR25) 1142fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1152fefc7c5SAl Cooper else if (timing == MMC_TIMING_UHS_SDR50) 1162fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1172fefc7c5SAl Cooper else if ((timing == MMC_TIMING_UHS_DDR50) || 1182fefc7c5SAl Cooper (timing == MMC_TIMING_MMC_DDR52)) 1192fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1202fefc7c5SAl Cooper else if (timing == MMC_TIMING_MMC_HS400) 1212fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 1222fefc7c5SAl Cooper sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1232fefc7c5SAl Cooper } 1242fefc7c5SAl Cooper 125d46ba2d1SAl Cooper static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) 126d46ba2d1SAl Cooper { 127d46ba2d1SAl Cooper sdhci_dumpregs(mmc_priv(mmc)); 128d46ba2d1SAl Cooper } 129d46ba2d1SAl Cooper 130d46ba2d1SAl Cooper static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc) 131d46ba2d1SAl Cooper { 132d46ba2d1SAl Cooper struct sdhci_host *host = mmc_priv(mmc); 133d46ba2d1SAl Cooper u32 reg; 134d46ba2d1SAl Cooper 135d46ba2d1SAl Cooper reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 136d46ba2d1SAl Cooper while (reg & SDHCI_DATA_AVAILABLE) { 137d46ba2d1SAl Cooper sdhci_readl(host, SDHCI_BUFFER); 138d46ba2d1SAl Cooper reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 139d46ba2d1SAl Cooper } 140d46ba2d1SAl Cooper 141d46ba2d1SAl Cooper sdhci_cqe_enable(mmc); 142d46ba2d1SAl Cooper } 143d46ba2d1SAl Cooper 144d46ba2d1SAl Cooper static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = { 145d46ba2d1SAl Cooper .enable = sdhci_brcmstb_cqe_enable, 146d46ba2d1SAl Cooper .disable = sdhci_cqe_disable, 147d46ba2d1SAl Cooper .dumpregs = sdhci_brcmstb_dumpregs, 148d46ba2d1SAl Cooper }; 149d46ba2d1SAl Cooper 150d46ba2d1SAl Cooper static struct sdhci_ops sdhci_brcmstb_ops = { 151476bf3d6SAl Cooper .set_clock = sdhci_set_clock, 152476bf3d6SAl Cooper .set_bus_width = sdhci_set_bus_width, 153476bf3d6SAl Cooper .reset = sdhci_reset, 154476bf3d6SAl Cooper .set_uhs_signaling = sdhci_set_uhs_signaling, 155476bf3d6SAl Cooper }; 156476bf3d6SAl Cooper 157d46ba2d1SAl Cooper static struct sdhci_ops sdhci_brcmstb_ops_7216 = { 158d46ba2d1SAl Cooper .set_clock = sdhci_brcmstb_set_clock, 159d46ba2d1SAl Cooper .set_bus_width = sdhci_set_bus_width, 1606bcc55feSAl Cooper .reset = brcmstb_reset, 1612fefc7c5SAl Cooper .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, 162d46ba2d1SAl Cooper }; 163d46ba2d1SAl Cooper 164d46ba2d1SAl Cooper static struct brcmstb_match_priv match_priv_7425 = { 165f3a70f99SAl Cooper .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | 166f3a70f99SAl Cooper BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 167476bf3d6SAl Cooper .ops = &sdhci_brcmstb_ops, 168476bf3d6SAl Cooper }; 169476bf3d6SAl Cooper 170d46ba2d1SAl Cooper static struct brcmstb_match_priv match_priv_7445 = { 171f3a70f99SAl Cooper .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 172d46ba2d1SAl Cooper .ops = &sdhci_brcmstb_ops, 17378ab82fdSAl Cooper }; 17478ab82fdSAl Cooper 17578ab82fdSAl Cooper static const struct brcmstb_match_priv match_priv_7216 = { 1766bcc55feSAl Cooper .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, 17778ab82fdSAl Cooper .hs400es = sdhci_brcmstb_hs400es, 178d46ba2d1SAl Cooper .ops = &sdhci_brcmstb_ops_7216, 17978ab82fdSAl Cooper }; 18078ab82fdSAl Cooper 18178ab82fdSAl Cooper static const struct of_device_id sdhci_brcm_of_match[] = { 18278ab82fdSAl Cooper { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, 18378ab82fdSAl Cooper { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, 18478ab82fdSAl Cooper { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, 18578ab82fdSAl Cooper {}, 18678ab82fdSAl Cooper }; 18778ab82fdSAl Cooper 188d46ba2d1SAl Cooper static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask) 189d46ba2d1SAl Cooper { 190d46ba2d1SAl Cooper int cmd_error = 0; 191d46ba2d1SAl Cooper int data_error = 0; 192d46ba2d1SAl Cooper 193d46ba2d1SAl Cooper if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 194d46ba2d1SAl Cooper return intmask; 195d46ba2d1SAl Cooper 196d46ba2d1SAl Cooper cqhci_irq(host->mmc, intmask, cmd_error, data_error); 197d46ba2d1SAl Cooper 198d46ba2d1SAl Cooper return 0; 199d46ba2d1SAl Cooper } 200d46ba2d1SAl Cooper 201d46ba2d1SAl Cooper static int sdhci_brcmstb_add_host(struct sdhci_host *host, 202d46ba2d1SAl Cooper struct sdhci_brcmstb_priv *priv) 203d46ba2d1SAl Cooper { 204d46ba2d1SAl Cooper struct cqhci_host *cq_host; 205d46ba2d1SAl Cooper bool dma64; 206d46ba2d1SAl Cooper int ret; 207d46ba2d1SAl Cooper 208f3a70f99SAl Cooper if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0) 209d46ba2d1SAl Cooper return sdhci_add_host(host); 210d46ba2d1SAl Cooper 211d46ba2d1SAl Cooper dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); 212d46ba2d1SAl Cooper host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 213d46ba2d1SAl Cooper ret = sdhci_setup_host(host); 214d46ba2d1SAl Cooper if (ret) 215d46ba2d1SAl Cooper return ret; 216d46ba2d1SAl Cooper 217d46ba2d1SAl Cooper cq_host = devm_kzalloc(mmc_dev(host->mmc), 218d46ba2d1SAl Cooper sizeof(*cq_host), GFP_KERNEL); 219d46ba2d1SAl Cooper if (!cq_host) { 220d46ba2d1SAl Cooper ret = -ENOMEM; 221d46ba2d1SAl Cooper goto cleanup; 222d46ba2d1SAl Cooper } 223d46ba2d1SAl Cooper 224d46ba2d1SAl Cooper cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 225d46ba2d1SAl Cooper cq_host->ops = &sdhci_brcmstb_cqhci_ops; 226d46ba2d1SAl Cooper 227d46ba2d1SAl Cooper dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 228d46ba2d1SAl Cooper if (dma64) { 229d46ba2d1SAl Cooper dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n"); 230d46ba2d1SAl Cooper cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 231d46ba2d1SAl Cooper } 232d46ba2d1SAl Cooper 233d46ba2d1SAl Cooper ret = cqhci_init(cq_host, host->mmc, dma64); 234d46ba2d1SAl Cooper if (ret) 235d46ba2d1SAl Cooper goto cleanup; 236d46ba2d1SAl Cooper 237d46ba2d1SAl Cooper ret = __sdhci_add_host(host); 238d46ba2d1SAl Cooper if (ret) 239d46ba2d1SAl Cooper goto cleanup; 240d46ba2d1SAl Cooper 241d46ba2d1SAl Cooper return 0; 242d46ba2d1SAl Cooper 243d46ba2d1SAl Cooper cleanup: 244d46ba2d1SAl Cooper sdhci_cleanup_host(host); 245d46ba2d1SAl Cooper return ret; 246d46ba2d1SAl Cooper } 247d46ba2d1SAl Cooper 248476bf3d6SAl Cooper static int sdhci_brcmstb_probe(struct platform_device *pdev) 249476bf3d6SAl Cooper { 25078ab82fdSAl Cooper const struct brcmstb_match_priv *match_priv; 251d46ba2d1SAl Cooper struct sdhci_pltfm_data brcmstb_pdata; 252476bf3d6SAl Cooper struct sdhci_pltfm_host *pltfm_host; 25378ab82fdSAl Cooper const struct of_device_id *match; 25478ab82fdSAl Cooper struct sdhci_brcmstb_priv *priv; 25597904a59SKamal Dasu u32 actual_clock_mhz; 25678ab82fdSAl Cooper struct sdhci_host *host; 25778ab82fdSAl Cooper struct resource *iomem; 258476bf3d6SAl Cooper struct clk *clk; 259c3c0ed75SNathan Chancellor struct clk *base_clk = NULL; 260476bf3d6SAl Cooper int res; 261476bf3d6SAl Cooper 26278ab82fdSAl Cooper match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); 26378ab82fdSAl Cooper match_priv = match->data; 26478ab82fdSAl Cooper 265d46ba2d1SAl Cooper dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible); 266d46ba2d1SAl Cooper 267b41123f4SKrzysztof Kozlowski clk = devm_clk_get_optional(&pdev->dev, NULL); 268b41123f4SKrzysztof Kozlowski if (IS_ERR(clk)) 269b41123f4SKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(clk), 270b41123f4SKrzysztof Kozlowski "Failed to get clock from Device Tree\n"); 271b41123f4SKrzysztof Kozlowski 272476bf3d6SAl Cooper res = clk_prepare_enable(clk); 273476bf3d6SAl Cooper if (res) 274476bf3d6SAl Cooper return res; 275476bf3d6SAl Cooper 276d46ba2d1SAl Cooper memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); 277d46ba2d1SAl Cooper brcmstb_pdata.ops = match_priv->ops; 278d46ba2d1SAl Cooper host = sdhci_pltfm_init(pdev, &brcmstb_pdata, 27978ab82fdSAl Cooper sizeof(struct sdhci_brcmstb_priv)); 280476bf3d6SAl Cooper if (IS_ERR(host)) { 281476bf3d6SAl Cooper res = PTR_ERR(host); 282476bf3d6SAl Cooper goto err_clk; 283476bf3d6SAl Cooper } 284476bf3d6SAl Cooper 28578ab82fdSAl Cooper pltfm_host = sdhci_priv(host); 28678ab82fdSAl Cooper priv = sdhci_pltfm_priv(pltfm_host); 287f3a70f99SAl Cooper if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 288f3a70f99SAl Cooper priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE; 289f3a70f99SAl Cooper match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; 290f3a70f99SAl Cooper } 29178ab82fdSAl Cooper 29278ab82fdSAl Cooper /* Map in the non-standard CFG registers */ 29378ab82fdSAl Cooper iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 29478ab82fdSAl Cooper priv->cfg_regs = devm_ioremap_resource(&pdev->dev, iomem); 29578ab82fdSAl Cooper if (IS_ERR(priv->cfg_regs)) { 29678ab82fdSAl Cooper res = PTR_ERR(priv->cfg_regs); 29778ab82fdSAl Cooper goto err; 29878ab82fdSAl Cooper } 29978ab82fdSAl Cooper 300476bf3d6SAl Cooper sdhci_get_of_property(pdev); 3011e20186eSStefan Wahren res = mmc_of_parse(host->mmc); 3021e20186eSStefan Wahren if (res) 3031e20186eSStefan Wahren goto err; 304476bf3d6SAl Cooper 305476bf3d6SAl Cooper /* 3066bcc55feSAl Cooper * Automatic clock gating does not work for SD cards that may 3076bcc55feSAl Cooper * voltage switch so only enable it for non-removable devices. 3086bcc55feSAl Cooper */ 3096bcc55feSAl Cooper if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) && 3106bcc55feSAl Cooper (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 3116bcc55feSAl Cooper priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK; 3126bcc55feSAl Cooper 3136bcc55feSAl Cooper /* 31478ab82fdSAl Cooper * If the chip has enhanced strobe and it's enabled, add 31578ab82fdSAl Cooper * callback 31678ab82fdSAl Cooper */ 31778ab82fdSAl Cooper if (match_priv->hs400es && 31878ab82fdSAl Cooper (host->mmc->caps2 & MMC_CAP2_HS400_ES)) 31978ab82fdSAl Cooper host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; 32078ab82fdSAl Cooper 32178ab82fdSAl Cooper /* 322476bf3d6SAl Cooper * Supply the existing CAPS, but clear the UHS modes. This 323476bf3d6SAl Cooper * will allow these modes to be specified by device tree 324476bf3d6SAl Cooper * properties through mmc_of_parse(). 325476bf3d6SAl Cooper */ 326476bf3d6SAl Cooper host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); 327f3a70f99SAl Cooper if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT) 3286a3d8cedSJaedon Shin host->caps &= ~SDHCI_CAN_64BIT; 329476bf3d6SAl Cooper host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 330476bf3d6SAl Cooper host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 331476bf3d6SAl Cooper SDHCI_SUPPORT_DDR50); 33278ab82fdSAl Cooper host->quirks |= SDHCI_QUIRK_MISSING_CAPS; 33378ab82fdSAl Cooper 334f3a70f99SAl Cooper if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) 33578ab82fdSAl Cooper host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 336476bf3d6SAl Cooper 33797904a59SKamal Dasu /* Change the base clock frequency if the DT property exists */ 33897904a59SKamal Dasu if (device_property_read_u32(&pdev->dev, "clock-frequency", 33997904a59SKamal Dasu &priv->base_freq_hz) != 0) 34097904a59SKamal Dasu goto add_host; 34197904a59SKamal Dasu 34297904a59SKamal Dasu base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq"); 34397904a59SKamal Dasu if (IS_ERR(base_clk)) { 34497904a59SKamal Dasu dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n"); 34597904a59SKamal Dasu goto add_host; 34697904a59SKamal Dasu } 34797904a59SKamal Dasu 34897904a59SKamal Dasu res = clk_prepare_enable(base_clk); 34997904a59SKamal Dasu if (res) 35097904a59SKamal Dasu goto err; 35197904a59SKamal Dasu 35297904a59SKamal Dasu /* set improved clock rate */ 35397904a59SKamal Dasu clk_set_rate(base_clk, priv->base_freq_hz); 35497904a59SKamal Dasu actual_clock_mhz = clk_get_rate(base_clk) / 1000000; 35597904a59SKamal Dasu 35697904a59SKamal Dasu host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; 35797904a59SKamal Dasu host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT); 35897904a59SKamal Dasu /* Disable presets because they are now incorrect */ 35997904a59SKamal Dasu host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 36097904a59SKamal Dasu 36197904a59SKamal Dasu dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n", 36297904a59SKamal Dasu actual_clock_mhz); 36397904a59SKamal Dasu priv->base_clk = base_clk; 36497904a59SKamal Dasu 36597904a59SKamal Dasu add_host: 366d46ba2d1SAl Cooper res = sdhci_brcmstb_add_host(host, priv); 367476bf3d6SAl Cooper if (res) 368476bf3d6SAl Cooper goto err; 369476bf3d6SAl Cooper 370476bf3d6SAl Cooper pltfm_host->clk = clk; 371476bf3d6SAl Cooper return res; 372476bf3d6SAl Cooper 373476bf3d6SAl Cooper err: 374476bf3d6SAl Cooper sdhci_pltfm_free(pdev); 375476bf3d6SAl Cooper err_clk: 37697904a59SKamal Dasu clk_disable_unprepare(base_clk); 377476bf3d6SAl Cooper clk_disable_unprepare(clk); 378476bf3d6SAl Cooper return res; 379476bf3d6SAl Cooper } 380476bf3d6SAl Cooper 381e7b5d63aSAl Cooper static void sdhci_brcmstb_shutdown(struct platform_device *pdev) 382e7b5d63aSAl Cooper { 3835b191dcbSAl Cooper sdhci_pltfm_suspend(&pdev->dev); 384e7b5d63aSAl Cooper } 385e7b5d63aSAl Cooper 386476bf3d6SAl Cooper MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match); 387476bf3d6SAl Cooper 38897904a59SKamal Dasu #ifdef CONFIG_PM_SLEEP 38997904a59SKamal Dasu static int sdhci_brcmstb_suspend(struct device *dev) 39097904a59SKamal Dasu { 39197904a59SKamal Dasu struct sdhci_host *host = dev_get_drvdata(dev); 39297904a59SKamal Dasu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 39397904a59SKamal Dasu struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 39497904a59SKamal Dasu 39597904a59SKamal Dasu clk_disable_unprepare(priv->base_clk); 39697904a59SKamal Dasu return sdhci_pltfm_suspend(dev); 39797904a59SKamal Dasu } 39897904a59SKamal Dasu 39997904a59SKamal Dasu static int sdhci_brcmstb_resume(struct device *dev) 40097904a59SKamal Dasu { 40197904a59SKamal Dasu struct sdhci_host *host = dev_get_drvdata(dev); 40297904a59SKamal Dasu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 40397904a59SKamal Dasu struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 40497904a59SKamal Dasu int ret; 40597904a59SKamal Dasu 40697904a59SKamal Dasu ret = sdhci_pltfm_resume(dev); 40797904a59SKamal Dasu if (!ret && priv->base_freq_hz) { 40897904a59SKamal Dasu ret = clk_prepare_enable(priv->base_clk); 409*886201c7SKamal Dasu /* 410*886201c7SKamal Dasu * Note: using clk_get_rate() below as clk_get_rate() 411*886201c7SKamal Dasu * honors CLK_GET_RATE_NOCACHE attribute, but clk_set_rate() 412*886201c7SKamal Dasu * may do implicit get_rate() calls that do not honor 413*886201c7SKamal Dasu * CLK_GET_RATE_NOCACHE. 414*886201c7SKamal Dasu */ 415*886201c7SKamal Dasu if (!ret && 416*886201c7SKamal Dasu (clk_get_rate(priv->base_clk) != priv->base_freq_hz)) 41797904a59SKamal Dasu ret = clk_set_rate(priv->base_clk, priv->base_freq_hz); 41897904a59SKamal Dasu } 41997904a59SKamal Dasu 42097904a59SKamal Dasu return ret; 42197904a59SKamal Dasu } 42297904a59SKamal Dasu #endif 42397904a59SKamal Dasu 42497904a59SKamal Dasu static const struct dev_pm_ops sdhci_brcmstb_pmops = { 42597904a59SKamal Dasu SET_SYSTEM_SLEEP_PM_OPS(sdhci_brcmstb_suspend, sdhci_brcmstb_resume) 42697904a59SKamal Dasu }; 42797904a59SKamal Dasu 428476bf3d6SAl Cooper static struct platform_driver sdhci_brcmstb_driver = { 429476bf3d6SAl Cooper .driver = { 430476bf3d6SAl Cooper .name = "sdhci-brcmstb", 4312a99f3faSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 43297904a59SKamal Dasu .pm = &sdhci_brcmstb_pmops, 433476bf3d6SAl Cooper .of_match_table = of_match_ptr(sdhci_brcm_of_match), 434476bf3d6SAl Cooper }, 435476bf3d6SAl Cooper .probe = sdhci_brcmstb_probe, 436476bf3d6SAl Cooper .remove = sdhci_pltfm_unregister, 437e7b5d63aSAl Cooper .shutdown = sdhci_brcmstb_shutdown, 438476bf3d6SAl Cooper }; 439476bf3d6SAl Cooper 440476bf3d6SAl Cooper module_platform_driver(sdhci_brcmstb_driver); 441476bf3d6SAl Cooper 442476bf3d6SAl Cooper MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs"); 443476bf3d6SAl Cooper MODULE_AUTHOR("Broadcom"); 444476bf3d6SAl Cooper MODULE_LICENSE("GPL v2"); 445