1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2013 Broadcom Corporation
3 
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/delay.h>
7 #include <linux/highmem.h>
8 #include <linux/platform_device.h>
9 #include <linux/mmc/host.h>
10 #include <linux/io.h>
11 #include <linux/clk.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/mmc/slot-gpio.h>
16 
17 #include "sdhci-pltfm.h"
18 #include "sdhci.h"
19 
20 #define SDHCI_SOFT_RESET			0x01000000
21 #define KONA_SDHOST_CORECTRL			0x8000
22 #define KONA_SDHOST_CD_PINCTRL			0x00000008
23 #define KONA_SDHOST_STOP_HCLK			0x00000004
24 #define KONA_SDHOST_RESET			0x00000002
25 #define KONA_SDHOST_EN				0x00000001
26 
27 #define KONA_SDHOST_CORESTAT			0x8004
28 #define KONA_SDHOST_WP				0x00000002
29 #define KONA_SDHOST_CD_SW			0x00000001
30 
31 #define KONA_SDHOST_COREIMR			0x8008
32 #define KONA_SDHOST_IP				0x00000001
33 
34 #define KONA_SDHOST_COREISR			0x800C
35 #define KONA_SDHOST_COREIMSR			0x8010
36 #define KONA_SDHOST_COREDBG1			0x8014
37 #define KONA_SDHOST_COREGPO_MASK		0x8018
38 
39 #define SD_DETECT_GPIO_DEBOUNCE_128MS		128
40 
41 #define KONA_MMC_AUTOSUSPEND_DELAY		(50)
42 
43 struct sdhci_bcm_kona_dev {
44 	struct mutex	write_lock; /* protect back to back writes */
45 };
46 
47 
48 static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
49 {
50 	unsigned int val;
51 	unsigned long timeout;
52 
53 	/* This timeout should be sufficent for core to reset */
54 	timeout = jiffies + msecs_to_jiffies(100);
55 
56 	/* reset the host using the top level reset */
57 	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
58 	val |= KONA_SDHOST_RESET;
59 	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
60 
61 	while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
62 		if (time_is_before_jiffies(timeout)) {
63 			pr_err("Error: sd host is stuck in reset!!!\n");
64 			return -EFAULT;
65 		}
66 	}
67 
68 	/* bring the host out of reset */
69 	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
70 	val &= ~KONA_SDHOST_RESET;
71 
72 	/*
73 	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
74 	 * Back-to-Back writes to same register needs delay when SD bus clock
75 	 * is very low w.r.t AHB clock, mainly during boot-time and during card
76 	 * insert-removal.
77 	 */
78 	usleep_range(1000, 5000);
79 	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
80 
81 	return 0;
82 }
83 
84 static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
85 {
86 	unsigned int val;
87 
88 	/* enable the interrupt from the IP core */
89 	val = sdhci_readl(host, KONA_SDHOST_COREIMR);
90 	val |= KONA_SDHOST_IP;
91 	sdhci_writel(host, val, KONA_SDHOST_COREIMR);
92 
93 	/* Enable the AHB clock gating module to the host */
94 	val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
95 	val |= KONA_SDHOST_EN;
96 
97 	/*
98 	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
99 	 * Back-to-Back writes to same register needs delay when SD bus clock
100 	 * is very low w.r.t AHB clock, mainly during boot-time and during card
101 	 * insert-removal.
102 	 */
103 	usleep_range(1000, 5000);
104 	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
105 }
106 
107 /*
108  * Software emulation of the SD card insertion/removal. Set insert=1 for insert
109  * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
110  * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
111  * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
112  */
113 static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
114 {
115 	struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
116 	struct sdhci_bcm_kona_dev *kona_dev = sdhci_pltfm_priv(pltfm_priv);
117 	u32 val;
118 
119 	/*
120 	 * Back-to-Back register write needs a delay of min 10uS.
121 	 * Back-to-Back writes to same register needs delay when SD bus clock
122 	 * is very low w.r.t AHB clock, mainly during boot-time and during card
123 	 * insert-removal.
124 	 * We keep 20uS
125 	 */
126 	mutex_lock(&kona_dev->write_lock);
127 	udelay(20);
128 	val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
129 
130 	if (insert) {
131 		int ret;
132 
133 		ret = mmc_gpio_get_ro(host->mmc);
134 		if (ret >= 0)
135 			val = (val & ~KONA_SDHOST_WP) |
136 				((ret) ? KONA_SDHOST_WP : 0);
137 
138 		val |= KONA_SDHOST_CD_SW;
139 		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
140 	} else {
141 		val &= ~KONA_SDHOST_CD_SW;
142 		sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
143 	}
144 	mutex_unlock(&kona_dev->write_lock);
145 
146 	return 0;
147 }
148 
149 /*
150  * SD card interrupt event callback
151  */
152 static void sdhci_bcm_kona_card_event(struct sdhci_host *host)
153 {
154 	if (mmc_gpio_get_cd(host->mmc) > 0) {
155 		dev_dbg(mmc_dev(host->mmc),
156 			"card inserted\n");
157 		sdhci_bcm_kona_sd_card_emulate(host, 1);
158 	} else {
159 		dev_dbg(mmc_dev(host->mmc),
160 			"card removed\n");
161 		sdhci_bcm_kona_sd_card_emulate(host, 0);
162 	}
163 }
164 
165 static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host,
166 				u8 power_mode)
167 {
168 	/*
169 	 *  JEDEC and SD spec specify supplying 74 continuous clocks to
170 	 * device after power up. With minimum bus (100KHz) that
171 	 * that translates to 740us
172 	 */
173 	if (power_mode != MMC_POWER_OFF)
174 		udelay(740);
175 }
176 
177 static const struct sdhci_ops sdhci_bcm_kona_ops = {
178 	.set_clock = sdhci_set_clock,
179 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
180 	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
181 	.platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks,
182 	.set_bus_width = sdhci_set_bus_width,
183 	.reset = sdhci_reset,
184 	.set_uhs_signaling = sdhci_set_uhs_signaling,
185 	.card_event = sdhci_bcm_kona_card_event,
186 };
187 
188 static const struct sdhci_pltfm_data sdhci_pltfm_data_kona = {
189 	.ops    = &sdhci_bcm_kona_ops,
190 	.quirks = SDHCI_QUIRK_NO_CARD_NO_RESET |
191 		SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_32BIT_DMA_ADDR |
192 		SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_32BIT_ADMA_SIZE |
193 		SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
194 		SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
195 };
196 
197 static const struct of_device_id sdhci_bcm_kona_of_match[] = {
198 	{ .compatible = "brcm,kona-sdhci"},
199 	{ .compatible = "bcm,kona-sdhci"}, /* deprecated name */
200 	{}
201 };
202 MODULE_DEVICE_TABLE(of, sdhci_bcm_kona_of_match);
203 
204 static int sdhci_bcm_kona_probe(struct platform_device *pdev)
205 {
206 	struct sdhci_bcm_kona_dev *kona_dev = NULL;
207 	struct sdhci_pltfm_host *pltfm_priv;
208 	struct device *dev = &pdev->dev;
209 	struct sdhci_host *host;
210 	int ret;
211 
212 	ret = 0;
213 
214 	host = sdhci_pltfm_init(pdev, &sdhci_pltfm_data_kona,
215 			sizeof(*kona_dev));
216 	if (IS_ERR(host))
217 		return PTR_ERR(host);
218 
219 	dev_dbg(dev, "%s: inited. IOADDR=%p\n", __func__, host->ioaddr);
220 
221 	pltfm_priv = sdhci_priv(host);
222 
223 	kona_dev = sdhci_pltfm_priv(pltfm_priv);
224 	mutex_init(&kona_dev->write_lock);
225 
226 	ret = mmc_of_parse(host->mmc);
227 	if (ret)
228 		goto err_pltfm_free;
229 
230 	if (!host->mmc->f_max) {
231 		dev_err(&pdev->dev, "Missing max-freq for SDHCI cfg\n");
232 		ret = -ENXIO;
233 		goto err_pltfm_free;
234 	}
235 
236 	/* Get and enable the core clock */
237 	pltfm_priv->clk = devm_clk_get(dev, NULL);
238 	if (IS_ERR(pltfm_priv->clk)) {
239 		dev_err(dev, "Failed to get core clock\n");
240 		ret = PTR_ERR(pltfm_priv->clk);
241 		goto err_pltfm_free;
242 	}
243 
244 	ret = clk_set_rate(pltfm_priv->clk, host->mmc->f_max);
245 	if (ret) {
246 		dev_err(dev, "Failed to set rate core clock\n");
247 		goto err_pltfm_free;
248 	}
249 
250 	ret = clk_prepare_enable(pltfm_priv->clk);
251 	if (ret) {
252 		dev_err(dev, "Failed to enable core clock\n");
253 		goto err_pltfm_free;
254 	}
255 
256 	dev_dbg(dev, "non-removable=%c\n",
257 		mmc_card_is_removable(host->mmc) ? 'N' : 'Y');
258 	dev_dbg(dev, "cd_gpio %c, wp_gpio %c\n",
259 		(mmc_gpio_get_cd(host->mmc) != -ENOSYS) ? 'Y' : 'N',
260 		(mmc_gpio_get_ro(host->mmc) != -ENOSYS) ? 'Y' : 'N');
261 
262 	if (!mmc_card_is_removable(host->mmc))
263 		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
264 
265 	dev_dbg(dev, "is_8bit=%c\n",
266 		(host->mmc->caps & MMC_CAP_8_BIT_DATA) ? 'Y' : 'N');
267 
268 	ret = sdhci_bcm_kona_sd_reset(host);
269 	if (ret)
270 		goto err_clk_disable;
271 
272 	sdhci_bcm_kona_sd_init(host);
273 
274 	ret = sdhci_add_host(host);
275 	if (ret)
276 		goto err_reset;
277 
278 	/* if device is eMMC, emulate card insert right here */
279 	if (!mmc_card_is_removable(host->mmc)) {
280 		ret = sdhci_bcm_kona_sd_card_emulate(host, 1);
281 		if (ret) {
282 			dev_err(dev,
283 				"unable to emulate card insertion\n");
284 			goto err_remove_host;
285 		}
286 	}
287 	/*
288 	 * Since the card detection GPIO interrupt is configured to be
289 	 * edge sensitive, check the initial GPIO value here, emulate
290 	 * only if the card is present
291 	 */
292 	if (mmc_gpio_get_cd(host->mmc) > 0)
293 		sdhci_bcm_kona_sd_card_emulate(host, 1);
294 
295 	dev_dbg(dev, "initialized properly\n");
296 	return 0;
297 
298 err_remove_host:
299 	sdhci_remove_host(host, 0);
300 
301 err_reset:
302 	sdhci_bcm_kona_sd_reset(host);
303 
304 err_clk_disable:
305 	clk_disable_unprepare(pltfm_priv->clk);
306 
307 err_pltfm_free:
308 	sdhci_pltfm_free(pdev);
309 
310 	dev_err(dev, "Probing of sdhci-pltfm failed: %d\n", ret);
311 	return ret;
312 }
313 
314 static struct platform_driver sdhci_bcm_kona_driver = {
315 	.driver		= {
316 		.name	= "sdhci-kona",
317 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
318 		.pm	= &sdhci_pltfm_pmops,
319 		.of_match_table = sdhci_bcm_kona_of_match,
320 	},
321 	.probe		= sdhci_bcm_kona_probe,
322 	.remove		= sdhci_pltfm_unregister,
323 };
324 module_platform_driver(sdhci_bcm_kona_driver);
325 
326 MODULE_DESCRIPTION("SDHCI driver for Broadcom Kona platform");
327 MODULE_AUTHOR("Broadcom");
328 MODULE_LICENSE("GPL v2");
329