1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Secure Digital Host Controller Interface ACPI driver. 4 * 5 * Copyright (c) 2012, Intel Corporation. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/init.h> 10 #include <linux/export.h> 11 #include <linux/module.h> 12 #include <linux/device.h> 13 #include <linux/platform_device.h> 14 #include <linux/ioport.h> 15 #include <linux/io.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/compiler.h> 18 #include <linux/stddef.h> 19 #include <linux/bitops.h> 20 #include <linux/types.h> 21 #include <linux/err.h> 22 #include <linux/interrupt.h> 23 #include <linux/acpi.h> 24 #include <linux/pm.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/delay.h> 27 #include <linux/dmi.h> 28 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/pm.h> 31 #include <linux/mmc/slot-gpio.h> 32 33 #ifdef CONFIG_X86 34 #include <linux/platform_data/x86/soc.h> 35 #include <asm/iosf_mbi.h> 36 #endif 37 38 #include "sdhci.h" 39 40 enum { 41 SDHCI_ACPI_SD_CD = BIT(0), 42 SDHCI_ACPI_RUNTIME_PM = BIT(1), 43 SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2), 44 }; 45 46 struct sdhci_acpi_chip { 47 const struct sdhci_ops *ops; 48 unsigned int quirks; 49 unsigned int quirks2; 50 unsigned long caps; 51 unsigned int caps2; 52 mmc_pm_flag_t pm_caps; 53 }; 54 55 struct sdhci_acpi_slot { 56 const struct sdhci_acpi_chip *chip; 57 unsigned int quirks; 58 unsigned int quirks2; 59 unsigned long caps; 60 unsigned int caps2; 61 mmc_pm_flag_t pm_caps; 62 unsigned int flags; 63 size_t priv_size; 64 int (*probe_slot)(struct platform_device *, struct acpi_device *); 65 int (*remove_slot)(struct platform_device *); 66 int (*free_slot)(struct platform_device *pdev); 67 int (*setup_host)(struct platform_device *pdev); 68 }; 69 70 struct sdhci_acpi_host { 71 struct sdhci_host *host; 72 const struct sdhci_acpi_slot *slot; 73 struct platform_device *pdev; 74 bool use_runtime_pm; 75 bool is_intel; 76 bool reset_signal_volt_on_suspend; 77 unsigned long private[] ____cacheline_aligned; 78 }; 79 80 enum { 81 DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP = BIT(0), 82 DMI_QUIRK_SD_NO_WRITE_PROTECT = BIT(1), 83 DMI_QUIRK_SD_CD_ACTIVE_HIGH = BIT(2), 84 }; 85 86 static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c) 87 { 88 return (void *)c->private; 89 } 90 91 static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag) 92 { 93 return c->slot && (c->slot->flags & flag); 94 } 95 96 #define INTEL_DSM_HS_CAPS_SDR25 BIT(0) 97 #define INTEL_DSM_HS_CAPS_DDR50 BIT(1) 98 #define INTEL_DSM_HS_CAPS_SDR50 BIT(2) 99 #define INTEL_DSM_HS_CAPS_SDR104 BIT(3) 100 101 enum { 102 INTEL_DSM_FNS = 0, 103 INTEL_DSM_V18_SWITCH = 3, 104 INTEL_DSM_V33_SWITCH = 4, 105 INTEL_DSM_HS_CAPS = 8, 106 }; 107 108 struct intel_host { 109 u32 dsm_fns; 110 u32 hs_caps; 111 }; 112 113 static const guid_t intel_dsm_guid = 114 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 115 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 116 117 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 118 unsigned int fn, u32 *result) 119 { 120 union acpi_object *obj; 121 int err = 0; 122 123 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 124 if (!obj) 125 return -EOPNOTSUPP; 126 127 if (obj->type == ACPI_TYPE_INTEGER) { 128 *result = obj->integer.value; 129 } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) { 130 size_t len = min_t(size_t, obj->buffer.length, 4); 131 132 *result = 0; 133 memcpy(result, obj->buffer.pointer, len); 134 } else { 135 dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n", 136 __func__, fn, obj->type, obj->buffer.length); 137 err = -EINVAL; 138 } 139 140 ACPI_FREE(obj); 141 142 return err; 143 } 144 145 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 146 unsigned int fn, u32 *result) 147 { 148 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 149 return -EOPNOTSUPP; 150 151 return __intel_dsm(intel_host, dev, fn, result); 152 } 153 154 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 155 struct mmc_host *mmc) 156 { 157 int err; 158 159 intel_host->hs_caps = ~0; 160 161 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 162 if (err) { 163 pr_debug("%s: DSM not supported, error %d\n", 164 mmc_hostname(mmc), err); 165 return; 166 } 167 168 pr_debug("%s: DSM function mask %#x\n", 169 mmc_hostname(mmc), intel_host->dsm_fns); 170 171 intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps); 172 } 173 174 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 175 struct mmc_ios *ios) 176 { 177 struct device *dev = mmc_dev(mmc); 178 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 179 struct intel_host *intel_host = sdhci_acpi_priv(c); 180 unsigned int fn; 181 u32 result = 0; 182 int err; 183 184 err = sdhci_start_signal_voltage_switch(mmc, ios); 185 if (err) 186 return err; 187 188 switch (ios->signal_voltage) { 189 case MMC_SIGNAL_VOLTAGE_330: 190 fn = INTEL_DSM_V33_SWITCH; 191 break; 192 case MMC_SIGNAL_VOLTAGE_180: 193 fn = INTEL_DSM_V18_SWITCH; 194 break; 195 default: 196 return 0; 197 } 198 199 err = intel_dsm(intel_host, dev, fn, &result); 200 pr_debug("%s: %s DSM fn %u error %d result %u\n", 201 mmc_hostname(mmc), __func__, fn, err, result); 202 203 return 0; 204 } 205 206 static void sdhci_acpi_int_hw_reset(struct sdhci_host *host) 207 { 208 u8 reg; 209 210 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 211 reg |= 0x10; 212 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 213 /* For eMMC, minimum is 1us but give it 9us for good measure */ 214 udelay(9); 215 reg &= ~0x10; 216 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 217 /* For eMMC, minimum is 200us but give it 300us for good measure */ 218 usleep_range(300, 1000); 219 } 220 221 static const struct sdhci_ops sdhci_acpi_ops_dflt = { 222 .set_clock = sdhci_set_clock, 223 .set_bus_width = sdhci_set_bus_width, 224 .reset = sdhci_reset, 225 .set_uhs_signaling = sdhci_set_uhs_signaling, 226 }; 227 228 static const struct sdhci_ops sdhci_acpi_ops_int = { 229 .set_clock = sdhci_set_clock, 230 .set_bus_width = sdhci_set_bus_width, 231 .reset = sdhci_reset, 232 .set_uhs_signaling = sdhci_set_uhs_signaling, 233 .hw_reset = sdhci_acpi_int_hw_reset, 234 }; 235 236 static const struct sdhci_acpi_chip sdhci_acpi_chip_int = { 237 .ops = &sdhci_acpi_ops_int, 238 }; 239 240 #ifdef CONFIG_X86 241 242 #define BYT_IOSF_SCCEP 0x63 243 #define BYT_IOSF_OCP_NETCTRL0 0x1078 244 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 245 246 static void sdhci_acpi_byt_setting(struct device *dev) 247 { 248 u32 val = 0; 249 250 if (!soc_intel_is_byt()) 251 return; 252 253 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 254 &val)) { 255 dev_err(dev, "%s read error\n", __func__); 256 return; 257 } 258 259 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 260 return; 261 262 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 263 264 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 265 val)) { 266 dev_err(dev, "%s write error\n", __func__); 267 return; 268 } 269 270 dev_dbg(dev, "%s completed\n", __func__); 271 } 272 273 static bool sdhci_acpi_byt_defer(struct device *dev) 274 { 275 if (!soc_intel_is_byt()) 276 return false; 277 278 if (!iosf_mbi_available()) 279 return true; 280 281 sdhci_acpi_byt_setting(dev); 282 283 return false; 284 } 285 286 #else 287 288 static inline void sdhci_acpi_byt_setting(struct device *dev) 289 { 290 } 291 292 static inline bool sdhci_acpi_byt_defer(struct device *dev) 293 { 294 return false; 295 } 296 297 #endif 298 299 static int bxt_get_cd(struct mmc_host *mmc) 300 { 301 int gpio_cd = mmc_gpio_get_cd(mmc); 302 303 if (!gpio_cd) 304 return 0; 305 306 return sdhci_get_cd_nogpio(mmc); 307 } 308 309 static int intel_probe_slot(struct platform_device *pdev, struct acpi_device *adev) 310 { 311 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 312 struct intel_host *intel_host = sdhci_acpi_priv(c); 313 struct sdhci_host *host = c->host; 314 315 if (acpi_dev_hid_uid_match(adev, "80860F14", "1") && 316 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 && 317 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807) 318 host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 319 320 if (acpi_dev_hid_uid_match(adev, "80865ACA", NULL)) 321 host->mmc_host_ops.get_cd = bxt_get_cd; 322 323 intel_dsm_init(intel_host, &pdev->dev, host->mmc); 324 325 host->mmc_host_ops.start_signal_voltage_switch = 326 intel_start_signal_voltage_switch; 327 328 c->is_intel = true; 329 330 return 0; 331 } 332 333 static int intel_setup_host(struct platform_device *pdev) 334 { 335 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 336 struct intel_host *intel_host = sdhci_acpi_priv(c); 337 338 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25)) 339 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25; 340 341 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50)) 342 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50; 343 344 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50)) 345 c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50; 346 347 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104)) 348 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104; 349 350 return 0; 351 } 352 353 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = { 354 .chip = &sdhci_acpi_chip_int, 355 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 356 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 357 MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY, 358 .flags = SDHCI_ACPI_RUNTIME_PM, 359 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 360 SDHCI_QUIRK_NO_LED, 361 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 362 SDHCI_QUIRK2_STOP_WITH_TC | 363 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400, 364 .probe_slot = intel_probe_slot, 365 .setup_host = intel_setup_host, 366 .priv_size = sizeof(struct intel_host), 367 }; 368 369 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = { 370 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 371 SDHCI_QUIRK_NO_LED | 372 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 373 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 374 .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD | 375 MMC_CAP_WAIT_WHILE_BUSY, 376 .flags = SDHCI_ACPI_RUNTIME_PM, 377 .pm_caps = MMC_PM_KEEP_POWER, 378 .probe_slot = intel_probe_slot, 379 .setup_host = intel_setup_host, 380 .priv_size = sizeof(struct intel_host), 381 }; 382 383 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = { 384 .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL | 385 SDHCI_ACPI_RUNTIME_PM, 386 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 387 SDHCI_QUIRK_NO_LED, 388 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 389 SDHCI_QUIRK2_STOP_WITH_TC, 390 .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM, 391 .probe_slot = intel_probe_slot, 392 .setup_host = intel_setup_host, 393 .priv_size = sizeof(struct intel_host), 394 }; 395 396 #define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG 0x1a8 397 #define VENDOR_SPECIFIC_PWRCTL_CTL_REG 0x1ac 398 static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr) 399 { 400 struct sdhci_host *host = ptr; 401 402 sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG); 403 sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG); 404 405 return IRQ_HANDLED; 406 } 407 408 static int qcom_probe_slot(struct platform_device *pdev, struct acpi_device *adev) 409 { 410 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 411 struct sdhci_host *host = c->host; 412 int *irq = sdhci_acpi_priv(c); 413 414 *irq = -EINVAL; 415 416 if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL)) 417 return 0; 418 419 *irq = platform_get_irq(pdev, 1); 420 if (*irq < 0) 421 return 0; 422 423 return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler, 424 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 425 "sdhci_qcom", host); 426 } 427 428 static int qcom_free_slot(struct platform_device *pdev) 429 { 430 struct device *dev = &pdev->dev; 431 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 432 struct sdhci_host *host = c->host; 433 struct acpi_device *adev; 434 int *irq = sdhci_acpi_priv(c); 435 436 adev = ACPI_COMPANION(dev); 437 if (!adev) 438 return -ENODEV; 439 440 if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL)) 441 return 0; 442 443 if (*irq < 0) 444 return 0; 445 446 free_irq(*irq, host); 447 return 0; 448 } 449 450 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = { 451 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION, 452 .quirks2 = SDHCI_QUIRK2_NO_1_8_V, 453 .caps = MMC_CAP_NONREMOVABLE, 454 .priv_size = sizeof(int), 455 .probe_slot = qcom_probe_slot, 456 .free_slot = qcom_free_slot, 457 }; 458 459 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = { 460 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION, 461 .caps = MMC_CAP_NONREMOVABLE, 462 }; 463 464 struct amd_sdhci_host { 465 bool tuned_clock; 466 bool dll_enabled; 467 }; 468 469 /* AMD sdhci reset dll register. */ 470 #define SDHCI_AMD_RESET_DLL_REGISTER 0x908 471 472 static int amd_select_drive_strength(struct mmc_card *card, 473 unsigned int max_dtr, int host_drv, 474 int card_drv, int *host_driver_strength) 475 { 476 struct sdhci_host *host = mmc_priv(card->host); 477 u16 preset, preset_driver_strength; 478 479 /* 480 * This method is only called by mmc_select_hs200 so we only need to 481 * read from the HS200 (SDR104) preset register. 482 * 483 * Firmware that has "invalid/default" presets return a driver strength 484 * of A. This matches the previously hard coded value. 485 */ 486 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 487 preset_driver_strength = FIELD_GET(SDHCI_PRESET_DRV_MASK, preset); 488 489 /* 490 * We want the controller driver strength to match the card's driver 491 * strength so they have similar rise/fall times. 492 * 493 * The controller driver strength set by this method is sticky for all 494 * timings after this method is called. This unfortunately means that 495 * while HS400 tuning is in progress we end up with mismatched driver 496 * strengths between the controller and the card. HS400 tuning requires 497 * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch 498 * happens while in DDR52 and HS modes. This has not been observed to 499 * cause problems. Enabling presets would fix this issue. 500 */ 501 *host_driver_strength = preset_driver_strength; 502 503 /* 504 * The resulting card driver strength is only set when switching the 505 * card's timing to HS200 or HS400. The card will use the default driver 506 * strength (B) for any other mode. 507 */ 508 return preset_driver_strength; 509 } 510 511 static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host, bool enable) 512 { 513 struct sdhci_acpi_host *acpi_host = sdhci_priv(host); 514 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host); 515 516 /* AMD Platform requires dll setting */ 517 sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER); 518 usleep_range(10, 20); 519 if (enable) 520 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER); 521 522 amd_host->dll_enabled = enable; 523 } 524 525 /* 526 * The initialization sequence for HS400 is: 527 * HS->HS200->Perform Tuning->HS->HS400 528 * 529 * The re-tuning sequence is: 530 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400 531 * 532 * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400 533 * mode. If we switch to a different mode, we need to disable the tuned clock. 534 * If we have previously performed tuning and switch back to HS200 or 535 * HS400, we can re-enable the tuned clock. 536 * 537 */ 538 static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 539 { 540 struct sdhci_host *host = mmc_priv(mmc); 541 struct sdhci_acpi_host *acpi_host = sdhci_priv(host); 542 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host); 543 unsigned int old_timing = host->timing; 544 u16 val; 545 546 sdhci_set_ios(mmc, ios); 547 548 if (old_timing != host->timing && amd_host->tuned_clock) { 549 if (host->timing == MMC_TIMING_MMC_HS400 || 550 host->timing == MMC_TIMING_MMC_HS200) { 551 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 552 val |= SDHCI_CTRL_TUNED_CLK; 553 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 554 } else { 555 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 556 val &= ~SDHCI_CTRL_TUNED_CLK; 557 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 558 } 559 560 /* DLL is only required for HS400 */ 561 if (host->timing == MMC_TIMING_MMC_HS400 && 562 !amd_host->dll_enabled) 563 sdhci_acpi_amd_hs400_dll(host, true); 564 } 565 } 566 567 static int amd_sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 568 { 569 int err; 570 struct sdhci_host *host = mmc_priv(mmc); 571 struct sdhci_acpi_host *acpi_host = sdhci_priv(host); 572 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host); 573 574 amd_host->tuned_clock = false; 575 576 err = sdhci_execute_tuning(mmc, opcode); 577 578 if (!err && !host->tuning_err) 579 amd_host->tuned_clock = true; 580 581 return err; 582 } 583 584 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 585 { 586 struct sdhci_acpi_host *acpi_host = sdhci_priv(host); 587 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host); 588 589 if (mask & SDHCI_RESET_ALL) { 590 amd_host->tuned_clock = false; 591 sdhci_acpi_amd_hs400_dll(host, false); 592 } 593 594 sdhci_reset(host, mask); 595 } 596 597 static const struct sdhci_ops sdhci_acpi_ops_amd = { 598 .set_clock = sdhci_set_clock, 599 .set_bus_width = sdhci_set_bus_width, 600 .reset = amd_sdhci_reset, 601 .set_uhs_signaling = sdhci_set_uhs_signaling, 602 }; 603 604 static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = { 605 .ops = &sdhci_acpi_ops_amd, 606 }; 607 608 static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev, 609 struct acpi_device *adev) 610 { 611 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 612 struct sdhci_host *host = c->host; 613 614 sdhci_read_caps(host); 615 if (host->caps1 & SDHCI_SUPPORT_DDR50) 616 host->mmc->caps = MMC_CAP_1_8V_DDR; 617 618 if ((host->caps1 & SDHCI_SUPPORT_SDR104) && 619 (host->mmc->caps & MMC_CAP_1_8V_DDR)) 620 host->mmc->caps2 = MMC_CAP2_HS400_1_8V; 621 622 /* 623 * There are two types of presets out in the wild: 624 * 1) Default/broken presets. 625 * These presets have two sets of problems: 626 * a) The clock divisor for SDR12, SDR25, and SDR50 is too small. 627 * This results in clock frequencies that are 2x higher than 628 * acceptable. i.e., SDR12 = 25 MHz, SDR25 = 50 MHz, SDR50 = 629 * 100 MHz.x 630 * b) The HS200 and HS400 driver strengths don't match. 631 * By default, the SDR104 preset register has a driver strength of 632 * A, but the (internal) HS400 preset register has a driver 633 * strength of B. As part of initializing HS400, HS200 tuning 634 * needs to be performed. Having different driver strengths 635 * between tuning and operation is wrong. It results in different 636 * rise/fall times that lead to incorrect sampling. 637 * 2) Firmware with properly initialized presets. 638 * These presets have proper clock divisors. i.e., SDR12 => 12MHz, 639 * SDR25 => 25 MHz, SDR50 => 50 MHz. Additionally the HS200 and 640 * HS400 preset driver strengths match. 641 * 642 * Enabling presets for HS400 doesn't work for the following reasons: 643 * 1) sdhci_set_ios has a hard coded list of timings that are used 644 * to determine if presets should be enabled. 645 * 2) sdhci_get_preset_value is using a non-standard register to 646 * read out HS400 presets. The AMD controller doesn't support this 647 * non-standard register. In fact, it doesn't expose the HS400 648 * preset register anywhere in the SDHCI memory map. This results 649 * in reading a garbage value and using the wrong presets. 650 * 651 * Since HS400 and HS200 presets must be identical, we could 652 * instead use the SDR104 preset register. 653 * 654 * If the above issues are resolved we could remove this quirk for 655 * firmware that has valid presets (i.e., SDR12 <= 12 MHz). 656 */ 657 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 658 659 host->mmc_host_ops.select_drive_strength = amd_select_drive_strength; 660 host->mmc_host_ops.set_ios = amd_set_ios; 661 host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning; 662 return 0; 663 } 664 665 static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = { 666 .chip = &sdhci_acpi_chip_amd, 667 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, 668 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 669 SDHCI_QUIRK_32BIT_DMA_SIZE | 670 SDHCI_QUIRK_32BIT_ADMA_SIZE, 671 .quirks2 = SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 672 .probe_slot = sdhci_acpi_emmc_amd_probe_slot, 673 .priv_size = sizeof(struct amd_sdhci_host), 674 }; 675 676 struct sdhci_acpi_uid_slot { 677 const char *hid; 678 const char *uid; 679 const struct sdhci_acpi_slot *slot; 680 }; 681 682 static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = { 683 { "80865ACA", NULL, &sdhci_acpi_slot_int_sd }, 684 { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc }, 685 { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio }, 686 { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc }, 687 { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio }, 688 { "80860F14" , "3" , &sdhci_acpi_slot_int_sd }, 689 { "80860F16" , NULL, &sdhci_acpi_slot_int_sd }, 690 { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio }, 691 { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd }, 692 { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio }, 693 { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio }, 694 { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio }, 695 { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd }, 696 { "PNP0D40" }, 697 { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v }, 698 { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd }, 699 { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc }, 700 { "AMDI0041", NULL, &sdhci_acpi_slot_amd_emmc }, 701 { }, 702 }; 703 704 static const struct acpi_device_id sdhci_acpi_ids[] = { 705 { "80865ACA" }, 706 { "80865ACC" }, 707 { "80865AD0" }, 708 { "80860F14" }, 709 { "80860F16" }, 710 { "INT33BB" }, 711 { "INT33C6" }, 712 { "INT3436" }, 713 { "INT344D" }, 714 { "PNP0D40" }, 715 { "QCOM8051" }, 716 { "QCOM8052" }, 717 { "AMDI0040" }, 718 { "AMDI0041" }, 719 { }, 720 }; 721 MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids); 722 723 /* Please keep this list sorted alphabetically */ 724 static const struct dmi_system_id sdhci_acpi_quirks[] = { 725 { 726 /* 727 * The Acer Aspire Switch 10 (SW5-012) microSD slot always 728 * reports the card being write-protected even though microSD 729 * cards do not have a write-protect switch at all. 730 */ 731 .matches = { 732 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 733 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"), 734 }, 735 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT, 736 }, 737 { 738 /* 739 * The Lenovo Miix 320-10ICR has a bug in the _PS0 method of 740 * the SHC1 ACPI device, this bug causes it to reprogram the 741 * wrong LDO (DLDO3) to 1.8V if 1.8V modes are used and the 742 * card is (runtime) suspended + resumed. DLDO3 is used for 743 * the LCD and setting it to 1.8V causes the LCD to go black. 744 */ 745 .matches = { 746 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 747 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"), 748 }, 749 .driver_data = (void *)DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP, 750 }, 751 { 752 /* 753 * Lenovo Yoga Tablet 2 Pro 1380F/L (13" Android version) this 754 * has broken WP reporting and an inverted CD signal. 755 * Note this has more or less the same BIOS as the Lenovo Yoga 756 * Tablet 2 830F/L or 1050F/L (8" and 10" Android), but unlike 757 * the 830 / 1050 models which share the same mainboard this 758 * model has a different mainboard and the inverted CD and 759 * broken WP are unique to this board. 760 */ 761 .matches = { 762 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."), 763 DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"), 764 DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"), 765 /* Full match so as to NOT match the 830/1050 BIOS */ 766 DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21.X64.0005.R00.1504101516"), 767 }, 768 .driver_data = (void *)(DMI_QUIRK_SD_NO_WRITE_PROTECT | 769 DMI_QUIRK_SD_CD_ACTIVE_HIGH), 770 }, 771 { 772 /* 773 * The Toshiba WT8-B's microSD slot always reports the card being 774 * write-protected. 775 */ 776 .matches = { 777 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 778 DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA ENCORE 2 WT8-B"), 779 }, 780 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT, 781 }, 782 { 783 /* 784 * The Toshiba WT10-A's microSD slot always reports the card being 785 * write-protected. 786 */ 787 .matches = { 788 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 789 DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA WT10-A"), 790 }, 791 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT, 792 }, 793 {} /* Terminating entry */ 794 }; 795 796 static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(struct acpi_device *adev) 797 { 798 const struct sdhci_acpi_uid_slot *u; 799 800 for (u = sdhci_acpi_uids; u->hid; u++) { 801 if (acpi_dev_hid_uid_match(adev, u->hid, u->uid)) 802 return u->slot; 803 } 804 return NULL; 805 } 806 807 static int sdhci_acpi_probe(struct platform_device *pdev) 808 { 809 struct device *dev = &pdev->dev; 810 const struct sdhci_acpi_slot *slot; 811 const struct dmi_system_id *id; 812 struct acpi_device *device; 813 struct sdhci_acpi_host *c; 814 struct sdhci_host *host; 815 struct resource *iomem; 816 resource_size_t len; 817 size_t priv_size; 818 int quirks = 0; 819 int err; 820 821 device = ACPI_COMPANION(dev); 822 if (!device) 823 return -ENODEV; 824 825 id = dmi_first_match(sdhci_acpi_quirks); 826 if (id) 827 quirks = (long)id->driver_data; 828 829 slot = sdhci_acpi_get_slot(device); 830 831 /* Power on the SDHCI controller and its children */ 832 acpi_device_fix_up_power_extended(device); 833 834 if (sdhci_acpi_byt_defer(dev)) 835 return -EPROBE_DEFER; 836 837 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 838 if (!iomem) 839 return -ENOMEM; 840 841 len = resource_size(iomem); 842 if (len < 0x100) 843 dev_err(dev, "Invalid iomem size!\n"); 844 845 if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev))) 846 return -ENOMEM; 847 848 priv_size = slot ? slot->priv_size : 0; 849 host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size); 850 if (IS_ERR(host)) 851 return PTR_ERR(host); 852 853 c = sdhci_priv(host); 854 c->host = host; 855 c->slot = slot; 856 c->pdev = pdev; 857 c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM); 858 859 platform_set_drvdata(pdev, c); 860 861 host->hw_name = "ACPI"; 862 host->ops = &sdhci_acpi_ops_dflt; 863 host->irq = platform_get_irq(pdev, 0); 864 if (host->irq < 0) { 865 err = host->irq; 866 goto err_free; 867 } 868 869 host->ioaddr = devm_ioremap(dev, iomem->start, 870 resource_size(iomem)); 871 if (host->ioaddr == NULL) { 872 err = -ENOMEM; 873 goto err_free; 874 } 875 876 if (c->slot) { 877 if (c->slot->probe_slot) { 878 err = c->slot->probe_slot(pdev, device); 879 if (err) 880 goto err_free; 881 } 882 if (c->slot->chip) { 883 host->ops = c->slot->chip->ops; 884 host->quirks |= c->slot->chip->quirks; 885 host->quirks2 |= c->slot->chip->quirks2; 886 host->mmc->caps |= c->slot->chip->caps; 887 host->mmc->caps2 |= c->slot->chip->caps2; 888 host->mmc->pm_caps |= c->slot->chip->pm_caps; 889 } 890 host->quirks |= c->slot->quirks; 891 host->quirks2 |= c->slot->quirks2; 892 host->mmc->caps |= c->slot->caps; 893 host->mmc->caps2 |= c->slot->caps2; 894 host->mmc->pm_caps |= c->slot->pm_caps; 895 } 896 897 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 898 899 if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) { 900 bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL); 901 902 if (quirks & DMI_QUIRK_SD_CD_ACTIVE_HIGH) 903 host->mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 904 905 err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0); 906 if (err) { 907 if (err == -EPROBE_DEFER) 908 goto err_free; 909 dev_warn(dev, "failed to setup card detect gpio\n"); 910 c->use_runtime_pm = false; 911 } 912 913 if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP) 914 c->reset_signal_volt_on_suspend = true; 915 916 if (quirks & DMI_QUIRK_SD_NO_WRITE_PROTECT) 917 host->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT; 918 } 919 920 err = sdhci_setup_host(host); 921 if (err) 922 goto err_free; 923 924 if (c->slot && c->slot->setup_host) { 925 err = c->slot->setup_host(pdev); 926 if (err) 927 goto err_cleanup; 928 } 929 930 err = __sdhci_add_host(host); 931 if (err) 932 goto err_cleanup; 933 934 if (c->use_runtime_pm) { 935 pm_runtime_set_active(dev); 936 pm_suspend_ignore_children(dev, 1); 937 pm_runtime_set_autosuspend_delay(dev, 50); 938 pm_runtime_use_autosuspend(dev); 939 pm_runtime_enable(dev); 940 } 941 942 device_enable_async_suspend(dev); 943 944 return 0; 945 946 err_cleanup: 947 sdhci_cleanup_host(c->host); 948 err_free: 949 if (c->slot && c->slot->free_slot) 950 c->slot->free_slot(pdev); 951 952 sdhci_free_host(c->host); 953 return err; 954 } 955 956 static void sdhci_acpi_remove(struct platform_device *pdev) 957 { 958 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 959 struct device *dev = &pdev->dev; 960 int dead; 961 962 if (c->use_runtime_pm) { 963 pm_runtime_get_sync(dev); 964 pm_runtime_disable(dev); 965 pm_runtime_put_noidle(dev); 966 } 967 968 if (c->slot && c->slot->remove_slot) 969 c->slot->remove_slot(pdev); 970 971 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0); 972 sdhci_remove_host(c->host, dead); 973 974 if (c->slot && c->slot->free_slot) 975 c->slot->free_slot(pdev); 976 977 sdhci_free_host(c->host); 978 } 979 980 static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed( 981 struct device *dev) 982 { 983 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 984 struct sdhci_host *host = c->host; 985 986 if (c->is_intel && c->reset_signal_volt_on_suspend && 987 host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) { 988 struct intel_host *intel_host = sdhci_acpi_priv(c); 989 unsigned int fn = INTEL_DSM_V33_SWITCH; 990 u32 result = 0; 991 992 intel_dsm(intel_host, dev, fn, &result); 993 } 994 } 995 996 #ifdef CONFIG_PM_SLEEP 997 998 static int sdhci_acpi_suspend(struct device *dev) 999 { 1000 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 1001 struct sdhci_host *host = c->host; 1002 int ret; 1003 1004 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1005 mmc_retune_needed(host->mmc); 1006 1007 ret = sdhci_suspend_host(host); 1008 if (ret) 1009 return ret; 1010 1011 sdhci_acpi_reset_signal_voltage_if_needed(dev); 1012 return 0; 1013 } 1014 1015 static int sdhci_acpi_resume(struct device *dev) 1016 { 1017 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 1018 1019 sdhci_acpi_byt_setting(&c->pdev->dev); 1020 1021 return sdhci_resume_host(c->host); 1022 } 1023 1024 #endif 1025 1026 #ifdef CONFIG_PM 1027 1028 static int sdhci_acpi_runtime_suspend(struct device *dev) 1029 { 1030 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 1031 struct sdhci_host *host = c->host; 1032 int ret; 1033 1034 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1035 mmc_retune_needed(host->mmc); 1036 1037 ret = sdhci_runtime_suspend_host(host); 1038 if (ret) 1039 return ret; 1040 1041 sdhci_acpi_reset_signal_voltage_if_needed(dev); 1042 return 0; 1043 } 1044 1045 static int sdhci_acpi_runtime_resume(struct device *dev) 1046 { 1047 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 1048 1049 sdhci_acpi_byt_setting(&c->pdev->dev); 1050 1051 return sdhci_runtime_resume_host(c->host, 0); 1052 } 1053 1054 #endif 1055 1056 static const struct dev_pm_ops sdhci_acpi_pm_ops = { 1057 SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume) 1058 SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend, 1059 sdhci_acpi_runtime_resume, NULL) 1060 }; 1061 1062 static struct platform_driver sdhci_acpi_driver = { 1063 .driver = { 1064 .name = "sdhci-acpi", 1065 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1066 .acpi_match_table = sdhci_acpi_ids, 1067 .pm = &sdhci_acpi_pm_ops, 1068 }, 1069 .probe = sdhci_acpi_probe, 1070 .remove_new = sdhci_acpi_remove, 1071 }; 1072 1073 module_platform_driver(sdhci_acpi_driver); 1074 1075 MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver"); 1076 MODULE_AUTHOR("Adrian Hunter"); 1077 MODULE_LICENSE("GPL v2"); 1078