1 /* 2 * Secure Digital Host Controller Interface ACPI driver. 3 * 4 * Copyright (c) 2012, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 */ 20 21 #include <linux/init.h> 22 #include <linux/export.h> 23 #include <linux/module.h> 24 #include <linux/device.h> 25 #include <linux/platform_device.h> 26 #include <linux/ioport.h> 27 #include <linux/io.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/compiler.h> 30 #include <linux/stddef.h> 31 #include <linux/bitops.h> 32 #include <linux/types.h> 33 #include <linux/err.h> 34 #include <linux/interrupt.h> 35 #include <linux/acpi.h> 36 #include <linux/pm.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/delay.h> 39 40 #include <linux/mmc/host.h> 41 #include <linux/mmc/pm.h> 42 #include <linux/mmc/slot-gpio.h> 43 44 #ifdef CONFIG_X86 45 #include <asm/cpu_device_id.h> 46 #include <asm/intel-family.h> 47 #include <asm/iosf_mbi.h> 48 #include <linux/pci.h> 49 #endif 50 51 #include "sdhci.h" 52 53 enum { 54 SDHCI_ACPI_SD_CD = BIT(0), 55 SDHCI_ACPI_RUNTIME_PM = BIT(1), 56 SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2), 57 }; 58 59 struct sdhci_acpi_chip { 60 const struct sdhci_ops *ops; 61 unsigned int quirks; 62 unsigned int quirks2; 63 unsigned long caps; 64 unsigned int caps2; 65 mmc_pm_flag_t pm_caps; 66 }; 67 68 struct sdhci_acpi_slot { 69 const struct sdhci_acpi_chip *chip; 70 unsigned int quirks; 71 unsigned int quirks2; 72 unsigned long caps; 73 unsigned int caps2; 74 mmc_pm_flag_t pm_caps; 75 unsigned int flags; 76 size_t priv_size; 77 int (*probe_slot)(struct platform_device *, const char *, const char *); 78 int (*remove_slot)(struct platform_device *); 79 int (*free_slot)(struct platform_device *pdev); 80 int (*setup_host)(struct platform_device *pdev); 81 }; 82 83 struct sdhci_acpi_host { 84 struct sdhci_host *host; 85 const struct sdhci_acpi_slot *slot; 86 struct platform_device *pdev; 87 bool use_runtime_pm; 88 unsigned long private[0] ____cacheline_aligned; 89 }; 90 91 static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c) 92 { 93 return (void *)c->private; 94 } 95 96 static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag) 97 { 98 return c->slot && (c->slot->flags & flag); 99 } 100 101 #define INTEL_DSM_HS_CAPS_SDR25 BIT(0) 102 #define INTEL_DSM_HS_CAPS_DDR50 BIT(1) 103 #define INTEL_DSM_HS_CAPS_SDR50 BIT(2) 104 #define INTEL_DSM_HS_CAPS_SDR104 BIT(3) 105 106 enum { 107 INTEL_DSM_FNS = 0, 108 INTEL_DSM_V18_SWITCH = 3, 109 INTEL_DSM_V33_SWITCH = 4, 110 INTEL_DSM_HS_CAPS = 8, 111 }; 112 113 struct intel_host { 114 u32 dsm_fns; 115 u32 hs_caps; 116 }; 117 118 static const guid_t intel_dsm_guid = 119 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 120 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 121 122 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 123 unsigned int fn, u32 *result) 124 { 125 union acpi_object *obj; 126 int err = 0; 127 128 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 129 if (!obj) 130 return -EOPNOTSUPP; 131 132 if (obj->type == ACPI_TYPE_INTEGER) { 133 *result = obj->integer.value; 134 } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) { 135 size_t len = min_t(size_t, obj->buffer.length, 4); 136 137 *result = 0; 138 memcpy(result, obj->buffer.pointer, len); 139 } else { 140 dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n", 141 __func__, fn, obj->type, obj->buffer.length); 142 err = -EINVAL; 143 } 144 145 ACPI_FREE(obj); 146 147 return err; 148 } 149 150 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 151 unsigned int fn, u32 *result) 152 { 153 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 154 return -EOPNOTSUPP; 155 156 return __intel_dsm(intel_host, dev, fn, result); 157 } 158 159 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 160 struct mmc_host *mmc) 161 { 162 int err; 163 164 intel_host->hs_caps = ~0; 165 166 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 167 if (err) { 168 pr_debug("%s: DSM not supported, error %d\n", 169 mmc_hostname(mmc), err); 170 return; 171 } 172 173 pr_debug("%s: DSM function mask %#x\n", 174 mmc_hostname(mmc), intel_host->dsm_fns); 175 176 intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps); 177 } 178 179 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 180 struct mmc_ios *ios) 181 { 182 struct device *dev = mmc_dev(mmc); 183 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 184 struct intel_host *intel_host = sdhci_acpi_priv(c); 185 unsigned int fn; 186 u32 result = 0; 187 int err; 188 189 err = sdhci_start_signal_voltage_switch(mmc, ios); 190 if (err) 191 return err; 192 193 switch (ios->signal_voltage) { 194 case MMC_SIGNAL_VOLTAGE_330: 195 fn = INTEL_DSM_V33_SWITCH; 196 break; 197 case MMC_SIGNAL_VOLTAGE_180: 198 fn = INTEL_DSM_V18_SWITCH; 199 break; 200 default: 201 return 0; 202 } 203 204 err = intel_dsm(intel_host, dev, fn, &result); 205 pr_debug("%s: %s DSM fn %u error %d result %u\n", 206 mmc_hostname(mmc), __func__, fn, err, result); 207 208 return 0; 209 } 210 211 static void sdhci_acpi_int_hw_reset(struct sdhci_host *host) 212 { 213 u8 reg; 214 215 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 216 reg |= 0x10; 217 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 218 /* For eMMC, minimum is 1us but give it 9us for good measure */ 219 udelay(9); 220 reg &= ~0x10; 221 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 222 /* For eMMC, minimum is 200us but give it 300us for good measure */ 223 usleep_range(300, 1000); 224 } 225 226 static const struct sdhci_ops sdhci_acpi_ops_dflt = { 227 .set_clock = sdhci_set_clock, 228 .set_bus_width = sdhci_set_bus_width, 229 .reset = sdhci_reset, 230 .set_uhs_signaling = sdhci_set_uhs_signaling, 231 }; 232 233 static const struct sdhci_ops sdhci_acpi_ops_int = { 234 .set_clock = sdhci_set_clock, 235 .set_bus_width = sdhci_set_bus_width, 236 .reset = sdhci_reset, 237 .set_uhs_signaling = sdhci_set_uhs_signaling, 238 .hw_reset = sdhci_acpi_int_hw_reset, 239 }; 240 241 static const struct sdhci_acpi_chip sdhci_acpi_chip_int = { 242 .ops = &sdhci_acpi_ops_int, 243 }; 244 245 #ifdef CONFIG_X86 246 247 static bool sdhci_acpi_byt(void) 248 { 249 static const struct x86_cpu_id byt[] = { 250 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT }, 251 {} 252 }; 253 254 return x86_match_cpu(byt); 255 } 256 257 static bool sdhci_acpi_cht(void) 258 { 259 static const struct x86_cpu_id cht[] = { 260 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, 261 {} 262 }; 263 264 return x86_match_cpu(cht); 265 } 266 267 #define BYT_IOSF_SCCEP 0x63 268 #define BYT_IOSF_OCP_NETCTRL0 0x1078 269 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 270 271 static void sdhci_acpi_byt_setting(struct device *dev) 272 { 273 u32 val = 0; 274 275 if (!sdhci_acpi_byt()) 276 return; 277 278 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 279 &val)) { 280 dev_err(dev, "%s read error\n", __func__); 281 return; 282 } 283 284 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 285 return; 286 287 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 288 289 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 290 val)) { 291 dev_err(dev, "%s write error\n", __func__); 292 return; 293 } 294 295 dev_dbg(dev, "%s completed\n", __func__); 296 } 297 298 static bool sdhci_acpi_byt_defer(struct device *dev) 299 { 300 if (!sdhci_acpi_byt()) 301 return false; 302 303 if (!iosf_mbi_available()) 304 return true; 305 306 sdhci_acpi_byt_setting(dev); 307 308 return false; 309 } 310 311 static bool sdhci_acpi_cht_pci_wifi(unsigned int vendor, unsigned int device, 312 unsigned int slot, unsigned int parent_slot) 313 { 314 struct pci_dev *dev, *parent, *from = NULL; 315 316 while (1) { 317 dev = pci_get_device(vendor, device, from); 318 pci_dev_put(from); 319 if (!dev) 320 break; 321 parent = pci_upstream_bridge(dev); 322 if (ACPI_COMPANION(&dev->dev) && PCI_SLOT(dev->devfn) == slot && 323 parent && PCI_SLOT(parent->devfn) == parent_slot && 324 !pci_upstream_bridge(parent)) { 325 pci_dev_put(dev); 326 return true; 327 } 328 from = dev; 329 } 330 331 return false; 332 } 333 334 /* 335 * GPDwin uses PCI wifi which conflicts with SDIO's use of 336 * acpi_device_fix_up_power() on child device nodes. Identifying GPDwin is 337 * problematic, but since SDIO is only used for wifi, the presence of the PCI 338 * wifi card in the expected slot with an ACPI companion node, is used to 339 * indicate that acpi_device_fix_up_power() should be avoided. 340 */ 341 static inline bool sdhci_acpi_no_fixup_child_power(const char *hid, 342 const char *uid) 343 { 344 return sdhci_acpi_cht() && 345 !strcmp(hid, "80860F14") && 346 !strcmp(uid, "2") && 347 sdhci_acpi_cht_pci_wifi(0x14e4, 0x43ec, 0, 28); 348 } 349 350 #else 351 352 static inline void sdhci_acpi_byt_setting(struct device *dev) 353 { 354 } 355 356 static inline bool sdhci_acpi_byt_defer(struct device *dev) 357 { 358 return false; 359 } 360 361 static inline bool sdhci_acpi_no_fixup_child_power(const char *hid, 362 const char *uid) 363 { 364 return false; 365 } 366 367 #endif 368 369 static int bxt_get_cd(struct mmc_host *mmc) 370 { 371 int gpio_cd = mmc_gpio_get_cd(mmc); 372 struct sdhci_host *host = mmc_priv(mmc); 373 unsigned long flags; 374 int ret = 0; 375 376 if (!gpio_cd) 377 return 0; 378 379 spin_lock_irqsave(&host->lock, flags); 380 381 if (host->flags & SDHCI_DEVICE_DEAD) 382 goto out; 383 384 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 385 out: 386 spin_unlock_irqrestore(&host->lock, flags); 387 388 return ret; 389 } 390 391 static int intel_probe_slot(struct platform_device *pdev, const char *hid, 392 const char *uid) 393 { 394 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 395 struct intel_host *intel_host = sdhci_acpi_priv(c); 396 struct sdhci_host *host = c->host; 397 398 if (hid && uid && !strcmp(hid, "80860F14") && !strcmp(uid, "1") && 399 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 && 400 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807) 401 host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 402 403 if (hid && !strcmp(hid, "80865ACA")) 404 host->mmc_host_ops.get_cd = bxt_get_cd; 405 406 intel_dsm_init(intel_host, &pdev->dev, host->mmc); 407 408 host->mmc_host_ops.start_signal_voltage_switch = 409 intel_start_signal_voltage_switch; 410 411 return 0; 412 } 413 414 static int intel_setup_host(struct platform_device *pdev) 415 { 416 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 417 struct intel_host *intel_host = sdhci_acpi_priv(c); 418 419 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25)) 420 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25; 421 422 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50)) 423 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50; 424 425 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50)) 426 c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50; 427 428 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104)) 429 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104; 430 431 return 0; 432 } 433 434 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = { 435 .chip = &sdhci_acpi_chip_int, 436 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 437 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 438 MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY, 439 .flags = SDHCI_ACPI_RUNTIME_PM, 440 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 441 SDHCI_QUIRK_NO_LED, 442 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 443 SDHCI_QUIRK2_STOP_WITH_TC | 444 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400, 445 .probe_slot = intel_probe_slot, 446 .setup_host = intel_setup_host, 447 .priv_size = sizeof(struct intel_host), 448 }; 449 450 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = { 451 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 452 SDHCI_QUIRK_NO_LED | 453 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 454 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 455 .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD | 456 MMC_CAP_WAIT_WHILE_BUSY, 457 .flags = SDHCI_ACPI_RUNTIME_PM, 458 .pm_caps = MMC_PM_KEEP_POWER, 459 .probe_slot = intel_probe_slot, 460 .setup_host = intel_setup_host, 461 .priv_size = sizeof(struct intel_host), 462 }; 463 464 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = { 465 .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL | 466 SDHCI_ACPI_RUNTIME_PM, 467 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 468 SDHCI_QUIRK_NO_LED, 469 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 470 SDHCI_QUIRK2_STOP_WITH_TC, 471 .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM, 472 .probe_slot = intel_probe_slot, 473 .setup_host = intel_setup_host, 474 .priv_size = sizeof(struct intel_host), 475 }; 476 477 #define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG 0x1a8 478 #define VENDOR_SPECIFIC_PWRCTL_CTL_REG 0x1ac 479 static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr) 480 { 481 struct sdhci_host *host = ptr; 482 483 sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG); 484 sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG); 485 486 return IRQ_HANDLED; 487 } 488 489 static int qcom_probe_slot(struct platform_device *pdev, const char *hid, 490 const char *uid) 491 { 492 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 493 struct sdhci_host *host = c->host; 494 int *irq = sdhci_acpi_priv(c); 495 496 *irq = -EINVAL; 497 498 if (strcmp(hid, "QCOM8051")) 499 return 0; 500 501 *irq = platform_get_irq(pdev, 1); 502 if (*irq < 0) 503 return 0; 504 505 return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler, 506 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 507 "sdhci_qcom", host); 508 } 509 510 static int qcom_free_slot(struct platform_device *pdev) 511 { 512 struct device *dev = &pdev->dev; 513 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 514 struct sdhci_host *host = c->host; 515 struct acpi_device *adev; 516 int *irq = sdhci_acpi_priv(c); 517 const char *hid; 518 519 adev = ACPI_COMPANION(dev); 520 if (!adev) 521 return -ENODEV; 522 523 hid = acpi_device_hid(adev); 524 if (strcmp(hid, "QCOM8051")) 525 return 0; 526 527 if (*irq < 0) 528 return 0; 529 530 free_irq(*irq, host); 531 return 0; 532 } 533 534 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = { 535 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION, 536 .quirks2 = SDHCI_QUIRK2_NO_1_8_V, 537 .caps = MMC_CAP_NONREMOVABLE, 538 .priv_size = sizeof(int), 539 .probe_slot = qcom_probe_slot, 540 .free_slot = qcom_free_slot, 541 }; 542 543 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = { 544 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION, 545 .caps = MMC_CAP_NONREMOVABLE, 546 }; 547 548 /* AMD sdhci reset dll register. */ 549 #define SDHCI_AMD_RESET_DLL_REGISTER 0x908 550 551 static int amd_select_drive_strength(struct mmc_card *card, 552 unsigned int max_dtr, int host_drv, 553 int card_drv, int *drv_type) 554 { 555 return MMC_SET_DRIVER_TYPE_A; 556 } 557 558 static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host) 559 { 560 /* AMD Platform requires dll setting */ 561 sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER); 562 usleep_range(10, 20); 563 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER); 564 } 565 566 /* 567 * For AMD Platform it is required to disable the tuning 568 * bit first controller to bring to HS Mode from HS200 569 * mode, later enable to tune to HS400 mode. 570 */ 571 static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 572 { 573 struct sdhci_host *host = mmc_priv(mmc); 574 unsigned int old_timing = host->timing; 575 576 sdhci_set_ios(mmc, ios); 577 if (old_timing == MMC_TIMING_MMC_HS200 && 578 ios->timing == MMC_TIMING_MMC_HS) 579 sdhci_writew(host, 0x9, SDHCI_HOST_CONTROL2); 580 if (old_timing != MMC_TIMING_MMC_HS400 && 581 ios->timing == MMC_TIMING_MMC_HS400) { 582 sdhci_writew(host, 0x80, SDHCI_HOST_CONTROL2); 583 sdhci_acpi_amd_hs400_dll(host); 584 } 585 } 586 587 static const struct sdhci_ops sdhci_acpi_ops_amd = { 588 .set_clock = sdhci_set_clock, 589 .set_bus_width = sdhci_set_bus_width, 590 .reset = sdhci_reset, 591 .set_uhs_signaling = sdhci_set_uhs_signaling, 592 }; 593 594 static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = { 595 .ops = &sdhci_acpi_ops_amd, 596 }; 597 598 static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev, 599 const char *hid, const char *uid) 600 { 601 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 602 struct sdhci_host *host = c->host; 603 604 sdhci_read_caps(host); 605 if (host->caps1 & SDHCI_SUPPORT_DDR50) 606 host->mmc->caps = MMC_CAP_1_8V_DDR; 607 608 if ((host->caps1 & SDHCI_SUPPORT_SDR104) && 609 (host->mmc->caps & MMC_CAP_1_8V_DDR)) 610 host->mmc->caps2 = MMC_CAP2_HS400_1_8V; 611 612 host->mmc_host_ops.select_drive_strength = amd_select_drive_strength; 613 host->mmc_host_ops.set_ios = amd_set_ios; 614 return 0; 615 } 616 617 static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = { 618 .chip = &sdhci_acpi_chip_amd, 619 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, 620 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_32BIT_DMA_SIZE | 621 SDHCI_QUIRK_32BIT_ADMA_SIZE, 622 .probe_slot = sdhci_acpi_emmc_amd_probe_slot, 623 }; 624 625 struct sdhci_acpi_uid_slot { 626 const char *hid; 627 const char *uid; 628 const struct sdhci_acpi_slot *slot; 629 }; 630 631 static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = { 632 { "80865ACA", NULL, &sdhci_acpi_slot_int_sd }, 633 { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc }, 634 { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio }, 635 { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc }, 636 { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio }, 637 { "80860F14" , "3" , &sdhci_acpi_slot_int_sd }, 638 { "80860F16" , NULL, &sdhci_acpi_slot_int_sd }, 639 { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio }, 640 { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd }, 641 { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio }, 642 { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio }, 643 { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio }, 644 { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd }, 645 { "PNP0D40" }, 646 { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v }, 647 { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd }, 648 { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc }, 649 { }, 650 }; 651 652 static const struct acpi_device_id sdhci_acpi_ids[] = { 653 { "80865ACA" }, 654 { "80865ACC" }, 655 { "80865AD0" }, 656 { "80860F14" }, 657 { "80860F16" }, 658 { "INT33BB" }, 659 { "INT33C6" }, 660 { "INT3436" }, 661 { "INT344D" }, 662 { "PNP0D40" }, 663 { "QCOM8051" }, 664 { "QCOM8052" }, 665 { "AMDI0040" }, 666 { }, 667 }; 668 MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids); 669 670 static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(const char *hid, 671 const char *uid) 672 { 673 const struct sdhci_acpi_uid_slot *u; 674 675 for (u = sdhci_acpi_uids; u->hid; u++) { 676 if (strcmp(u->hid, hid)) 677 continue; 678 if (!u->uid) 679 return u->slot; 680 if (uid && !strcmp(u->uid, uid)) 681 return u->slot; 682 } 683 return NULL; 684 } 685 686 static int sdhci_acpi_probe(struct platform_device *pdev) 687 { 688 struct device *dev = &pdev->dev; 689 const struct sdhci_acpi_slot *slot; 690 struct acpi_device *device, *child; 691 struct sdhci_acpi_host *c; 692 struct sdhci_host *host; 693 struct resource *iomem; 694 resource_size_t len; 695 size_t priv_size; 696 const char *hid; 697 const char *uid; 698 int err; 699 700 device = ACPI_COMPANION(dev); 701 if (!device) 702 return -ENODEV; 703 704 hid = acpi_device_hid(device); 705 uid = acpi_device_uid(device); 706 707 slot = sdhci_acpi_get_slot(hid, uid); 708 709 /* Power on the SDHCI controller and its children */ 710 acpi_device_fix_up_power(device); 711 if (!sdhci_acpi_no_fixup_child_power(hid, uid)) { 712 list_for_each_entry(child, &device->children, node) 713 if (child->status.present && child->status.enabled) 714 acpi_device_fix_up_power(child); 715 } 716 717 if (sdhci_acpi_byt_defer(dev)) 718 return -EPROBE_DEFER; 719 720 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 721 if (!iomem) 722 return -ENOMEM; 723 724 len = resource_size(iomem); 725 if (len < 0x100) 726 dev_err(dev, "Invalid iomem size!\n"); 727 728 if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev))) 729 return -ENOMEM; 730 731 priv_size = slot ? slot->priv_size : 0; 732 host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size); 733 if (IS_ERR(host)) 734 return PTR_ERR(host); 735 736 c = sdhci_priv(host); 737 c->host = host; 738 c->slot = slot; 739 c->pdev = pdev; 740 c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM); 741 742 platform_set_drvdata(pdev, c); 743 744 host->hw_name = "ACPI"; 745 host->ops = &sdhci_acpi_ops_dflt; 746 host->irq = platform_get_irq(pdev, 0); 747 if (host->irq < 0) { 748 err = -EINVAL; 749 goto err_free; 750 } 751 752 host->ioaddr = devm_ioremap_nocache(dev, iomem->start, 753 resource_size(iomem)); 754 if (host->ioaddr == NULL) { 755 err = -ENOMEM; 756 goto err_free; 757 } 758 759 if (c->slot) { 760 if (c->slot->probe_slot) { 761 err = c->slot->probe_slot(pdev, hid, uid); 762 if (err) 763 goto err_free; 764 } 765 if (c->slot->chip) { 766 host->ops = c->slot->chip->ops; 767 host->quirks |= c->slot->chip->quirks; 768 host->quirks2 |= c->slot->chip->quirks2; 769 host->mmc->caps |= c->slot->chip->caps; 770 host->mmc->caps2 |= c->slot->chip->caps2; 771 host->mmc->pm_caps |= c->slot->chip->pm_caps; 772 } 773 host->quirks |= c->slot->quirks; 774 host->quirks2 |= c->slot->quirks2; 775 host->mmc->caps |= c->slot->caps; 776 host->mmc->caps2 |= c->slot->caps2; 777 host->mmc->pm_caps |= c->slot->pm_caps; 778 } 779 780 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 781 782 if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) { 783 bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL); 784 785 err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0, NULL); 786 if (err) { 787 if (err == -EPROBE_DEFER) 788 goto err_free; 789 dev_warn(dev, "failed to setup card detect gpio\n"); 790 c->use_runtime_pm = false; 791 } 792 } 793 794 err = sdhci_setup_host(host); 795 if (err) 796 goto err_free; 797 798 if (c->slot && c->slot->setup_host) { 799 err = c->slot->setup_host(pdev); 800 if (err) 801 goto err_cleanup; 802 } 803 804 err = __sdhci_add_host(host); 805 if (err) 806 goto err_cleanup; 807 808 if (c->use_runtime_pm) { 809 pm_runtime_set_active(dev); 810 pm_suspend_ignore_children(dev, 1); 811 pm_runtime_set_autosuspend_delay(dev, 50); 812 pm_runtime_use_autosuspend(dev); 813 pm_runtime_enable(dev); 814 } 815 816 device_enable_async_suspend(dev); 817 818 return 0; 819 820 err_cleanup: 821 sdhci_cleanup_host(c->host); 822 err_free: 823 if (c->slot && c->slot->free_slot) 824 c->slot->free_slot(pdev); 825 826 sdhci_free_host(c->host); 827 return err; 828 } 829 830 static int sdhci_acpi_remove(struct platform_device *pdev) 831 { 832 struct sdhci_acpi_host *c = platform_get_drvdata(pdev); 833 struct device *dev = &pdev->dev; 834 int dead; 835 836 if (c->use_runtime_pm) { 837 pm_runtime_get_sync(dev); 838 pm_runtime_disable(dev); 839 pm_runtime_put_noidle(dev); 840 } 841 842 if (c->slot && c->slot->remove_slot) 843 c->slot->remove_slot(pdev); 844 845 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0); 846 sdhci_remove_host(c->host, dead); 847 848 if (c->slot && c->slot->free_slot) 849 c->slot->free_slot(pdev); 850 851 sdhci_free_host(c->host); 852 853 return 0; 854 } 855 856 #ifdef CONFIG_PM_SLEEP 857 858 static int sdhci_acpi_suspend(struct device *dev) 859 { 860 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 861 struct sdhci_host *host = c->host; 862 863 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 864 mmc_retune_needed(host->mmc); 865 866 return sdhci_suspend_host(host); 867 } 868 869 static int sdhci_acpi_resume(struct device *dev) 870 { 871 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 872 873 sdhci_acpi_byt_setting(&c->pdev->dev); 874 875 return sdhci_resume_host(c->host); 876 } 877 878 #endif 879 880 #ifdef CONFIG_PM 881 882 static int sdhci_acpi_runtime_suspend(struct device *dev) 883 { 884 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 885 struct sdhci_host *host = c->host; 886 887 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 888 mmc_retune_needed(host->mmc); 889 890 return sdhci_runtime_suspend_host(host); 891 } 892 893 static int sdhci_acpi_runtime_resume(struct device *dev) 894 { 895 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 896 897 sdhci_acpi_byt_setting(&c->pdev->dev); 898 899 return sdhci_runtime_resume_host(c->host); 900 } 901 902 #endif 903 904 static const struct dev_pm_ops sdhci_acpi_pm_ops = { 905 SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume) 906 SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend, 907 sdhci_acpi_runtime_resume, NULL) 908 }; 909 910 static struct platform_driver sdhci_acpi_driver = { 911 .driver = { 912 .name = "sdhci-acpi", 913 .acpi_match_table = sdhci_acpi_ids, 914 .pm = &sdhci_acpi_pm_ops, 915 }, 916 .probe = sdhci_acpi_probe, 917 .remove = sdhci_acpi_remove, 918 }; 919 920 module_platform_driver(sdhci_acpi_driver); 921 922 MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver"); 923 MODULE_AUTHOR("Adrian Hunter"); 924 MODULE_LICENSE("GPL v2"); 925