1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Realtek PCI-Express SD/MMC Card Interface driver 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Wei WANG <wei_wang@realsil.com.cn> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/slab.h> 12 #include <linux/highmem.h> 13 #include <linux/delay.h> 14 #include <linux/platform_device.h> 15 #include <linux/workqueue.h> 16 #include <linux/mmc/host.h> 17 #include <linux/mmc/mmc.h> 18 #include <linux/mmc/sd.h> 19 #include <linux/mmc/sdio.h> 20 #include <linux/mmc/card.h> 21 #include <linux/rtsx_pci.h> 22 #include <asm/unaligned.h> 23 #include <linux/pm_runtime.h> 24 25 struct realtek_pci_sdmmc { 26 struct platform_device *pdev; 27 struct rtsx_pcr *pcr; 28 struct mmc_host *mmc; 29 struct mmc_request *mrq; 30 #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" 31 32 struct work_struct work; 33 struct mutex host_mutex; 34 35 u8 ssc_depth; 36 unsigned int clock; 37 bool vpclk; 38 bool double_clk; 39 bool eject; 40 bool initial_mode; 41 int power_state; 42 #define SDMMC_POWER_ON 1 43 #define SDMMC_POWER_OFF 0 44 45 int sg_count; 46 s32 cookie; 47 int cookie_sg_count; 48 bool using_cookie; 49 }; 50 51 static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios); 52 53 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 54 { 55 return &(host->pdev->dev); 56 } 57 58 static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 59 { 60 rtsx_pci_write_register(host->pcr, CARD_STOP, 61 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 62 } 63 64 #ifdef DEBUG 65 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end) 66 { 67 u16 len = end - start + 1; 68 int i; 69 u8 data[8]; 70 71 for (i = 0; i < len; i += 8) { 72 int j; 73 int n = min(8, len - i); 74 75 memset(&data, 0, sizeof(data)); 76 for (j = 0; j < n; j++) 77 rtsx_pci_read_register(host->pcr, start + i + j, 78 data + j); 79 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n", 80 start + i, n, data); 81 } 82 } 83 84 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 85 { 86 dump_reg_range(host, 0xFDA0, 0xFDB3); 87 dump_reg_range(host, 0xFD52, 0xFD69); 88 } 89 #else 90 #define sd_print_debug_regs(host) 91 #endif /* DEBUG */ 92 93 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host) 94 { 95 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST; 96 } 97 98 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd) 99 { 100 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 101 SD_CMD_START | cmd->opcode); 102 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg); 103 } 104 105 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz) 106 { 107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); 108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); 109 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); 110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); 111 } 112 113 static int sd_response_type(struct mmc_command *cmd) 114 { 115 switch (mmc_resp_type(cmd)) { 116 case MMC_RSP_NONE: 117 return SD_RSP_TYPE_R0; 118 case MMC_RSP_R1: 119 return SD_RSP_TYPE_R1; 120 case MMC_RSP_R1_NO_CRC: 121 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; 122 case MMC_RSP_R1B: 123 return SD_RSP_TYPE_R1b; 124 case MMC_RSP_R2: 125 return SD_RSP_TYPE_R2; 126 case MMC_RSP_R3: 127 return SD_RSP_TYPE_R3; 128 default: 129 return -EINVAL; 130 } 131 } 132 133 static int sd_status_index(int resp_type) 134 { 135 if (resp_type == SD_RSP_TYPE_R0) 136 return 0; 137 else if (resp_type == SD_RSP_TYPE_R2) 138 return 16; 139 140 return 5; 141 } 142 /* 143 * sd_pre_dma_transfer - do dma_map_sg() or using cookie 144 * 145 * @pre: if called in pre_req() 146 * return: 147 * 0 - do dma_map_sg() 148 * 1 - using cookie 149 */ 150 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, 151 struct mmc_data *data, bool pre) 152 { 153 struct rtsx_pcr *pcr = host->pcr; 154 int read = data->flags & MMC_DATA_READ; 155 int count = 0; 156 int using_cookie = 0; 157 158 if (!pre && data->host_cookie && data->host_cookie != host->cookie) { 159 dev_err(sdmmc_dev(host), 160 "error: data->host_cookie = %d, host->cookie = %d\n", 161 data->host_cookie, host->cookie); 162 data->host_cookie = 0; 163 } 164 165 if (pre || data->host_cookie != host->cookie) { 166 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); 167 } else { 168 count = host->cookie_sg_count; 169 using_cookie = 1; 170 } 171 172 if (pre) { 173 host->cookie_sg_count = count; 174 if (++host->cookie < 0) 175 host->cookie = 1; 176 data->host_cookie = host->cookie; 177 } else { 178 host->sg_count = count; 179 } 180 181 return using_cookie; 182 } 183 184 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 185 { 186 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 187 struct mmc_data *data = mrq->data; 188 189 if (data->host_cookie) { 190 dev_err(sdmmc_dev(host), 191 "error: reset data->host_cookie = %d\n", 192 data->host_cookie); 193 data->host_cookie = 0; 194 } 195 196 sd_pre_dma_transfer(host, data, true); 197 dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); 198 } 199 200 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 201 int err) 202 { 203 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 204 struct rtsx_pcr *pcr = host->pcr; 205 struct mmc_data *data = mrq->data; 206 int read = data->flags & MMC_DATA_READ; 207 208 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); 209 data->host_cookie = 0; 210 } 211 212 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 213 struct mmc_command *cmd) 214 { 215 struct rtsx_pcr *pcr = host->pcr; 216 u8 cmd_idx = (u8)cmd->opcode; 217 u32 arg = cmd->arg; 218 int err = 0; 219 int timeout = 100; 220 int i; 221 u8 *ptr; 222 int rsp_type; 223 int stat_idx; 224 bool clock_toggled = false; 225 226 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 227 __func__, cmd_idx, arg); 228 229 rsp_type = sd_response_type(cmd); 230 if (rsp_type < 0) 231 goto out; 232 233 stat_idx = sd_status_index(rsp_type); 234 235 if (rsp_type == SD_RSP_TYPE_R1b) 236 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000; 237 238 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 239 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 240 0xFF, SD_CLK_TOGGLE_EN); 241 if (err < 0) 242 goto out; 243 244 clock_toggled = true; 245 } 246 247 rtsx_pci_init_cmd(pcr); 248 sd_cmd_set_sd_cmd(pcr, cmd); 249 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 250 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 251 0x01, PINGPONG_BUFFER); 252 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 253 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 254 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 255 SD_TRANSFER_END | SD_STAT_IDLE, 256 SD_TRANSFER_END | SD_STAT_IDLE); 257 258 if (rsp_type == SD_RSP_TYPE_R2) { 259 /* Read data from ping-pong buffer */ 260 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 261 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 262 } else if (rsp_type != SD_RSP_TYPE_R0) { 263 /* Read data from SD_CMDx registers */ 264 for (i = SD_CMD0; i <= SD_CMD4; i++) 265 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 266 } 267 268 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 269 270 err = rtsx_pci_send_cmd(pcr, timeout); 271 if (err < 0) { 272 sd_print_debug_regs(host); 273 sd_clear_error(host); 274 dev_dbg(sdmmc_dev(host), 275 "rtsx_pci_send_cmd error (err = %d)\n", err); 276 goto out; 277 } 278 279 if (rsp_type == SD_RSP_TYPE_R0) { 280 err = 0; 281 goto out; 282 } 283 284 /* Eliminate returned value of CHECK_REG_CMD */ 285 ptr = rtsx_pci_get_cmd_data(pcr) + 1; 286 287 /* Check (Start,Transmission) bit of Response */ 288 if ((ptr[0] & 0xC0) != 0) { 289 err = -EILSEQ; 290 dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 291 goto out; 292 } 293 294 /* Check CRC7 */ 295 if (!(rsp_type & SD_NO_CHECK_CRC7)) { 296 if (ptr[stat_idx] & SD_CRC7_ERR) { 297 err = -EILSEQ; 298 dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 299 goto out; 300 } 301 } 302 303 if (rsp_type == SD_RSP_TYPE_R2) { 304 /* 305 * The controller offloads the last byte {CRC-7, end bit 1'b1} 306 * of response type R2. Assign dummy CRC, 0, and end bit to the 307 * byte(ptr[16], goes into the LSB of resp[3] later). 308 */ 309 ptr[16] = 1; 310 311 for (i = 0; i < 4; i++) { 312 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 313 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 314 i, cmd->resp[i]); 315 } 316 } else { 317 cmd->resp[0] = get_unaligned_be32(ptr + 1); 318 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 319 cmd->resp[0]); 320 } 321 322 out: 323 cmd->error = err; 324 325 if (err && clock_toggled) 326 rtsx_pci_write_register(pcr, SD_BUS_STAT, 327 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 328 } 329 330 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd, 331 u16 byte_cnt, u8 *buf, int buf_len, int timeout) 332 { 333 struct rtsx_pcr *pcr = host->pcr; 334 int err; 335 u8 trans_mode; 336 337 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 338 __func__, cmd->opcode, cmd->arg); 339 340 if (!buf) 341 buf_len = 0; 342 343 if (cmd->opcode == MMC_SEND_TUNING_BLOCK) 344 trans_mode = SD_TM_AUTO_TUNING; 345 else 346 trans_mode = SD_TM_NORMAL_READ; 347 348 rtsx_pci_init_cmd(pcr); 349 sd_cmd_set_sd_cmd(pcr, cmd); 350 sd_cmd_set_data_len(pcr, 1, byte_cnt); 351 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 352 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 353 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 354 if (trans_mode != SD_TM_AUTO_TUNING) 355 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 356 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 357 358 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 359 0xFF, trans_mode | SD_TRANSFER_START); 360 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 361 SD_TRANSFER_END, SD_TRANSFER_END); 362 363 err = rtsx_pci_send_cmd(pcr, timeout); 364 if (err < 0) { 365 sd_print_debug_regs(host); 366 dev_dbg(sdmmc_dev(host), 367 "rtsx_pci_send_cmd fail (err = %d)\n", err); 368 return err; 369 } 370 371 if (buf && buf_len) { 372 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 373 if (err < 0) { 374 dev_dbg(sdmmc_dev(host), 375 "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 376 return err; 377 } 378 } 379 380 return 0; 381 } 382 383 static int sd_write_data(struct realtek_pci_sdmmc *host, 384 struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len, 385 int timeout) 386 { 387 struct rtsx_pcr *pcr = host->pcr; 388 int err; 389 390 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 391 __func__, cmd->opcode, cmd->arg); 392 393 if (!buf) 394 buf_len = 0; 395 396 sd_send_cmd_get_rsp(host, cmd); 397 if (cmd->error) 398 return cmd->error; 399 400 if (buf && buf_len) { 401 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 402 if (err < 0) { 403 dev_dbg(sdmmc_dev(host), 404 "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 405 return err; 406 } 407 } 408 409 rtsx_pci_init_cmd(pcr); 410 sd_cmd_set_data_len(pcr, 1, byte_cnt); 411 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 412 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 413 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0); 414 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 415 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 416 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 417 SD_TRANSFER_END, SD_TRANSFER_END); 418 419 err = rtsx_pci_send_cmd(pcr, timeout); 420 if (err < 0) { 421 sd_print_debug_regs(host); 422 dev_dbg(sdmmc_dev(host), 423 "rtsx_pci_send_cmd fail (err = %d)\n", err); 424 return err; 425 } 426 427 return 0; 428 } 429 430 static int sd_read_long_data(struct realtek_pci_sdmmc *host, 431 struct mmc_request *mrq) 432 { 433 struct rtsx_pcr *pcr = host->pcr; 434 struct mmc_host *mmc = host->mmc; 435 struct mmc_card *card = mmc->card; 436 struct mmc_command *cmd = mrq->cmd; 437 struct mmc_data *data = mrq->data; 438 int uhs = mmc_card_uhs(card); 439 u8 cfg2 = 0; 440 int err; 441 int resp_type; 442 size_t data_len = data->blksz * data->blocks; 443 444 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 445 __func__, cmd->opcode, cmd->arg); 446 447 resp_type = sd_response_type(cmd); 448 if (resp_type < 0) 449 return resp_type; 450 451 if (!uhs) 452 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 453 454 rtsx_pci_init_cmd(pcr); 455 sd_cmd_set_sd_cmd(pcr, cmd); 456 sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 457 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 458 DMA_DONE_INT, DMA_DONE_INT); 459 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 460 0xFF, (u8)(data_len >> 24)); 461 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 462 0xFF, (u8)(data_len >> 16)); 463 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 464 0xFF, (u8)(data_len >> 8)); 465 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 466 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 467 0x03 | DMA_PACK_SIZE_MASK, 468 DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 469 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 470 0x01, RING_BUFFER); 471 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); 472 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 473 SD_TRANSFER_START | SD_TM_AUTO_READ_2); 474 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 475 SD_TRANSFER_END, SD_TRANSFER_END); 476 rtsx_pci_send_cmd_no_wait(pcr); 477 478 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000); 479 if (err < 0) { 480 sd_print_debug_regs(host); 481 sd_clear_error(host); 482 return err; 483 } 484 485 return 0; 486 } 487 488 static int sd_write_long_data(struct realtek_pci_sdmmc *host, 489 struct mmc_request *mrq) 490 { 491 struct rtsx_pcr *pcr = host->pcr; 492 struct mmc_host *mmc = host->mmc; 493 struct mmc_card *card = mmc->card; 494 struct mmc_command *cmd = mrq->cmd; 495 struct mmc_data *data = mrq->data; 496 int uhs = mmc_card_uhs(card); 497 u8 cfg2; 498 int err; 499 size_t data_len = data->blksz * data->blocks; 500 501 sd_send_cmd_get_rsp(host, cmd); 502 if (cmd->error) 503 return cmd->error; 504 505 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 506 __func__, cmd->opcode, cmd->arg); 507 508 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 509 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 510 511 if (!uhs) 512 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 513 514 rtsx_pci_init_cmd(pcr); 515 sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 516 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 517 DMA_DONE_INT, DMA_DONE_INT); 518 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 519 0xFF, (u8)(data_len >> 24)); 520 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 521 0xFF, (u8)(data_len >> 16)); 522 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 523 0xFF, (u8)(data_len >> 8)); 524 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 525 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 526 0x03 | DMA_PACK_SIZE_MASK, 527 DMA_DIR_TO_CARD | DMA_EN | DMA_512); 528 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 529 0x01, RING_BUFFER); 530 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 531 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 532 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 533 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 534 SD_TRANSFER_END, SD_TRANSFER_END); 535 rtsx_pci_send_cmd_no_wait(pcr); 536 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000); 537 if (err < 0) { 538 sd_clear_error(host); 539 return err; 540 } 541 542 return 0; 543 } 544 545 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 546 { 547 rtsx_pci_write_register(host->pcr, SD_CFG1, 548 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 549 } 550 551 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 552 { 553 rtsx_pci_write_register(host->pcr, SD_CFG1, 554 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 555 } 556 557 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 558 { 559 struct mmc_data *data = mrq->data; 560 int err; 561 562 if (host->sg_count < 0) { 563 data->error = host->sg_count; 564 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n", 565 __func__, host->sg_count); 566 return data->error; 567 } 568 569 if (data->flags & MMC_DATA_READ) { 570 if (host->initial_mode) 571 sd_disable_initial_mode(host); 572 573 err = sd_read_long_data(host, mrq); 574 575 if (host->initial_mode) 576 sd_enable_initial_mode(host); 577 578 return err; 579 } 580 581 return sd_write_long_data(host, mrq); 582 } 583 584 static void sd_normal_rw(struct realtek_pci_sdmmc *host, 585 struct mmc_request *mrq) 586 { 587 struct mmc_command *cmd = mrq->cmd; 588 struct mmc_data *data = mrq->data; 589 u8 *buf; 590 591 buf = kzalloc(data->blksz, GFP_NOIO); 592 if (!buf) { 593 cmd->error = -ENOMEM; 594 return; 595 } 596 597 if (data->flags & MMC_DATA_READ) { 598 if (host->initial_mode) 599 sd_disable_initial_mode(host); 600 601 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf, 602 data->blksz, 200); 603 604 if (host->initial_mode) 605 sd_enable_initial_mode(host); 606 607 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 608 } else { 609 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 610 611 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf, 612 data->blksz, 200); 613 } 614 615 kfree(buf); 616 } 617 618 static int sd_change_phase(struct realtek_pci_sdmmc *host, 619 u8 sample_point, bool rx) 620 { 621 struct rtsx_pcr *pcr = host->pcr; 622 u16 SD_VP_CTL = 0; 623 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 624 __func__, rx ? "RX" : "TX", sample_point); 625 626 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 627 if (rx) { 628 SD_VP_CTL = SD_VPRX_CTL; 629 rtsx_pci_write_register(pcr, SD_VPRX_CTL, 630 PHASE_SELECT_MASK, sample_point); 631 } else { 632 SD_VP_CTL = SD_VPTX_CTL; 633 rtsx_pci_write_register(pcr, SD_VPTX_CTL, 634 PHASE_SELECT_MASK, sample_point); 635 } 636 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0); 637 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 638 PHASE_NOT_RESET); 639 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0); 640 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 641 642 return 0; 643 } 644 645 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 646 { 647 bit %= RTSX_PHASE_MAX; 648 return phase_map & (1 << bit); 649 } 650 651 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 652 { 653 int i; 654 655 for (i = 0; i < RTSX_PHASE_MAX; i++) { 656 if (test_phase_bit(phase_map, start_bit + i) == 0) 657 return i; 658 } 659 return RTSX_PHASE_MAX; 660 } 661 662 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 663 { 664 int start = 0, len = 0; 665 int start_final = 0, len_final = 0; 666 u8 final_phase = 0xFF; 667 668 if (phase_map == 0) { 669 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 670 return final_phase; 671 } 672 673 while (start < RTSX_PHASE_MAX) { 674 len = sd_get_phase_len(phase_map, start); 675 if (len_final < len) { 676 start_final = start; 677 len_final = len; 678 } 679 start += len ? len : 1; 680 } 681 682 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 683 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 684 phase_map, len_final, final_phase); 685 686 return final_phase; 687 } 688 689 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 690 { 691 int i; 692 u8 val = 0; 693 694 for (i = 0; i < 100; i++) { 695 rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 696 if (val & SD_DATA_IDLE) 697 return; 698 699 udelay(100); 700 } 701 } 702 703 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 704 u8 opcode, u8 sample_point) 705 { 706 int err; 707 struct mmc_command cmd = {}; 708 struct rtsx_pcr *pcr = host->pcr; 709 710 sd_change_phase(host, sample_point, true); 711 712 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 713 SD_RSP_80CLK_TIMEOUT_EN); 714 715 cmd.opcode = opcode; 716 err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100); 717 if (err < 0) { 718 /* Wait till SD DATA IDLE */ 719 sd_wait_data_idle(host); 720 sd_clear_error(host); 721 rtsx_pci_write_register(pcr, SD_CFG3, 722 SD_RSP_80CLK_TIMEOUT_EN, 0); 723 return err; 724 } 725 726 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); 727 return 0; 728 } 729 730 static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 731 u8 opcode, u32 *phase_map) 732 { 733 int err, i; 734 u32 raw_phase_map = 0; 735 736 for (i = 0; i < RTSX_PHASE_MAX; i++) { 737 err = sd_tuning_rx_cmd(host, opcode, (u8)i); 738 if (err == 0) 739 raw_phase_map |= 1 << i; 740 } 741 742 if (phase_map) 743 *phase_map = raw_phase_map; 744 745 return 0; 746 } 747 748 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 749 { 750 int err, i; 751 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 752 u8 final_phase; 753 754 for (i = 0; i < RX_TUNING_CNT; i++) { 755 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 756 if (err < 0) 757 return err; 758 759 if (raw_phase_map[i] == 0) 760 break; 761 } 762 763 phase_map = 0xFFFFFFFF; 764 for (i = 0; i < RX_TUNING_CNT; i++) { 765 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 766 i, raw_phase_map[i]); 767 phase_map &= raw_phase_map[i]; 768 } 769 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 770 771 if (phase_map) { 772 final_phase = sd_search_final_phase(host, phase_map); 773 if (final_phase == 0xFF) 774 return -EINVAL; 775 776 err = sd_change_phase(host, final_phase, true); 777 if (err < 0) 778 return err; 779 } else { 780 return -EINVAL; 781 } 782 783 return 0; 784 } 785 786 static inline int sdio_extblock_cmd(struct mmc_command *cmd, 787 struct mmc_data *data) 788 { 789 return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512); 790 } 791 792 static inline int sd_rw_cmd(struct mmc_command *cmd) 793 { 794 return mmc_op_multi(cmd->opcode) || 795 (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 796 (cmd->opcode == MMC_WRITE_BLOCK); 797 } 798 799 static void sd_request(struct work_struct *work) 800 { 801 struct realtek_pci_sdmmc *host = container_of(work, 802 struct realtek_pci_sdmmc, work); 803 struct rtsx_pcr *pcr = host->pcr; 804 805 struct mmc_host *mmc = host->mmc; 806 struct mmc_request *mrq = host->mrq; 807 struct mmc_command *cmd = mrq->cmd; 808 struct mmc_data *data = mrq->data; 809 struct device *dev = &host->pdev->dev; 810 811 unsigned int data_size = 0; 812 int err; 813 814 if (host->eject || !sd_get_cd_int(host)) { 815 cmd->error = -ENOMEDIUM; 816 goto finish; 817 } 818 819 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 820 if (err) { 821 cmd->error = err; 822 goto finish; 823 } 824 825 mutex_lock(&pcr->pcr_mutex); 826 pm_runtime_get_sync(dev); 827 828 rtsx_pci_start_run(pcr); 829 830 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 831 host->initial_mode, host->double_clk, host->vpclk); 832 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 833 rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 834 CARD_SHARE_MASK, CARD_SHARE_48_SD); 835 836 mutex_lock(&host->host_mutex); 837 host->mrq = mrq; 838 mutex_unlock(&host->host_mutex); 839 840 if (mrq->data) 841 data_size = data->blocks * data->blksz; 842 843 if (!data_size) { 844 sd_send_cmd_get_rsp(host, cmd); 845 } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) { 846 cmd->error = sd_rw_multi(host, mrq); 847 if (!host->using_cookie) 848 sdmmc_post_req(host->mmc, host->mrq, 0); 849 850 if (mmc_op_multi(cmd->opcode) && mrq->stop) 851 sd_send_cmd_get_rsp(host, mrq->stop); 852 } else { 853 sd_normal_rw(host, mrq); 854 } 855 856 if (mrq->data) { 857 if (cmd->error || data->error) 858 data->bytes_xfered = 0; 859 else 860 data->bytes_xfered = data->blocks * data->blksz; 861 } 862 863 pm_runtime_mark_last_busy(dev); 864 pm_runtime_put_autosuspend(dev); 865 mutex_unlock(&pcr->pcr_mutex); 866 867 finish: 868 if (cmd->error) { 869 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n", 870 cmd->opcode, cmd->arg, cmd->error); 871 } 872 873 mutex_lock(&host->host_mutex); 874 host->mrq = NULL; 875 mutex_unlock(&host->host_mutex); 876 877 mmc_request_done(mmc, mrq); 878 } 879 880 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 881 { 882 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 883 struct mmc_data *data = mrq->data; 884 885 mutex_lock(&host->host_mutex); 886 host->mrq = mrq; 887 mutex_unlock(&host->host_mutex); 888 889 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data)) 890 host->using_cookie = sd_pre_dma_transfer(host, data, false); 891 892 schedule_work(&host->work); 893 } 894 895 static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 896 unsigned char bus_width) 897 { 898 int err = 0; 899 u8 width[] = { 900 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 901 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 902 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 903 }; 904 905 if (bus_width <= MMC_BUS_WIDTH_8) 906 err = rtsx_pci_write_register(host->pcr, SD_CFG1, 907 0x03, width[bus_width]); 908 909 return err; 910 } 911 912 static int sd_power_on(struct realtek_pci_sdmmc *host) 913 { 914 struct rtsx_pcr *pcr = host->pcr; 915 struct mmc_host *mmc = host->mmc; 916 int err; 917 u32 val; 918 u8 test_mode; 919 920 if (host->power_state == SDMMC_POWER_ON) 921 return 0; 922 923 msleep(100); 924 925 rtsx_pci_init_cmd(pcr); 926 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 927 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 928 CARD_SHARE_MASK, CARD_SHARE_48_SD); 929 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 930 SD_CLK_EN, SD_CLK_EN); 931 err = rtsx_pci_send_cmd(pcr, 100); 932 if (err < 0) 933 return err; 934 935 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 936 if (err < 0) 937 return err; 938 939 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 940 if (err < 0) 941 return err; 942 943 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 944 if (err < 0) 945 return err; 946 947 if (PCI_PID(pcr) == PID_5261) { 948 /* 949 * If test mode is set switch to SD Express mandatorily, 950 * this is only for factory testing. 951 */ 952 rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode); 953 if (test_mode & RTS5261_FW_EXPRESS_TEST_MASK) { 954 sdmmc_init_sd_express(mmc, NULL); 955 return 0; 956 } 957 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) 958 mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; 959 /* 960 * HW read wp status when resuming from S3/S4, 961 * and then picks SD legacy interface if it's set 962 * in read-only mode. 963 */ 964 val = rtsx_pci_readl(pcr, RTSX_BIPR); 965 if (val & SD_WRITE_PROTECT) { 966 pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS; 967 mmc->caps2 &= ~(MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V); 968 } 969 } 970 971 host->power_state = SDMMC_POWER_ON; 972 return 0; 973 } 974 975 static int sd_power_off(struct realtek_pci_sdmmc *host) 976 { 977 struct rtsx_pcr *pcr = host->pcr; 978 int err; 979 980 host->power_state = SDMMC_POWER_OFF; 981 982 rtsx_pci_init_cmd(pcr); 983 984 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 985 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 986 987 err = rtsx_pci_send_cmd(pcr, 100); 988 if (err < 0) 989 return err; 990 991 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 992 if (err < 0) 993 return err; 994 995 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 996 } 997 998 static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 999 unsigned char power_mode) 1000 { 1001 int err; 1002 1003 if (power_mode == MMC_POWER_OFF) 1004 err = sd_power_off(host); 1005 else 1006 err = sd_power_on(host); 1007 1008 return err; 1009 } 1010 1011 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 1012 { 1013 struct rtsx_pcr *pcr = host->pcr; 1014 int err = 0; 1015 1016 rtsx_pci_init_cmd(pcr); 1017 1018 switch (timing) { 1019 case MMC_TIMING_UHS_SDR104: 1020 case MMC_TIMING_UHS_SDR50: 1021 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1022 0x0C | SD_ASYNC_FIFO_NOT_RST, 1023 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1025 CLK_LOW_FREQ, CLK_LOW_FREQ); 1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1027 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 1028 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1029 break; 1030 1031 case MMC_TIMING_MMC_DDR52: 1032 case MMC_TIMING_UHS_DDR50: 1033 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1034 0x0C | SD_ASYNC_FIFO_NOT_RST, 1035 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 1036 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1037 CLK_LOW_FREQ, CLK_LOW_FREQ); 1038 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1039 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 1040 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1041 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1042 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 1043 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1044 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 1045 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 1046 break; 1047 1048 case MMC_TIMING_MMC_HS: 1049 case MMC_TIMING_SD_HS: 1050 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1051 0x0C, SD_20_MODE); 1052 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1053 CLK_LOW_FREQ, CLK_LOW_FREQ); 1054 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1055 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1056 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1057 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1058 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 1059 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1060 SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 1061 break; 1062 1063 default: 1064 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1065 SD_CFG1, 0x0C, SD_20_MODE); 1066 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1067 CLK_LOW_FREQ, CLK_LOW_FREQ); 1068 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1069 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1070 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1071 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1072 SD_PUSH_POINT_CTL, 0xFF, 0); 1073 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1074 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 1075 break; 1076 } 1077 1078 err = rtsx_pci_send_cmd(pcr, 100); 1079 1080 return err; 1081 } 1082 1083 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1084 { 1085 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1086 struct rtsx_pcr *pcr = host->pcr; 1087 struct device *dev = &host->pdev->dev; 1088 1089 if (host->eject) 1090 return; 1091 1092 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 1093 return; 1094 1095 mutex_lock(&pcr->pcr_mutex); 1096 pm_runtime_get_sync(dev); 1097 1098 rtsx_pci_start_run(pcr); 1099 1100 sd_set_bus_width(host, ios->bus_width); 1101 sd_set_power_mode(host, ios->power_mode); 1102 sd_set_timing(host, ios->timing); 1103 1104 host->vpclk = false; 1105 host->double_clk = true; 1106 1107 switch (ios->timing) { 1108 case MMC_TIMING_UHS_SDR104: 1109 case MMC_TIMING_UHS_SDR50: 1110 host->ssc_depth = RTSX_SSC_DEPTH_2M; 1111 host->vpclk = true; 1112 host->double_clk = false; 1113 break; 1114 case MMC_TIMING_MMC_DDR52: 1115 case MMC_TIMING_UHS_DDR50: 1116 case MMC_TIMING_UHS_SDR25: 1117 host->ssc_depth = RTSX_SSC_DEPTH_1M; 1118 break; 1119 default: 1120 host->ssc_depth = RTSX_SSC_DEPTH_500K; 1121 break; 1122 } 1123 1124 host->initial_mode = (ios->clock <= 1000000) ? true : false; 1125 1126 host->clock = ios->clock; 1127 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 1128 host->initial_mode, host->double_clk, host->vpclk); 1129 1130 pm_runtime_mark_last_busy(dev); 1131 pm_runtime_put_autosuspend(dev); 1132 mutex_unlock(&pcr->pcr_mutex); 1133 } 1134 1135 static int sdmmc_get_ro(struct mmc_host *mmc) 1136 { 1137 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1138 struct rtsx_pcr *pcr = host->pcr; 1139 struct device *dev = &host->pdev->dev; 1140 int ro = 0; 1141 u32 val; 1142 1143 if (host->eject) 1144 return -ENOMEDIUM; 1145 1146 mutex_lock(&pcr->pcr_mutex); 1147 pm_runtime_get_sync(dev); 1148 1149 rtsx_pci_start_run(pcr); 1150 1151 /* Check SD mechanical write-protect switch */ 1152 val = rtsx_pci_readl(pcr, RTSX_BIPR); 1153 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1154 if (val & SD_WRITE_PROTECT) 1155 ro = 1; 1156 1157 pm_runtime_mark_last_busy(dev); 1158 pm_runtime_put_autosuspend(dev); 1159 mutex_unlock(&pcr->pcr_mutex); 1160 1161 return ro; 1162 } 1163 1164 static int sdmmc_get_cd(struct mmc_host *mmc) 1165 { 1166 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1167 struct rtsx_pcr *pcr = host->pcr; 1168 struct device *dev = &host->pdev->dev; 1169 int cd = 0; 1170 u32 val; 1171 1172 if (host->eject) 1173 return cd; 1174 1175 mutex_lock(&pcr->pcr_mutex); 1176 pm_runtime_get_sync(dev); 1177 1178 rtsx_pci_start_run(pcr); 1179 1180 /* Check SD card detect */ 1181 val = rtsx_pci_card_exist(pcr); 1182 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1183 if (val & SD_EXIST) 1184 cd = 1; 1185 1186 pm_runtime_mark_last_busy(dev); 1187 pm_runtime_put_autosuspend(dev); 1188 mutex_unlock(&pcr->pcr_mutex); 1189 1190 return cd; 1191 } 1192 1193 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1194 { 1195 struct rtsx_pcr *pcr = host->pcr; 1196 int err; 1197 u8 stat; 1198 1199 /* Reference to Signal Voltage Switch Sequence in SD spec. 1200 * Wait for a period of time so that the card can drive SD_CMD and 1201 * SD_DAT[3:0] to low after sending back CMD11 response. 1202 */ 1203 mdelay(1); 1204 1205 /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1206 * If either one of SD_CMD,SD_DAT[3:0] is not low, 1207 * abort the voltage switch sequence; 1208 */ 1209 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1210 if (err < 0) 1211 return err; 1212 1213 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1214 SD_DAT1_STATUS | SD_DAT0_STATUS)) 1215 return -EINVAL; 1216 1217 /* Stop toggle SD clock */ 1218 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1219 0xFF, SD_CLK_FORCE_STOP); 1220 if (err < 0) 1221 return err; 1222 1223 return 0; 1224 } 1225 1226 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1227 { 1228 struct rtsx_pcr *pcr = host->pcr; 1229 int err; 1230 u8 stat, mask, val; 1231 1232 /* Wait 1.8V output of voltage regulator in card stable */ 1233 msleep(50); 1234 1235 /* Toggle SD clock again */ 1236 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1237 if (err < 0) 1238 return err; 1239 1240 /* Wait for a period of time so that the card can drive 1241 * SD_DAT[3:0] to high at 1.8V 1242 */ 1243 msleep(20); 1244 1245 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1246 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1247 if (err < 0) 1248 return err; 1249 1250 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1251 SD_DAT1_STATUS | SD_DAT0_STATUS; 1252 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1253 SD_DAT1_STATUS | SD_DAT0_STATUS; 1254 if ((stat & mask) != val) { 1255 dev_dbg(sdmmc_dev(host), 1256 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1257 rtsx_pci_write_register(pcr, SD_BUS_STAT, 1258 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1259 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1260 return -EINVAL; 1261 } 1262 1263 return 0; 1264 } 1265 1266 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1267 { 1268 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1269 struct rtsx_pcr *pcr = host->pcr; 1270 struct device *dev = &host->pdev->dev; 1271 int err = 0; 1272 u8 voltage; 1273 1274 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1275 __func__, ios->signal_voltage); 1276 1277 if (host->eject) 1278 return -ENOMEDIUM; 1279 1280 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1281 if (err) 1282 return err; 1283 1284 mutex_lock(&pcr->pcr_mutex); 1285 pm_runtime_get_sync(dev); 1286 1287 rtsx_pci_start_run(pcr); 1288 1289 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1290 voltage = OUTPUT_3V3; 1291 else 1292 voltage = OUTPUT_1V8; 1293 1294 if (voltage == OUTPUT_1V8) { 1295 err = sd_wait_voltage_stable_1(host); 1296 if (err < 0) 1297 goto out; 1298 } 1299 1300 err = rtsx_pci_switch_output_voltage(pcr, voltage); 1301 if (err < 0) 1302 goto out; 1303 1304 if (voltage == OUTPUT_1V8) { 1305 err = sd_wait_voltage_stable_2(host); 1306 if (err < 0) 1307 goto out; 1308 } 1309 1310 out: 1311 /* Stop toggle SD clock in idle */ 1312 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1313 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1314 1315 pm_runtime_mark_last_busy(dev); 1316 pm_runtime_put_autosuspend(dev); 1317 mutex_unlock(&pcr->pcr_mutex); 1318 1319 return err; 1320 } 1321 1322 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1323 { 1324 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1325 struct rtsx_pcr *pcr = host->pcr; 1326 struct device *dev = &host->pdev->dev; 1327 int err = 0; 1328 1329 if (host->eject) 1330 return -ENOMEDIUM; 1331 1332 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1333 if (err) 1334 return err; 1335 1336 mutex_lock(&pcr->pcr_mutex); 1337 pm_runtime_get_sync(dev); 1338 1339 rtsx_pci_start_run(pcr); 1340 1341 /* Set initial TX phase */ 1342 switch (mmc->ios.timing) { 1343 case MMC_TIMING_UHS_SDR104: 1344 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 1345 break; 1346 1347 case MMC_TIMING_UHS_SDR50: 1348 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 1349 break; 1350 1351 case MMC_TIMING_UHS_DDR50: 1352 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 1353 break; 1354 1355 default: 1356 err = 0; 1357 } 1358 1359 if (err) 1360 goto out; 1361 1362 /* Tuning RX phase */ 1363 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 1364 (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 1365 err = sd_tuning_rx(host, opcode); 1366 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 1367 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 1368 1369 out: 1370 pm_runtime_mark_last_busy(dev); 1371 pm_runtime_put_autosuspend(dev); 1372 mutex_unlock(&pcr->pcr_mutex); 1373 1374 return err; 1375 } 1376 1377 static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) 1378 { 1379 u32 relink_time; 1380 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1381 struct rtsx_pcr *pcr = host->pcr; 1382 1383 /* Set relink_time for changing to PCIe card */ 1384 relink_time = 0x8FFF; 1385 1386 rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time); 1387 rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8); 1388 rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16); 1389 1390 rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80); 1391 rtsx_pci_write_register(pcr, LDO_VCC_CFG0, 1392 RTS5261_LDO1_OCP_THD_MASK, 1393 pcr->option.sd_800mA_ocp_thd); 1394 1395 if (pcr->ops->disable_auto_blink) 1396 pcr->ops->disable_auto_blink(pcr); 1397 1398 /* For PCIe/NVMe mode can't enter delink issue */ 1399 pcr->hw_param.interrupt_en &= ~(SD_INT_EN); 1400 rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en); 1401 1402 rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4, 1403 RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN); 1404 rtsx_pci_write_register(pcr, RTS5261_FW_CFG0, 1405 RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS); 1406 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, 1407 RTS5261_MCU_CLOCK_GATING, RTS5261_MCU_CLOCK_GATING); 1408 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, 1409 RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK 1410 | RTS5261_DRIVER_ENABLE_FW, 1411 RTS5261_MCU_CLOCK_SEL_16M | RTS5261_DRIVER_ENABLE_FW); 1412 host->eject = true; 1413 return 0; 1414 } 1415 1416 static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 1417 .pre_req = sdmmc_pre_req, 1418 .post_req = sdmmc_post_req, 1419 .request = sdmmc_request, 1420 .set_ios = sdmmc_set_ios, 1421 .get_ro = sdmmc_get_ro, 1422 .get_cd = sdmmc_get_cd, 1423 .start_signal_voltage_switch = sdmmc_switch_voltage, 1424 .execute_tuning = sdmmc_execute_tuning, 1425 .init_sd_express = sdmmc_init_sd_express, 1426 }; 1427 1428 static void init_extra_caps(struct realtek_pci_sdmmc *host) 1429 { 1430 struct mmc_host *mmc = host->mmc; 1431 struct rtsx_pcr *pcr = host->pcr; 1432 1433 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1434 1435 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1436 mmc->caps |= MMC_CAP_UHS_SDR50; 1437 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1438 mmc->caps |= MMC_CAP_UHS_SDR104; 1439 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1440 mmc->caps |= MMC_CAP_UHS_DDR50; 1441 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1442 mmc->caps |= MMC_CAP_1_8V_DDR; 1443 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1444 mmc->caps |= MMC_CAP_8_BIT_DATA; 1445 if (pcr->extra_caps & EXTRA_CAPS_NO_MMC) 1446 mmc->caps2 |= MMC_CAP2_NO_MMC; 1447 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) 1448 mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; 1449 } 1450 1451 static void realtek_init_host(struct realtek_pci_sdmmc *host) 1452 { 1453 struct mmc_host *mmc = host->mmc; 1454 struct rtsx_pcr *pcr = host->pcr; 1455 1456 mmc->f_min = 250000; 1457 mmc->f_max = 208000000; 1458 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1459 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1460 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1461 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1462 if (pcr->rtd3_en) 1463 mmc->caps = mmc->caps | MMC_CAP_AGGRESSIVE_PM; 1464 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE | 1465 MMC_CAP2_NO_SDIO; 1466 mmc->max_current_330 = 400; 1467 mmc->max_current_180 = 800; 1468 mmc->ops = &realtek_pci_sdmmc_ops; 1469 1470 init_extra_caps(host); 1471 1472 mmc->max_segs = 256; 1473 mmc->max_seg_size = 65536; 1474 mmc->max_blk_size = 512; 1475 mmc->max_blk_count = 65535; 1476 mmc->max_req_size = 524288; 1477 } 1478 1479 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1480 { 1481 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1482 1483 host->cookie = -1; 1484 mmc_detect_change(host->mmc, 0); 1485 } 1486 1487 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1488 { 1489 struct mmc_host *mmc; 1490 struct realtek_pci_sdmmc *host; 1491 struct rtsx_pcr *pcr; 1492 struct pcr_handle *handle = pdev->dev.platform_data; 1493 1494 if (!handle) 1495 return -ENXIO; 1496 1497 pcr = handle->pcr; 1498 if (!pcr) 1499 return -ENXIO; 1500 1501 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1502 1503 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1504 if (!mmc) 1505 return -ENOMEM; 1506 1507 host = mmc_priv(mmc); 1508 host->pcr = pcr; 1509 host->mmc = mmc; 1510 host->pdev = pdev; 1511 host->cookie = -1; 1512 host->power_state = SDMMC_POWER_OFF; 1513 INIT_WORK(&host->work, sd_request); 1514 platform_set_drvdata(pdev, host); 1515 pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1516 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1517 1518 mutex_init(&host->host_mutex); 1519 1520 realtek_init_host(host); 1521 1522 pm_runtime_no_callbacks(&pdev->dev); 1523 pm_runtime_set_active(&pdev->dev); 1524 pm_runtime_enable(&pdev->dev); 1525 pm_runtime_set_autosuspend_delay(&pdev->dev, 200); 1526 pm_runtime_mark_last_busy(&pdev->dev); 1527 pm_runtime_use_autosuspend(&pdev->dev); 1528 1529 mmc_add_host(mmc); 1530 1531 return 0; 1532 } 1533 1534 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1535 { 1536 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1537 struct rtsx_pcr *pcr; 1538 struct mmc_host *mmc; 1539 1540 if (!host) 1541 return 0; 1542 1543 pcr = host->pcr; 1544 pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1545 pcr->slots[RTSX_SD_CARD].card_event = NULL; 1546 mmc = host->mmc; 1547 1548 cancel_work_sync(&host->work); 1549 1550 mutex_lock(&host->host_mutex); 1551 if (host->mrq) { 1552 dev_dbg(&(pdev->dev), 1553 "%s: Controller removed during transfer\n", 1554 mmc_hostname(mmc)); 1555 1556 rtsx_pci_complete_unfinished_transfer(pcr); 1557 1558 host->mrq->cmd->error = -ENOMEDIUM; 1559 if (host->mrq->stop) 1560 host->mrq->stop->error = -ENOMEDIUM; 1561 mmc_request_done(mmc, host->mrq); 1562 } 1563 mutex_unlock(&host->host_mutex); 1564 1565 mmc_remove_host(mmc); 1566 host->eject = true; 1567 1568 flush_work(&host->work); 1569 1570 pm_runtime_dont_use_autosuspend(&pdev->dev); 1571 pm_runtime_disable(&pdev->dev); 1572 1573 mmc_free_host(mmc); 1574 1575 dev_dbg(&(pdev->dev), 1576 ": Realtek PCI-E SDMMC controller has been removed\n"); 1577 1578 return 0; 1579 } 1580 1581 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1582 { 1583 .name = DRV_NAME_RTSX_PCI_SDMMC, 1584 }, { 1585 /* sentinel */ 1586 } 1587 }; 1588 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1589 1590 static struct platform_driver rtsx_pci_sdmmc_driver = { 1591 .probe = rtsx_pci_sdmmc_drv_probe, 1592 .remove = rtsx_pci_sdmmc_drv_remove, 1593 .id_table = rtsx_pci_sdmmc_ids, 1594 .driver = { 1595 .name = DRV_NAME_RTSX_PCI_SDMMC, 1596 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1597 }, 1598 }; 1599 module_platform_driver(rtsx_pci_sdmmc_driver); 1600 1601 MODULE_LICENSE("GPL"); 1602 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1603 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1604