1 /* Realtek PCI-Express SD/MMC Card Interface driver 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG <wei_wang@realsil.com.cn> 20 */ 21 22 #include <linux/module.h> 23 #include <linux/slab.h> 24 #include <linux/highmem.h> 25 #include <linux/delay.h> 26 #include <linux/platform_device.h> 27 #include <linux/mmc/host.h> 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/sd.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mfd/rtsx_pci.h> 32 #include <asm/unaligned.h> 33 34 struct realtek_pci_sdmmc { 35 struct platform_device *pdev; 36 struct rtsx_pcr *pcr; 37 struct mmc_host *mmc; 38 struct mmc_request *mrq; 39 40 struct mutex host_mutex; 41 42 u8 ssc_depth; 43 unsigned int clock; 44 bool vpclk; 45 bool double_clk; 46 bool eject; 47 bool initial_mode; 48 int power_state; 49 #define SDMMC_POWER_ON 1 50 #define SDMMC_POWER_OFF 0 51 }; 52 53 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 54 { 55 return &(host->pdev->dev); 56 } 57 58 static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 59 { 60 rtsx_pci_write_register(host->pcr, CARD_STOP, 61 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 62 } 63 64 #ifdef DEBUG 65 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 66 { 67 struct rtsx_pcr *pcr = host->pcr; 68 u16 i; 69 u8 *ptr; 70 71 /* Print SD host internal registers */ 72 rtsx_pci_init_cmd(pcr); 73 for (i = 0xFDA0; i <= 0xFDAE; i++) 74 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 75 for (i = 0xFD52; i <= 0xFD69; i++) 76 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 77 rtsx_pci_send_cmd(pcr, 100); 78 79 ptr = rtsx_pci_get_cmd_data(pcr); 80 for (i = 0xFDA0; i <= 0xFDAE; i++) 81 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 82 for (i = 0xFD52; i <= 0xFD69; i++) 83 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 84 } 85 #else 86 #define sd_print_debug_regs(host) 87 #endif /* DEBUG */ 88 89 static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 90 u8 *buf, int buf_len, int timeout) 91 { 92 struct rtsx_pcr *pcr = host->pcr; 93 int err, i; 94 u8 trans_mode; 95 96 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40); 97 98 if (!buf) 99 buf_len = 0; 100 101 if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK) 102 trans_mode = SD_TM_AUTO_TUNING; 103 else 104 trans_mode = SD_TM_NORMAL_READ; 105 106 rtsx_pci_init_cmd(pcr); 107 108 for (i = 0; i < 5; i++) 109 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]); 110 111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 112 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 113 0xFF, (u8)(byte_cnt >> 8)); 114 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 116 117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 118 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 119 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 120 if (trans_mode != SD_TM_AUTO_TUNING) 121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 122 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 123 124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 125 0xFF, trans_mode | SD_TRANSFER_START); 126 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 127 SD_TRANSFER_END, SD_TRANSFER_END); 128 129 err = rtsx_pci_send_cmd(pcr, timeout); 130 if (err < 0) { 131 sd_print_debug_regs(host); 132 dev_dbg(sdmmc_dev(host), 133 "rtsx_pci_send_cmd fail (err = %d)\n", err); 134 return err; 135 } 136 137 if (buf && buf_len) { 138 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 139 if (err < 0) { 140 dev_dbg(sdmmc_dev(host), 141 "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 142 return err; 143 } 144 } 145 146 return 0; 147 } 148 149 static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 150 u8 *buf, int buf_len, int timeout) 151 { 152 struct rtsx_pcr *pcr = host->pcr; 153 int err, i; 154 u8 trans_mode; 155 156 if (!buf) 157 buf_len = 0; 158 159 if (buf && buf_len) { 160 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 161 if (err < 0) { 162 dev_dbg(sdmmc_dev(host), 163 "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 164 return err; 165 } 166 } 167 168 trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3; 169 rtsx_pci_init_cmd(pcr); 170 171 if (cmd) { 172 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__, 173 cmd[0] - 0x40); 174 175 for (i = 0; i < 5; i++) 176 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 177 SD_CMD0 + i, 0xFF, cmd[i]); 178 } 179 180 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 181 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 182 0xFF, (u8)(byte_cnt >> 8)); 183 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 184 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 185 186 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 187 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 188 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 189 190 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 191 trans_mode | SD_TRANSFER_START); 192 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 193 SD_TRANSFER_END, SD_TRANSFER_END); 194 195 err = rtsx_pci_send_cmd(pcr, timeout); 196 if (err < 0) { 197 sd_print_debug_regs(host); 198 dev_dbg(sdmmc_dev(host), 199 "rtsx_pci_send_cmd fail (err = %d)\n", err); 200 return err; 201 } 202 203 return 0; 204 } 205 206 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 207 struct mmc_command *cmd) 208 { 209 struct rtsx_pcr *pcr = host->pcr; 210 u8 cmd_idx = (u8)cmd->opcode; 211 u32 arg = cmd->arg; 212 int err = 0; 213 int timeout = 100; 214 int i; 215 u8 *ptr; 216 int stat_idx = 0; 217 u8 rsp_type; 218 int rsp_len = 5; 219 bool clock_toggled = false; 220 221 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 222 __func__, cmd_idx, arg); 223 224 /* Response type: 225 * R0 226 * R1, R5, R6, R7 227 * R1b 228 * R2 229 * R3, R4 230 */ 231 switch (mmc_resp_type(cmd)) { 232 case MMC_RSP_NONE: 233 rsp_type = SD_RSP_TYPE_R0; 234 rsp_len = 0; 235 break; 236 case MMC_RSP_R1: 237 rsp_type = SD_RSP_TYPE_R1; 238 break; 239 case MMC_RSP_R1B: 240 rsp_type = SD_RSP_TYPE_R1b; 241 break; 242 case MMC_RSP_R2: 243 rsp_type = SD_RSP_TYPE_R2; 244 rsp_len = 16; 245 break; 246 case MMC_RSP_R3: 247 rsp_type = SD_RSP_TYPE_R3; 248 break; 249 default: 250 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n"); 251 err = -EINVAL; 252 goto out; 253 } 254 255 if (rsp_type == SD_RSP_TYPE_R1b) 256 timeout = 3000; 257 258 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 259 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 260 0xFF, SD_CLK_TOGGLE_EN); 261 if (err < 0) 262 goto out; 263 264 clock_toggled = true; 265 } 266 267 rtsx_pci_init_cmd(pcr); 268 269 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx); 270 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24)); 271 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16)); 272 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8)); 273 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg); 274 275 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 276 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 277 0x01, PINGPONG_BUFFER); 278 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 279 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 280 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 281 SD_TRANSFER_END | SD_STAT_IDLE, 282 SD_TRANSFER_END | SD_STAT_IDLE); 283 284 if (rsp_type == SD_RSP_TYPE_R2) { 285 /* Read data from ping-pong buffer */ 286 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 287 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 288 stat_idx = 16; 289 } else if (rsp_type != SD_RSP_TYPE_R0) { 290 /* Read data from SD_CMDx registers */ 291 for (i = SD_CMD0; i <= SD_CMD4; i++) 292 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 293 stat_idx = 5; 294 } 295 296 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 297 298 err = rtsx_pci_send_cmd(pcr, timeout); 299 if (err < 0) { 300 sd_print_debug_regs(host); 301 sd_clear_error(host); 302 dev_dbg(sdmmc_dev(host), 303 "rtsx_pci_send_cmd error (err = %d)\n", err); 304 goto out; 305 } 306 307 if (rsp_type == SD_RSP_TYPE_R0) { 308 err = 0; 309 goto out; 310 } 311 312 /* Eliminate returned value of CHECK_REG_CMD */ 313 ptr = rtsx_pci_get_cmd_data(pcr) + 1; 314 315 /* Check (Start,Transmission) bit of Response */ 316 if ((ptr[0] & 0xC0) != 0) { 317 err = -EILSEQ; 318 dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 319 goto out; 320 } 321 322 /* Check CRC7 */ 323 if (!(rsp_type & SD_NO_CHECK_CRC7)) { 324 if (ptr[stat_idx] & SD_CRC7_ERR) { 325 err = -EILSEQ; 326 dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 327 goto out; 328 } 329 } 330 331 if (rsp_type == SD_RSP_TYPE_R2) { 332 for (i = 0; i < 4; i++) { 333 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 334 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 335 i, cmd->resp[i]); 336 } 337 } else { 338 cmd->resp[0] = get_unaligned_be32(ptr + 1); 339 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 340 cmd->resp[0]); 341 } 342 343 out: 344 cmd->error = err; 345 346 if (err && clock_toggled) 347 rtsx_pci_write_register(pcr, SD_BUS_STAT, 348 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 349 } 350 351 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 352 { 353 struct rtsx_pcr *pcr = host->pcr; 354 struct mmc_host *mmc = host->mmc; 355 struct mmc_card *card = mmc->card; 356 struct mmc_data *data = mrq->data; 357 int uhs = mmc_card_uhs(card); 358 int read = (data->flags & MMC_DATA_READ) ? 1 : 0; 359 u8 cfg2, trans_mode; 360 int err; 361 size_t data_len = data->blksz * data->blocks; 362 363 if (read) { 364 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 365 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0; 366 trans_mode = SD_TM_AUTO_READ_3; 367 } else { 368 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 369 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 370 trans_mode = SD_TM_AUTO_WRITE_3; 371 } 372 373 if (!uhs) 374 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 375 376 rtsx_pci_init_cmd(pcr); 377 378 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00); 379 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02); 380 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 381 0xFF, (u8)data->blocks); 382 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 383 0xFF, (u8)(data->blocks >> 8)); 384 385 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 386 DMA_DONE_INT, DMA_DONE_INT); 387 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 388 0xFF, (u8)(data_len >> 24)); 389 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 390 0xFF, (u8)(data_len >> 16)); 391 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 392 0xFF, (u8)(data_len >> 8)); 393 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 394 if (read) { 395 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 396 0x03 | DMA_PACK_SIZE_MASK, 397 DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 398 } else { 399 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 400 0x03 | DMA_PACK_SIZE_MASK, 401 DMA_DIR_TO_CARD | DMA_EN | DMA_512); 402 } 403 404 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 405 0x01, RING_BUFFER); 406 407 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 408 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 409 trans_mode | SD_TRANSFER_START); 410 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 411 SD_TRANSFER_END, SD_TRANSFER_END); 412 413 rtsx_pci_send_cmd_no_wait(pcr); 414 415 err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000); 416 if (err < 0) { 417 sd_clear_error(host); 418 return err; 419 } 420 421 return 0; 422 } 423 424 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 425 { 426 rtsx_pci_write_register(host->pcr, SD_CFG1, 427 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 428 } 429 430 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 431 { 432 rtsx_pci_write_register(host->pcr, SD_CFG1, 433 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 434 } 435 436 static void sd_normal_rw(struct realtek_pci_sdmmc *host, 437 struct mmc_request *mrq) 438 { 439 struct mmc_command *cmd = mrq->cmd; 440 struct mmc_data *data = mrq->data; 441 u8 _cmd[5], *buf; 442 443 _cmd[0] = 0x40 | (u8)cmd->opcode; 444 put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1])); 445 446 buf = kzalloc(data->blksz, GFP_NOIO); 447 if (!buf) { 448 cmd->error = -ENOMEM; 449 return; 450 } 451 452 if (data->flags & MMC_DATA_READ) { 453 if (host->initial_mode) 454 sd_disable_initial_mode(host); 455 456 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf, 457 data->blksz, 200); 458 459 if (host->initial_mode) 460 sd_enable_initial_mode(host); 461 462 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 463 } else { 464 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 465 466 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf, 467 data->blksz, 200); 468 } 469 470 kfree(buf); 471 } 472 473 static int sd_change_phase(struct realtek_pci_sdmmc *host, 474 u8 sample_point, bool rx) 475 { 476 struct rtsx_pcr *pcr = host->pcr; 477 int err; 478 479 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 480 __func__, rx ? "RX" : "TX", sample_point); 481 482 rtsx_pci_init_cmd(pcr); 483 484 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 485 if (rx) 486 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 487 SD_VPRX_CTL, 0x1F, sample_point); 488 else 489 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 490 SD_VPTX_CTL, 0x1F, sample_point); 491 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); 492 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 493 PHASE_NOT_RESET, PHASE_NOT_RESET); 494 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); 495 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 496 497 err = rtsx_pci_send_cmd(pcr, 100); 498 if (err < 0) 499 return err; 500 501 return 0; 502 } 503 504 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 505 { 506 bit %= RTSX_PHASE_MAX; 507 return phase_map & (1 << bit); 508 } 509 510 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 511 { 512 int i; 513 514 for (i = 0; i < RTSX_PHASE_MAX; i++) { 515 if (test_phase_bit(phase_map, start_bit + i) == 0) 516 return i; 517 } 518 return RTSX_PHASE_MAX; 519 } 520 521 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 522 { 523 int start = 0, len = 0; 524 int start_final = 0, len_final = 0; 525 u8 final_phase = 0xFF; 526 527 if (phase_map == 0) { 528 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 529 return final_phase; 530 } 531 532 while (start < RTSX_PHASE_MAX) { 533 len = sd_get_phase_len(phase_map, start); 534 if (len_final < len) { 535 start_final = start; 536 len_final = len; 537 } 538 start += len ? len : 1; 539 } 540 541 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 542 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 543 phase_map, len_final, final_phase); 544 545 return final_phase; 546 } 547 548 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 549 { 550 int err, i; 551 u8 val = 0; 552 553 for (i = 0; i < 100; i++) { 554 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 555 if (val & SD_DATA_IDLE) 556 return; 557 558 udelay(100); 559 } 560 } 561 562 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 563 u8 opcode, u8 sample_point) 564 { 565 int err; 566 u8 cmd[5] = {0}; 567 568 err = sd_change_phase(host, sample_point, true); 569 if (err < 0) 570 return err; 571 572 cmd[0] = 0x40 | opcode; 573 err = sd_read_data(host, cmd, 0x40, NULL, 0, 100); 574 if (err < 0) { 575 /* Wait till SD DATA IDLE */ 576 sd_wait_data_idle(host); 577 sd_clear_error(host); 578 return err; 579 } 580 581 return 0; 582 } 583 584 static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 585 u8 opcode, u32 *phase_map) 586 { 587 int err, i; 588 u32 raw_phase_map = 0; 589 590 for (i = 0; i < RTSX_PHASE_MAX; i++) { 591 err = sd_tuning_rx_cmd(host, opcode, (u8)i); 592 if (err == 0) 593 raw_phase_map |= 1 << i; 594 } 595 596 if (phase_map) 597 *phase_map = raw_phase_map; 598 599 return 0; 600 } 601 602 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 603 { 604 int err, i; 605 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 606 u8 final_phase; 607 608 for (i = 0; i < RX_TUNING_CNT; i++) { 609 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 610 if (err < 0) 611 return err; 612 613 if (raw_phase_map[i] == 0) 614 break; 615 } 616 617 phase_map = 0xFFFFFFFF; 618 for (i = 0; i < RX_TUNING_CNT; i++) { 619 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 620 i, raw_phase_map[i]); 621 phase_map &= raw_phase_map[i]; 622 } 623 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 624 625 if (phase_map) { 626 final_phase = sd_search_final_phase(host, phase_map); 627 if (final_phase == 0xFF) 628 return -EINVAL; 629 630 err = sd_change_phase(host, final_phase, true); 631 if (err < 0) 632 return err; 633 } else { 634 return -EINVAL; 635 } 636 637 return 0; 638 } 639 640 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 641 { 642 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 643 struct rtsx_pcr *pcr = host->pcr; 644 struct mmc_command *cmd = mrq->cmd; 645 struct mmc_data *data = mrq->data; 646 unsigned int data_size = 0; 647 int err; 648 649 if (host->eject) { 650 cmd->error = -ENOMEDIUM; 651 goto finish; 652 } 653 654 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 655 if (err) { 656 cmd->error = err; 657 goto finish; 658 } 659 660 mutex_lock(&pcr->pcr_mutex); 661 662 rtsx_pci_start_run(pcr); 663 664 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 665 host->initial_mode, host->double_clk, host->vpclk); 666 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 667 rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 668 CARD_SHARE_MASK, CARD_SHARE_48_SD); 669 670 mutex_lock(&host->host_mutex); 671 host->mrq = mrq; 672 mutex_unlock(&host->host_mutex); 673 674 if (mrq->data) 675 data_size = data->blocks * data->blksz; 676 677 if (!data_size || mmc_op_multi(cmd->opcode) || 678 (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 679 (cmd->opcode == MMC_WRITE_BLOCK)) { 680 sd_send_cmd_get_rsp(host, cmd); 681 682 if (!cmd->error && data_size) { 683 sd_rw_multi(host, mrq); 684 685 if (mmc_op_multi(cmd->opcode) && mrq->stop) 686 sd_send_cmd_get_rsp(host, mrq->stop); 687 } 688 } else { 689 sd_normal_rw(host, mrq); 690 } 691 692 if (mrq->data) { 693 if (cmd->error || data->error) 694 data->bytes_xfered = 0; 695 else 696 data->bytes_xfered = data->blocks * data->blksz; 697 } 698 699 mutex_unlock(&pcr->pcr_mutex); 700 701 finish: 702 if (cmd->error) 703 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error); 704 705 mutex_lock(&host->host_mutex); 706 host->mrq = NULL; 707 mutex_unlock(&host->host_mutex); 708 709 mmc_request_done(mmc, mrq); 710 } 711 712 static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 713 unsigned char bus_width) 714 { 715 int err = 0; 716 u8 width[] = { 717 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 718 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 719 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 720 }; 721 722 if (bus_width <= MMC_BUS_WIDTH_8) 723 err = rtsx_pci_write_register(host->pcr, SD_CFG1, 724 0x03, width[bus_width]); 725 726 return err; 727 } 728 729 static int sd_power_on(struct realtek_pci_sdmmc *host) 730 { 731 struct rtsx_pcr *pcr = host->pcr; 732 int err; 733 734 if (host->power_state == SDMMC_POWER_ON) 735 return 0; 736 737 rtsx_pci_init_cmd(pcr); 738 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 739 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 740 CARD_SHARE_MASK, CARD_SHARE_48_SD); 741 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 742 SD_CLK_EN, SD_CLK_EN); 743 err = rtsx_pci_send_cmd(pcr, 100); 744 if (err < 0) 745 return err; 746 747 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 748 if (err < 0) 749 return err; 750 751 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 752 if (err < 0) 753 return err; 754 755 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 756 if (err < 0) 757 return err; 758 759 host->power_state = SDMMC_POWER_ON; 760 return 0; 761 } 762 763 static int sd_power_off(struct realtek_pci_sdmmc *host) 764 { 765 struct rtsx_pcr *pcr = host->pcr; 766 int err; 767 768 host->power_state = SDMMC_POWER_OFF; 769 770 rtsx_pci_init_cmd(pcr); 771 772 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 773 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 774 775 err = rtsx_pci_send_cmd(pcr, 100); 776 if (err < 0) 777 return err; 778 779 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 780 if (err < 0) 781 return err; 782 783 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 784 } 785 786 static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 787 unsigned char power_mode) 788 { 789 int err; 790 791 if (power_mode == MMC_POWER_OFF) 792 err = sd_power_off(host); 793 else 794 err = sd_power_on(host); 795 796 return err; 797 } 798 799 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 800 { 801 struct rtsx_pcr *pcr = host->pcr; 802 int err = 0; 803 804 rtsx_pci_init_cmd(pcr); 805 806 switch (timing) { 807 case MMC_TIMING_UHS_SDR104: 808 case MMC_TIMING_UHS_SDR50: 809 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 810 0x0C | SD_ASYNC_FIFO_NOT_RST, 811 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 812 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 813 CLK_LOW_FREQ, CLK_LOW_FREQ); 814 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 815 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 816 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 817 break; 818 819 case MMC_TIMING_UHS_DDR50: 820 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 821 0x0C | SD_ASYNC_FIFO_NOT_RST, 822 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 823 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 824 CLK_LOW_FREQ, CLK_LOW_FREQ); 825 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 826 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 827 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 828 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 829 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 830 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 831 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 832 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 833 break; 834 835 case MMC_TIMING_MMC_HS: 836 case MMC_TIMING_SD_HS: 837 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 838 0x0C, SD_20_MODE); 839 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 840 CLK_LOW_FREQ, CLK_LOW_FREQ); 841 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 842 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 843 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 844 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 845 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 846 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 847 SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 848 break; 849 850 default: 851 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 852 SD_CFG1, 0x0C, SD_20_MODE); 853 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 854 CLK_LOW_FREQ, CLK_LOW_FREQ); 855 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 856 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 857 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 858 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 859 SD_PUSH_POINT_CTL, 0xFF, 0); 860 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 861 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 862 break; 863 } 864 865 err = rtsx_pci_send_cmd(pcr, 100); 866 867 return err; 868 } 869 870 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 871 { 872 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 873 struct rtsx_pcr *pcr = host->pcr; 874 875 if (host->eject) 876 return; 877 878 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 879 return; 880 881 mutex_lock(&pcr->pcr_mutex); 882 883 rtsx_pci_start_run(pcr); 884 885 sd_set_bus_width(host, ios->bus_width); 886 sd_set_power_mode(host, ios->power_mode); 887 sd_set_timing(host, ios->timing); 888 889 host->vpclk = false; 890 host->double_clk = true; 891 892 switch (ios->timing) { 893 case MMC_TIMING_UHS_SDR104: 894 case MMC_TIMING_UHS_SDR50: 895 host->ssc_depth = RTSX_SSC_DEPTH_2M; 896 host->vpclk = true; 897 host->double_clk = false; 898 break; 899 case MMC_TIMING_UHS_DDR50: 900 case MMC_TIMING_UHS_SDR25: 901 host->ssc_depth = RTSX_SSC_DEPTH_1M; 902 break; 903 default: 904 host->ssc_depth = RTSX_SSC_DEPTH_500K; 905 break; 906 } 907 908 host->initial_mode = (ios->clock <= 1000000) ? true : false; 909 910 host->clock = ios->clock; 911 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 912 host->initial_mode, host->double_clk, host->vpclk); 913 914 mutex_unlock(&pcr->pcr_mutex); 915 } 916 917 static int sdmmc_get_ro(struct mmc_host *mmc) 918 { 919 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 920 struct rtsx_pcr *pcr = host->pcr; 921 int ro = 0; 922 u32 val; 923 924 if (host->eject) 925 return -ENOMEDIUM; 926 927 mutex_lock(&pcr->pcr_mutex); 928 929 rtsx_pci_start_run(pcr); 930 931 /* Check SD mechanical write-protect switch */ 932 val = rtsx_pci_readl(pcr, RTSX_BIPR); 933 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 934 if (val & SD_WRITE_PROTECT) 935 ro = 1; 936 937 mutex_unlock(&pcr->pcr_mutex); 938 939 return ro; 940 } 941 942 static int sdmmc_get_cd(struct mmc_host *mmc) 943 { 944 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 945 struct rtsx_pcr *pcr = host->pcr; 946 int cd = 0; 947 u32 val; 948 949 if (host->eject) 950 return -ENOMEDIUM; 951 952 mutex_lock(&pcr->pcr_mutex); 953 954 rtsx_pci_start_run(pcr); 955 956 /* Check SD card detect */ 957 val = rtsx_pci_card_exist(pcr); 958 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 959 if (val & SD_EXIST) 960 cd = 1; 961 962 mutex_unlock(&pcr->pcr_mutex); 963 964 return cd; 965 } 966 967 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 968 { 969 struct rtsx_pcr *pcr = host->pcr; 970 int err; 971 u8 stat; 972 973 /* Reference to Signal Voltage Switch Sequence in SD spec. 974 * Wait for a period of time so that the card can drive SD_CMD and 975 * SD_DAT[3:0] to low after sending back CMD11 response. 976 */ 977 mdelay(1); 978 979 /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 980 * If either one of SD_CMD,SD_DAT[3:0] is not low, 981 * abort the voltage switch sequence; 982 */ 983 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 984 if (err < 0) 985 return err; 986 987 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 988 SD_DAT1_STATUS | SD_DAT0_STATUS)) 989 return -EINVAL; 990 991 /* Stop toggle SD clock */ 992 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 993 0xFF, SD_CLK_FORCE_STOP); 994 if (err < 0) 995 return err; 996 997 return 0; 998 } 999 1000 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1001 { 1002 struct rtsx_pcr *pcr = host->pcr; 1003 int err; 1004 u8 stat, mask, val; 1005 1006 /* Wait 1.8V output of voltage regulator in card stable */ 1007 msleep(50); 1008 1009 /* Toggle SD clock again */ 1010 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1011 if (err < 0) 1012 return err; 1013 1014 /* Wait for a period of time so that the card can drive 1015 * SD_DAT[3:0] to high at 1.8V 1016 */ 1017 msleep(20); 1018 1019 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1020 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1021 if (err < 0) 1022 return err; 1023 1024 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1025 SD_DAT1_STATUS | SD_DAT0_STATUS; 1026 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1027 SD_DAT1_STATUS | SD_DAT0_STATUS; 1028 if ((stat & mask) != val) { 1029 dev_dbg(sdmmc_dev(host), 1030 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1031 rtsx_pci_write_register(pcr, SD_BUS_STAT, 1032 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1033 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1034 return -EINVAL; 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1041 { 1042 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1043 struct rtsx_pcr *pcr = host->pcr; 1044 int err = 0; 1045 u8 voltage; 1046 1047 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1048 __func__, ios->signal_voltage); 1049 1050 if (host->eject) 1051 return -ENOMEDIUM; 1052 1053 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1054 if (err) 1055 return err; 1056 1057 mutex_lock(&pcr->pcr_mutex); 1058 1059 rtsx_pci_start_run(pcr); 1060 1061 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1062 voltage = OUTPUT_3V3; 1063 else 1064 voltage = OUTPUT_1V8; 1065 1066 if (voltage == OUTPUT_1V8) { 1067 err = sd_wait_voltage_stable_1(host); 1068 if (err < 0) 1069 goto out; 1070 } 1071 1072 err = rtsx_pci_switch_output_voltage(pcr, voltage); 1073 if (err < 0) 1074 goto out; 1075 1076 if (voltage == OUTPUT_1V8) { 1077 err = sd_wait_voltage_stable_2(host); 1078 if (err < 0) 1079 goto out; 1080 } 1081 1082 out: 1083 /* Stop toggle SD clock in idle */ 1084 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1085 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1086 1087 mutex_unlock(&pcr->pcr_mutex); 1088 1089 return err; 1090 } 1091 1092 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1093 { 1094 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1095 struct rtsx_pcr *pcr = host->pcr; 1096 int err = 0; 1097 1098 if (host->eject) 1099 return -ENOMEDIUM; 1100 1101 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1102 if (err) 1103 return err; 1104 1105 mutex_lock(&pcr->pcr_mutex); 1106 1107 rtsx_pci_start_run(pcr); 1108 1109 /* Set initial TX phase */ 1110 switch (mmc->ios.timing) { 1111 case MMC_TIMING_UHS_SDR104: 1112 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 1113 break; 1114 1115 case MMC_TIMING_UHS_SDR50: 1116 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 1117 break; 1118 1119 case MMC_TIMING_UHS_DDR50: 1120 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 1121 break; 1122 1123 default: 1124 err = 0; 1125 } 1126 1127 if (err) 1128 goto out; 1129 1130 /* Tuning RX phase */ 1131 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 1132 (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 1133 err = sd_tuning_rx(host, opcode); 1134 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 1135 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 1136 1137 out: 1138 mutex_unlock(&pcr->pcr_mutex); 1139 1140 return err; 1141 } 1142 1143 static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 1144 .request = sdmmc_request, 1145 .set_ios = sdmmc_set_ios, 1146 .get_ro = sdmmc_get_ro, 1147 .get_cd = sdmmc_get_cd, 1148 .start_signal_voltage_switch = sdmmc_switch_voltage, 1149 .execute_tuning = sdmmc_execute_tuning, 1150 }; 1151 1152 static void init_extra_caps(struct realtek_pci_sdmmc *host) 1153 { 1154 struct mmc_host *mmc = host->mmc; 1155 struct rtsx_pcr *pcr = host->pcr; 1156 1157 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1158 1159 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1160 mmc->caps |= MMC_CAP_UHS_SDR50; 1161 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1162 mmc->caps |= MMC_CAP_UHS_SDR104; 1163 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1164 mmc->caps |= MMC_CAP_UHS_DDR50; 1165 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1166 mmc->caps |= MMC_CAP_1_8V_DDR; 1167 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1168 mmc->caps |= MMC_CAP_8_BIT_DATA; 1169 } 1170 1171 static void realtek_init_host(struct realtek_pci_sdmmc *host) 1172 { 1173 struct mmc_host *mmc = host->mmc; 1174 1175 mmc->f_min = 250000; 1176 mmc->f_max = 208000000; 1177 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1178 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1179 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1180 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1181 mmc->max_current_330 = 400; 1182 mmc->max_current_180 = 800; 1183 mmc->ops = &realtek_pci_sdmmc_ops; 1184 1185 init_extra_caps(host); 1186 1187 mmc->max_segs = 256; 1188 mmc->max_seg_size = 65536; 1189 mmc->max_blk_size = 512; 1190 mmc->max_blk_count = 65535; 1191 mmc->max_req_size = 524288; 1192 } 1193 1194 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1195 { 1196 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1197 1198 mmc_detect_change(host->mmc, 0); 1199 } 1200 1201 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1202 { 1203 struct mmc_host *mmc; 1204 struct realtek_pci_sdmmc *host; 1205 struct rtsx_pcr *pcr; 1206 struct pcr_handle *handle = pdev->dev.platform_data; 1207 1208 if (!handle) 1209 return -ENXIO; 1210 1211 pcr = handle->pcr; 1212 if (!pcr) 1213 return -ENXIO; 1214 1215 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1216 1217 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1218 if (!mmc) 1219 return -ENOMEM; 1220 1221 host = mmc_priv(mmc); 1222 host->pcr = pcr; 1223 host->mmc = mmc; 1224 host->pdev = pdev; 1225 host->power_state = SDMMC_POWER_OFF; 1226 platform_set_drvdata(pdev, host); 1227 pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1228 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1229 1230 mutex_init(&host->host_mutex); 1231 1232 realtek_init_host(host); 1233 1234 mmc_add_host(mmc); 1235 1236 return 0; 1237 } 1238 1239 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1240 { 1241 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1242 struct rtsx_pcr *pcr; 1243 struct mmc_host *mmc; 1244 1245 if (!host) 1246 return 0; 1247 1248 pcr = host->pcr; 1249 pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1250 pcr->slots[RTSX_SD_CARD].card_event = NULL; 1251 mmc = host->mmc; 1252 1253 mutex_lock(&host->host_mutex); 1254 if (host->mrq) { 1255 dev_dbg(&(pdev->dev), 1256 "%s: Controller removed during transfer\n", 1257 mmc_hostname(mmc)); 1258 1259 rtsx_pci_complete_unfinished_transfer(pcr); 1260 1261 host->mrq->cmd->error = -ENOMEDIUM; 1262 if (host->mrq->stop) 1263 host->mrq->stop->error = -ENOMEDIUM; 1264 mmc_request_done(mmc, host->mrq); 1265 } 1266 mutex_unlock(&host->host_mutex); 1267 1268 mmc_remove_host(mmc); 1269 host->eject = true; 1270 1271 mmc_free_host(mmc); 1272 1273 dev_dbg(&(pdev->dev), 1274 ": Realtek PCI-E SDMMC controller has been removed\n"); 1275 1276 return 0; 1277 } 1278 1279 static struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1280 { 1281 .name = DRV_NAME_RTSX_PCI_SDMMC, 1282 }, { 1283 /* sentinel */ 1284 } 1285 }; 1286 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1287 1288 static struct platform_driver rtsx_pci_sdmmc_driver = { 1289 .probe = rtsx_pci_sdmmc_drv_probe, 1290 .remove = rtsx_pci_sdmmc_drv_remove, 1291 .id_table = rtsx_pci_sdmmc_ids, 1292 .driver = { 1293 .owner = THIS_MODULE, 1294 .name = DRV_NAME_RTSX_PCI_SDMMC, 1295 }, 1296 }; 1297 module_platform_driver(rtsx_pci_sdmmc_driver); 1298 1299 MODULE_LICENSE("GPL"); 1300 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1301 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1302