1aaf4989bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver
3ff984e57SWei WANG *
462282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5ff984e57SWei WANG *
6ff984e57SWei WANG * Author:
7ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn>
8ff984e57SWei WANG */
9ff984e57SWei WANG
10ff984e57SWei WANG #include <linux/module.h>
11433e075cSWei WANG #include <linux/slab.h>
12ff984e57SWei WANG #include <linux/highmem.h>
13ff984e57SWei WANG #include <linux/delay.h>
14ff984e57SWei WANG #include <linux/platform_device.h>
156291e715SMicky Ching #include <linux/workqueue.h>
16ff984e57SWei WANG #include <linux/mmc/host.h>
17ff984e57SWei WANG #include <linux/mmc/mmc.h>
18ff984e57SWei WANG #include <linux/mmc/sd.h>
191dcb3579SMicky Ching #include <linux/mmc/sdio.h>
20ff984e57SWei WANG #include <linux/mmc/card.h>
21e455b69dSRui Feng #include <linux/rtsx_pci.h>
22ff984e57SWei WANG #include <asm/unaligned.h>
235b4258f6SRicky Wu #include <linux/pm_runtime.h>
24ff984e57SWei WANG
25ff984e57SWei WANG struct realtek_pci_sdmmc {
26ff984e57SWei WANG struct platform_device *pdev;
27ff984e57SWei WANG struct rtsx_pcr *pcr;
28ff984e57SWei WANG struct mmc_host *mmc;
29ff984e57SWei WANG struct mmc_request *mrq;
306291e715SMicky Ching #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
31ff984e57SWei WANG
326291e715SMicky Ching struct work_struct work;
3398fcc576SMicky Ching struct mutex host_mutex;
34ff984e57SWei WANG
35ff984e57SWei WANG u8 ssc_depth;
36ff984e57SWei WANG unsigned int clock;
37ff984e57SWei WANG bool vpclk;
38ff984e57SWei WANG bool double_clk;
39ff984e57SWei WANG bool eject;
40ff984e57SWei WANG bool initial_mode;
411f311c94SRicky WU int prev_power_state;
42be186ad5SMicky Ching int sg_count;
436291e715SMicky Ching s32 cookie;
44be186ad5SMicky Ching int cookie_sg_count;
456291e715SMicky Ching bool using_cookie;
46ff984e57SWei WANG };
47ff984e57SWei WANG
486b7b58f4SRui Feng static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios);
496b7b58f4SRui Feng
sdmmc_dev(struct realtek_pci_sdmmc * host)50ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
51ff984e57SWei WANG {
52ff984e57SWei WANG return &(host->pdev->dev);
53ff984e57SWei WANG }
54ff984e57SWei WANG
sd_clear_error(struct realtek_pci_sdmmc * host)55ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
56ff984e57SWei WANG {
57ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP,
58ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
59ff984e57SWei WANG }
60ff984e57SWei WANG
61ff984e57SWei WANG #ifdef DEBUG
dump_reg_range(struct realtek_pci_sdmmc * host,u16 start,u16 end)62755987f9SMicky Ching static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
63755987f9SMicky Ching {
64755987f9SMicky Ching u16 len = end - start + 1;
65755987f9SMicky Ching int i;
66755987f9SMicky Ching u8 data[8];
67755987f9SMicky Ching
68755987f9SMicky Ching for (i = 0; i < len; i += 8) {
69755987f9SMicky Ching int j;
70755987f9SMicky Ching int n = min(8, len - i);
71755987f9SMicky Ching
72755987f9SMicky Ching memset(&data, 0, sizeof(data));
73755987f9SMicky Ching for (j = 0; j < n; j++)
74755987f9SMicky Ching rtsx_pci_read_register(host->pcr, start + i + j,
75755987f9SMicky Ching data + j);
76755987f9SMicky Ching dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
77755987f9SMicky Ching start + i, n, data);
78755987f9SMicky Ching }
79755987f9SMicky Ching }
80755987f9SMicky Ching
sd_print_debug_regs(struct realtek_pci_sdmmc * host)81ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
82ff984e57SWei WANG {
83755987f9SMicky Ching dump_reg_range(host, 0xFDA0, 0xFDB3);
84755987f9SMicky Ching dump_reg_range(host, 0xFD52, 0xFD69);
85ff984e57SWei WANG }
86ff984e57SWei WANG #else
87ff984e57SWei WANG #define sd_print_debug_regs(host)
88ff984e57SWei WANG #endif /* DEBUG */
89ff984e57SWei WANG
sd_get_cd_int(struct realtek_pci_sdmmc * host)90b22217f9SMicky Ching static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
91b22217f9SMicky Ching {
92b22217f9SMicky Ching return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
93b22217f9SMicky Ching }
94b22217f9SMicky Ching
sd_cmd_set_sd_cmd(struct rtsx_pcr * pcr,struct mmc_command * cmd)952d48e5f1SMicky Ching static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
962d48e5f1SMicky Ching {
972d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
982d48e5f1SMicky Ching SD_CMD_START | cmd->opcode);
992d48e5f1SMicky Ching rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
1002d48e5f1SMicky Ching }
1012d48e5f1SMicky Ching
sd_cmd_set_data_len(struct rtsx_pcr * pcr,u16 blocks,u16 blksz)1022d48e5f1SMicky Ching static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
1032d48e5f1SMicky Ching {
1042d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
1052d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
1062d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
1072d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
1082d48e5f1SMicky Ching }
1092d48e5f1SMicky Ching
sd_response_type(struct mmc_command * cmd)1102d48e5f1SMicky Ching static int sd_response_type(struct mmc_command *cmd)
1112d48e5f1SMicky Ching {
1122d48e5f1SMicky Ching switch (mmc_resp_type(cmd)) {
1132d48e5f1SMicky Ching case MMC_RSP_NONE:
1142d48e5f1SMicky Ching return SD_RSP_TYPE_R0;
1152d48e5f1SMicky Ching case MMC_RSP_R1:
1162d48e5f1SMicky Ching return SD_RSP_TYPE_R1;
1178c8d0ecbSWolfram Sang case MMC_RSP_R1_NO_CRC:
1182d48e5f1SMicky Ching return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
1192d48e5f1SMicky Ching case MMC_RSP_R1B:
1202d48e5f1SMicky Ching return SD_RSP_TYPE_R1b;
1212d48e5f1SMicky Ching case MMC_RSP_R2:
1222d48e5f1SMicky Ching return SD_RSP_TYPE_R2;
1232d48e5f1SMicky Ching case MMC_RSP_R3:
1242d48e5f1SMicky Ching return SD_RSP_TYPE_R3;
1252d48e5f1SMicky Ching default:
1262d48e5f1SMicky Ching return -EINVAL;
1272d48e5f1SMicky Ching }
1282d48e5f1SMicky Ching }
1292d48e5f1SMicky Ching
sd_status_index(int resp_type)1302d48e5f1SMicky Ching static int sd_status_index(int resp_type)
1312d48e5f1SMicky Ching {
1322d48e5f1SMicky Ching if (resp_type == SD_RSP_TYPE_R0)
1332d48e5f1SMicky Ching return 0;
1342d48e5f1SMicky Ching else if (resp_type == SD_RSP_TYPE_R2)
1352d48e5f1SMicky Ching return 16;
1362d48e5f1SMicky Ching
1372d48e5f1SMicky Ching return 5;
1382d48e5f1SMicky Ching }
1396291e715SMicky Ching /*
1406291e715SMicky Ching * sd_pre_dma_transfer - do dma_map_sg() or using cookie
1416291e715SMicky Ching *
1426291e715SMicky Ching * @pre: if called in pre_req()
1436291e715SMicky Ching * return:
1446291e715SMicky Ching * 0 - do dma_map_sg()
1456291e715SMicky Ching * 1 - using cookie
1466291e715SMicky Ching */
sd_pre_dma_transfer(struct realtek_pci_sdmmc * host,struct mmc_data * data,bool pre)1476291e715SMicky Ching static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
1486291e715SMicky Ching struct mmc_data *data, bool pre)
1496291e715SMicky Ching {
1506291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr;
1516291e715SMicky Ching int read = data->flags & MMC_DATA_READ;
1526291e715SMicky Ching int count = 0;
1536291e715SMicky Ching int using_cookie = 0;
1546291e715SMicky Ching
1556291e715SMicky Ching if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
1566291e715SMicky Ching dev_err(sdmmc_dev(host),
1576291e715SMicky Ching "error: data->host_cookie = %d, host->cookie = %d\n",
1586291e715SMicky Ching data->host_cookie, host->cookie);
1596291e715SMicky Ching data->host_cookie = 0;
1606291e715SMicky Ching }
1616291e715SMicky Ching
1626291e715SMicky Ching if (pre || data->host_cookie != host->cookie) {
1636291e715SMicky Ching count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
1646291e715SMicky Ching } else {
1656291e715SMicky Ching count = host->cookie_sg_count;
1666291e715SMicky Ching using_cookie = 1;
1676291e715SMicky Ching }
1686291e715SMicky Ching
1696291e715SMicky Ching if (pre) {
1706291e715SMicky Ching host->cookie_sg_count = count;
1716291e715SMicky Ching if (++host->cookie < 0)
1726291e715SMicky Ching host->cookie = 1;
1736291e715SMicky Ching data->host_cookie = host->cookie;
1746291e715SMicky Ching } else {
1756291e715SMicky Ching host->sg_count = count;
1766291e715SMicky Ching }
1776291e715SMicky Ching
1786291e715SMicky Ching return using_cookie;
1796291e715SMicky Ching }
1806291e715SMicky Ching
sdmmc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)181d3c6aac3SLinus Walleij static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1826291e715SMicky Ching {
1836291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1846291e715SMicky Ching struct mmc_data *data = mrq->data;
1856291e715SMicky Ching
1866291e715SMicky Ching if (data->host_cookie) {
1876291e715SMicky Ching dev_err(sdmmc_dev(host),
1886291e715SMicky Ching "error: reset data->host_cookie = %d\n",
1896291e715SMicky Ching data->host_cookie);
1906291e715SMicky Ching data->host_cookie = 0;
1916291e715SMicky Ching }
1926291e715SMicky Ching
1936291e715SMicky Ching sd_pre_dma_transfer(host, data, true);
1946291e715SMicky Ching dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
1956291e715SMicky Ching }
1966291e715SMicky Ching
sdmmc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1976291e715SMicky Ching static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1986291e715SMicky Ching int err)
1996291e715SMicky Ching {
2006291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc);
2016291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr;
2026291e715SMicky Ching struct mmc_data *data = mrq->data;
2036291e715SMicky Ching int read = data->flags & MMC_DATA_READ;
2046291e715SMicky Ching
2056291e715SMicky Ching rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
2066291e715SMicky Ching data->host_cookie = 0;
2076291e715SMicky Ching }
2086291e715SMicky Ching
sd_send_cmd_get_rsp(struct realtek_pci_sdmmc * host,struct mmc_command * cmd)20998fcc576SMicky Ching static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
21098fcc576SMicky Ching struct mmc_command *cmd)
211ff984e57SWei WANG {
212ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
213ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode;
214ff984e57SWei WANG u32 arg = cmd->arg;
215ff984e57SWei WANG int err = 0;
216ff984e57SWei WANG int timeout = 100;
217ff984e57SWei WANG int i;
21898fcc576SMicky Ching u8 *ptr;
2192d48e5f1SMicky Ching int rsp_type;
2202d48e5f1SMicky Ching int stat_idx;
22198fcc576SMicky Ching bool clock_toggled = false;
222ff984e57SWei WANG
223ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
224ff984e57SWei WANG __func__, cmd_idx, arg);
225ff984e57SWei WANG
2262d48e5f1SMicky Ching rsp_type = sd_response_type(cmd);
2272d48e5f1SMicky Ching if (rsp_type < 0)
228ff984e57SWei WANG goto out;
2292d48e5f1SMicky Ching
2302d48e5f1SMicky Ching stat_idx = sd_status_index(rsp_type);
231ff984e57SWei WANG
232ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b)
23327f4bf7dSUlf Hansson timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
234ff984e57SWei WANG
235ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) {
236ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
237ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN);
238ff984e57SWei WANG if (err < 0)
239ff984e57SWei WANG goto out;
24098fcc576SMicky Ching
24198fcc576SMicky Ching clock_toggled = true;
242ff984e57SWei WANG }
243ff984e57SWei WANG
244ff984e57SWei WANG rtsx_pci_init_cmd(pcr);
2452d48e5f1SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd);
246ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
247ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
248ff984e57SWei WANG 0x01, PINGPONG_BUFFER);
249ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
250ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
251ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
252ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE,
253ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE);
254ff984e57SWei WANG
255ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) {
256ff984e57SWei WANG /* Read data from ping-pong buffer */
257ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
258ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
259ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) {
260ff984e57SWei WANG /* Read data from SD_CMDx registers */
261ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++)
262ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
263ff984e57SWei WANG }
264ff984e57SWei WANG
265ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
266ff984e57SWei WANG
26798fcc576SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout);
26898fcc576SMicky Ching if (err < 0) {
26998fcc576SMicky Ching sd_print_debug_regs(host);
27098fcc576SMicky Ching sd_clear_error(host);
27198fcc576SMicky Ching dev_dbg(sdmmc_dev(host),
27298fcc576SMicky Ching "rtsx_pci_send_cmd error (err = %d)\n", err);
273ff984e57SWei WANG goto out;
274ff984e57SWei WANG }
275ff984e57SWei WANG
276ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) {
277ff984e57SWei WANG err = 0;
278ff984e57SWei WANG goto out;
279ff984e57SWei WANG }
280ff984e57SWei WANG
281ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */
282ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1;
283ff984e57SWei WANG
284ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */
285ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) {
286ff984e57SWei WANG err = -EILSEQ;
287ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
288ff984e57SWei WANG goto out;
289ff984e57SWei WANG }
290ff984e57SWei WANG
291ff984e57SWei WANG /* Check CRC7 */
292ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) {
293ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) {
294ff984e57SWei WANG err = -EILSEQ;
295ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n");
296ff984e57SWei WANG goto out;
297ff984e57SWei WANG }
298ff984e57SWei WANG }
299ff984e57SWei WANG
300ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) {
301d1419d50SRoger Tseng /*
302d1419d50SRoger Tseng * The controller offloads the last byte {CRC-7, end bit 1'b1}
303d1419d50SRoger Tseng * of response type R2. Assign dummy CRC, 0, and end bit to the
304d1419d50SRoger Tseng * byte(ptr[16], goes into the LSB of resp[3] later).
305d1419d50SRoger Tseng */
306d1419d50SRoger Tseng ptr[16] = 1;
307d1419d50SRoger Tseng
308ff984e57SWei WANG for (i = 0; i < 4; i++) {
309ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
310ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
311ff984e57SWei WANG i, cmd->resp[i]);
312ff984e57SWei WANG }
313ff984e57SWei WANG } else {
314ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1);
315ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
316ff984e57SWei WANG cmd->resp[0]);
317ff984e57SWei WANG }
318ff984e57SWei WANG
319ff984e57SWei WANG out:
320ff984e57SWei WANG cmd->error = err;
3211b8055b4SWei WANG
32298fcc576SMicky Ching if (err && clock_toggled)
32398fcc576SMicky Ching rtsx_pci_write_register(pcr, SD_BUS_STAT,
32498fcc576SMicky Ching SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
325ff984e57SWei WANG }
326ff984e57SWei WANG
sd_read_data(struct realtek_pci_sdmmc * host,struct mmc_command * cmd,u16 byte_cnt,u8 * buf,int buf_len,int timeout)32756d1c0d9SMicky Ching static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
32856d1c0d9SMicky Ching u16 byte_cnt, u8 *buf, int buf_len, int timeout)
32956d1c0d9SMicky Ching {
33056d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr;
33156d1c0d9SMicky Ching int err;
33256d1c0d9SMicky Ching u8 trans_mode;
33356d1c0d9SMicky Ching
33456d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
33556d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg);
33656d1c0d9SMicky Ching
33756d1c0d9SMicky Ching if (!buf)
33856d1c0d9SMicky Ching buf_len = 0;
33956d1c0d9SMicky Ching
34056d1c0d9SMicky Ching if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
34156d1c0d9SMicky Ching trans_mode = SD_TM_AUTO_TUNING;
34256d1c0d9SMicky Ching else
34356d1c0d9SMicky Ching trans_mode = SD_TM_NORMAL_READ;
34456d1c0d9SMicky Ching
34556d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr);
34656d1c0d9SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd);
34756d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt);
34856d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
34956d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
35056d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
35156d1c0d9SMicky Ching if (trans_mode != SD_TM_AUTO_TUNING)
35256d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
35356d1c0d9SMicky Ching CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
35456d1c0d9SMicky Ching
35556d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
35656d1c0d9SMicky Ching 0xFF, trans_mode | SD_TRANSFER_START);
35756d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
35856d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END);
35956d1c0d9SMicky Ching
36056d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout);
36156d1c0d9SMicky Ching if (err < 0) {
36256d1c0d9SMicky Ching sd_print_debug_regs(host);
36356d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host),
36456d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err);
36556d1c0d9SMicky Ching return err;
36656d1c0d9SMicky Ching }
36756d1c0d9SMicky Ching
36856d1c0d9SMicky Ching if (buf && buf_len) {
36956d1c0d9SMicky Ching err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
37056d1c0d9SMicky Ching if (err < 0) {
37156d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host),
37256d1c0d9SMicky Ching "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
37356d1c0d9SMicky Ching return err;
37456d1c0d9SMicky Ching }
37556d1c0d9SMicky Ching }
37656d1c0d9SMicky Ching
37756d1c0d9SMicky Ching return 0;
37856d1c0d9SMicky Ching }
37956d1c0d9SMicky Ching
sd_write_data(struct realtek_pci_sdmmc * host,struct mmc_command * cmd,u16 byte_cnt,u8 * buf,int buf_len,int timeout)38056d1c0d9SMicky Ching static int sd_write_data(struct realtek_pci_sdmmc *host,
38156d1c0d9SMicky Ching struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
38256d1c0d9SMicky Ching int timeout)
38356d1c0d9SMicky Ching {
38456d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr;
38556d1c0d9SMicky Ching int err;
38656d1c0d9SMicky Ching
38756d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
38856d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg);
38956d1c0d9SMicky Ching
39056d1c0d9SMicky Ching if (!buf)
39156d1c0d9SMicky Ching buf_len = 0;
39256d1c0d9SMicky Ching
39356d1c0d9SMicky Ching sd_send_cmd_get_rsp(host, cmd);
39456d1c0d9SMicky Ching if (cmd->error)
39556d1c0d9SMicky Ching return cmd->error;
39656d1c0d9SMicky Ching
39756d1c0d9SMicky Ching if (buf && buf_len) {
39856d1c0d9SMicky Ching err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
39956d1c0d9SMicky Ching if (err < 0) {
40056d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host),
40156d1c0d9SMicky Ching "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
40256d1c0d9SMicky Ching return err;
40356d1c0d9SMicky Ching }
40456d1c0d9SMicky Ching }
40556d1c0d9SMicky Ching
40656d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr);
40756d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt);
40856d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
40956d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
41056d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
41156d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
41256d1c0d9SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
41356d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
41456d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END);
41556d1c0d9SMicky Ching
41656d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout);
41756d1c0d9SMicky Ching if (err < 0) {
41856d1c0d9SMicky Ching sd_print_debug_regs(host);
41956d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host),
42056d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err);
42156d1c0d9SMicky Ching return err;
42256d1c0d9SMicky Ching }
42356d1c0d9SMicky Ching
42456d1c0d9SMicky Ching return 0;
42556d1c0d9SMicky Ching }
42656d1c0d9SMicky Ching
sd_read_long_data(struct realtek_pci_sdmmc * host,struct mmc_request * mrq)4271dcb3579SMicky Ching static int sd_read_long_data(struct realtek_pci_sdmmc *host,
4281dcb3579SMicky Ching struct mmc_request *mrq)
429ff984e57SWei WANG {
430ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
431ff984e57SWei WANG struct mmc_host *mmc = host->mmc;
432ff984e57SWei WANG struct mmc_card *card = mmc->card;
4331dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd;
434ff984e57SWei WANG struct mmc_data *data = mrq->data;
43571ef1ea4SJackey Shen int uhs = mmc_card_uhs(card);
4361dcb3579SMicky Ching u8 cfg2 = 0;
437ff984e57SWei WANG int err;
4381dcb3579SMicky Ching int resp_type;
439ff984e57SWei WANG size_t data_len = data->blksz * data->blocks;
440ff984e57SWei WANG
4411dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
4421dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg);
4431dcb3579SMicky Ching
4441dcb3579SMicky Ching resp_type = sd_response_type(cmd);
4451dcb3579SMicky Ching if (resp_type < 0)
4461dcb3579SMicky Ching return resp_type;
447ff984e57SWei WANG
448ff984e57SWei WANG if (!uhs)
449ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
450ff984e57SWei WANG
451ff984e57SWei WANG rtsx_pci_init_cmd(pcr);
4521dcb3579SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd);
4531dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
454ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
455ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT);
456ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
457ff984e57SWei WANG 0xFF, (u8)(data_len >> 24));
458ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
459ff984e57SWei WANG 0xFF, (u8)(data_len >> 16));
460ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
461ff984e57SWei WANG 0xFF, (u8)(data_len >> 8));
462ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
463ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
464ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK,
465ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
4661dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
4671dcb3579SMicky Ching 0x01, RING_BUFFER);
4681dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
4691dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
4701dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_READ_2);
4711dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
4721dcb3579SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END);
4731dcb3579SMicky Ching rtsx_pci_send_cmd_no_wait(pcr);
4741dcb3579SMicky Ching
4751dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
4761dcb3579SMicky Ching if (err < 0) {
4771dcb3579SMicky Ching sd_print_debug_regs(host);
4781dcb3579SMicky Ching sd_clear_error(host);
4791dcb3579SMicky Ching return err;
4801dcb3579SMicky Ching }
4811dcb3579SMicky Ching
4821dcb3579SMicky Ching return 0;
4831dcb3579SMicky Ching }
4841dcb3579SMicky Ching
sd_write_long_data(struct realtek_pci_sdmmc * host,struct mmc_request * mrq)4851dcb3579SMicky Ching static int sd_write_long_data(struct realtek_pci_sdmmc *host,
4861dcb3579SMicky Ching struct mmc_request *mrq)
4871dcb3579SMicky Ching {
4881dcb3579SMicky Ching struct rtsx_pcr *pcr = host->pcr;
4891dcb3579SMicky Ching struct mmc_host *mmc = host->mmc;
4901dcb3579SMicky Ching struct mmc_card *card = mmc->card;
4911dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd;
4921dcb3579SMicky Ching struct mmc_data *data = mrq->data;
4931dcb3579SMicky Ching int uhs = mmc_card_uhs(card);
4941dcb3579SMicky Ching u8 cfg2;
4951dcb3579SMicky Ching int err;
4961dcb3579SMicky Ching size_t data_len = data->blksz * data->blocks;
4971dcb3579SMicky Ching
4981dcb3579SMicky Ching sd_send_cmd_get_rsp(host, cmd);
4991dcb3579SMicky Ching if (cmd->error)
5001dcb3579SMicky Ching return cmd->error;
5011dcb3579SMicky Ching
5021dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
5031dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg);
5041dcb3579SMicky Ching
5051dcb3579SMicky Ching cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
5061dcb3579SMicky Ching SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
5071dcb3579SMicky Ching
5081dcb3579SMicky Ching if (!uhs)
5091dcb3579SMicky Ching cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
5101dcb3579SMicky Ching
5111dcb3579SMicky Ching rtsx_pci_init_cmd(pcr);
5121dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
5131dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
5141dcb3579SMicky Ching DMA_DONE_INT, DMA_DONE_INT);
5151dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
5161dcb3579SMicky Ching 0xFF, (u8)(data_len >> 24));
5171dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
5181dcb3579SMicky Ching 0xFF, (u8)(data_len >> 16));
5191dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
5201dcb3579SMicky Ching 0xFF, (u8)(data_len >> 8));
5211dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
522ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
523ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK,
524ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512);
525ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
526ff984e57SWei WANG 0x01, RING_BUFFER);
52738d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
528ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
5291dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
530ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
531ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END);
532ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr);
5331dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
534ff984e57SWei WANG if (err < 0) {
53598fcc576SMicky Ching sd_clear_error(host);
53698fcc576SMicky Ching return err;
537c42deffdSMicky Ching }
53898fcc576SMicky Ching
539c42deffdSMicky Ching return 0;
540ff984e57SWei WANG }
541ff984e57SWei WANG
sd_enable_initial_mode(struct realtek_pci_sdmmc * host)542ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
543ff984e57SWei WANG {
544ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1,
545ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
546ff984e57SWei WANG }
547ff984e57SWei WANG
sd_disable_initial_mode(struct realtek_pci_sdmmc * host)548ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
549ff984e57SWei WANG {
550ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1,
551ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
552ff984e57SWei WANG }
553ff984e57SWei WANG
sd_rw_multi(struct realtek_pci_sdmmc * host,struct mmc_request * mrq)5543ac5e452SThomas Hebb static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
5553ac5e452SThomas Hebb {
5563ac5e452SThomas Hebb struct mmc_data *data = mrq->data;
5573ac5e452SThomas Hebb int err;
5583ac5e452SThomas Hebb
5593ac5e452SThomas Hebb if (host->sg_count < 0) {
5603ac5e452SThomas Hebb data->error = host->sg_count;
5613ac5e452SThomas Hebb dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
5623ac5e452SThomas Hebb __func__, host->sg_count);
5633ac5e452SThomas Hebb return data->error;
5643ac5e452SThomas Hebb }
5653ac5e452SThomas Hebb
5663ac5e452SThomas Hebb if (data->flags & MMC_DATA_READ) {
5673ac5e452SThomas Hebb if (host->initial_mode)
5683ac5e452SThomas Hebb sd_disable_initial_mode(host);
5693ac5e452SThomas Hebb
5703ac5e452SThomas Hebb err = sd_read_long_data(host, mrq);
5713ac5e452SThomas Hebb
5723ac5e452SThomas Hebb if (host->initial_mode)
5733ac5e452SThomas Hebb sd_enable_initial_mode(host);
5743ac5e452SThomas Hebb
5753ac5e452SThomas Hebb return err;
5763ac5e452SThomas Hebb }
5773ac5e452SThomas Hebb
5783ac5e452SThomas Hebb return sd_write_long_data(host, mrq);
5793ac5e452SThomas Hebb }
5803ac5e452SThomas Hebb
sd_normal_rw(struct realtek_pci_sdmmc * host,struct mmc_request * mrq)581ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host,
582ff984e57SWei WANG struct mmc_request *mrq)
583ff984e57SWei WANG {
584ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd;
585ff984e57SWei WANG struct mmc_data *data = mrq->data;
5861dcb3579SMicky Ching u8 *buf;
587ff984e57SWei WANG
588ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO);
589ff984e57SWei WANG if (!buf) {
590ff984e57SWei WANG cmd->error = -ENOMEM;
591ff984e57SWei WANG return;
592ff984e57SWei WANG }
593ff984e57SWei WANG
594ff984e57SWei WANG if (data->flags & MMC_DATA_READ) {
595ff984e57SWei WANG if (host->initial_mode)
596ff984e57SWei WANG sd_disable_initial_mode(host);
597ff984e57SWei WANG
5981dcb3579SMicky Ching cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
599ff984e57SWei WANG data->blksz, 200);
600ff984e57SWei WANG
601ff984e57SWei WANG if (host->initial_mode)
602ff984e57SWei WANG sd_enable_initial_mode(host);
603ff984e57SWei WANG
604ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
605ff984e57SWei WANG } else {
606ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
607ff984e57SWei WANG
6081dcb3579SMicky Ching cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
609ff984e57SWei WANG data->blksz, 200);
610ff984e57SWei WANG }
611ff984e57SWei WANG
612ff984e57SWei WANG kfree(buf);
613ff984e57SWei WANG }
614ff984e57SWei WANG
sd_change_phase(struct realtek_pci_sdmmc * host,u8 sample_point,bool rx)61584d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host,
61684d72f9cSWei WANG u8 sample_point, bool rx)
617ff984e57SWei WANG {
618ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
6194686392cSRicky Wu u16 SD_VP_CTL = 0;
62084d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
62184d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point);
622ff984e57SWei WANG
623563be8b6Srui_feng rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
6244686392cSRicky Wu if (rx) {
6254686392cSRicky Wu SD_VP_CTL = SD_VPRX_CTL;
626563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_VPRX_CTL,
627563be8b6Srui_feng PHASE_SELECT_MASK, sample_point);
6284686392cSRicky Wu } else {
6294686392cSRicky Wu SD_VP_CTL = SD_VPTX_CTL;
630563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_VPTX_CTL,
631563be8b6Srui_feng PHASE_SELECT_MASK, sample_point);
6324686392cSRicky Wu }
6334686392cSRicky Wu rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
6344686392cSRicky Wu rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
635563be8b6Srui_feng PHASE_NOT_RESET);
636563be8b6Srui_feng rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
637563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
638ff984e57SWei WANG
639ff984e57SWei WANG return 0;
640ff984e57SWei WANG }
641ff984e57SWei WANG
test_phase_bit(u32 phase_map,unsigned int bit)642abcc6b29SMicky Ching static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
643abcc6b29SMicky Ching {
644abcc6b29SMicky Ching bit %= RTSX_PHASE_MAX;
645abcc6b29SMicky Ching return phase_map & (1 << bit);
646abcc6b29SMicky Ching }
647abcc6b29SMicky Ching
sd_get_phase_len(u32 phase_map,unsigned int start_bit)648abcc6b29SMicky Ching static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
649abcc6b29SMicky Ching {
650abcc6b29SMicky Ching int i;
651abcc6b29SMicky Ching
652abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) {
653abcc6b29SMicky Ching if (test_phase_bit(phase_map, start_bit + i) == 0)
654abcc6b29SMicky Ching return i;
655abcc6b29SMicky Ching }
656abcc6b29SMicky Ching return RTSX_PHASE_MAX;
657abcc6b29SMicky Ching }
658abcc6b29SMicky Ching
sd_search_final_phase(struct realtek_pci_sdmmc * host,u32 phase_map)659ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
660ff984e57SWei WANG {
661abcc6b29SMicky Ching int start = 0, len = 0;
662abcc6b29SMicky Ching int start_final = 0, len_final = 0;
663ff984e57SWei WANG u8 final_phase = 0xFF;
664ff984e57SWei WANG
665abcc6b29SMicky Ching if (phase_map == 0) {
666abcc6b29SMicky Ching dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
667abcc6b29SMicky Ching return final_phase;
668ff984e57SWei WANG }
669ff984e57SWei WANG
670abcc6b29SMicky Ching while (start < RTSX_PHASE_MAX) {
671abcc6b29SMicky Ching len = sd_get_phase_len(phase_map, start);
672abcc6b29SMicky Ching if (len_final < len) {
673abcc6b29SMicky Ching start_final = start;
674abcc6b29SMicky Ching len_final = len;
675abcc6b29SMicky Ching }
676abcc6b29SMicky Ching start += len ? len : 1;
677ff984e57SWei WANG }
678ff984e57SWei WANG
679abcc6b29SMicky Ching final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
680abcc6b29SMicky Ching dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
681abcc6b29SMicky Ching phase_map, len_final, final_phase);
682ff984e57SWei WANG
683ff984e57SWei WANG return final_phase;
684ff984e57SWei WANG }
685ff984e57SWei WANG
sd_wait_data_idle(struct realtek_pci_sdmmc * host)686ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
687ff984e57SWei WANG {
688679209b3SLee Jones int i;
689ff984e57SWei WANG u8 val = 0;
690ff984e57SWei WANG
691ff984e57SWei WANG for (i = 0; i < 100; i++) {
692679209b3SLee Jones rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
693ff984e57SWei WANG if (val & SD_DATA_IDLE)
694ff984e57SWei WANG return;
695ff984e57SWei WANG
696ff984e57SWei WANG udelay(100);
697ff984e57SWei WANG }
698ff984e57SWei WANG }
699ff984e57SWei WANG
sd_tuning_rx_cmd(struct realtek_pci_sdmmc * host,u8 opcode,u8 sample_point)700ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
701ff984e57SWei WANG u8 opcode, u8 sample_point)
702ff984e57SWei WANG {
703ff984e57SWei WANG int err;
704c7836d15SMasahiro Yamada struct mmc_command cmd = {};
705563be8b6Srui_feng struct rtsx_pcr *pcr = host->pcr;
706ff984e57SWei WANG
707563be8b6Srui_feng sd_change_phase(host, sample_point, true);
708563be8b6Srui_feng
709563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
710563be8b6Srui_feng SD_RSP_80CLK_TIMEOUT_EN);
711ff984e57SWei WANG
7121dcb3579SMicky Ching cmd.opcode = opcode;
7131dcb3579SMicky Ching err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
714ff984e57SWei WANG if (err < 0) {
715ff984e57SWei WANG /* Wait till SD DATA IDLE */
716ff984e57SWei WANG sd_wait_data_idle(host);
717ff984e57SWei WANG sd_clear_error(host);
718563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3,
719563be8b6Srui_feng SD_RSP_80CLK_TIMEOUT_EN, 0);
720ff984e57SWei WANG return err;
721ff984e57SWei WANG }
722ff984e57SWei WANG
723563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
724ff984e57SWei WANG return 0;
725ff984e57SWei WANG }
726ff984e57SWei WANG
sd_tuning_phase(struct realtek_pci_sdmmc * host,u8 opcode,u32 * phase_map)727ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
728ff984e57SWei WANG u8 opcode, u32 *phase_map)
729ff984e57SWei WANG {
730ff984e57SWei WANG int err, i;
731ff984e57SWei WANG u32 raw_phase_map = 0;
732ff984e57SWei WANG
733abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) {
734ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i);
735ff984e57SWei WANG if (err == 0)
736ff984e57SWei WANG raw_phase_map |= 1 << i;
737ff984e57SWei WANG }
738ff984e57SWei WANG
739ff984e57SWei WANG if (phase_map)
740ff984e57SWei WANG *phase_map = raw_phase_map;
741ff984e57SWei WANG
742ff984e57SWei WANG return 0;
743ff984e57SWei WANG }
744ff984e57SWei WANG
sd_tuning_rx(struct realtek_pci_sdmmc * host,u8 opcode)745ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
746ff984e57SWei WANG {
747ff984e57SWei WANG int err, i;
748ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
749ff984e57SWei WANG u8 final_phase;
750ff984e57SWei WANG
751ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) {
752ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
753ff984e57SWei WANG if (err < 0)
754ff984e57SWei WANG return err;
755ff984e57SWei WANG
756ff984e57SWei WANG if (raw_phase_map[i] == 0)
757ff984e57SWei WANG break;
758ff984e57SWei WANG }
759ff984e57SWei WANG
760ff984e57SWei WANG phase_map = 0xFFFFFFFF;
761ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) {
762ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
763ff984e57SWei WANG i, raw_phase_map[i]);
764ff984e57SWei WANG phase_map &= raw_phase_map[i];
765ff984e57SWei WANG }
766ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
767ff984e57SWei WANG
768ff984e57SWei WANG if (phase_map) {
769ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map);
770ff984e57SWei WANG if (final_phase == 0xFF)
771ff984e57SWei WANG return -EINVAL;
772ff984e57SWei WANG
77384d72f9cSWei WANG err = sd_change_phase(host, final_phase, true);
774ff984e57SWei WANG if (err < 0)
775ff984e57SWei WANG return err;
776ff984e57SWei WANG } else {
777ff984e57SWei WANG return -EINVAL;
778ff984e57SWei WANG }
779ff984e57SWei WANG
780ff984e57SWei WANG return 0;
781ff984e57SWei WANG }
782ff984e57SWei WANG
sdio_extblock_cmd(struct mmc_command * cmd,struct mmc_data * data)7831dcb3579SMicky Ching static inline int sdio_extblock_cmd(struct mmc_command *cmd,
7841dcb3579SMicky Ching struct mmc_data *data)
7851dcb3579SMicky Ching {
7861dcb3579SMicky Ching return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
7871dcb3579SMicky Ching }
7881dcb3579SMicky Ching
sd_rw_cmd(struct mmc_command * cmd)7896291e715SMicky Ching static inline int sd_rw_cmd(struct mmc_command *cmd)
790ff984e57SWei WANG {
7916291e715SMicky Ching return mmc_op_multi(cmd->opcode) ||
7926291e715SMicky Ching (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
7936291e715SMicky Ching (cmd->opcode == MMC_WRITE_BLOCK);
7946291e715SMicky Ching }
7956291e715SMicky Ching
sd_request(struct work_struct * work)7966291e715SMicky Ching static void sd_request(struct work_struct *work)
7976291e715SMicky Ching {
7986291e715SMicky Ching struct realtek_pci_sdmmc *host = container_of(work,
7996291e715SMicky Ching struct realtek_pci_sdmmc, work);
800ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
8016291e715SMicky Ching
8026291e715SMicky Ching struct mmc_host *mmc = host->mmc;
8036291e715SMicky Ching struct mmc_request *mrq = host->mrq;
804ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd;
805ff984e57SWei WANG struct mmc_data *data = mrq->data;
8066291e715SMicky Ching
807ff984e57SWei WANG unsigned int data_size = 0;
808c3481955SWei WANG int err;
809ff984e57SWei WANG
810b22217f9SMicky Ching if (host->eject || !sd_get_cd_int(host)) {
811ff984e57SWei WANG cmd->error = -ENOMEDIUM;
812ff984e57SWei WANG goto finish;
813ff984e57SWei WANG }
814ff984e57SWei WANG
815c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
816c3481955SWei WANG if (err) {
817c3481955SWei WANG cmd->error = err;
818c3481955SWei WANG goto finish;
819c3481955SWei WANG }
820c3481955SWei WANG
82198fcc576SMicky Ching mutex_lock(&pcr->pcr_mutex);
82298fcc576SMicky Ching
823ff984e57SWei WANG rtsx_pci_start_run(pcr);
824ff984e57SWei WANG
825ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
826ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk);
827ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
828ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
829ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD);
830ff984e57SWei WANG
83198fcc576SMicky Ching mutex_lock(&host->host_mutex);
83298fcc576SMicky Ching host->mrq = mrq;
83398fcc576SMicky Ching mutex_unlock(&host->host_mutex);
83498fcc576SMicky Ching
835ff984e57SWei WANG if (mrq->data)
836ff984e57SWei WANG data_size = data->blocks * data->blksz;
837ff984e57SWei WANG
8381dcb3579SMicky Ching if (!data_size) {
83998fcc576SMicky Ching sd_send_cmd_get_rsp(host, cmd);
8401dcb3579SMicky Ching } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
8411dcb3579SMicky Ching cmd->error = sd_rw_multi(host, mrq);
8426291e715SMicky Ching if (!host->using_cookie)
8436291e715SMicky Ching sdmmc_post_req(host->mmc, host->mrq, 0);
84498fcc576SMicky Ching
84598fcc576SMicky Ching if (mmc_op_multi(cmd->opcode) && mrq->stop)
84698fcc576SMicky Ching sd_send_cmd_get_rsp(host, mrq->stop);
84798fcc576SMicky Ching } else {
84898fcc576SMicky Ching sd_normal_rw(host, mrq);
84998fcc576SMicky Ching }
85098fcc576SMicky Ching
85198fcc576SMicky Ching if (mrq->data) {
85298fcc576SMicky Ching if (cmd->error || data->error)
85398fcc576SMicky Ching data->bytes_xfered = 0;
85498fcc576SMicky Ching else
85598fcc576SMicky Ching data->bytes_xfered = data->blocks * data->blksz;
85698fcc576SMicky Ching }
85798fcc576SMicky Ching
85898fcc576SMicky Ching mutex_unlock(&pcr->pcr_mutex);
859ff984e57SWei WANG
860ff984e57SWei WANG finish:
8611dcb3579SMicky Ching if (cmd->error) {
8621dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
8631dcb3579SMicky Ching cmd->opcode, cmd->arg, cmd->error);
8641dcb3579SMicky Ching }
86598fcc576SMicky Ching
86698fcc576SMicky Ching mutex_lock(&host->host_mutex);
86798fcc576SMicky Ching host->mrq = NULL;
86898fcc576SMicky Ching mutex_unlock(&host->host_mutex);
86998fcc576SMicky Ching
87098fcc576SMicky Ching mmc_request_done(mmc, mrq);
871ff984e57SWei WANG }
872ff984e57SWei WANG
sdmmc_request(struct mmc_host * mmc,struct mmc_request * mrq)8736291e715SMicky Ching static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
8746291e715SMicky Ching {
8756291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc);
8766291e715SMicky Ching struct mmc_data *data = mrq->data;
8776291e715SMicky Ching
8786291e715SMicky Ching mutex_lock(&host->host_mutex);
8796291e715SMicky Ching host->mrq = mrq;
8806291e715SMicky Ching mutex_unlock(&host->host_mutex);
8816291e715SMicky Ching
8821dcb3579SMicky Ching if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
8836291e715SMicky Ching host->using_cookie = sd_pre_dma_transfer(host, data, false);
8846291e715SMicky Ching
8856ea62579SBhaktipriya Shridhar schedule_work(&host->work);
8866291e715SMicky Ching }
8876291e715SMicky Ching
sd_set_bus_width(struct realtek_pci_sdmmc * host,unsigned char bus_width)888ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
889ff984e57SWei WANG unsigned char bus_width)
890ff984e57SWei WANG {
891ff984e57SWei WANG int err = 0;
892ff984e57SWei WANG u8 width[] = {
893ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
894ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
895ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
896ff984e57SWei WANG };
897ff984e57SWei WANG
898ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8)
899ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1,
900ff984e57SWei WANG 0x03, width[bus_width]);
901ff984e57SWei WANG
902ff984e57SWei WANG return err;
903ff984e57SWei WANG }
904ff984e57SWei WANG
sd_power_on(struct realtek_pci_sdmmc * host,unsigned char power_mode)9051f311c94SRicky WU static int sd_power_on(struct realtek_pci_sdmmc *host, unsigned char power_mode)
906ff984e57SWei WANG {
907ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
9089ff43c7bSRui Feng struct mmc_host *mmc = host->mmc;
909ff984e57SWei WANG int err;
9109ff43c7bSRui Feng u32 val;
9116b7b58f4SRui Feng u8 test_mode;
912ff984e57SWei WANG
9131f311c94SRicky WU if (host->prev_power_state == MMC_POWER_ON)
914d88691beSWei WANG return 0;
915d88691beSWei WANG
9161f311c94SRicky WU if (host->prev_power_state == MMC_POWER_UP) {
9171f311c94SRicky WU rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);
9181f311c94SRicky WU goto finish;
9191f311c94SRicky WU }
9201f311c94SRicky WU
92112b1c5edSRicky Wu msleep(100);
92212b1c5edSRicky Wu
923ff984e57SWei WANG rtsx_pci_init_cmd(pcr);
924ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
925ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
926ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD);
927ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
928ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN);
929ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100);
930ff984e57SWei WANG if (err < 0)
931ff984e57SWei WANG return err;
932ff984e57SWei WANG
933ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
934ff984e57SWei WANG if (err < 0)
935ff984e57SWei WANG return err;
936ff984e57SWei WANG
937ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
938ff984e57SWei WANG if (err < 0)
939ff984e57SWei WANG return err;
940ff984e57SWei WANG
9411f311c94SRicky WU mdelay(1);
9421f311c94SRicky WU
943ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
944ff984e57SWei WANG if (err < 0)
945ff984e57SWei WANG return err;
946ff984e57SWei WANG
9471f311c94SRicky WU /* send at least 74 clocks */
9481f311c94SRicky WU rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
9491f311c94SRicky WU
9509ff43c7bSRui Feng if (PCI_PID(pcr) == PID_5261) {
9516b7b58f4SRui Feng /*
9526b7b58f4SRui Feng * If test mode is set switch to SD Express mandatorily,
9536b7b58f4SRui Feng * this is only for factory testing.
9546b7b58f4SRui Feng */
9556b7b58f4SRui Feng rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode);
9566b7b58f4SRui Feng if (test_mode & RTS5261_FW_EXPRESS_TEST_MASK) {
9576b7b58f4SRui Feng sdmmc_init_sd_express(mmc, NULL);
9586b7b58f4SRui Feng return 0;
9596b7b58f4SRui Feng }
9609ff43c7bSRui Feng if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
9619ff43c7bSRui Feng mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V;
9629ff43c7bSRui Feng /*
9639ff43c7bSRui Feng * HW read wp status when resuming from S3/S4,
9649ff43c7bSRui Feng * and then picks SD legacy interface if it's set
9659ff43c7bSRui Feng * in read-only mode.
9669ff43c7bSRui Feng */
9679ff43c7bSRui Feng val = rtsx_pci_readl(pcr, RTSX_BIPR);
9689ff43c7bSRui Feng if (val & SD_WRITE_PROTECT) {
9699ff43c7bSRui Feng pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS;
9709ff43c7bSRui Feng mmc->caps2 &= ~(MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V);
9719ff43c7bSRui Feng }
9729ff43c7bSRui Feng }
9739ff43c7bSRui Feng
9741f311c94SRicky WU finish:
9751f311c94SRicky WU host->prev_power_state = power_mode;
976ff984e57SWei WANG return 0;
977ff984e57SWei WANG }
978ff984e57SWei WANG
sd_power_off(struct realtek_pci_sdmmc * host)979ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host)
980ff984e57SWei WANG {
981ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
982ff984e57SWei WANG int err;
983ff984e57SWei WANG
9841f311c94SRicky WU host->prev_power_state = MMC_POWER_OFF;
985d88691beSWei WANG
986ff984e57SWei WANG rtsx_pci_init_cmd(pcr);
987ff984e57SWei WANG
988ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
989ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
990ff984e57SWei WANG
991ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100);
992ff984e57SWei WANG if (err < 0)
993ff984e57SWei WANG return err;
994ff984e57SWei WANG
995ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
996ff984e57SWei WANG if (err < 0)
997ff984e57SWei WANG return err;
998ff984e57SWei WANG
999ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1000ff984e57SWei WANG }
1001ff984e57SWei WANG
sd_set_power_mode(struct realtek_pci_sdmmc * host,unsigned char power_mode)1002ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
1003ff984e57SWei WANG unsigned char power_mode)
1004ff984e57SWei WANG {
1005ff984e57SWei WANG int err;
1006ff984e57SWei WANG
1007ff984e57SWei WANG if (power_mode == MMC_POWER_OFF)
1008ff984e57SWei WANG err = sd_power_off(host);
1009ff984e57SWei WANG else
10101f311c94SRicky WU err = sd_power_on(host, power_mode);
1011ff984e57SWei WANG
1012ff984e57SWei WANG return err;
1013ff984e57SWei WANG }
1014ff984e57SWei WANG
sd_set_timing(struct realtek_pci_sdmmc * host,unsigned char timing)101584d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
1016ff984e57SWei WANG {
1017ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
1018ff984e57SWei WANG int err = 0;
1019ff984e57SWei WANG
1020ff984e57SWei WANG rtsx_pci_init_cmd(pcr);
1021ff984e57SWei WANG
1022ff984e57SWei WANG switch (timing) {
1023ff984e57SWei WANG case MMC_TIMING_UHS_SDR104:
1024ff984e57SWei WANG case MMC_TIMING_UHS_SDR50:
1025ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1026ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST,
1027ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
1028ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1029ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ);
1030ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1031ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1032ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1033ff984e57SWei WANG break;
1034ff984e57SWei WANG
10351a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52:
1036ff984e57SWei WANG case MMC_TIMING_UHS_DDR50:
1037ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1038ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST,
1039ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1040ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1041ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ);
1042ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1043ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1044ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1045ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1046ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1047ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1048ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1049ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1050ff984e57SWei WANG break;
1051ff984e57SWei WANG
1052ff984e57SWei WANG case MMC_TIMING_MMC_HS:
1053ff984e57SWei WANG case MMC_TIMING_SD_HS:
1054ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1055ff984e57SWei WANG 0x0C, SD_20_MODE);
1056ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1057ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ);
1058ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1059ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1060ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1061ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1062ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1063ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1064ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1065ff984e57SWei WANG break;
1066ff984e57SWei WANG
1067ff984e57SWei WANG default:
1068ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1069ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE);
1070ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1071ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ);
1072ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1073ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1074ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1075ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1076ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0);
1077ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1078ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1079ff984e57SWei WANG break;
1080ff984e57SWei WANG }
1081ff984e57SWei WANG
1082ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100);
1083ff984e57SWei WANG
1084ff984e57SWei WANG return err;
1085ff984e57SWei WANG }
1086ff984e57SWei WANG
sdmmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1087ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1088ff984e57SWei WANG {
1089ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1090ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
1091ff984e57SWei WANG
1092ff984e57SWei WANG if (host->eject)
1093ff984e57SWei WANG return;
1094ff984e57SWei WANG
1095c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1096c3481955SWei WANG return;
1097c3481955SWei WANG
1098ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex);
1099ff984e57SWei WANG
1100ff984e57SWei WANG rtsx_pci_start_run(pcr);
1101ff984e57SWei WANG
1102ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width);
1103ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode);
110484d72f9cSWei WANG sd_set_timing(host, ios->timing);
1105ff984e57SWei WANG
1106ff984e57SWei WANG host->vpclk = false;
1107ff984e57SWei WANG host->double_clk = true;
1108ff984e57SWei WANG
1109ff984e57SWei WANG switch (ios->timing) {
1110ff984e57SWei WANG case MMC_TIMING_UHS_SDR104:
1111ff984e57SWei WANG case MMC_TIMING_UHS_SDR50:
1112ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M;
1113ff984e57SWei WANG host->vpclk = true;
1114ff984e57SWei WANG host->double_clk = false;
1115ff984e57SWei WANG break;
11161a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52:
1117ff984e57SWei WANG case MMC_TIMING_UHS_DDR50:
1118ff984e57SWei WANG case MMC_TIMING_UHS_SDR25:
1119ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M;
1120ff984e57SWei WANG break;
1121ff984e57SWei WANG default:
1122ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K;
1123ff984e57SWei WANG break;
1124ff984e57SWei WANG }
1125ff984e57SWei WANG
1126ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false;
1127ff984e57SWei WANG
1128ff984e57SWei WANG host->clock = ios->clock;
1129ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1130ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk);
1131ff984e57SWei WANG
1132ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex);
1133ff984e57SWei WANG }
1134ff984e57SWei WANG
sdmmc_get_ro(struct mmc_host * mmc)1135ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc)
1136ff984e57SWei WANG {
1137ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1138ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
1139ff984e57SWei WANG int ro = 0;
1140ff984e57SWei WANG u32 val;
1141ff984e57SWei WANG
1142ff984e57SWei WANG if (host->eject)
1143ff984e57SWei WANG return -ENOMEDIUM;
1144ff984e57SWei WANG
1145ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex);
1146ff984e57SWei WANG
1147ff984e57SWei WANG rtsx_pci_start_run(pcr);
1148ff984e57SWei WANG
1149ff984e57SWei WANG /* Check SD mechanical write-protect switch */
1150ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR);
1151ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1152ff984e57SWei WANG if (val & SD_WRITE_PROTECT)
1153ff984e57SWei WANG ro = 1;
1154ff984e57SWei WANG
1155ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex);
1156ff984e57SWei WANG
1157ff984e57SWei WANG return ro;
1158ff984e57SWei WANG }
1159ff984e57SWei WANG
sdmmc_get_cd(struct mmc_host * mmc)1160ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc)
1161ff984e57SWei WANG {
1162ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1163ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
1164ff984e57SWei WANG int cd = 0;
1165ff984e57SWei WANG u32 val;
1166ff984e57SWei WANG
1167ff984e57SWei WANG if (host->eject)
1168b22217f9SMicky Ching return cd;
1169ff984e57SWei WANG
1170ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex);
1171ff984e57SWei WANG
1172ff984e57SWei WANG rtsx_pci_start_run(pcr);
1173ff984e57SWei WANG
1174ff984e57SWei WANG /* Check SD card detect */
1175ff984e57SWei WANG val = rtsx_pci_card_exist(pcr);
1176ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1177ff984e57SWei WANG if (val & SD_EXIST)
1178ff984e57SWei WANG cd = 1;
1179ff984e57SWei WANG
1180ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex);
1181ff984e57SWei WANG
1182ff984e57SWei WANG return cd;
1183ff984e57SWei WANG }
1184ff984e57SWei WANG
sd_wait_voltage_stable_1(struct realtek_pci_sdmmc * host)1185ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1186ff984e57SWei WANG {
1187ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
1188ff984e57SWei WANG int err;
1189ff984e57SWei WANG u8 stat;
1190ff984e57SWei WANG
1191ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec.
1192ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and
1193ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response.
1194ff984e57SWei WANG */
1195ff984e57SWei WANG mdelay(1);
1196ff984e57SWei WANG
1197ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1198ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low,
1199ff984e57SWei WANG * abort the voltage switch sequence;
1200ff984e57SWei WANG */
1201ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1202ff984e57SWei WANG if (err < 0)
1203ff984e57SWei WANG return err;
1204ff984e57SWei WANG
1205ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1206ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS))
1207ff984e57SWei WANG return -EINVAL;
1208ff984e57SWei WANG
1209ff984e57SWei WANG /* Stop toggle SD clock */
1210ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1211ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP);
1212ff984e57SWei WANG if (err < 0)
1213ff984e57SWei WANG return err;
1214ff984e57SWei WANG
1215ff984e57SWei WANG return 0;
1216ff984e57SWei WANG }
1217ff984e57SWei WANG
sd_wait_voltage_stable_2(struct realtek_pci_sdmmc * host)1218ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1219ff984e57SWei WANG {
1220ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
1221ff984e57SWei WANG int err;
1222ff984e57SWei WANG u8 stat, mask, val;
1223ff984e57SWei WANG
1224ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */
1225ff984e57SWei WANG msleep(50);
1226ff984e57SWei WANG
1227ff984e57SWei WANG /* Toggle SD clock again */
1228ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1229ff984e57SWei WANG if (err < 0)
1230ff984e57SWei WANG return err;
1231ff984e57SWei WANG
1232ff984e57SWei WANG /* Wait for a period of time so that the card can drive
1233ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V
1234ff984e57SWei WANG */
1235ff984e57SWei WANG msleep(20);
1236ff984e57SWei WANG
1237ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1238ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1239ff984e57SWei WANG if (err < 0)
1240ff984e57SWei WANG return err;
1241ff984e57SWei WANG
1242ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1243ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS;
1244ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1245ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS;
1246ff984e57SWei WANG if ((stat & mask) != val) {
1247ff984e57SWei WANG dev_dbg(sdmmc_dev(host),
1248ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1249ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT,
1250ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1251ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1252ff984e57SWei WANG return -EINVAL;
1253ff984e57SWei WANG }
1254ff984e57SWei WANG
1255ff984e57SWei WANG return 0;
1256ff984e57SWei WANG }
1257ff984e57SWei WANG
sdmmc_switch_voltage(struct mmc_host * mmc,struct mmc_ios * ios)1258ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1259ff984e57SWei WANG {
1260ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1261ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
1262ff984e57SWei WANG int err = 0;
1263ff984e57SWei WANG u8 voltage;
1264ff984e57SWei WANG
1265ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1266ff984e57SWei WANG __func__, ios->signal_voltage);
1267ff984e57SWei WANG
1268ff984e57SWei WANG if (host->eject)
1269ff984e57SWei WANG return -ENOMEDIUM;
1270ff984e57SWei WANG
1271c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1272c3481955SWei WANG if (err)
1273c3481955SWei WANG return err;
1274c3481955SWei WANG
1275ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex);
1276ff984e57SWei WANG
1277ff984e57SWei WANG rtsx_pci_start_run(pcr);
1278ff984e57SWei WANG
1279ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1280ef85e736SWei WANG voltage = OUTPUT_3V3;
1281ff984e57SWei WANG else
1282ef85e736SWei WANG voltage = OUTPUT_1V8;
1283ff984e57SWei WANG
1284ef85e736SWei WANG if (voltage == OUTPUT_1V8) {
1285ff984e57SWei WANG err = sd_wait_voltage_stable_1(host);
1286ff984e57SWei WANG if (err < 0)
1287ff984e57SWei WANG goto out;
1288ff984e57SWei WANG }
1289ff984e57SWei WANG
1290ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage);
1291ff984e57SWei WANG if (err < 0)
1292ff984e57SWei WANG goto out;
1293ff984e57SWei WANG
1294ef85e736SWei WANG if (voltage == OUTPUT_1V8) {
1295ff984e57SWei WANG err = sd_wait_voltage_stable_2(host);
1296ff984e57SWei WANG if (err < 0)
1297ff984e57SWei WANG goto out;
1298ff984e57SWei WANG }
1299ff984e57SWei WANG
13001b8055b4SWei WANG out:
1301ff984e57SWei WANG /* Stop toggle SD clock in idle */
1302ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1303ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1304ff984e57SWei WANG
1305ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex);
1306ff984e57SWei WANG
1307ff984e57SWei WANG return err;
1308ff984e57SWei WANG }
1309ff984e57SWei WANG
sdmmc_execute_tuning(struct mmc_host * mmc,u32 opcode)1310ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1311ff984e57SWei WANG {
1312ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1313ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
1314ff984e57SWei WANG int err = 0;
1315ff984e57SWei WANG
1316ff984e57SWei WANG if (host->eject)
1317ff984e57SWei WANG return -ENOMEDIUM;
1318ff984e57SWei WANG
1319c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1320c3481955SWei WANG if (err)
1321c3481955SWei WANG return err;
1322c3481955SWei WANG
1323ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex);
1324ff984e57SWei WANG
1325ff984e57SWei WANG rtsx_pci_start_run(pcr);
1326ff984e57SWei WANG
132784d72f9cSWei WANG /* Set initial TX phase */
132884d72f9cSWei WANG switch (mmc->ios.timing) {
132984d72f9cSWei WANG case MMC_TIMING_UHS_SDR104:
133084d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
133184d72f9cSWei WANG break;
1332ff984e57SWei WANG
133384d72f9cSWei WANG case MMC_TIMING_UHS_SDR50:
133484d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
133584d72f9cSWei WANG break;
133684d72f9cSWei WANG
133784d72f9cSWei WANG case MMC_TIMING_UHS_DDR50:
133884d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
133984d72f9cSWei WANG break;
134084d72f9cSWei WANG
134184d72f9cSWei WANG default:
134284d72f9cSWei WANG err = 0;
134384d72f9cSWei WANG }
134484d72f9cSWei WANG
134584d72f9cSWei WANG if (err)
134684d72f9cSWei WANG goto out;
134784d72f9cSWei WANG
134884d72f9cSWei WANG /* Tuning RX phase */
134984d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
135084d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
135184d72f9cSWei WANG err = sd_tuning_rx(host, opcode);
135284d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
135384d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
135484d72f9cSWei WANG
135584d72f9cSWei WANG out:
1356ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex);
1357ff984e57SWei WANG
1358ff984e57SWei WANG return err;
1359ff984e57SWei WANG }
1360ff984e57SWei WANG
sdmmc_init_sd_express(struct mmc_host * mmc,struct mmc_ios * ios)13619ff43c7bSRui Feng static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
13629ff43c7bSRui Feng {
13639ff43c7bSRui Feng u32 relink_time;
13649ff43c7bSRui Feng struct realtek_pci_sdmmc *host = mmc_priv(mmc);
13659ff43c7bSRui Feng struct rtsx_pcr *pcr = host->pcr;
13669ff43c7bSRui Feng
13679ff43c7bSRui Feng /* Set relink_time for changing to PCIe card */
13689ff43c7bSRui Feng relink_time = 0x8FFF;
13699ff43c7bSRui Feng
13709ff43c7bSRui Feng rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time);
13719ff43c7bSRui Feng rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8);
13729ff43c7bSRui Feng rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16);
13739ff43c7bSRui Feng
13749ff43c7bSRui Feng rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80);
13759ff43c7bSRui Feng rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
13769ff43c7bSRui Feng RTS5261_LDO1_OCP_THD_MASK,
13779ff43c7bSRui Feng pcr->option.sd_800mA_ocp_thd);
13789ff43c7bSRui Feng
13799ff43c7bSRui Feng if (pcr->ops->disable_auto_blink)
13809ff43c7bSRui Feng pcr->ops->disable_auto_blink(pcr);
13819ff43c7bSRui Feng
13829ff43c7bSRui Feng /* For PCIe/NVMe mode can't enter delink issue */
13839ff43c7bSRui Feng pcr->hw_param.interrupt_en &= ~(SD_INT_EN);
13849ff43c7bSRui Feng rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en);
13859ff43c7bSRui Feng
13869ff43c7bSRui Feng rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
13879ff43c7bSRui Feng RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN);
13889ff43c7bSRui Feng rtsx_pci_write_register(pcr, RTS5261_FW_CFG0,
13899ff43c7bSRui Feng RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS);
13909ff43c7bSRui Feng rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
13916b7b58f4SRui Feng RTS5261_MCU_CLOCK_GATING, RTS5261_MCU_CLOCK_GATING);
13926b7b58f4SRui Feng rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
13939ff43c7bSRui Feng RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK
13946b7b58f4SRui Feng | RTS5261_DRIVER_ENABLE_FW,
13956b7b58f4SRui Feng RTS5261_MCU_CLOCK_SEL_16M | RTS5261_DRIVER_ENABLE_FW);
13969ff43c7bSRui Feng host->eject = true;
13979ff43c7bSRui Feng return 0;
13989ff43c7bSRui Feng }
13999ff43c7bSRui Feng
1400ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
14016291e715SMicky Ching .pre_req = sdmmc_pre_req,
14026291e715SMicky Ching .post_req = sdmmc_post_req,
1403ff984e57SWei WANG .request = sdmmc_request,
1404ff984e57SWei WANG .set_ios = sdmmc_set_ios,
1405ff984e57SWei WANG .get_ro = sdmmc_get_ro,
1406ff984e57SWei WANG .get_cd = sdmmc_get_cd,
1407ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage,
1408ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning,
14099ff43c7bSRui Feng .init_sd_express = sdmmc_init_sd_express,
1410ff984e57SWei WANG };
1411ff984e57SWei WANG
init_extra_caps(struct realtek_pci_sdmmc * host)1412ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host)
1413ff984e57SWei WANG {
1414ff984e57SWei WANG struct mmc_host *mmc = host->mmc;
1415ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr;
1416ff984e57SWei WANG
1417ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1418ff984e57SWei WANG
1419ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1420ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50;
1421ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1422ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104;
1423ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1424ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50;
1425ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1426ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR;
1427ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1428ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA;
1429849a9366SRicky Wu if (pcr->extra_caps & EXTRA_CAPS_NO_MMC)
1430849a9366SRicky Wu mmc->caps2 |= MMC_CAP2_NO_MMC;
14319ff43c7bSRui Feng if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
14329ff43c7bSRui Feng mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V;
1433ff984e57SWei WANG }
1434ff984e57SWei WANG
realtek_init_host(struct realtek_pci_sdmmc * host)1435ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host)
1436ff984e57SWei WANG {
1437ff984e57SWei WANG struct mmc_host *mmc = host->mmc;
14385b4258f6SRicky Wu struct rtsx_pcr *pcr = host->pcr;
1439ff984e57SWei WANG
1440ff984e57SWei WANG mmc->f_min = 250000;
1441ff984e57SWei WANG mmc->f_max = 208000000;
1442ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1443ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1444ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
14451be64c79SUlf Hansson MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
14465b4258f6SRicky Wu if (pcr->rtd3_en)
14475b4258f6SRicky Wu mmc->caps = mmc->caps | MMC_CAP_AGGRESSIVE_PM;
14488b280564SRicky Wu mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE |
14498b280564SRicky Wu MMC_CAP2_NO_SDIO;
1450ff984e57SWei WANG mmc->max_current_330 = 400;
1451ff984e57SWei WANG mmc->max_current_180 = 800;
1452ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops;
1453ff984e57SWei WANG
1454ff984e57SWei WANG init_extra_caps(host);
1455ff984e57SWei WANG
1456ff984e57SWei WANG mmc->max_segs = 256;
1457ff984e57SWei WANG mmc->max_seg_size = 65536;
1458ff984e57SWei WANG mmc->max_blk_size = 512;
1459ff984e57SWei WANG mmc->max_blk_count = 65535;
1460ff984e57SWei WANG mmc->max_req_size = 524288;
1461ff984e57SWei WANG }
1462ff984e57SWei WANG
rtsx_pci_sdmmc_card_event(struct platform_device * pdev)1463ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1464ff984e57SWei WANG {
1465ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1466ff984e57SWei WANG
14672057647fSMicky Ching host->cookie = -1;
1468ff984e57SWei WANG mmc_detect_change(host->mmc, 0);
1469ff984e57SWei WANG }
1470ff984e57SWei WANG
rtsx_pci_sdmmc_drv_probe(struct platform_device * pdev)1471ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1472ff984e57SWei WANG {
1473ff984e57SWei WANG struct mmc_host *mmc;
1474ff984e57SWei WANG struct realtek_pci_sdmmc *host;
1475ff984e57SWei WANG struct rtsx_pcr *pcr;
1476ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data;
14770c87db77SYang Yingliang int ret;
1478ff984e57SWei WANG
1479ff984e57SWei WANG if (!handle)
1480ff984e57SWei WANG return -ENXIO;
1481ff984e57SWei WANG
1482ff984e57SWei WANG pcr = handle->pcr;
1483ff984e57SWei WANG if (!pcr)
1484ff984e57SWei WANG return -ENXIO;
1485ff984e57SWei WANG
1486ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1487ff984e57SWei WANG
1488ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1489ff984e57SWei WANG if (!mmc)
1490ff984e57SWei WANG return -ENOMEM;
1491ff984e57SWei WANG
1492ff984e57SWei WANG host = mmc_priv(mmc);
1493ff984e57SWei WANG host->pcr = pcr;
14941f311c94SRicky WU mmc->ios.power_delay_ms = 5;
1495ff984e57SWei WANG host->mmc = mmc;
1496ff984e57SWei WANG host->pdev = pdev;
14972057647fSMicky Ching host->cookie = -1;
14981f311c94SRicky WU host->prev_power_state = MMC_POWER_OFF;
14996291e715SMicky Ching INIT_WORK(&host->work, sd_request);
1500ff984e57SWei WANG platform_set_drvdata(pdev, host);
1501ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1502ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1503ff984e57SWei WANG
150498fcc576SMicky Ching mutex_init(&host->host_mutex);
1505ff984e57SWei WANG
1506ff984e57SWei WANG realtek_init_host(host);
1507ff984e57SWei WANG
15087499b529SKai-Heng Feng pm_runtime_no_callbacks(&pdev->dev);
15097499b529SKai-Heng Feng pm_runtime_set_active(&pdev->dev);
15105b4258f6SRicky Wu pm_runtime_enable(&pdev->dev);
15117499b529SKai-Heng Feng pm_runtime_set_autosuspend_delay(&pdev->dev, 200);
15127499b529SKai-Heng Feng pm_runtime_mark_last_busy(&pdev->dev);
15137499b529SKai-Heng Feng pm_runtime_use_autosuspend(&pdev->dev);
15145b4258f6SRicky Wu
15150c87db77SYang Yingliang ret = mmc_add_host(mmc);
15160c87db77SYang Yingliang if (ret) {
15170c87db77SYang Yingliang pm_runtime_dont_use_autosuspend(&pdev->dev);
15180c87db77SYang Yingliang pm_runtime_disable(&pdev->dev);
15190c87db77SYang Yingliang mmc_free_host(mmc);
15200c87db77SYang Yingliang return ret;
15210c87db77SYang Yingliang }
1522ff984e57SWei WANG
1523ff984e57SWei WANG return 0;
1524ff984e57SWei WANG }
1525ff984e57SWei WANG
rtsx_pci_sdmmc_drv_remove(struct platform_device * pdev)1526*dda6da1bSYangtao Li static void rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1527ff984e57SWei WANG {
1528ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1529ff984e57SWei WANG struct rtsx_pcr *pcr;
1530ff984e57SWei WANG struct mmc_host *mmc;
1531ff984e57SWei WANG
1532ff984e57SWei WANG pcr = host->pcr;
1533ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1534ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL;
1535ff984e57SWei WANG mmc = host->mmc;
1536ff984e57SWei WANG
15376291e715SMicky Ching cancel_work_sync(&host->work);
15386291e715SMicky Ching
153998fcc576SMicky Ching mutex_lock(&host->host_mutex);
1540ff984e57SWei WANG if (host->mrq) {
1541ff984e57SWei WANG dev_dbg(&(pdev->dev),
1542ff984e57SWei WANG "%s: Controller removed during transfer\n",
1543ff984e57SWei WANG mmc_hostname(mmc));
1544ff984e57SWei WANG
154598fcc576SMicky Ching rtsx_pci_complete_unfinished_transfer(pcr);
1546ff984e57SWei WANG
154798fcc576SMicky Ching host->mrq->cmd->error = -ENOMEDIUM;
154898fcc576SMicky Ching if (host->mrq->stop)
154998fcc576SMicky Ching host->mrq->stop->error = -ENOMEDIUM;
155098fcc576SMicky Ching mmc_request_done(mmc, host->mrq);
1551ff984e57SWei WANG }
155298fcc576SMicky Ching mutex_unlock(&host->host_mutex);
1553ff984e57SWei WANG
1554ff984e57SWei WANG mmc_remove_host(mmc);
1555640e09bcSMicky Ching host->eject = true;
1556640e09bcSMicky Ching
15576ea62579SBhaktipriya Shridhar flush_work(&host->work);
15586291e715SMicky Ching
15597499b529SKai-Heng Feng pm_runtime_dont_use_autosuspend(&pdev->dev);
15607499b529SKai-Heng Feng pm_runtime_disable(&pdev->dev);
15617499b529SKai-Heng Feng
1562ff984e57SWei WANG mmc_free_host(mmc);
1563ff984e57SWei WANG
1564ff984e57SWei WANG dev_dbg(&(pdev->dev),
1565ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n");
1566ff984e57SWei WANG }
1567ff984e57SWei WANG
1568f2483b0dSKrzysztof Kozlowski static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1569ff984e57SWei WANG {
1570ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC,
1571ff984e57SWei WANG }, {
1572ff984e57SWei WANG /* sentinel */
1573ff984e57SWei WANG }
1574ff984e57SWei WANG };
1575ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1576ff984e57SWei WANG
1577ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = {
1578ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe,
1579*dda6da1bSYangtao Li .remove_new = rtsx_pci_sdmmc_drv_remove,
1580ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids,
1581ff984e57SWei WANG .driver = {
1582ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC,
158321b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1584ff984e57SWei WANG },
1585ff984e57SWei WANG };
1586ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver);
1587ff984e57SWei WANG
1588ff984e57SWei WANG MODULE_LICENSE("GPL");
1589ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1590ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
1591