1ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 2ff984e57SWei WANG * 3ff984e57SWei WANG * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. 4ff984e57SWei WANG * 5ff984e57SWei WANG * This program is free software; you can redistribute it and/or modify it 6ff984e57SWei WANG * under the terms of the GNU General Public License as published by the 7ff984e57SWei WANG * Free Software Foundation; either version 2, or (at your option) any 8ff984e57SWei WANG * later version. 9ff984e57SWei WANG * 10ff984e57SWei WANG * This program is distributed in the hope that it will be useful, but 11ff984e57SWei WANG * WITHOUT ANY WARRANTY; without even the implied warranty of 12ff984e57SWei WANG * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13ff984e57SWei WANG * General Public License for more details. 14ff984e57SWei WANG * 15ff984e57SWei WANG * You should have received a copy of the GNU General Public License along 16ff984e57SWei WANG * with this program; if not, see <http://www.gnu.org/licenses/>. 17ff984e57SWei WANG * 18ff984e57SWei WANG * Author: 19ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 20ff984e57SWei WANG * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China 21ff984e57SWei WANG */ 22ff984e57SWei WANG 23ff984e57SWei WANG #include <linux/module.h> 24433e075cSWei WANG #include <linux/slab.h> 25ff984e57SWei WANG #include <linux/highmem.h> 26ff984e57SWei WANG #include <linux/delay.h> 27ff984e57SWei WANG #include <linux/platform_device.h> 28ff984e57SWei WANG #include <linux/mmc/host.h> 29ff984e57SWei WANG #include <linux/mmc/mmc.h> 30ff984e57SWei WANG #include <linux/mmc/sd.h> 31ff984e57SWei WANG #include <linux/mmc/card.h> 32ff984e57SWei WANG #include <linux/mfd/rtsx_pci.h> 33ff984e57SWei WANG #include <asm/unaligned.h> 34ff984e57SWei WANG 35ff984e57SWei WANG /* SD Tuning Data Structure 36ff984e57SWei WANG * Record continuous timing phase path 37ff984e57SWei WANG */ 38ff984e57SWei WANG struct timing_phase_path { 39ff984e57SWei WANG int start; 40ff984e57SWei WANG int end; 41ff984e57SWei WANG int mid; 42ff984e57SWei WANG int len; 43ff984e57SWei WANG }; 44ff984e57SWei WANG 45ff984e57SWei WANG struct realtek_pci_sdmmc { 46ff984e57SWei WANG struct platform_device *pdev; 47ff984e57SWei WANG struct rtsx_pcr *pcr; 48ff984e57SWei WANG struct mmc_host *mmc; 49ff984e57SWei WANG struct mmc_request *mrq; 50ff984e57SWei WANG 51ff984e57SWei WANG struct mutex host_mutex; 52ff984e57SWei WANG 53ff984e57SWei WANG u8 ssc_depth; 54ff984e57SWei WANG unsigned int clock; 55ff984e57SWei WANG bool vpclk; 56ff984e57SWei WANG bool double_clk; 57ff984e57SWei WANG bool eject; 58ff984e57SWei WANG bool initial_mode; 59ff984e57SWei WANG bool ddr_mode; 60d88691beSWei WANG int power_state; 61d88691beSWei WANG #define SDMMC_POWER_ON 1 62d88691beSWei WANG #define SDMMC_POWER_OFF 0 63ff984e57SWei WANG }; 64ff984e57SWei WANG 65ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 66ff984e57SWei WANG { 67ff984e57SWei WANG return &(host->pdev->dev); 68ff984e57SWei WANG } 69ff984e57SWei WANG 70ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 71ff984e57SWei WANG { 72ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 73ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 74ff984e57SWei WANG } 75ff984e57SWei WANG 76ff984e57SWei WANG #ifdef DEBUG 77ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 78ff984e57SWei WANG { 79ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 80ff984e57SWei WANG u16 i; 81ff984e57SWei WANG u8 *ptr; 82ff984e57SWei WANG 83ff984e57SWei WANG /* Print SD host internal registers */ 84ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 85ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 86ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 87ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 88ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 89ff984e57SWei WANG rtsx_pci_send_cmd(pcr, 100); 90ff984e57SWei WANG 91ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr); 92ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 93ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 94ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 95ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 96ff984e57SWei WANG } 97ff984e57SWei WANG #else 98ff984e57SWei WANG #define sd_print_debug_regs(host) 99ff984e57SWei WANG #endif /* DEBUG */ 100ff984e57SWei WANG 101ff984e57SWei WANG static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 102ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 103ff984e57SWei WANG { 104ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 105ff984e57SWei WANG int err, i; 106ff984e57SWei WANG u8 trans_mode; 107ff984e57SWei WANG 108ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40); 109ff984e57SWei WANG 110ff984e57SWei WANG if (!buf) 111ff984e57SWei WANG buf_len = 0; 112ff984e57SWei WANG 113ff984e57SWei WANG if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK) 114ff984e57SWei WANG trans_mode = SD_TM_AUTO_TUNING; 115ff984e57SWei WANG else 116ff984e57SWei WANG trans_mode = SD_TM_NORMAL_READ; 117ff984e57SWei WANG 118ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 119ff984e57SWei WANG 120ff984e57SWei WANG for (i = 0; i < 5; i++) 121ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]); 122ff984e57SWei WANG 123ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 124ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 125ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 126ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 127ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 128ff984e57SWei WANG 129ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 130ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 131ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 132ff984e57SWei WANG if (trans_mode != SD_TM_AUTO_TUNING) 133ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 134ff984e57SWei WANG CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 135ff984e57SWei WANG 136ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 137ff984e57SWei WANG 0xFF, trans_mode | SD_TRANSFER_START); 138ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 139ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 140ff984e57SWei WANG 141ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 142ff984e57SWei WANG if (err < 0) { 143ff984e57SWei WANG sd_print_debug_regs(host); 144ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 145ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 146ff984e57SWei WANG return err; 147ff984e57SWei WANG } 148ff984e57SWei WANG 149ff984e57SWei WANG if (buf && buf_len) { 150ff984e57SWei WANG err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 151ff984e57SWei WANG if (err < 0) { 152ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 153ff984e57SWei WANG "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 154ff984e57SWei WANG return err; 155ff984e57SWei WANG } 156ff984e57SWei WANG } 157ff984e57SWei WANG 158ff984e57SWei WANG return 0; 159ff984e57SWei WANG } 160ff984e57SWei WANG 161ff984e57SWei WANG static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 162ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 163ff984e57SWei WANG { 164ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 165ff984e57SWei WANG int err, i; 166ff984e57SWei WANG u8 trans_mode; 167ff984e57SWei WANG 168ff984e57SWei WANG if (!buf) 169ff984e57SWei WANG buf_len = 0; 170ff984e57SWei WANG 171ff984e57SWei WANG if (buf && buf_len) { 172ff984e57SWei WANG err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 173ff984e57SWei WANG if (err < 0) { 174ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 175ff984e57SWei WANG "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 176ff984e57SWei WANG return err; 177ff984e57SWei WANG } 178ff984e57SWei WANG } 179ff984e57SWei WANG 180ff984e57SWei WANG trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3; 181ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 182ff984e57SWei WANG 183ff984e57SWei WANG if (cmd) { 184ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__, 185ff984e57SWei WANG cmd[0] - 0x40); 186ff984e57SWei WANG 187ff984e57SWei WANG for (i = 0; i < 5; i++) 188ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 189ff984e57SWei WANG SD_CMD0 + i, 0xFF, cmd[i]); 190ff984e57SWei WANG } 191ff984e57SWei WANG 192ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 193ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 194ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 195ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 196ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 197ff984e57SWei WANG 198ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 199ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 200ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 201ff984e57SWei WANG 202ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 203ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 204ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 205ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 206ff984e57SWei WANG 207ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 208ff984e57SWei WANG if (err < 0) { 209ff984e57SWei WANG sd_print_debug_regs(host); 210ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 211ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 212ff984e57SWei WANG return err; 213ff984e57SWei WANG } 214ff984e57SWei WANG 215ff984e57SWei WANG return 0; 216ff984e57SWei WANG } 217ff984e57SWei WANG 218ff984e57SWei WANG static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 219ff984e57SWei WANG struct mmc_command *cmd) 220ff984e57SWei WANG { 221ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 222ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 223ff984e57SWei WANG u32 arg = cmd->arg; 224ff984e57SWei WANG int err = 0; 225ff984e57SWei WANG int timeout = 100; 226ff984e57SWei WANG int i; 227ff984e57SWei WANG u8 *ptr; 228ff984e57SWei WANG int stat_idx = 0; 229ff984e57SWei WANG u8 rsp_type; 230ff984e57SWei WANG int rsp_len = 5; 231ff984e57SWei WANG 232ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 233ff984e57SWei WANG __func__, cmd_idx, arg); 234ff984e57SWei WANG 235ff984e57SWei WANG /* Response type: 236ff984e57SWei WANG * R0 237ff984e57SWei WANG * R1, R5, R6, R7 238ff984e57SWei WANG * R1b 239ff984e57SWei WANG * R2 240ff984e57SWei WANG * R3, R4 241ff984e57SWei WANG */ 242ff984e57SWei WANG switch (mmc_resp_type(cmd)) { 243ff984e57SWei WANG case MMC_RSP_NONE: 244ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R0; 245ff984e57SWei WANG rsp_len = 0; 246ff984e57SWei WANG break; 247ff984e57SWei WANG case MMC_RSP_R1: 248ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1; 249ff984e57SWei WANG break; 250ff984e57SWei WANG case MMC_RSP_R1B: 251ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1b; 252ff984e57SWei WANG break; 253ff984e57SWei WANG case MMC_RSP_R2: 254ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R2; 255ff984e57SWei WANG rsp_len = 16; 256ff984e57SWei WANG break; 257ff984e57SWei WANG case MMC_RSP_R3: 258ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R3; 259ff984e57SWei WANG break; 260ff984e57SWei WANG default: 261ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n"); 262ff984e57SWei WANG err = -EINVAL; 263ff984e57SWei WANG goto out; 264ff984e57SWei WANG } 265ff984e57SWei WANG 266ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 267ff984e57SWei WANG timeout = 3000; 268ff984e57SWei WANG 269ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 270ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 271ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 272ff984e57SWei WANG if (err < 0) 273ff984e57SWei WANG goto out; 274ff984e57SWei WANG } 275ff984e57SWei WANG 276ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 277ff984e57SWei WANG 278ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx); 279ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24)); 280ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16)); 281ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8)); 282ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg); 283ff984e57SWei WANG 284ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 285ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 286ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 287ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 288ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 289ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 290ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 291ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 292ff984e57SWei WANG 293ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 294ff984e57SWei WANG /* Read data from ping-pong buffer */ 295ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 296ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 297ff984e57SWei WANG stat_idx = 16; 298ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 299ff984e57SWei WANG /* Read data from SD_CMDx registers */ 300ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 301ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 302ff984e57SWei WANG stat_idx = 5; 303ff984e57SWei WANG } 304ff984e57SWei WANG 305ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 306ff984e57SWei WANG 307ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 308ff984e57SWei WANG if (err < 0) { 309ff984e57SWei WANG sd_print_debug_regs(host); 310ff984e57SWei WANG sd_clear_error(host); 311ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 312ff984e57SWei WANG "rtsx_pci_send_cmd error (err = %d)\n", err); 313ff984e57SWei WANG goto out; 314ff984e57SWei WANG } 315ff984e57SWei WANG 316ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 317ff984e57SWei WANG err = 0; 318ff984e57SWei WANG goto out; 319ff984e57SWei WANG } 320ff984e57SWei WANG 321ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 322ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 323ff984e57SWei WANG 324ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 325ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 326ff984e57SWei WANG err = -EILSEQ; 327ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 328ff984e57SWei WANG goto out; 329ff984e57SWei WANG } 330ff984e57SWei WANG 331ff984e57SWei WANG /* Check CRC7 */ 332ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 333ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 334ff984e57SWei WANG err = -EILSEQ; 335ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 336ff984e57SWei WANG goto out; 337ff984e57SWei WANG } 338ff984e57SWei WANG } 339ff984e57SWei WANG 340ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 341ff984e57SWei WANG for (i = 0; i < 4; i++) { 342ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 343ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 344ff984e57SWei WANG i, cmd->resp[i]); 345ff984e57SWei WANG } 346ff984e57SWei WANG } else { 347ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 348ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 349ff984e57SWei WANG cmd->resp[0]); 350ff984e57SWei WANG } 351ff984e57SWei WANG 352ff984e57SWei WANG out: 353ff984e57SWei WANG cmd->error = err; 354ff984e57SWei WANG } 355ff984e57SWei WANG 356ff984e57SWei WANG static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 357ff984e57SWei WANG { 358ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 359ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 360ff984e57SWei WANG struct mmc_card *card = mmc->card; 361ff984e57SWei WANG struct mmc_data *data = mrq->data; 362ff984e57SWei WANG int uhs = mmc_sd_card_uhs(card); 363ff984e57SWei WANG int read = (data->flags & MMC_DATA_READ) ? 1 : 0; 364ff984e57SWei WANG u8 cfg2, trans_mode; 365ff984e57SWei WANG int err; 366ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 367ff984e57SWei WANG 368ff984e57SWei WANG if (read) { 369ff984e57SWei WANG cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 370ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0; 371ff984e57SWei WANG trans_mode = SD_TM_AUTO_READ_3; 372ff984e57SWei WANG } else { 373ff984e57SWei WANG cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 374ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 375ff984e57SWei WANG trans_mode = SD_TM_AUTO_WRITE_3; 376ff984e57SWei WANG } 377ff984e57SWei WANG 378ff984e57SWei WANG if (!uhs) 379ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 380ff984e57SWei WANG 381ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 382ff984e57SWei WANG 383ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00); 384ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02); 385ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 386ff984e57SWei WANG 0xFF, (u8)data->blocks); 387ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 388ff984e57SWei WANG 0xFF, (u8)(data->blocks >> 8)); 389ff984e57SWei WANG 390ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 391ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 392ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 393ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 394ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 395ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 396ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 397ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 398ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 399ff984e57SWei WANG if (read) { 400ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 401ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 402ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 403ff984e57SWei WANG } else { 404ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 405ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 406ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 407ff984e57SWei WANG } 408ff984e57SWei WANG 409ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 410ff984e57SWei WANG 0x01, RING_BUFFER); 411ff984e57SWei WANG 41238d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 413ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 414ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 415ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 416ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 417ff984e57SWei WANG 418ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 419ff984e57SWei WANG 420ff984e57SWei WANG err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000); 421ff984e57SWei WANG if (err < 0) { 422ff984e57SWei WANG sd_clear_error(host); 423ff984e57SWei WANG return err; 424ff984e57SWei WANG } 425ff984e57SWei WANG 426ff984e57SWei WANG return 0; 427ff984e57SWei WANG } 428ff984e57SWei WANG 429ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 430ff984e57SWei WANG { 431ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 432ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 433ff984e57SWei WANG } 434ff984e57SWei WANG 435ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 436ff984e57SWei WANG { 437ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 438ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 439ff984e57SWei WANG } 440ff984e57SWei WANG 441ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 442ff984e57SWei WANG struct mmc_request *mrq) 443ff984e57SWei WANG { 444ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 445ff984e57SWei WANG struct mmc_data *data = mrq->data; 446ff984e57SWei WANG u8 _cmd[5], *buf; 447ff984e57SWei WANG 448ff984e57SWei WANG _cmd[0] = 0x40 | (u8)cmd->opcode; 449ff984e57SWei WANG put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1])); 450ff984e57SWei WANG 451ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 452ff984e57SWei WANG if (!buf) { 453ff984e57SWei WANG cmd->error = -ENOMEM; 454ff984e57SWei WANG return; 455ff984e57SWei WANG } 456ff984e57SWei WANG 457ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 458ff984e57SWei WANG if (host->initial_mode) 459ff984e57SWei WANG sd_disable_initial_mode(host); 460ff984e57SWei WANG 461ff984e57SWei WANG cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf, 462ff984e57SWei WANG data->blksz, 200); 463ff984e57SWei WANG 464ff984e57SWei WANG if (host->initial_mode) 465ff984e57SWei WANG sd_enable_initial_mode(host); 466ff984e57SWei WANG 467ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 468ff984e57SWei WANG } else { 469ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 470ff984e57SWei WANG 471ff984e57SWei WANG cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf, 472ff984e57SWei WANG data->blksz, 200); 473ff984e57SWei WANG } 474ff984e57SWei WANG 475ff984e57SWei WANG kfree(buf); 476ff984e57SWei WANG } 477ff984e57SWei WANG 478ff984e57SWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, u8 sample_point) 479ff984e57SWei WANG { 480ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 481ff984e57SWei WANG int err; 482ff984e57SWei WANG 483ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: sample_point = %d\n", 484ff984e57SWei WANG __func__, sample_point); 485ff984e57SWei WANG 486ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 487ff984e57SWei WANG 488ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 489ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPRX_CTL, 0x1F, sample_point); 490ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); 491ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 492ff984e57SWei WANG PHASE_NOT_RESET, PHASE_NOT_RESET); 493ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); 494ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 495ff984e57SWei WANG 496ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 497ff984e57SWei WANG if (err < 0) 498ff984e57SWei WANG return err; 499ff984e57SWei WANG 500ff984e57SWei WANG return 0; 501ff984e57SWei WANG } 502ff984e57SWei WANG 503ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 504ff984e57SWei WANG { 505ff984e57SWei WANG struct timing_phase_path path[MAX_PHASE + 1]; 506ff984e57SWei WANG int i, j, cont_path_cnt; 507ff984e57SWei WANG int new_block, max_len, final_path_idx; 508ff984e57SWei WANG u8 final_phase = 0xFF; 509ff984e57SWei WANG 510ff984e57SWei WANG /* Parse phase_map, take it as a bit-ring */ 511ff984e57SWei WANG cont_path_cnt = 0; 512ff984e57SWei WANG new_block = 1; 513ff984e57SWei WANG j = 0; 514ff984e57SWei WANG for (i = 0; i < MAX_PHASE + 1; i++) { 515ff984e57SWei WANG if (phase_map & (1 << i)) { 516ff984e57SWei WANG if (new_block) { 517ff984e57SWei WANG new_block = 0; 518ff984e57SWei WANG j = cont_path_cnt++; 519ff984e57SWei WANG path[j].start = i; 520ff984e57SWei WANG path[j].end = i; 521ff984e57SWei WANG } else { 522ff984e57SWei WANG path[j].end = i; 523ff984e57SWei WANG } 524ff984e57SWei WANG } else { 525ff984e57SWei WANG new_block = 1; 526ff984e57SWei WANG if (cont_path_cnt) { 527ff984e57SWei WANG /* Calculate path length and middle point */ 528ff984e57SWei WANG int idx = cont_path_cnt - 1; 529ff984e57SWei WANG path[idx].len = 530ff984e57SWei WANG path[idx].end - path[idx].start + 1; 531ff984e57SWei WANG path[idx].mid = 532ff984e57SWei WANG path[idx].start + path[idx].len / 2; 533ff984e57SWei WANG } 534ff984e57SWei WANG } 535ff984e57SWei WANG } 536ff984e57SWei WANG 537ff984e57SWei WANG if (cont_path_cnt == 0) { 538ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "No continuous phase path\n"); 539ff984e57SWei WANG goto finish; 540ff984e57SWei WANG } else { 541ff984e57SWei WANG /* Calculate last continuous path length and middle point */ 542ff984e57SWei WANG int idx = cont_path_cnt - 1; 543ff984e57SWei WANG path[idx].len = path[idx].end - path[idx].start + 1; 544ff984e57SWei WANG path[idx].mid = path[idx].start + path[idx].len / 2; 545ff984e57SWei WANG } 546ff984e57SWei WANG 547ff984e57SWei WANG /* Connect the first and last continuous paths if they are adjacent */ 548ff984e57SWei WANG if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) { 549ff984e57SWei WANG /* Using negative index */ 550ff984e57SWei WANG path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1; 551ff984e57SWei WANG path[0].len += path[cont_path_cnt - 1].len; 552ff984e57SWei WANG path[0].mid = path[0].start + path[0].len / 2; 553ff984e57SWei WANG /* Convert negative middle point index to positive one */ 554ff984e57SWei WANG if (path[0].mid < 0) 555ff984e57SWei WANG path[0].mid += MAX_PHASE + 1; 556ff984e57SWei WANG cont_path_cnt--; 557ff984e57SWei WANG } 558ff984e57SWei WANG 559ff984e57SWei WANG /* Choose the longest continuous phase path */ 560ff984e57SWei WANG max_len = 0; 561ff984e57SWei WANG final_phase = 0; 562ff984e57SWei WANG final_path_idx = 0; 563ff984e57SWei WANG for (i = 0; i < cont_path_cnt; i++) { 564ff984e57SWei WANG if (path[i].len > max_len) { 565ff984e57SWei WANG max_len = path[i].len; 566ff984e57SWei WANG final_phase = (u8)path[i].mid; 567ff984e57SWei WANG final_path_idx = i; 568ff984e57SWei WANG } 569ff984e57SWei WANG 570ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n", 571ff984e57SWei WANG i, path[i].start); 572ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n", 573ff984e57SWei WANG i, path[i].end); 574ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n", 575ff984e57SWei WANG i, path[i].len); 576ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n", 577ff984e57SWei WANG i, path[i].mid); 578ff984e57SWei WANG } 579ff984e57SWei WANG 580ff984e57SWei WANG finish: 581ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase); 582ff984e57SWei WANG return final_phase; 583ff984e57SWei WANG } 584ff984e57SWei WANG 585ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 586ff984e57SWei WANG { 587ff984e57SWei WANG int err, i; 588ff984e57SWei WANG u8 val = 0; 589ff984e57SWei WANG 590ff984e57SWei WANG for (i = 0; i < 100; i++) { 591ff984e57SWei WANG err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 592ff984e57SWei WANG if (val & SD_DATA_IDLE) 593ff984e57SWei WANG return; 594ff984e57SWei WANG 595ff984e57SWei WANG udelay(100); 596ff984e57SWei WANG } 597ff984e57SWei WANG } 598ff984e57SWei WANG 599ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 600ff984e57SWei WANG u8 opcode, u8 sample_point) 601ff984e57SWei WANG { 602ff984e57SWei WANG int err; 603ff984e57SWei WANG u8 cmd[5] = {0}; 604ff984e57SWei WANG 605ff984e57SWei WANG err = sd_change_phase(host, sample_point); 606ff984e57SWei WANG if (err < 0) 607ff984e57SWei WANG return err; 608ff984e57SWei WANG 609ff984e57SWei WANG cmd[0] = 0x40 | opcode; 610ff984e57SWei WANG err = sd_read_data(host, cmd, 0x40, NULL, 0, 100); 611ff984e57SWei WANG if (err < 0) { 612ff984e57SWei WANG /* Wait till SD DATA IDLE */ 613ff984e57SWei WANG sd_wait_data_idle(host); 614ff984e57SWei WANG sd_clear_error(host); 615ff984e57SWei WANG return err; 616ff984e57SWei WANG } 617ff984e57SWei WANG 618ff984e57SWei WANG return 0; 619ff984e57SWei WANG } 620ff984e57SWei WANG 621ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 622ff984e57SWei WANG u8 opcode, u32 *phase_map) 623ff984e57SWei WANG { 624ff984e57SWei WANG int err, i; 625ff984e57SWei WANG u32 raw_phase_map = 0; 626ff984e57SWei WANG 627ff984e57SWei WANG for (i = MAX_PHASE; i >= 0; i--) { 628ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 629ff984e57SWei WANG if (err == 0) 630ff984e57SWei WANG raw_phase_map |= 1 << i; 631ff984e57SWei WANG } 632ff984e57SWei WANG 633ff984e57SWei WANG if (phase_map) 634ff984e57SWei WANG *phase_map = raw_phase_map; 635ff984e57SWei WANG 636ff984e57SWei WANG return 0; 637ff984e57SWei WANG } 638ff984e57SWei WANG 639ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 640ff984e57SWei WANG { 641ff984e57SWei WANG int err, i; 642ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 643ff984e57SWei WANG u8 final_phase; 644ff984e57SWei WANG 645ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 646ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 647ff984e57SWei WANG if (err < 0) 648ff984e57SWei WANG return err; 649ff984e57SWei WANG 650ff984e57SWei WANG if (raw_phase_map[i] == 0) 651ff984e57SWei WANG break; 652ff984e57SWei WANG } 653ff984e57SWei WANG 654ff984e57SWei WANG phase_map = 0xFFFFFFFF; 655ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 656ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 657ff984e57SWei WANG i, raw_phase_map[i]); 658ff984e57SWei WANG phase_map &= raw_phase_map[i]; 659ff984e57SWei WANG } 660ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 661ff984e57SWei WANG 662ff984e57SWei WANG if (phase_map) { 663ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 664ff984e57SWei WANG if (final_phase == 0xFF) 665ff984e57SWei WANG return -EINVAL; 666ff984e57SWei WANG 667ff984e57SWei WANG err = sd_change_phase(host, final_phase); 668ff984e57SWei WANG if (err < 0) 669ff984e57SWei WANG return err; 670ff984e57SWei WANG } else { 671ff984e57SWei WANG return -EINVAL; 672ff984e57SWei WANG } 673ff984e57SWei WANG 674ff984e57SWei WANG return 0; 675ff984e57SWei WANG } 676ff984e57SWei WANG 677ff984e57SWei WANG static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 678ff984e57SWei WANG { 679ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 680ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 681ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 682ff984e57SWei WANG struct mmc_data *data = mrq->data; 683ff984e57SWei WANG unsigned int data_size = 0; 684c3481955SWei WANG int err; 685ff984e57SWei WANG 686ff984e57SWei WANG if (host->eject) { 687ff984e57SWei WANG cmd->error = -ENOMEDIUM; 688ff984e57SWei WANG goto finish; 689ff984e57SWei WANG } 690ff984e57SWei WANG 691c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 692c3481955SWei WANG if (err) { 693c3481955SWei WANG cmd->error = err; 694c3481955SWei WANG goto finish; 695c3481955SWei WANG } 696c3481955SWei WANG 697ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 698ff984e57SWei WANG 699ff984e57SWei WANG rtsx_pci_start_run(pcr); 700ff984e57SWei WANG 701ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 702ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 703ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 704ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 705ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 706ff984e57SWei WANG 707ff984e57SWei WANG mutex_lock(&host->host_mutex); 708ff984e57SWei WANG host->mrq = mrq; 709ff984e57SWei WANG mutex_unlock(&host->host_mutex); 710ff984e57SWei WANG 711ff984e57SWei WANG if (mrq->data) 712ff984e57SWei WANG data_size = data->blocks * data->blksz; 713ff984e57SWei WANG 714ff984e57SWei WANG if (!data_size || mmc_op_multi(cmd->opcode) || 715ff984e57SWei WANG (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 716ff984e57SWei WANG (cmd->opcode == MMC_WRITE_BLOCK)) { 717ff984e57SWei WANG sd_send_cmd_get_rsp(host, cmd); 718ff984e57SWei WANG 719ff984e57SWei WANG if (!cmd->error && data_size) { 720ff984e57SWei WANG sd_rw_multi(host, mrq); 721ff984e57SWei WANG 722ff984e57SWei WANG if (mmc_op_multi(cmd->opcode) && mrq->stop) 723ff984e57SWei WANG sd_send_cmd_get_rsp(host, mrq->stop); 724ff984e57SWei WANG } 725ff984e57SWei WANG } else { 726ff984e57SWei WANG sd_normal_rw(host, mrq); 727ff984e57SWei WANG } 728ff984e57SWei WANG 729ff984e57SWei WANG if (mrq->data) { 730ff984e57SWei WANG if (cmd->error || data->error) 731ff984e57SWei WANG data->bytes_xfered = 0; 732ff984e57SWei WANG else 733ff984e57SWei WANG data->bytes_xfered = data->blocks * data->blksz; 734ff984e57SWei WANG } 735ff984e57SWei WANG 736ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 737ff984e57SWei WANG 738ff984e57SWei WANG finish: 739ff984e57SWei WANG if (cmd->error) 740ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error); 741ff984e57SWei WANG 742ff984e57SWei WANG mutex_lock(&host->host_mutex); 743ff984e57SWei WANG host->mrq = NULL; 744ff984e57SWei WANG mutex_unlock(&host->host_mutex); 745ff984e57SWei WANG 746ff984e57SWei WANG mmc_request_done(mmc, mrq); 747ff984e57SWei WANG } 748ff984e57SWei WANG 749ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 750ff984e57SWei WANG unsigned char bus_width) 751ff984e57SWei WANG { 752ff984e57SWei WANG int err = 0; 753ff984e57SWei WANG u8 width[] = { 754ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 755ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 756ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 757ff984e57SWei WANG }; 758ff984e57SWei WANG 759ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 760ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 761ff984e57SWei WANG 0x03, width[bus_width]); 762ff984e57SWei WANG 763ff984e57SWei WANG return err; 764ff984e57SWei WANG } 765ff984e57SWei WANG 766ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 767ff984e57SWei WANG { 768ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 769ff984e57SWei WANG int err; 770ff984e57SWei WANG 771d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 772d88691beSWei WANG return 0; 773d88691beSWei WANG 774ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 775ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 776ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 777ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 778ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 779ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 780ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 781ff984e57SWei WANG if (err < 0) 782ff984e57SWei WANG return err; 783ff984e57SWei WANG 784ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 785ff984e57SWei WANG if (err < 0) 786ff984e57SWei WANG return err; 787ff984e57SWei WANG 788ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 789ff984e57SWei WANG if (err < 0) 790ff984e57SWei WANG return err; 791ff984e57SWei WANG 792ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 793ff984e57SWei WANG if (err < 0) 794ff984e57SWei WANG return err; 795ff984e57SWei WANG 796d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 797ff984e57SWei WANG return 0; 798ff984e57SWei WANG } 799ff984e57SWei WANG 800ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 801ff984e57SWei WANG { 802ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 803ff984e57SWei WANG int err; 804ff984e57SWei WANG 805d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 806d88691beSWei WANG 807ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 808ff984e57SWei WANG 809ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 810ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 811ff984e57SWei WANG 812ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 813ff984e57SWei WANG if (err < 0) 814ff984e57SWei WANG return err; 815ff984e57SWei WANG 816ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 817ff984e57SWei WANG if (err < 0) 818ff984e57SWei WANG return err; 819ff984e57SWei WANG 820ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 821ff984e57SWei WANG } 822ff984e57SWei WANG 823ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 824ff984e57SWei WANG unsigned char power_mode) 825ff984e57SWei WANG { 826ff984e57SWei WANG int err; 827ff984e57SWei WANG 828ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 829ff984e57SWei WANG err = sd_power_off(host); 830ff984e57SWei WANG else 831ff984e57SWei WANG err = sd_power_on(host); 832ff984e57SWei WANG 833ff984e57SWei WANG return err; 834ff984e57SWei WANG } 835ff984e57SWei WANG 836ff984e57SWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, 837ff984e57SWei WANG unsigned char timing, bool *ddr_mode) 838ff984e57SWei WANG { 839ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 840ff984e57SWei WANG int err = 0; 841ff984e57SWei WANG 842ff984e57SWei WANG *ddr_mode = false; 843ff984e57SWei WANG 844ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 845ff984e57SWei WANG 846ff984e57SWei WANG switch (timing) { 847ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 848ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 849ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 850ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 851ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 852ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 853ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 854ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 855ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 856ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 857ff984e57SWei WANG break; 858ff984e57SWei WANG 859ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 860ff984e57SWei WANG *ddr_mode = true; 861ff984e57SWei WANG 862ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 863ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 864ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 865ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 866ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 867ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 868ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 869ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 870ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 871ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 872ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 873ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 874ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 875ff984e57SWei WANG break; 876ff984e57SWei WANG 877ff984e57SWei WANG case MMC_TIMING_MMC_HS: 878ff984e57SWei WANG case MMC_TIMING_SD_HS: 879ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 880ff984e57SWei WANG 0x0C, SD_20_MODE); 881ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 882ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 883ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 884ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 885ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 886ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 887ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 888ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 889ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 890ff984e57SWei WANG break; 891ff984e57SWei WANG 892ff984e57SWei WANG default: 893ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 894ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 895ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 896ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 897ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 898ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 899ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 900ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 901ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 902ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 903ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 904ff984e57SWei WANG break; 905ff984e57SWei WANG } 906ff984e57SWei WANG 907ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 908ff984e57SWei WANG 909ff984e57SWei WANG return err; 910ff984e57SWei WANG } 911ff984e57SWei WANG 912ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 913ff984e57SWei WANG { 914ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 915ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 916ff984e57SWei WANG 917ff984e57SWei WANG if (host->eject) 918ff984e57SWei WANG return; 919ff984e57SWei WANG 920c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 921c3481955SWei WANG return; 922c3481955SWei WANG 923ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 924ff984e57SWei WANG 925ff984e57SWei WANG rtsx_pci_start_run(pcr); 926ff984e57SWei WANG 927ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 928ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 929ff984e57SWei WANG sd_set_timing(host, ios->timing, &host->ddr_mode); 930ff984e57SWei WANG 931ff984e57SWei WANG host->vpclk = false; 932ff984e57SWei WANG host->double_clk = true; 933ff984e57SWei WANG 934ff984e57SWei WANG switch (ios->timing) { 935ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 936ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 937ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 938ff984e57SWei WANG host->vpclk = true; 939ff984e57SWei WANG host->double_clk = false; 940ff984e57SWei WANG break; 941ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 942ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 943ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 944ff984e57SWei WANG break; 945ff984e57SWei WANG default: 946ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 947ff984e57SWei WANG break; 948ff984e57SWei WANG } 949ff984e57SWei WANG 950ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 951ff984e57SWei WANG 952ff984e57SWei WANG host->clock = ios->clock; 953ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 954ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 955ff984e57SWei WANG 956ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 957ff984e57SWei WANG } 958ff984e57SWei WANG 959ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 960ff984e57SWei WANG { 961ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 962ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 963ff984e57SWei WANG int ro = 0; 964ff984e57SWei WANG u32 val; 965ff984e57SWei WANG 966ff984e57SWei WANG if (host->eject) 967ff984e57SWei WANG return -ENOMEDIUM; 968ff984e57SWei WANG 969ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 970ff984e57SWei WANG 971ff984e57SWei WANG rtsx_pci_start_run(pcr); 972ff984e57SWei WANG 973ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 974ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 975ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 976ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 977ff984e57SWei WANG ro = 1; 978ff984e57SWei WANG 979ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 980ff984e57SWei WANG 981ff984e57SWei WANG return ro; 982ff984e57SWei WANG } 983ff984e57SWei WANG 984ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 985ff984e57SWei WANG { 986ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 987ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 988ff984e57SWei WANG int cd = 0; 989ff984e57SWei WANG u32 val; 990ff984e57SWei WANG 991ff984e57SWei WANG if (host->eject) 992ff984e57SWei WANG return -ENOMEDIUM; 993ff984e57SWei WANG 994ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 995ff984e57SWei WANG 996ff984e57SWei WANG rtsx_pci_start_run(pcr); 997ff984e57SWei WANG 998ff984e57SWei WANG /* Check SD card detect */ 999ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 1000ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1001ff984e57SWei WANG if (val & SD_EXIST) 1002ff984e57SWei WANG cd = 1; 1003ff984e57SWei WANG 1004ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1005ff984e57SWei WANG 1006ff984e57SWei WANG return cd; 1007ff984e57SWei WANG } 1008ff984e57SWei WANG 1009ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1010ff984e57SWei WANG { 1011ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1012ff984e57SWei WANG int err; 1013ff984e57SWei WANG u8 stat; 1014ff984e57SWei WANG 1015ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 1016ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 1017ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 1018ff984e57SWei WANG */ 1019ff984e57SWei WANG mdelay(1); 1020ff984e57SWei WANG 1021ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1022ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 1023ff984e57SWei WANG * abort the voltage switch sequence; 1024ff984e57SWei WANG */ 1025ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1026ff984e57SWei WANG if (err < 0) 1027ff984e57SWei WANG return err; 1028ff984e57SWei WANG 1029ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1030ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 1031ff984e57SWei WANG return -EINVAL; 1032ff984e57SWei WANG 1033ff984e57SWei WANG /* Stop toggle SD clock */ 1034ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1035ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 1036ff984e57SWei WANG if (err < 0) 1037ff984e57SWei WANG return err; 1038ff984e57SWei WANG 1039ff984e57SWei WANG return 0; 1040ff984e57SWei WANG } 1041ff984e57SWei WANG 1042ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1043ff984e57SWei WANG { 1044ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1045ff984e57SWei WANG int err; 1046ff984e57SWei WANG u8 stat, mask, val; 1047ff984e57SWei WANG 1048ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1049ff984e57SWei WANG msleep(50); 1050ff984e57SWei WANG 1051ff984e57SWei WANG /* Toggle SD clock again */ 1052ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1053ff984e57SWei WANG if (err < 0) 1054ff984e57SWei WANG return err; 1055ff984e57SWei WANG 1056ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1057ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1058ff984e57SWei WANG */ 1059ff984e57SWei WANG msleep(20); 1060ff984e57SWei WANG 1061ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1062ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1063ff984e57SWei WANG if (err < 0) 1064ff984e57SWei WANG return err; 1065ff984e57SWei WANG 1066ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1067ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1068ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1069ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1070ff984e57SWei WANG if ((stat & mask) != val) { 1071ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1072ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1073ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1074ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1075ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1076ff984e57SWei WANG return -EINVAL; 1077ff984e57SWei WANG } 1078ff984e57SWei WANG 1079ff984e57SWei WANG return 0; 1080ff984e57SWei WANG } 1081ff984e57SWei WANG 1082ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1083ff984e57SWei WANG { 1084ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1085ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1086ff984e57SWei WANG int err = 0; 1087ff984e57SWei WANG u8 voltage; 1088ff984e57SWei WANG 1089ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1090ff984e57SWei WANG __func__, ios->signal_voltage); 1091ff984e57SWei WANG 1092ff984e57SWei WANG if (host->eject) 1093ff984e57SWei WANG return -ENOMEDIUM; 1094ff984e57SWei WANG 1095c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1096c3481955SWei WANG if (err) 1097c3481955SWei WANG return err; 1098c3481955SWei WANG 1099ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1100ff984e57SWei WANG 1101ff984e57SWei WANG rtsx_pci_start_run(pcr); 1102ff984e57SWei WANG 1103ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1104ef85e736SWei WANG voltage = OUTPUT_3V3; 1105ff984e57SWei WANG else 1106ef85e736SWei WANG voltage = OUTPUT_1V8; 1107ff984e57SWei WANG 1108ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1109ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1110ff984e57SWei WANG if (err < 0) 1111ff984e57SWei WANG goto out; 1112ff984e57SWei WANG } 1113ff984e57SWei WANG 1114ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1115ff984e57SWei WANG if (err < 0) 1116ff984e57SWei WANG goto out; 1117ff984e57SWei WANG 1118ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1119ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1120ff984e57SWei WANG if (err < 0) 1121ff984e57SWei WANG goto out; 1122ff984e57SWei WANG } 1123ff984e57SWei WANG 1124ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1125ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1126ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1127ff984e57SWei WANG 1128ff984e57SWei WANG out: 1129ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1130ff984e57SWei WANG 1131ff984e57SWei WANG return err; 1132ff984e57SWei WANG } 1133ff984e57SWei WANG 1134ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1135ff984e57SWei WANG { 1136ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1137ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1138ff984e57SWei WANG int err = 0; 1139ff984e57SWei WANG 1140ff984e57SWei WANG if (host->eject) 1141ff984e57SWei WANG return -ENOMEDIUM; 1142ff984e57SWei WANG 1143c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1144c3481955SWei WANG if (err) 1145c3481955SWei WANG return err; 1146c3481955SWei WANG 1147ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1148ff984e57SWei WANG 1149ff984e57SWei WANG rtsx_pci_start_run(pcr); 1150ff984e57SWei WANG 1151ff984e57SWei WANG if (!host->ddr_mode) 1152ff984e57SWei WANG err = sd_tuning_rx(host, MMC_SEND_TUNING_BLOCK); 1153ff984e57SWei WANG 1154ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1155ff984e57SWei WANG 1156ff984e57SWei WANG return err; 1157ff984e57SWei WANG } 1158ff984e57SWei WANG 1159ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 1160ff984e57SWei WANG .request = sdmmc_request, 1161ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1162ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1163ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1164ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1165ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 1166ff984e57SWei WANG }; 1167ff984e57SWei WANG 1168ff984e57SWei WANG #ifdef CONFIG_PM 1169ff984e57SWei WANG static int rtsx_pci_sdmmc_suspend(struct platform_device *pdev, 1170ff984e57SWei WANG pm_message_t state) 1171ff984e57SWei WANG { 1172ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1173ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1174ff984e57SWei WANG int err; 1175ff984e57SWei WANG 1176ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "--> %s\n", __func__); 1177ff984e57SWei WANG 1178ff984e57SWei WANG err = mmc_suspend_host(mmc); 1179ff984e57SWei WANG if (err) 1180ff984e57SWei WANG return err; 1181ff984e57SWei WANG 1182ff984e57SWei WANG return 0; 1183ff984e57SWei WANG } 1184ff984e57SWei WANG 1185ff984e57SWei WANG static int rtsx_pci_sdmmc_resume(struct platform_device *pdev) 1186ff984e57SWei WANG { 1187ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1188ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1189ff984e57SWei WANG 1190ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "--> %s\n", __func__); 1191ff984e57SWei WANG 1192ff984e57SWei WANG return mmc_resume_host(mmc); 1193ff984e57SWei WANG } 1194ff984e57SWei WANG #else /* CONFIG_PM */ 1195ff984e57SWei WANG #define rtsx_pci_sdmmc_suspend NULL 1196ff984e57SWei WANG #define rtsx_pci_sdmmc_resume NULL 1197ff984e57SWei WANG #endif /* CONFIG_PM */ 1198ff984e57SWei WANG 1199ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1200ff984e57SWei WANG { 1201ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1202ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1203ff984e57SWei WANG 1204ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1205ff984e57SWei WANG 1206ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1207ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1208ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1209ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1210ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1211ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1212ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1213ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1214ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1215ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1216ff984e57SWei WANG } 1217ff984e57SWei WANG 1218ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1219ff984e57SWei WANG { 1220ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1221ff984e57SWei WANG 1222ff984e57SWei WANG mmc->f_min = 250000; 1223ff984e57SWei WANG mmc->f_max = 208000000; 1224ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1225ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1226ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1227ff984e57SWei WANG MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1228ff984e57SWei WANG mmc->max_current_330 = 400; 1229ff984e57SWei WANG mmc->max_current_180 = 800; 1230ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1231ff984e57SWei WANG 1232ff984e57SWei WANG init_extra_caps(host); 1233ff984e57SWei WANG 1234ff984e57SWei WANG mmc->max_segs = 256; 1235ff984e57SWei WANG mmc->max_seg_size = 65536; 1236ff984e57SWei WANG mmc->max_blk_size = 512; 1237ff984e57SWei WANG mmc->max_blk_count = 65535; 1238ff984e57SWei WANG mmc->max_req_size = 524288; 1239ff984e57SWei WANG } 1240ff984e57SWei WANG 1241ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1242ff984e57SWei WANG { 1243ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1244ff984e57SWei WANG 1245ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1246ff984e57SWei WANG } 1247ff984e57SWei WANG 1248ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1249ff984e57SWei WANG { 1250ff984e57SWei WANG struct mmc_host *mmc; 1251ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1252ff984e57SWei WANG struct rtsx_pcr *pcr; 1253ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1254ff984e57SWei WANG 1255ff984e57SWei WANG if (!handle) 1256ff984e57SWei WANG return -ENXIO; 1257ff984e57SWei WANG 1258ff984e57SWei WANG pcr = handle->pcr; 1259ff984e57SWei WANG if (!pcr) 1260ff984e57SWei WANG return -ENXIO; 1261ff984e57SWei WANG 1262ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1263ff984e57SWei WANG 1264ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1265ff984e57SWei WANG if (!mmc) 1266ff984e57SWei WANG return -ENOMEM; 1267ff984e57SWei WANG 1268ff984e57SWei WANG host = mmc_priv(mmc); 1269ff984e57SWei WANG host->pcr = pcr; 1270ff984e57SWei WANG host->mmc = mmc; 1271ff984e57SWei WANG host->pdev = pdev; 1272d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 1273ff984e57SWei WANG platform_set_drvdata(pdev, host); 1274ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1275ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1276ff984e57SWei WANG 1277ff984e57SWei WANG mutex_init(&host->host_mutex); 1278ff984e57SWei WANG 1279ff984e57SWei WANG realtek_init_host(host); 1280ff984e57SWei WANG 1281ff984e57SWei WANG mmc_add_host(mmc); 1282ff984e57SWei WANG 1283ff984e57SWei WANG return 0; 1284ff984e57SWei WANG } 1285ff984e57SWei WANG 1286ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1287ff984e57SWei WANG { 1288ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1289ff984e57SWei WANG struct rtsx_pcr *pcr; 1290ff984e57SWei WANG struct mmc_host *mmc; 1291ff984e57SWei WANG 1292ff984e57SWei WANG if (!host) 1293ff984e57SWei WANG return 0; 1294ff984e57SWei WANG 1295ff984e57SWei WANG pcr = host->pcr; 1296ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1297ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1298ff984e57SWei WANG mmc = host->mmc; 1299ff984e57SWei WANG host->eject = true; 1300ff984e57SWei WANG 1301ff984e57SWei WANG mutex_lock(&host->host_mutex); 1302ff984e57SWei WANG if (host->mrq) { 1303ff984e57SWei WANG dev_dbg(&(pdev->dev), 1304ff984e57SWei WANG "%s: Controller removed during transfer\n", 1305ff984e57SWei WANG mmc_hostname(mmc)); 1306ff984e57SWei WANG 1307ff984e57SWei WANG rtsx_pci_complete_unfinished_transfer(pcr); 1308ff984e57SWei WANG 1309ff984e57SWei WANG host->mrq->cmd->error = -ENOMEDIUM; 1310ff984e57SWei WANG if (host->mrq->stop) 1311ff984e57SWei WANG host->mrq->stop->error = -ENOMEDIUM; 1312ff984e57SWei WANG mmc_request_done(mmc, host->mrq); 1313ff984e57SWei WANG } 1314ff984e57SWei WANG mutex_unlock(&host->host_mutex); 1315ff984e57SWei WANG 1316ff984e57SWei WANG mmc_remove_host(mmc); 1317ff984e57SWei WANG mmc_free_host(mmc); 1318ff984e57SWei WANG 1319ff984e57SWei WANG platform_set_drvdata(pdev, NULL); 1320ff984e57SWei WANG 1321ff984e57SWei WANG dev_dbg(&(pdev->dev), 1322ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1323ff984e57SWei WANG 1324ff984e57SWei WANG return 0; 1325ff984e57SWei WANG } 1326ff984e57SWei WANG 1327ff984e57SWei WANG static struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1328ff984e57SWei WANG { 1329ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1330ff984e57SWei WANG }, { 1331ff984e57SWei WANG /* sentinel */ 1332ff984e57SWei WANG } 1333ff984e57SWei WANG }; 1334ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1335ff984e57SWei WANG 1336ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1337ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1338ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1339ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1340ff984e57SWei WANG .suspend = rtsx_pci_sdmmc_suspend, 1341ff984e57SWei WANG .resume = rtsx_pci_sdmmc_resume, 1342ff984e57SWei WANG .driver = { 1343ff984e57SWei WANG .owner = THIS_MODULE, 1344ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1345ff984e57SWei WANG }, 1346ff984e57SWei WANG }; 1347ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1348ff984e57SWei WANG 1349ff984e57SWei WANG MODULE_LICENSE("GPL"); 1350ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1351ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1352