1ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 2ff984e57SWei WANG * 362282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4ff984e57SWei WANG * 5ff984e57SWei WANG * This program is free software; you can redistribute it and/or modify it 6ff984e57SWei WANG * under the terms of the GNU General Public License as published by the 7ff984e57SWei WANG * Free Software Foundation; either version 2, or (at your option) any 8ff984e57SWei WANG * later version. 9ff984e57SWei WANG * 10ff984e57SWei WANG * This program is distributed in the hope that it will be useful, but 11ff984e57SWei WANG * WITHOUT ANY WARRANTY; without even the implied warranty of 12ff984e57SWei WANG * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13ff984e57SWei WANG * General Public License for more details. 14ff984e57SWei WANG * 15ff984e57SWei WANG * You should have received a copy of the GNU General Public License along 16ff984e57SWei WANG * with this program; if not, see <http://www.gnu.org/licenses/>. 17ff984e57SWei WANG * 18ff984e57SWei WANG * Author: 19ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 20ff984e57SWei WANG */ 21ff984e57SWei WANG 22ff984e57SWei WANG #include <linux/module.h> 23433e075cSWei WANG #include <linux/slab.h> 24ff984e57SWei WANG #include <linux/highmem.h> 25ff984e57SWei WANG #include <linux/delay.h> 26ff984e57SWei WANG #include <linux/platform_device.h> 276291e715SMicky Ching #include <linux/workqueue.h> 28ff984e57SWei WANG #include <linux/mmc/host.h> 29ff984e57SWei WANG #include <linux/mmc/mmc.h> 30ff984e57SWei WANG #include <linux/mmc/sd.h> 31ff984e57SWei WANG #include <linux/mmc/card.h> 32ff984e57SWei WANG #include <linux/mfd/rtsx_pci.h> 33ff984e57SWei WANG #include <asm/unaligned.h> 34ff984e57SWei WANG 35ff984e57SWei WANG struct realtek_pci_sdmmc { 36ff984e57SWei WANG struct platform_device *pdev; 37ff984e57SWei WANG struct rtsx_pcr *pcr; 38ff984e57SWei WANG struct mmc_host *mmc; 39ff984e57SWei WANG struct mmc_request *mrq; 406291e715SMicky Ching struct workqueue_struct *workq; 416291e715SMicky Ching #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" 42ff984e57SWei WANG 436291e715SMicky Ching struct work_struct work; 4498fcc576SMicky Ching struct mutex host_mutex; 45ff984e57SWei WANG 46ff984e57SWei WANG u8 ssc_depth; 47ff984e57SWei WANG unsigned int clock; 48ff984e57SWei WANG bool vpclk; 49ff984e57SWei WANG bool double_clk; 50ff984e57SWei WANG bool eject; 51ff984e57SWei WANG bool initial_mode; 52d88691beSWei WANG int power_state; 53d88691beSWei WANG #define SDMMC_POWER_ON 1 54d88691beSWei WANG #define SDMMC_POWER_OFF 0 556291e715SMicky Ching 566291e715SMicky Ching unsigned int sg_count; 576291e715SMicky Ching s32 cookie; 586291e715SMicky Ching unsigned int cookie_sg_count; 596291e715SMicky Ching bool using_cookie; 60ff984e57SWei WANG }; 61ff984e57SWei WANG 62ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 63ff984e57SWei WANG { 64ff984e57SWei WANG return &(host->pdev->dev); 65ff984e57SWei WANG } 66ff984e57SWei WANG 67ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 68ff984e57SWei WANG { 69ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 70ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 71ff984e57SWei WANG } 72ff984e57SWei WANG 73ff984e57SWei WANG #ifdef DEBUG 74ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 75ff984e57SWei WANG { 76ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 77ff984e57SWei WANG u16 i; 78ff984e57SWei WANG u8 *ptr; 79ff984e57SWei WANG 80ff984e57SWei WANG /* Print SD host internal registers */ 81ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 82ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 83ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 84ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 85ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 86ff984e57SWei WANG rtsx_pci_send_cmd(pcr, 100); 87ff984e57SWei WANG 88ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr); 89ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 90ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 91ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 92ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 93ff984e57SWei WANG } 94ff984e57SWei WANG #else 95ff984e57SWei WANG #define sd_print_debug_regs(host) 96ff984e57SWei WANG #endif /* DEBUG */ 97ff984e57SWei WANG 986291e715SMicky Ching /* 996291e715SMicky Ching * sd_pre_dma_transfer - do dma_map_sg() or using cookie 1006291e715SMicky Ching * 1016291e715SMicky Ching * @pre: if called in pre_req() 1026291e715SMicky Ching * return: 1036291e715SMicky Ching * 0 - do dma_map_sg() 1046291e715SMicky Ching * 1 - using cookie 1056291e715SMicky Ching */ 1066291e715SMicky Ching static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, 1076291e715SMicky Ching struct mmc_data *data, bool pre) 1086291e715SMicky Ching { 1096291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 1106291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 1116291e715SMicky Ching int count = 0; 1126291e715SMicky Ching int using_cookie = 0; 1136291e715SMicky Ching 1146291e715SMicky Ching if (!pre && data->host_cookie && data->host_cookie != host->cookie) { 1156291e715SMicky Ching dev_err(sdmmc_dev(host), 1166291e715SMicky Ching "error: data->host_cookie = %d, host->cookie = %d\n", 1176291e715SMicky Ching data->host_cookie, host->cookie); 1186291e715SMicky Ching data->host_cookie = 0; 1196291e715SMicky Ching } 1206291e715SMicky Ching 1216291e715SMicky Ching if (pre || data->host_cookie != host->cookie) { 1226291e715SMicky Ching count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); 1236291e715SMicky Ching } else { 1246291e715SMicky Ching count = host->cookie_sg_count; 1256291e715SMicky Ching using_cookie = 1; 1266291e715SMicky Ching } 1276291e715SMicky Ching 1286291e715SMicky Ching if (pre) { 1296291e715SMicky Ching host->cookie_sg_count = count; 1306291e715SMicky Ching if (++host->cookie < 0) 1316291e715SMicky Ching host->cookie = 1; 1326291e715SMicky Ching data->host_cookie = host->cookie; 1336291e715SMicky Ching } else { 1346291e715SMicky Ching host->sg_count = count; 1356291e715SMicky Ching } 1366291e715SMicky Ching 1376291e715SMicky Ching return using_cookie; 1386291e715SMicky Ching } 1396291e715SMicky Ching 1406291e715SMicky Ching static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 1416291e715SMicky Ching bool is_first_req) 1426291e715SMicky Ching { 1436291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1446291e715SMicky Ching struct mmc_data *data = mrq->data; 1456291e715SMicky Ching 1466291e715SMicky Ching if (data->host_cookie) { 1476291e715SMicky Ching dev_err(sdmmc_dev(host), 1486291e715SMicky Ching "error: reset data->host_cookie = %d\n", 1496291e715SMicky Ching data->host_cookie); 1506291e715SMicky Ching data->host_cookie = 0; 1516291e715SMicky Ching } 1526291e715SMicky Ching 1536291e715SMicky Ching sd_pre_dma_transfer(host, data, true); 1546291e715SMicky Ching dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); 1556291e715SMicky Ching } 1566291e715SMicky Ching 1576291e715SMicky Ching static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1586291e715SMicky Ching int err) 1596291e715SMicky Ching { 1606291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1616291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 1626291e715SMicky Ching struct mmc_data *data = mrq->data; 1636291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 1646291e715SMicky Ching 1656291e715SMicky Ching rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); 1666291e715SMicky Ching data->host_cookie = 0; 1676291e715SMicky Ching } 1686291e715SMicky Ching 169ff984e57SWei WANG static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 170ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 171ff984e57SWei WANG { 172ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 173ff984e57SWei WANG int err, i; 174ff984e57SWei WANG u8 trans_mode; 175ff984e57SWei WANG 176ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40); 177ff984e57SWei WANG 178ff984e57SWei WANG if (!buf) 179ff984e57SWei WANG buf_len = 0; 180ff984e57SWei WANG 181ff984e57SWei WANG if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK) 182ff984e57SWei WANG trans_mode = SD_TM_AUTO_TUNING; 183ff984e57SWei WANG else 184ff984e57SWei WANG trans_mode = SD_TM_NORMAL_READ; 185ff984e57SWei WANG 186ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 187ff984e57SWei WANG 188ff984e57SWei WANG for (i = 0; i < 5; i++) 189ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]); 190ff984e57SWei WANG 191ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 192ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 193ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 194ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 195ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 196ff984e57SWei WANG 197ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 198ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 199ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 200ff984e57SWei WANG if (trans_mode != SD_TM_AUTO_TUNING) 201ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 202ff984e57SWei WANG CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 203ff984e57SWei WANG 204ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 205ff984e57SWei WANG 0xFF, trans_mode | SD_TRANSFER_START); 206ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 207ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 208ff984e57SWei WANG 209ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 210ff984e57SWei WANG if (err < 0) { 211ff984e57SWei WANG sd_print_debug_regs(host); 212ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 213ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 214ff984e57SWei WANG return err; 215ff984e57SWei WANG } 216ff984e57SWei WANG 217ff984e57SWei WANG if (buf && buf_len) { 218ff984e57SWei WANG err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 219ff984e57SWei WANG if (err < 0) { 220ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 221ff984e57SWei WANG "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 222ff984e57SWei WANG return err; 223ff984e57SWei WANG } 224ff984e57SWei WANG } 225ff984e57SWei WANG 226ff984e57SWei WANG return 0; 227ff984e57SWei WANG } 228ff984e57SWei WANG 229ff984e57SWei WANG static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 230ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 231ff984e57SWei WANG { 232ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 233ff984e57SWei WANG int err, i; 234ff984e57SWei WANG u8 trans_mode; 235ff984e57SWei WANG 236ff984e57SWei WANG if (!buf) 237ff984e57SWei WANG buf_len = 0; 238ff984e57SWei WANG 239ff984e57SWei WANG if (buf && buf_len) { 240ff984e57SWei WANG err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 241ff984e57SWei WANG if (err < 0) { 242ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 243ff984e57SWei WANG "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 244ff984e57SWei WANG return err; 245ff984e57SWei WANG } 246ff984e57SWei WANG } 247ff984e57SWei WANG 248ff984e57SWei WANG trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3; 249ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 250ff984e57SWei WANG 251ff984e57SWei WANG if (cmd) { 252ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__, 253ff984e57SWei WANG cmd[0] - 0x40); 254ff984e57SWei WANG 255ff984e57SWei WANG for (i = 0; i < 5; i++) 256ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 257ff984e57SWei WANG SD_CMD0 + i, 0xFF, cmd[i]); 258ff984e57SWei WANG } 259ff984e57SWei WANG 260ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 261ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 262ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 263ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 264ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 265ff984e57SWei WANG 266ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 267ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 268ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 269ff984e57SWei WANG 270ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 271ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 272ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 273ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 274ff984e57SWei WANG 275ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 276ff984e57SWei WANG if (err < 0) { 277ff984e57SWei WANG sd_print_debug_regs(host); 278ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 279ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 280ff984e57SWei WANG return err; 281ff984e57SWei WANG } 282ff984e57SWei WANG 283ff984e57SWei WANG return 0; 284ff984e57SWei WANG } 285ff984e57SWei WANG 28698fcc576SMicky Ching static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 28798fcc576SMicky Ching struct mmc_command *cmd) 288ff984e57SWei WANG { 289ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 290ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 291ff984e57SWei WANG u32 arg = cmd->arg; 292ff984e57SWei WANG int err = 0; 293ff984e57SWei WANG int timeout = 100; 294ff984e57SWei WANG int i; 29598fcc576SMicky Ching u8 *ptr; 29698fcc576SMicky Ching int stat_idx = 0; 297ff984e57SWei WANG u8 rsp_type; 298ff984e57SWei WANG int rsp_len = 5; 29998fcc576SMicky Ching bool clock_toggled = false; 300ff984e57SWei WANG 301ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 302ff984e57SWei WANG __func__, cmd_idx, arg); 303ff984e57SWei WANG 304ff984e57SWei WANG /* Response type: 305ff984e57SWei WANG * R0 306ff984e57SWei WANG * R1, R5, R6, R7 307ff984e57SWei WANG * R1b 308ff984e57SWei WANG * R2 309ff984e57SWei WANG * R3, R4 310ff984e57SWei WANG */ 311ff984e57SWei WANG switch (mmc_resp_type(cmd)) { 312ff984e57SWei WANG case MMC_RSP_NONE: 313ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R0; 314ff984e57SWei WANG rsp_len = 0; 315ff984e57SWei WANG break; 316ff984e57SWei WANG case MMC_RSP_R1: 317ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1; 318ff984e57SWei WANG break; 3195027251eSMicky Ching case MMC_RSP_R1 & ~MMC_RSP_CRC: 3205027251eSMicky Ching rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; 3215027251eSMicky Ching break; 322ff984e57SWei WANG case MMC_RSP_R1B: 323ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1b; 324ff984e57SWei WANG break; 325ff984e57SWei WANG case MMC_RSP_R2: 326ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R2; 327ff984e57SWei WANG rsp_len = 16; 328ff984e57SWei WANG break; 329ff984e57SWei WANG case MMC_RSP_R3: 330ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R3; 331ff984e57SWei WANG break; 332ff984e57SWei WANG default: 333ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n"); 334ff984e57SWei WANG err = -EINVAL; 335ff984e57SWei WANG goto out; 336ff984e57SWei WANG } 337ff984e57SWei WANG 338ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 339ff984e57SWei WANG timeout = 3000; 340ff984e57SWei WANG 341ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 342ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 343ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 344ff984e57SWei WANG if (err < 0) 345ff984e57SWei WANG goto out; 34698fcc576SMicky Ching 34798fcc576SMicky Ching clock_toggled = true; 348ff984e57SWei WANG } 349ff984e57SWei WANG 350ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 351ff984e57SWei WANG 352ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx); 353ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24)); 354ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16)); 355ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8)); 356ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg); 357ff984e57SWei WANG 358ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 359ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 360ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 361ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 362ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 363ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 364ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 365ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 366ff984e57SWei WANG 367ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 368ff984e57SWei WANG /* Read data from ping-pong buffer */ 369ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 370ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 37198fcc576SMicky Ching stat_idx = 16; 372ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 373ff984e57SWei WANG /* Read data from SD_CMDx registers */ 374ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 375ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 37698fcc576SMicky Ching stat_idx = 5; 377ff984e57SWei WANG } 378ff984e57SWei WANG 379ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 380ff984e57SWei WANG 38198fcc576SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 38298fcc576SMicky Ching if (err < 0) { 38398fcc576SMicky Ching sd_print_debug_regs(host); 38498fcc576SMicky Ching sd_clear_error(host); 38598fcc576SMicky Ching dev_dbg(sdmmc_dev(host), 38698fcc576SMicky Ching "rtsx_pci_send_cmd error (err = %d)\n", err); 387ff984e57SWei WANG goto out; 388ff984e57SWei WANG } 389ff984e57SWei WANG 390ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 391ff984e57SWei WANG err = 0; 392ff984e57SWei WANG goto out; 393ff984e57SWei WANG } 394ff984e57SWei WANG 395ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 396ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 397ff984e57SWei WANG 398ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 399ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 400ff984e57SWei WANG err = -EILSEQ; 401ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 402ff984e57SWei WANG goto out; 403ff984e57SWei WANG } 404ff984e57SWei WANG 405ff984e57SWei WANG /* Check CRC7 */ 406ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 407ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 408ff984e57SWei WANG err = -EILSEQ; 409ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 410ff984e57SWei WANG goto out; 411ff984e57SWei WANG } 412ff984e57SWei WANG } 413ff984e57SWei WANG 414ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 415d1419d50SRoger Tseng /* 416d1419d50SRoger Tseng * The controller offloads the last byte {CRC-7, end bit 1'b1} 417d1419d50SRoger Tseng * of response type R2. Assign dummy CRC, 0, and end bit to the 418d1419d50SRoger Tseng * byte(ptr[16], goes into the LSB of resp[3] later). 419d1419d50SRoger Tseng */ 420d1419d50SRoger Tseng ptr[16] = 1; 421d1419d50SRoger Tseng 422ff984e57SWei WANG for (i = 0; i < 4; i++) { 423ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 424ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 425ff984e57SWei WANG i, cmd->resp[i]); 426ff984e57SWei WANG } 427ff984e57SWei WANG } else { 428ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 429ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 430ff984e57SWei WANG cmd->resp[0]); 431ff984e57SWei WANG } 432ff984e57SWei WANG 433ff984e57SWei WANG out: 434ff984e57SWei WANG cmd->error = err; 4351b8055b4SWei WANG 43698fcc576SMicky Ching if (err && clock_toggled) 43798fcc576SMicky Ching rtsx_pci_write_register(pcr, SD_BUS_STAT, 43898fcc576SMicky Ching SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 439ff984e57SWei WANG } 440ff984e57SWei WANG 44198fcc576SMicky Ching static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 442ff984e57SWei WANG { 443ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 444ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 445ff984e57SWei WANG struct mmc_card *card = mmc->card; 446ff984e57SWei WANG struct mmc_data *data = mrq->data; 44771ef1ea4SJackey Shen int uhs = mmc_card_uhs(card); 44898fcc576SMicky Ching int read = (data->flags & MMC_DATA_READ) ? 1 : 0; 449ff984e57SWei WANG u8 cfg2, trans_mode; 450ff984e57SWei WANG int err; 451ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 452ff984e57SWei WANG 453ff984e57SWei WANG if (read) { 454ff984e57SWei WANG cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 455ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0; 456ff984e57SWei WANG trans_mode = SD_TM_AUTO_READ_3; 457ff984e57SWei WANG } else { 458ff984e57SWei WANG cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 459ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 460ff984e57SWei WANG trans_mode = SD_TM_AUTO_WRITE_3; 461ff984e57SWei WANG } 462ff984e57SWei WANG 463ff984e57SWei WANG if (!uhs) 464ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 465ff984e57SWei WANG 466ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 467ff984e57SWei WANG 468ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00); 469ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02); 470ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 471ff984e57SWei WANG 0xFF, (u8)data->blocks); 472ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 473ff984e57SWei WANG 0xFF, (u8)(data->blocks >> 8)); 474ff984e57SWei WANG 475ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 476ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 477ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 478ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 479ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 480ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 481ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 482ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 483ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 484ff984e57SWei WANG if (read) { 485ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 486ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 487ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 488ff984e57SWei WANG } else { 489ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 490ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 491ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 492ff984e57SWei WANG } 493ff984e57SWei WANG 494ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 495ff984e57SWei WANG 0x01, RING_BUFFER); 496ff984e57SWei WANG 49738d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 498ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 499ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 500ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 501ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 502ff984e57SWei WANG 503ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 504ff984e57SWei WANG 5056291e715SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, read, 10000); 506ff984e57SWei WANG if (err < 0) { 50798fcc576SMicky Ching sd_clear_error(host); 50898fcc576SMicky Ching return err; 509c42deffdSMicky Ching } 51098fcc576SMicky Ching 511c42deffdSMicky Ching return 0; 512ff984e57SWei WANG } 513ff984e57SWei WANG 514ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 515ff984e57SWei WANG { 516ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 517ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 518ff984e57SWei WANG } 519ff984e57SWei WANG 520ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 521ff984e57SWei WANG { 522ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 523ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 524ff984e57SWei WANG } 525ff984e57SWei WANG 526ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 527ff984e57SWei WANG struct mmc_request *mrq) 528ff984e57SWei WANG { 529ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 530ff984e57SWei WANG struct mmc_data *data = mrq->data; 531ff984e57SWei WANG u8 _cmd[5], *buf; 532ff984e57SWei WANG 533ff984e57SWei WANG _cmd[0] = 0x40 | (u8)cmd->opcode; 534ff984e57SWei WANG put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1])); 535ff984e57SWei WANG 536ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 537ff984e57SWei WANG if (!buf) { 538ff984e57SWei WANG cmd->error = -ENOMEM; 539ff984e57SWei WANG return; 540ff984e57SWei WANG } 541ff984e57SWei WANG 542ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 543ff984e57SWei WANG if (host->initial_mode) 544ff984e57SWei WANG sd_disable_initial_mode(host); 545ff984e57SWei WANG 546ff984e57SWei WANG cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf, 547ff984e57SWei WANG data->blksz, 200); 548ff984e57SWei WANG 549ff984e57SWei WANG if (host->initial_mode) 550ff984e57SWei WANG sd_enable_initial_mode(host); 551ff984e57SWei WANG 552ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 553ff984e57SWei WANG } else { 554ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 555ff984e57SWei WANG 556ff984e57SWei WANG cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf, 557ff984e57SWei WANG data->blksz, 200); 558ff984e57SWei WANG } 559ff984e57SWei WANG 560ff984e57SWei WANG kfree(buf); 561ff984e57SWei WANG } 562ff984e57SWei WANG 56384d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, 56484d72f9cSWei WANG u8 sample_point, bool rx) 565ff984e57SWei WANG { 566ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 567ff984e57SWei WANG int err; 568ff984e57SWei WANG 56984d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 57084d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point); 571ff984e57SWei WANG 572ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 573ff984e57SWei WANG 574ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 57584d72f9cSWei WANG if (rx) 57684d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 57784d72f9cSWei WANG SD_VPRX_CTL, 0x1F, sample_point); 57884d72f9cSWei WANG else 57984d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 58084d72f9cSWei WANG SD_VPTX_CTL, 0x1F, sample_point); 581ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); 582ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 583ff984e57SWei WANG PHASE_NOT_RESET, PHASE_NOT_RESET); 584ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); 585ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 586ff984e57SWei WANG 587ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 588ff984e57SWei WANG if (err < 0) 589ff984e57SWei WANG return err; 590ff984e57SWei WANG 591ff984e57SWei WANG return 0; 592ff984e57SWei WANG } 593ff984e57SWei WANG 594abcc6b29SMicky Ching static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 595abcc6b29SMicky Ching { 596abcc6b29SMicky Ching bit %= RTSX_PHASE_MAX; 597abcc6b29SMicky Ching return phase_map & (1 << bit); 598abcc6b29SMicky Ching } 599abcc6b29SMicky Ching 600abcc6b29SMicky Ching static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 601abcc6b29SMicky Ching { 602abcc6b29SMicky Ching int i; 603abcc6b29SMicky Ching 604abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 605abcc6b29SMicky Ching if (test_phase_bit(phase_map, start_bit + i) == 0) 606abcc6b29SMicky Ching return i; 607abcc6b29SMicky Ching } 608abcc6b29SMicky Ching return RTSX_PHASE_MAX; 609abcc6b29SMicky Ching } 610abcc6b29SMicky Ching 611ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 612ff984e57SWei WANG { 613abcc6b29SMicky Ching int start = 0, len = 0; 614abcc6b29SMicky Ching int start_final = 0, len_final = 0; 615ff984e57SWei WANG u8 final_phase = 0xFF; 616ff984e57SWei WANG 617abcc6b29SMicky Ching if (phase_map == 0) { 618abcc6b29SMicky Ching dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 619abcc6b29SMicky Ching return final_phase; 620ff984e57SWei WANG } 621ff984e57SWei WANG 622abcc6b29SMicky Ching while (start < RTSX_PHASE_MAX) { 623abcc6b29SMicky Ching len = sd_get_phase_len(phase_map, start); 624abcc6b29SMicky Ching if (len_final < len) { 625abcc6b29SMicky Ching start_final = start; 626abcc6b29SMicky Ching len_final = len; 627abcc6b29SMicky Ching } 628abcc6b29SMicky Ching start += len ? len : 1; 629ff984e57SWei WANG } 630ff984e57SWei WANG 631abcc6b29SMicky Ching final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 632abcc6b29SMicky Ching dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 633abcc6b29SMicky Ching phase_map, len_final, final_phase); 634ff984e57SWei WANG 635ff984e57SWei WANG return final_phase; 636ff984e57SWei WANG } 637ff984e57SWei WANG 638ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 639ff984e57SWei WANG { 640ff984e57SWei WANG int err, i; 641ff984e57SWei WANG u8 val = 0; 642ff984e57SWei WANG 643ff984e57SWei WANG for (i = 0; i < 100; i++) { 644ff984e57SWei WANG err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 645ff984e57SWei WANG if (val & SD_DATA_IDLE) 646ff984e57SWei WANG return; 647ff984e57SWei WANG 648ff984e57SWei WANG udelay(100); 649ff984e57SWei WANG } 650ff984e57SWei WANG } 651ff984e57SWei WANG 652ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 653ff984e57SWei WANG u8 opcode, u8 sample_point) 654ff984e57SWei WANG { 655ff984e57SWei WANG int err; 656ff984e57SWei WANG u8 cmd[5] = {0}; 657ff984e57SWei WANG 65884d72f9cSWei WANG err = sd_change_phase(host, sample_point, true); 659ff984e57SWei WANG if (err < 0) 660ff984e57SWei WANG return err; 661ff984e57SWei WANG 662ff984e57SWei WANG cmd[0] = 0x40 | opcode; 663ff984e57SWei WANG err = sd_read_data(host, cmd, 0x40, NULL, 0, 100); 664ff984e57SWei WANG if (err < 0) { 665ff984e57SWei WANG /* Wait till SD DATA IDLE */ 666ff984e57SWei WANG sd_wait_data_idle(host); 667ff984e57SWei WANG sd_clear_error(host); 668ff984e57SWei WANG return err; 669ff984e57SWei WANG } 670ff984e57SWei WANG 671ff984e57SWei WANG return 0; 672ff984e57SWei WANG } 673ff984e57SWei WANG 674ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 675ff984e57SWei WANG u8 opcode, u32 *phase_map) 676ff984e57SWei WANG { 677ff984e57SWei WANG int err, i; 678ff984e57SWei WANG u32 raw_phase_map = 0; 679ff984e57SWei WANG 680abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 681ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 682ff984e57SWei WANG if (err == 0) 683ff984e57SWei WANG raw_phase_map |= 1 << i; 684ff984e57SWei WANG } 685ff984e57SWei WANG 686ff984e57SWei WANG if (phase_map) 687ff984e57SWei WANG *phase_map = raw_phase_map; 688ff984e57SWei WANG 689ff984e57SWei WANG return 0; 690ff984e57SWei WANG } 691ff984e57SWei WANG 692ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 693ff984e57SWei WANG { 694ff984e57SWei WANG int err, i; 695ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 696ff984e57SWei WANG u8 final_phase; 697ff984e57SWei WANG 698ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 699ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 700ff984e57SWei WANG if (err < 0) 701ff984e57SWei WANG return err; 702ff984e57SWei WANG 703ff984e57SWei WANG if (raw_phase_map[i] == 0) 704ff984e57SWei WANG break; 705ff984e57SWei WANG } 706ff984e57SWei WANG 707ff984e57SWei WANG phase_map = 0xFFFFFFFF; 708ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 709ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 710ff984e57SWei WANG i, raw_phase_map[i]); 711ff984e57SWei WANG phase_map &= raw_phase_map[i]; 712ff984e57SWei WANG } 713ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 714ff984e57SWei WANG 715ff984e57SWei WANG if (phase_map) { 716ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 717ff984e57SWei WANG if (final_phase == 0xFF) 718ff984e57SWei WANG return -EINVAL; 719ff984e57SWei WANG 72084d72f9cSWei WANG err = sd_change_phase(host, final_phase, true); 721ff984e57SWei WANG if (err < 0) 722ff984e57SWei WANG return err; 723ff984e57SWei WANG } else { 724ff984e57SWei WANG return -EINVAL; 725ff984e57SWei WANG } 726ff984e57SWei WANG 727ff984e57SWei WANG return 0; 728ff984e57SWei WANG } 729ff984e57SWei WANG 7306291e715SMicky Ching static inline int sd_rw_cmd(struct mmc_command *cmd) 731ff984e57SWei WANG { 7326291e715SMicky Ching return mmc_op_multi(cmd->opcode) || 7336291e715SMicky Ching (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 7346291e715SMicky Ching (cmd->opcode == MMC_WRITE_BLOCK); 7356291e715SMicky Ching } 7366291e715SMicky Ching 7376291e715SMicky Ching static void sd_request(struct work_struct *work) 7386291e715SMicky Ching { 7396291e715SMicky Ching struct realtek_pci_sdmmc *host = container_of(work, 7406291e715SMicky Ching struct realtek_pci_sdmmc, work); 741ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 7426291e715SMicky Ching 7436291e715SMicky Ching struct mmc_host *mmc = host->mmc; 7446291e715SMicky Ching struct mmc_request *mrq = host->mrq; 745ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 746ff984e57SWei WANG struct mmc_data *data = mrq->data; 7476291e715SMicky Ching 748ff984e57SWei WANG unsigned int data_size = 0; 749c3481955SWei WANG int err; 750ff984e57SWei WANG 751ff984e57SWei WANG if (host->eject) { 752ff984e57SWei WANG cmd->error = -ENOMEDIUM; 753ff984e57SWei WANG goto finish; 754ff984e57SWei WANG } 755ff984e57SWei WANG 756c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 757c3481955SWei WANG if (err) { 758c3481955SWei WANG cmd->error = err; 759c3481955SWei WANG goto finish; 760c3481955SWei WANG } 761c3481955SWei WANG 76298fcc576SMicky Ching mutex_lock(&pcr->pcr_mutex); 76398fcc576SMicky Ching 764ff984e57SWei WANG rtsx_pci_start_run(pcr); 765ff984e57SWei WANG 766ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 767ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 768ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 769ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 770ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 771ff984e57SWei WANG 77298fcc576SMicky Ching mutex_lock(&host->host_mutex); 77398fcc576SMicky Ching host->mrq = mrq; 77498fcc576SMicky Ching mutex_unlock(&host->host_mutex); 77598fcc576SMicky Ching 776ff984e57SWei WANG if (mrq->data) 777ff984e57SWei WANG data_size = data->blocks * data->blksz; 778ff984e57SWei WANG 7796291e715SMicky Ching if (!data_size || sd_rw_cmd(cmd)) { 78098fcc576SMicky Ching sd_send_cmd_get_rsp(host, cmd); 781ff984e57SWei WANG 78298fcc576SMicky Ching if (!cmd->error && data_size) { 78398fcc576SMicky Ching sd_rw_multi(host, mrq); 7846291e715SMicky Ching if (!host->using_cookie) 7856291e715SMicky Ching sdmmc_post_req(host->mmc, host->mrq, 0); 78698fcc576SMicky Ching 78798fcc576SMicky Ching if (mmc_op_multi(cmd->opcode) && mrq->stop) 78898fcc576SMicky Ching sd_send_cmd_get_rsp(host, mrq->stop); 789ff984e57SWei WANG } 79098fcc576SMicky Ching } else { 79198fcc576SMicky Ching sd_normal_rw(host, mrq); 79298fcc576SMicky Ching } 79398fcc576SMicky Ching 79498fcc576SMicky Ching if (mrq->data) { 79598fcc576SMicky Ching if (cmd->error || data->error) 79698fcc576SMicky Ching data->bytes_xfered = 0; 79798fcc576SMicky Ching else 79898fcc576SMicky Ching data->bytes_xfered = data->blocks * data->blksz; 79998fcc576SMicky Ching } 80098fcc576SMicky Ching 80198fcc576SMicky Ching mutex_unlock(&pcr->pcr_mutex); 802ff984e57SWei WANG 803ff984e57SWei WANG finish: 80498fcc576SMicky Ching if (cmd->error) 80598fcc576SMicky Ching dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error); 80698fcc576SMicky Ching 80798fcc576SMicky Ching mutex_lock(&host->host_mutex); 80898fcc576SMicky Ching host->mrq = NULL; 80998fcc576SMicky Ching mutex_unlock(&host->host_mutex); 81098fcc576SMicky Ching 81198fcc576SMicky Ching mmc_request_done(mmc, mrq); 812ff984e57SWei WANG } 813ff984e57SWei WANG 8146291e715SMicky Ching static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 8156291e715SMicky Ching { 8166291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 8176291e715SMicky Ching struct mmc_data *data = mrq->data; 8186291e715SMicky Ching 8196291e715SMicky Ching mutex_lock(&host->host_mutex); 8206291e715SMicky Ching host->mrq = mrq; 8216291e715SMicky Ching mutex_unlock(&host->host_mutex); 8226291e715SMicky Ching 8236291e715SMicky Ching if (sd_rw_cmd(mrq->cmd)) 8246291e715SMicky Ching host->using_cookie = sd_pre_dma_transfer(host, data, false); 8256291e715SMicky Ching 8266291e715SMicky Ching queue_work(host->workq, &host->work); 8276291e715SMicky Ching } 8286291e715SMicky Ching 829ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 830ff984e57SWei WANG unsigned char bus_width) 831ff984e57SWei WANG { 832ff984e57SWei WANG int err = 0; 833ff984e57SWei WANG u8 width[] = { 834ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 835ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 836ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 837ff984e57SWei WANG }; 838ff984e57SWei WANG 839ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 840ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 841ff984e57SWei WANG 0x03, width[bus_width]); 842ff984e57SWei WANG 843ff984e57SWei WANG return err; 844ff984e57SWei WANG } 845ff984e57SWei WANG 846ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 847ff984e57SWei WANG { 848ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 849ff984e57SWei WANG int err; 850ff984e57SWei WANG 851d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 852d88691beSWei WANG return 0; 853d88691beSWei WANG 854ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 855ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 856ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 857ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 858ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 859ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 860ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 861ff984e57SWei WANG if (err < 0) 862ff984e57SWei WANG return err; 863ff984e57SWei WANG 864ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 865ff984e57SWei WANG if (err < 0) 866ff984e57SWei WANG return err; 867ff984e57SWei WANG 868ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 869ff984e57SWei WANG if (err < 0) 870ff984e57SWei WANG return err; 871ff984e57SWei WANG 872ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 873ff984e57SWei WANG if (err < 0) 874ff984e57SWei WANG return err; 875ff984e57SWei WANG 876d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 877ff984e57SWei WANG return 0; 878ff984e57SWei WANG } 879ff984e57SWei WANG 880ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 881ff984e57SWei WANG { 882ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 883ff984e57SWei WANG int err; 884ff984e57SWei WANG 885d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 886d88691beSWei WANG 887ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 888ff984e57SWei WANG 889ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 890ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 891ff984e57SWei WANG 892ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 893ff984e57SWei WANG if (err < 0) 894ff984e57SWei WANG return err; 895ff984e57SWei WANG 896ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 897ff984e57SWei WANG if (err < 0) 898ff984e57SWei WANG return err; 899ff984e57SWei WANG 900ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 901ff984e57SWei WANG } 902ff984e57SWei WANG 903ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 904ff984e57SWei WANG unsigned char power_mode) 905ff984e57SWei WANG { 906ff984e57SWei WANG int err; 907ff984e57SWei WANG 908ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 909ff984e57SWei WANG err = sd_power_off(host); 910ff984e57SWei WANG else 911ff984e57SWei WANG err = sd_power_on(host); 912ff984e57SWei WANG 913ff984e57SWei WANG return err; 914ff984e57SWei WANG } 915ff984e57SWei WANG 91684d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 917ff984e57SWei WANG { 918ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 919ff984e57SWei WANG int err = 0; 920ff984e57SWei WANG 921ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 922ff984e57SWei WANG 923ff984e57SWei WANG switch (timing) { 924ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 925ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 926ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 927ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 928ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 929ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 930ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 931ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 932ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 933ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 934ff984e57SWei WANG break; 935ff984e57SWei WANG 9361a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 937ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 938ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 939ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 940ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 941ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 942ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 943ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 944ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 945ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 946ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 947ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 948ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 949ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 950ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 951ff984e57SWei WANG break; 952ff984e57SWei WANG 953ff984e57SWei WANG case MMC_TIMING_MMC_HS: 954ff984e57SWei WANG case MMC_TIMING_SD_HS: 955ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 956ff984e57SWei WANG 0x0C, SD_20_MODE); 957ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 958ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 959ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 960ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 961ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 962ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 963ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 964ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 965ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 966ff984e57SWei WANG break; 967ff984e57SWei WANG 968ff984e57SWei WANG default: 969ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 970ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 971ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 972ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 973ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 974ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 975ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 976ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 977ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 978ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 979ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 980ff984e57SWei WANG break; 981ff984e57SWei WANG } 982ff984e57SWei WANG 983ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 984ff984e57SWei WANG 985ff984e57SWei WANG return err; 986ff984e57SWei WANG } 987ff984e57SWei WANG 988ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 989ff984e57SWei WANG { 990ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 991ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 992ff984e57SWei WANG 993ff984e57SWei WANG if (host->eject) 994ff984e57SWei WANG return; 995ff984e57SWei WANG 996c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 997c3481955SWei WANG return; 998c3481955SWei WANG 999ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1000ff984e57SWei WANG 1001ff984e57SWei WANG rtsx_pci_start_run(pcr); 1002ff984e57SWei WANG 1003ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 1004ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 100584d72f9cSWei WANG sd_set_timing(host, ios->timing); 1006ff984e57SWei WANG 1007ff984e57SWei WANG host->vpclk = false; 1008ff984e57SWei WANG host->double_clk = true; 1009ff984e57SWei WANG 1010ff984e57SWei WANG switch (ios->timing) { 1011ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1012ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1013ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 1014ff984e57SWei WANG host->vpclk = true; 1015ff984e57SWei WANG host->double_clk = false; 1016ff984e57SWei WANG break; 10171a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 1018ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1019ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 1020ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 1021ff984e57SWei WANG break; 1022ff984e57SWei WANG default: 1023ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 1024ff984e57SWei WANG break; 1025ff984e57SWei WANG } 1026ff984e57SWei WANG 1027ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 1028ff984e57SWei WANG 1029ff984e57SWei WANG host->clock = ios->clock; 1030ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 1031ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 1032ff984e57SWei WANG 1033ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1034ff984e57SWei WANG } 1035ff984e57SWei WANG 1036ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 1037ff984e57SWei WANG { 1038ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1039ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1040ff984e57SWei WANG int ro = 0; 1041ff984e57SWei WANG u32 val; 1042ff984e57SWei WANG 1043ff984e57SWei WANG if (host->eject) 1044ff984e57SWei WANG return -ENOMEDIUM; 1045ff984e57SWei WANG 1046ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1047ff984e57SWei WANG 1048ff984e57SWei WANG rtsx_pci_start_run(pcr); 1049ff984e57SWei WANG 1050ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 1051ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 1052ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1053ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 1054ff984e57SWei WANG ro = 1; 1055ff984e57SWei WANG 1056ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1057ff984e57SWei WANG 1058ff984e57SWei WANG return ro; 1059ff984e57SWei WANG } 1060ff984e57SWei WANG 1061ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 1062ff984e57SWei WANG { 1063ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1064ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1065ff984e57SWei WANG int cd = 0; 1066ff984e57SWei WANG u32 val; 1067ff984e57SWei WANG 1068ff984e57SWei WANG if (host->eject) 1069ff984e57SWei WANG return -ENOMEDIUM; 1070ff984e57SWei WANG 1071ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1072ff984e57SWei WANG 1073ff984e57SWei WANG rtsx_pci_start_run(pcr); 1074ff984e57SWei WANG 1075ff984e57SWei WANG /* Check SD card detect */ 1076ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 1077ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1078ff984e57SWei WANG if (val & SD_EXIST) 1079ff984e57SWei WANG cd = 1; 1080ff984e57SWei WANG 1081ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1082ff984e57SWei WANG 1083ff984e57SWei WANG return cd; 1084ff984e57SWei WANG } 1085ff984e57SWei WANG 1086ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1087ff984e57SWei WANG { 1088ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1089ff984e57SWei WANG int err; 1090ff984e57SWei WANG u8 stat; 1091ff984e57SWei WANG 1092ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 1093ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 1094ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 1095ff984e57SWei WANG */ 1096ff984e57SWei WANG mdelay(1); 1097ff984e57SWei WANG 1098ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1099ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 1100ff984e57SWei WANG * abort the voltage switch sequence; 1101ff984e57SWei WANG */ 1102ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1103ff984e57SWei WANG if (err < 0) 1104ff984e57SWei WANG return err; 1105ff984e57SWei WANG 1106ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1107ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 1108ff984e57SWei WANG return -EINVAL; 1109ff984e57SWei WANG 1110ff984e57SWei WANG /* Stop toggle SD clock */ 1111ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1112ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 1113ff984e57SWei WANG if (err < 0) 1114ff984e57SWei WANG return err; 1115ff984e57SWei WANG 1116ff984e57SWei WANG return 0; 1117ff984e57SWei WANG } 1118ff984e57SWei WANG 1119ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1120ff984e57SWei WANG { 1121ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1122ff984e57SWei WANG int err; 1123ff984e57SWei WANG u8 stat, mask, val; 1124ff984e57SWei WANG 1125ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1126ff984e57SWei WANG msleep(50); 1127ff984e57SWei WANG 1128ff984e57SWei WANG /* Toggle SD clock again */ 1129ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1130ff984e57SWei WANG if (err < 0) 1131ff984e57SWei WANG return err; 1132ff984e57SWei WANG 1133ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1134ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1135ff984e57SWei WANG */ 1136ff984e57SWei WANG msleep(20); 1137ff984e57SWei WANG 1138ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1139ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1140ff984e57SWei WANG if (err < 0) 1141ff984e57SWei WANG return err; 1142ff984e57SWei WANG 1143ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1144ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1145ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1146ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1147ff984e57SWei WANG if ((stat & mask) != val) { 1148ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1149ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1150ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1151ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1152ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1153ff984e57SWei WANG return -EINVAL; 1154ff984e57SWei WANG } 1155ff984e57SWei WANG 1156ff984e57SWei WANG return 0; 1157ff984e57SWei WANG } 1158ff984e57SWei WANG 1159ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1160ff984e57SWei WANG { 1161ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1162ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1163ff984e57SWei WANG int err = 0; 1164ff984e57SWei WANG u8 voltage; 1165ff984e57SWei WANG 1166ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1167ff984e57SWei WANG __func__, ios->signal_voltage); 1168ff984e57SWei WANG 1169ff984e57SWei WANG if (host->eject) 1170ff984e57SWei WANG return -ENOMEDIUM; 1171ff984e57SWei WANG 1172c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1173c3481955SWei WANG if (err) 1174c3481955SWei WANG return err; 1175c3481955SWei WANG 1176ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1177ff984e57SWei WANG 1178ff984e57SWei WANG rtsx_pci_start_run(pcr); 1179ff984e57SWei WANG 1180ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1181ef85e736SWei WANG voltage = OUTPUT_3V3; 1182ff984e57SWei WANG else 1183ef85e736SWei WANG voltage = OUTPUT_1V8; 1184ff984e57SWei WANG 1185ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1186ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1187ff984e57SWei WANG if (err < 0) 1188ff984e57SWei WANG goto out; 1189ff984e57SWei WANG } 1190ff984e57SWei WANG 1191ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1192ff984e57SWei WANG if (err < 0) 1193ff984e57SWei WANG goto out; 1194ff984e57SWei WANG 1195ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1196ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1197ff984e57SWei WANG if (err < 0) 1198ff984e57SWei WANG goto out; 1199ff984e57SWei WANG } 1200ff984e57SWei WANG 12011b8055b4SWei WANG out: 1202ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1203ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1204ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1205ff984e57SWei WANG 1206ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1207ff984e57SWei WANG 1208ff984e57SWei WANG return err; 1209ff984e57SWei WANG } 1210ff984e57SWei WANG 1211ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1212ff984e57SWei WANG { 1213ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1214ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1215ff984e57SWei WANG int err = 0; 1216ff984e57SWei WANG 1217ff984e57SWei WANG if (host->eject) 1218ff984e57SWei WANG return -ENOMEDIUM; 1219ff984e57SWei WANG 1220c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1221c3481955SWei WANG if (err) 1222c3481955SWei WANG return err; 1223c3481955SWei WANG 1224ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1225ff984e57SWei WANG 1226ff984e57SWei WANG rtsx_pci_start_run(pcr); 1227ff984e57SWei WANG 122884d72f9cSWei WANG /* Set initial TX phase */ 122984d72f9cSWei WANG switch (mmc->ios.timing) { 123084d72f9cSWei WANG case MMC_TIMING_UHS_SDR104: 123184d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 123284d72f9cSWei WANG break; 1233ff984e57SWei WANG 123484d72f9cSWei WANG case MMC_TIMING_UHS_SDR50: 123584d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 123684d72f9cSWei WANG break; 123784d72f9cSWei WANG 123884d72f9cSWei WANG case MMC_TIMING_UHS_DDR50: 123984d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 124084d72f9cSWei WANG break; 124184d72f9cSWei WANG 124284d72f9cSWei WANG default: 124384d72f9cSWei WANG err = 0; 124484d72f9cSWei WANG } 124584d72f9cSWei WANG 124684d72f9cSWei WANG if (err) 124784d72f9cSWei WANG goto out; 124884d72f9cSWei WANG 124984d72f9cSWei WANG /* Tuning RX phase */ 125084d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 125184d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 125284d72f9cSWei WANG err = sd_tuning_rx(host, opcode); 125384d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 125484d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 125584d72f9cSWei WANG 125684d72f9cSWei WANG out: 1257ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1258ff984e57SWei WANG 1259ff984e57SWei WANG return err; 1260ff984e57SWei WANG } 1261ff984e57SWei WANG 1262ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 12636291e715SMicky Ching .pre_req = sdmmc_pre_req, 12646291e715SMicky Ching .post_req = sdmmc_post_req, 1265ff984e57SWei WANG .request = sdmmc_request, 1266ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1267ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1268ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1269ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1270ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 1271ff984e57SWei WANG }; 1272ff984e57SWei WANG 1273ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1274ff984e57SWei WANG { 1275ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1276ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1277ff984e57SWei WANG 1278ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1279ff984e57SWei WANG 1280ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1281ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1282ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1283ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1284ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1285ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1286ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1287ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1288ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1289ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1290ff984e57SWei WANG } 1291ff984e57SWei WANG 1292ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1293ff984e57SWei WANG { 1294ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1295ff984e57SWei WANG 1296ff984e57SWei WANG mmc->f_min = 250000; 1297ff984e57SWei WANG mmc->f_max = 208000000; 1298ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1299ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1300ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1301ff984e57SWei WANG MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1302ff984e57SWei WANG mmc->max_current_330 = 400; 1303ff984e57SWei WANG mmc->max_current_180 = 800; 1304ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1305ff984e57SWei WANG 1306ff984e57SWei WANG init_extra_caps(host); 1307ff984e57SWei WANG 1308ff984e57SWei WANG mmc->max_segs = 256; 1309ff984e57SWei WANG mmc->max_seg_size = 65536; 1310ff984e57SWei WANG mmc->max_blk_size = 512; 1311ff984e57SWei WANG mmc->max_blk_count = 65535; 1312ff984e57SWei WANG mmc->max_req_size = 524288; 1313ff984e57SWei WANG } 1314ff984e57SWei WANG 1315ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1316ff984e57SWei WANG { 1317ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1318ff984e57SWei WANG 1319ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1320ff984e57SWei WANG } 1321ff984e57SWei WANG 1322ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1323ff984e57SWei WANG { 1324ff984e57SWei WANG struct mmc_host *mmc; 1325ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1326ff984e57SWei WANG struct rtsx_pcr *pcr; 1327ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1328ff984e57SWei WANG 1329ff984e57SWei WANG if (!handle) 1330ff984e57SWei WANG return -ENXIO; 1331ff984e57SWei WANG 1332ff984e57SWei WANG pcr = handle->pcr; 1333ff984e57SWei WANG if (!pcr) 1334ff984e57SWei WANG return -ENXIO; 1335ff984e57SWei WANG 1336ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1337ff984e57SWei WANG 1338ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1339ff984e57SWei WANG if (!mmc) 1340ff984e57SWei WANG return -ENOMEM; 1341ff984e57SWei WANG 1342ff984e57SWei WANG host = mmc_priv(mmc); 13436291e715SMicky Ching host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME); 13446291e715SMicky Ching if (!host->workq) { 13456291e715SMicky Ching mmc_free_host(mmc); 13466291e715SMicky Ching return -ENOMEM; 13476291e715SMicky Ching } 1348ff984e57SWei WANG host->pcr = pcr; 1349ff984e57SWei WANG host->mmc = mmc; 1350ff984e57SWei WANG host->pdev = pdev; 1351d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 13526291e715SMicky Ching INIT_WORK(&host->work, sd_request); 1353ff984e57SWei WANG platform_set_drvdata(pdev, host); 1354ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1355ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1356ff984e57SWei WANG 135798fcc576SMicky Ching mutex_init(&host->host_mutex); 1358ff984e57SWei WANG 1359ff984e57SWei WANG realtek_init_host(host); 1360ff984e57SWei WANG 1361ff984e57SWei WANG mmc_add_host(mmc); 1362ff984e57SWei WANG 1363ff984e57SWei WANG return 0; 1364ff984e57SWei WANG } 1365ff984e57SWei WANG 1366ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1367ff984e57SWei WANG { 1368ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1369ff984e57SWei WANG struct rtsx_pcr *pcr; 1370ff984e57SWei WANG struct mmc_host *mmc; 1371ff984e57SWei WANG 1372ff984e57SWei WANG if (!host) 1373ff984e57SWei WANG return 0; 1374ff984e57SWei WANG 1375ff984e57SWei WANG pcr = host->pcr; 1376ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1377ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1378ff984e57SWei WANG mmc = host->mmc; 1379ff984e57SWei WANG 13806291e715SMicky Ching cancel_work_sync(&host->work); 13816291e715SMicky Ching 138298fcc576SMicky Ching mutex_lock(&host->host_mutex); 1383ff984e57SWei WANG if (host->mrq) { 1384ff984e57SWei WANG dev_dbg(&(pdev->dev), 1385ff984e57SWei WANG "%s: Controller removed during transfer\n", 1386ff984e57SWei WANG mmc_hostname(mmc)); 1387ff984e57SWei WANG 138898fcc576SMicky Ching rtsx_pci_complete_unfinished_transfer(pcr); 1389ff984e57SWei WANG 139098fcc576SMicky Ching host->mrq->cmd->error = -ENOMEDIUM; 139198fcc576SMicky Ching if (host->mrq->stop) 139298fcc576SMicky Ching host->mrq->stop->error = -ENOMEDIUM; 139398fcc576SMicky Ching mmc_request_done(mmc, host->mrq); 1394ff984e57SWei WANG } 139598fcc576SMicky Ching mutex_unlock(&host->host_mutex); 1396ff984e57SWei WANG 1397ff984e57SWei WANG mmc_remove_host(mmc); 1398640e09bcSMicky Ching host->eject = true; 1399640e09bcSMicky Ching 14006291e715SMicky Ching flush_workqueue(host->workq); 14016291e715SMicky Ching destroy_workqueue(host->workq); 14026291e715SMicky Ching host->workq = NULL; 14036291e715SMicky Ching 1404ff984e57SWei WANG mmc_free_host(mmc); 1405ff984e57SWei WANG 1406ff984e57SWei WANG dev_dbg(&(pdev->dev), 1407ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1408ff984e57SWei WANG 1409ff984e57SWei WANG return 0; 1410ff984e57SWei WANG } 1411ff984e57SWei WANG 1412ff984e57SWei WANG static struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1413ff984e57SWei WANG { 1414ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1415ff984e57SWei WANG }, { 1416ff984e57SWei WANG /* sentinel */ 1417ff984e57SWei WANG } 1418ff984e57SWei WANG }; 1419ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1420ff984e57SWei WANG 1421ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1422ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1423ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1424ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1425ff984e57SWei WANG .driver = { 1426ff984e57SWei WANG .owner = THIS_MODULE, 1427ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1428ff984e57SWei WANG }, 1429ff984e57SWei WANG }; 1430ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1431ff984e57SWei WANG 1432ff984e57SWei WANG MODULE_LICENSE("GPL"); 1433ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1434ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1435