1ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 2ff984e57SWei WANG * 362282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4ff984e57SWei WANG * 5ff984e57SWei WANG * This program is free software; you can redistribute it and/or modify it 6ff984e57SWei WANG * under the terms of the GNU General Public License as published by the 7ff984e57SWei WANG * Free Software Foundation; either version 2, or (at your option) any 8ff984e57SWei WANG * later version. 9ff984e57SWei WANG * 10ff984e57SWei WANG * This program is distributed in the hope that it will be useful, but 11ff984e57SWei WANG * WITHOUT ANY WARRANTY; without even the implied warranty of 12ff984e57SWei WANG * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13ff984e57SWei WANG * General Public License for more details. 14ff984e57SWei WANG * 15ff984e57SWei WANG * You should have received a copy of the GNU General Public License along 16ff984e57SWei WANG * with this program; if not, see <http://www.gnu.org/licenses/>. 17ff984e57SWei WANG * 18ff984e57SWei WANG * Author: 19ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 20ff984e57SWei WANG */ 21ff984e57SWei WANG 22ff984e57SWei WANG #include <linux/module.h> 23433e075cSWei WANG #include <linux/slab.h> 24ff984e57SWei WANG #include <linux/highmem.h> 25ff984e57SWei WANG #include <linux/delay.h> 26ff984e57SWei WANG #include <linux/platform_device.h> 27ff984e57SWei WANG #include <linux/mmc/host.h> 28ff984e57SWei WANG #include <linux/mmc/mmc.h> 29ff984e57SWei WANG #include <linux/mmc/sd.h> 30ff984e57SWei WANG #include <linux/mmc/card.h> 31ff984e57SWei WANG #include <linux/mfd/rtsx_pci.h> 32ff984e57SWei WANG #include <asm/unaligned.h> 33ff984e57SWei WANG 34c42deffdSMicky Ching struct realtek_next { 35c42deffdSMicky Ching unsigned int sg_count; 36c42deffdSMicky Ching s32 cookie; 37c42deffdSMicky Ching }; 38c42deffdSMicky Ching 39ff984e57SWei WANG struct realtek_pci_sdmmc { 40ff984e57SWei WANG struct platform_device *pdev; 41ff984e57SWei WANG struct rtsx_pcr *pcr; 42ff984e57SWei WANG struct mmc_host *mmc; 43ff984e57SWei WANG struct mmc_request *mrq; 44c42deffdSMicky Ching struct mmc_command *cmd; 45c42deffdSMicky Ching struct mmc_data *data; 46ff984e57SWei WANG 47c42deffdSMicky Ching spinlock_t lock; 48c42deffdSMicky Ching struct timer_list timer; 49c42deffdSMicky Ching struct tasklet_struct cmd_tasklet; 50c42deffdSMicky Ching struct tasklet_struct data_tasklet; 51c42deffdSMicky Ching struct tasklet_struct finish_tasklet; 52ff984e57SWei WANG 53c42deffdSMicky Ching u8 rsp_type; 54c42deffdSMicky Ching u8 rsp_len; 55c42deffdSMicky Ching int sg_count; 56ff984e57SWei WANG u8 ssc_depth; 57ff984e57SWei WANG unsigned int clock; 58ff984e57SWei WANG bool vpclk; 59ff984e57SWei WANG bool double_clk; 60ff984e57SWei WANG bool eject; 61ff984e57SWei WANG bool initial_mode; 62d88691beSWei WANG int power_state; 63d88691beSWei WANG #define SDMMC_POWER_ON 1 64d88691beSWei WANG #define SDMMC_POWER_OFF 0 65c42deffdSMicky Ching 66c42deffdSMicky Ching struct realtek_next next_data; 67ff984e57SWei WANG }; 68ff984e57SWei WANG 69c42deffdSMicky Ching static int sd_start_multi_rw(struct realtek_pci_sdmmc *host, 70c42deffdSMicky Ching struct mmc_request *mrq); 71c42deffdSMicky Ching 72ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 73ff984e57SWei WANG { 74ff984e57SWei WANG return &(host->pdev->dev); 75ff984e57SWei WANG } 76ff984e57SWei WANG 77ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 78ff984e57SWei WANG { 79ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 80ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 81ff984e57SWei WANG } 82ff984e57SWei WANG 83ff984e57SWei WANG #ifdef DEBUG 84ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 85ff984e57SWei WANG { 86ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 87ff984e57SWei WANG u16 i; 88ff984e57SWei WANG u8 *ptr; 89ff984e57SWei WANG 90ff984e57SWei WANG /* Print SD host internal registers */ 91ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 92ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 93ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 94ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 95ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 96ff984e57SWei WANG rtsx_pci_send_cmd(pcr, 100); 97ff984e57SWei WANG 98ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr); 99ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 100ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 101ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 102ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 103ff984e57SWei WANG } 104ff984e57SWei WANG #else 105ff984e57SWei WANG #define sd_print_debug_regs(host) 106ff984e57SWei WANG #endif /* DEBUG */ 107ff984e57SWei WANG 108c42deffdSMicky Ching static void sd_isr_done_transfer(struct platform_device *pdev) 109c42deffdSMicky Ching { 110c42deffdSMicky Ching struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 111c42deffdSMicky Ching 112c42deffdSMicky Ching spin_lock(&host->lock); 113c42deffdSMicky Ching if (host->cmd) 114c42deffdSMicky Ching tasklet_schedule(&host->cmd_tasklet); 115c42deffdSMicky Ching if (host->data) 116c42deffdSMicky Ching tasklet_schedule(&host->data_tasklet); 117c42deffdSMicky Ching spin_unlock(&host->lock); 118c42deffdSMicky Ching } 119c42deffdSMicky Ching 120c42deffdSMicky Ching static void sd_request_timeout(unsigned long host_addr) 121c42deffdSMicky Ching { 122c42deffdSMicky Ching struct realtek_pci_sdmmc *host = (struct realtek_pci_sdmmc *)host_addr; 123c42deffdSMicky Ching unsigned long flags; 124c42deffdSMicky Ching 125c42deffdSMicky Ching spin_lock_irqsave(&host->lock, flags); 126c42deffdSMicky Ching 127c42deffdSMicky Ching if (!host->mrq) { 128c42deffdSMicky Ching dev_err(sdmmc_dev(host), "error: no request exist\n"); 129c42deffdSMicky Ching goto out; 130c42deffdSMicky Ching } 131c42deffdSMicky Ching 132c42deffdSMicky Ching if (host->cmd) 133c42deffdSMicky Ching host->cmd->error = -ETIMEDOUT; 134c42deffdSMicky Ching if (host->data) 135c42deffdSMicky Ching host->data->error = -ETIMEDOUT; 136c42deffdSMicky Ching 137c42deffdSMicky Ching dev_dbg(sdmmc_dev(host), "timeout for request\n"); 138c42deffdSMicky Ching 139c42deffdSMicky Ching out: 140c42deffdSMicky Ching tasklet_schedule(&host->finish_tasklet); 141c42deffdSMicky Ching spin_unlock_irqrestore(&host->lock, flags); 142c42deffdSMicky Ching } 143c42deffdSMicky Ching 144c42deffdSMicky Ching static void sd_finish_request(unsigned long host_addr) 145c42deffdSMicky Ching { 146c42deffdSMicky Ching struct realtek_pci_sdmmc *host = (struct realtek_pci_sdmmc *)host_addr; 147c42deffdSMicky Ching struct rtsx_pcr *pcr = host->pcr; 148c42deffdSMicky Ching struct mmc_request *mrq; 149c42deffdSMicky Ching struct mmc_command *cmd; 150c42deffdSMicky Ching struct mmc_data *data; 151c42deffdSMicky Ching unsigned long flags; 152c42deffdSMicky Ching bool any_error; 153c42deffdSMicky Ching 154c42deffdSMicky Ching spin_lock_irqsave(&host->lock, flags); 155c42deffdSMicky Ching 156c42deffdSMicky Ching del_timer(&host->timer); 157c42deffdSMicky Ching mrq = host->mrq; 158c42deffdSMicky Ching if (!mrq) { 159c42deffdSMicky Ching dev_err(sdmmc_dev(host), "error: no request need finish\n"); 160c42deffdSMicky Ching goto out; 161c42deffdSMicky Ching } 162c42deffdSMicky Ching 163c42deffdSMicky Ching cmd = mrq->cmd; 164c42deffdSMicky Ching data = mrq->data; 165c42deffdSMicky Ching 166c42deffdSMicky Ching any_error = (mrq->sbc && mrq->sbc->error) || 167c42deffdSMicky Ching (mrq->stop && mrq->stop->error) || 168c42deffdSMicky Ching (cmd && cmd->error) || (data && data->error); 169c42deffdSMicky Ching 170c42deffdSMicky Ching if (any_error) { 171c42deffdSMicky Ching rtsx_pci_stop_cmd(pcr); 172c42deffdSMicky Ching sd_clear_error(host); 173c42deffdSMicky Ching } 174c42deffdSMicky Ching 175c42deffdSMicky Ching if (data) { 176c42deffdSMicky Ching if (any_error) 177c42deffdSMicky Ching data->bytes_xfered = 0; 178c42deffdSMicky Ching else 179c42deffdSMicky Ching data->bytes_xfered = data->blocks * data->blksz; 180c42deffdSMicky Ching 181c42deffdSMicky Ching if (!data->host_cookie) 182c42deffdSMicky Ching rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, 183c42deffdSMicky Ching data->flags & MMC_DATA_READ); 184c42deffdSMicky Ching 185c42deffdSMicky Ching } 186c42deffdSMicky Ching 187c42deffdSMicky Ching host->mrq = NULL; 188c42deffdSMicky Ching host->cmd = NULL; 189c42deffdSMicky Ching host->data = NULL; 190c42deffdSMicky Ching 191c42deffdSMicky Ching out: 192c42deffdSMicky Ching spin_unlock_irqrestore(&host->lock, flags); 193c42deffdSMicky Ching mutex_unlock(&pcr->pcr_mutex); 194c42deffdSMicky Ching mmc_request_done(host->mmc, mrq); 195c42deffdSMicky Ching } 196c42deffdSMicky Ching 197ff984e57SWei WANG static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 198ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 199ff984e57SWei WANG { 200ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 201ff984e57SWei WANG int err, i; 202ff984e57SWei WANG u8 trans_mode; 203ff984e57SWei WANG 204ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40); 205ff984e57SWei WANG 206ff984e57SWei WANG if (!buf) 207ff984e57SWei WANG buf_len = 0; 208ff984e57SWei WANG 209ff984e57SWei WANG if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK) 210ff984e57SWei WANG trans_mode = SD_TM_AUTO_TUNING; 211ff984e57SWei WANG else 212ff984e57SWei WANG trans_mode = SD_TM_NORMAL_READ; 213ff984e57SWei WANG 214ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 215ff984e57SWei WANG 216ff984e57SWei WANG for (i = 0; i < 5; i++) 217ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]); 218ff984e57SWei WANG 219ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 220ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 221ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 222ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 223ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 224ff984e57SWei WANG 225ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 226ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 227ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 228ff984e57SWei WANG if (trans_mode != SD_TM_AUTO_TUNING) 229ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 230ff984e57SWei WANG CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 231ff984e57SWei WANG 232ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 233ff984e57SWei WANG 0xFF, trans_mode | SD_TRANSFER_START); 234ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 235ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 236ff984e57SWei WANG 237ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 238ff984e57SWei WANG if (err < 0) { 239ff984e57SWei WANG sd_print_debug_regs(host); 240ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 241ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 242ff984e57SWei WANG return err; 243ff984e57SWei WANG } 244ff984e57SWei WANG 245ff984e57SWei WANG if (buf && buf_len) { 246ff984e57SWei WANG err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 247ff984e57SWei WANG if (err < 0) { 248ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 249ff984e57SWei WANG "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 250ff984e57SWei WANG return err; 251ff984e57SWei WANG } 252ff984e57SWei WANG } 253ff984e57SWei WANG 254ff984e57SWei WANG return 0; 255ff984e57SWei WANG } 256ff984e57SWei WANG 257ff984e57SWei WANG static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 258ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 259ff984e57SWei WANG { 260ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 261ff984e57SWei WANG int err, i; 262ff984e57SWei WANG u8 trans_mode; 263ff984e57SWei WANG 264ff984e57SWei WANG if (!buf) 265ff984e57SWei WANG buf_len = 0; 266ff984e57SWei WANG 267ff984e57SWei WANG if (buf && buf_len) { 268ff984e57SWei WANG err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 269ff984e57SWei WANG if (err < 0) { 270ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 271ff984e57SWei WANG "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 272ff984e57SWei WANG return err; 273ff984e57SWei WANG } 274ff984e57SWei WANG } 275ff984e57SWei WANG 276ff984e57SWei WANG trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3; 277ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 278ff984e57SWei WANG 279ff984e57SWei WANG if (cmd) { 280ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__, 281ff984e57SWei WANG cmd[0] - 0x40); 282ff984e57SWei WANG 283ff984e57SWei WANG for (i = 0; i < 5; i++) 284ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 285ff984e57SWei WANG SD_CMD0 + i, 0xFF, cmd[i]); 286ff984e57SWei WANG } 287ff984e57SWei WANG 288ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 289ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 290ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 291ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 292ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 293ff984e57SWei WANG 294ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 295ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 296ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 297ff984e57SWei WANG 298ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 299ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 300ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 301ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 302ff984e57SWei WANG 303ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 304ff984e57SWei WANG if (err < 0) { 305ff984e57SWei WANG sd_print_debug_regs(host); 306ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 307ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 308ff984e57SWei WANG return err; 309ff984e57SWei WANG } 310ff984e57SWei WANG 311ff984e57SWei WANG return 0; 312ff984e57SWei WANG } 313ff984e57SWei WANG 314c42deffdSMicky Ching static void sd_send_cmd(struct realtek_pci_sdmmc *host, struct mmc_command *cmd) 315ff984e57SWei WANG { 316ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 317ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 318ff984e57SWei WANG u32 arg = cmd->arg; 319ff984e57SWei WANG int err = 0; 320ff984e57SWei WANG int timeout = 100; 321ff984e57SWei WANG int i; 322ff984e57SWei WANG u8 rsp_type; 323ff984e57SWei WANG int rsp_len = 5; 324c42deffdSMicky Ching unsigned long flags; 325c42deffdSMicky Ching 326c42deffdSMicky Ching if (host->cmd) 327c42deffdSMicky Ching dev_err(sdmmc_dev(host), "error: cmd already exist\n"); 328c42deffdSMicky Ching 329c42deffdSMicky Ching host->cmd = cmd; 330ff984e57SWei WANG 331ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 332ff984e57SWei WANG __func__, cmd_idx, arg); 333ff984e57SWei WANG 334ff984e57SWei WANG /* Response type: 335ff984e57SWei WANG * R0 336ff984e57SWei WANG * R1, R5, R6, R7 337ff984e57SWei WANG * R1b 338ff984e57SWei WANG * R2 339ff984e57SWei WANG * R3, R4 340ff984e57SWei WANG */ 341ff984e57SWei WANG switch (mmc_resp_type(cmd)) { 342ff984e57SWei WANG case MMC_RSP_NONE: 343ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R0; 344ff984e57SWei WANG rsp_len = 0; 345ff984e57SWei WANG break; 346ff984e57SWei WANG case MMC_RSP_R1: 347ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1; 348ff984e57SWei WANG break; 349ff984e57SWei WANG case MMC_RSP_R1B: 350ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1b; 351ff984e57SWei WANG break; 352ff984e57SWei WANG case MMC_RSP_R2: 353ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R2; 354ff984e57SWei WANG rsp_len = 16; 355ff984e57SWei WANG break; 356ff984e57SWei WANG case MMC_RSP_R3: 357ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R3; 358ff984e57SWei WANG break; 359ff984e57SWei WANG default: 360ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n"); 361ff984e57SWei WANG err = -EINVAL; 362ff984e57SWei WANG goto out; 363ff984e57SWei WANG } 364c42deffdSMicky Ching host->rsp_type = rsp_type; 365c42deffdSMicky Ching host->rsp_len = rsp_len; 366ff984e57SWei WANG 367ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 368ff984e57SWei WANG timeout = 3000; 369ff984e57SWei WANG 370ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 371ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 372ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 373ff984e57SWei WANG if (err < 0) 374ff984e57SWei WANG goto out; 375ff984e57SWei WANG } 376ff984e57SWei WANG 377ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 378ff984e57SWei WANG 379ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx); 380ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24)); 381ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16)); 382ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8)); 383ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg); 384ff984e57SWei WANG 385ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 386ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 387ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 388ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 389ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 390ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 391ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 392ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 393ff984e57SWei WANG 394ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 395ff984e57SWei WANG /* Read data from ping-pong buffer */ 396ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 397ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 398ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 399ff984e57SWei WANG /* Read data from SD_CMDx registers */ 400ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 401ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 402ff984e57SWei WANG } 403ff984e57SWei WANG 404ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 405ff984e57SWei WANG 406c42deffdSMicky Ching mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout)); 407c42deffdSMicky Ching 408c42deffdSMicky Ching spin_lock_irqsave(&pcr->lock, flags); 409c42deffdSMicky Ching pcr->trans_result = TRANS_NOT_READY; 410c42deffdSMicky Ching rtsx_pci_send_cmd_no_wait(pcr); 411c42deffdSMicky Ching spin_unlock_irqrestore(&pcr->lock, flags); 412c42deffdSMicky Ching 413c42deffdSMicky Ching return; 414c42deffdSMicky Ching 415c42deffdSMicky Ching out: 416c42deffdSMicky Ching cmd->error = err; 417c42deffdSMicky Ching tasklet_schedule(&host->finish_tasklet); 418c42deffdSMicky Ching } 419c42deffdSMicky Ching 420c42deffdSMicky Ching static void sd_get_rsp(unsigned long host_addr) 421c42deffdSMicky Ching { 422c42deffdSMicky Ching struct realtek_pci_sdmmc *host = (struct realtek_pci_sdmmc *)host_addr; 423c42deffdSMicky Ching struct rtsx_pcr *pcr = host->pcr; 424c42deffdSMicky Ching struct mmc_command *cmd; 425c42deffdSMicky Ching int i, err = 0, stat_idx; 426c42deffdSMicky Ching u8 *ptr, rsp_type; 427c42deffdSMicky Ching unsigned long flags; 428c42deffdSMicky Ching 429c42deffdSMicky Ching spin_lock_irqsave(&host->lock, flags); 430c42deffdSMicky Ching 431c42deffdSMicky Ching cmd = host->cmd; 432c42deffdSMicky Ching host->cmd = NULL; 433c42deffdSMicky Ching 434c42deffdSMicky Ching if (!cmd) { 435c42deffdSMicky Ching dev_err(sdmmc_dev(host), "error: cmd not exist\n"); 436ff984e57SWei WANG goto out; 437ff984e57SWei WANG } 438ff984e57SWei WANG 439c42deffdSMicky Ching spin_lock(&pcr->lock); 440c42deffdSMicky Ching if (pcr->trans_result == TRANS_NO_DEVICE) 441c42deffdSMicky Ching err = -ENODEV; 442c42deffdSMicky Ching else if (pcr->trans_result != TRANS_RESULT_OK) 443c42deffdSMicky Ching err = -EINVAL; 444c42deffdSMicky Ching spin_unlock(&pcr->lock); 445c42deffdSMicky Ching 446c42deffdSMicky Ching if (err < 0) 447c42deffdSMicky Ching goto out; 448c42deffdSMicky Ching 449c42deffdSMicky Ching rsp_type = host->rsp_type; 450c42deffdSMicky Ching stat_idx = host->rsp_len; 451c42deffdSMicky Ching 452ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 453ff984e57SWei WANG err = 0; 454ff984e57SWei WANG goto out; 455ff984e57SWei WANG } 456ff984e57SWei WANG 457ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 458ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 459ff984e57SWei WANG 460ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 461ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 462ff984e57SWei WANG err = -EILSEQ; 463ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 464ff984e57SWei WANG goto out; 465ff984e57SWei WANG } 466ff984e57SWei WANG 467ff984e57SWei WANG /* Check CRC7 */ 468ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 469ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 470ff984e57SWei WANG err = -EILSEQ; 471ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 472ff984e57SWei WANG goto out; 473ff984e57SWei WANG } 474ff984e57SWei WANG } 475ff984e57SWei WANG 476ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 477ff984e57SWei WANG for (i = 0; i < 4; i++) { 478ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 479ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 480ff984e57SWei WANG i, cmd->resp[i]); 481ff984e57SWei WANG } 482ff984e57SWei WANG } else { 483ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 484ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 485ff984e57SWei WANG cmd->resp[0]); 486ff984e57SWei WANG } 487ff984e57SWei WANG 488c42deffdSMicky Ching if (cmd == host->mrq->sbc) { 489c42deffdSMicky Ching sd_send_cmd(host, host->mrq->cmd); 490c42deffdSMicky Ching spin_unlock_irqrestore(&host->lock, flags); 491c42deffdSMicky Ching return; 492c42deffdSMicky Ching } 493c42deffdSMicky Ching 494c42deffdSMicky Ching if (cmd == host->mrq->stop) 495c42deffdSMicky Ching goto out; 496c42deffdSMicky Ching 497c42deffdSMicky Ching if (cmd->data) { 498c42deffdSMicky Ching sd_start_multi_rw(host, host->mrq); 499c42deffdSMicky Ching spin_unlock_irqrestore(&host->lock, flags); 500c42deffdSMicky Ching return; 501c42deffdSMicky Ching } 502c42deffdSMicky Ching 503ff984e57SWei WANG out: 504ff984e57SWei WANG cmd->error = err; 5051b8055b4SWei WANG 506c42deffdSMicky Ching tasklet_schedule(&host->finish_tasklet); 507c42deffdSMicky Ching spin_unlock_irqrestore(&host->lock, flags); 508ff984e57SWei WANG } 509ff984e57SWei WANG 510c42deffdSMicky Ching static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, 511c42deffdSMicky Ching struct mmc_data *data, struct realtek_next *next) 512c42deffdSMicky Ching { 513c42deffdSMicky Ching struct rtsx_pcr *pcr = host->pcr; 514c42deffdSMicky Ching int read = data->flags & MMC_DATA_READ; 515c42deffdSMicky Ching int sg_count = 0; 516c42deffdSMicky Ching 517c42deffdSMicky Ching if (!next && data->host_cookie && 518c42deffdSMicky Ching data->host_cookie != host->next_data.cookie) { 519c42deffdSMicky Ching dev_err(sdmmc_dev(host), 520c42deffdSMicky Ching "error: invalid cookie data[%d] host[%d]\n", 521c42deffdSMicky Ching data->host_cookie, host->next_data.cookie); 522c42deffdSMicky Ching data->host_cookie = 0; 523c42deffdSMicky Ching } 524c42deffdSMicky Ching 525c42deffdSMicky Ching if (next || (!next && data->host_cookie != host->next_data.cookie)) 526c42deffdSMicky Ching sg_count = rtsx_pci_dma_map_sg(pcr, 527c42deffdSMicky Ching data->sg, data->sg_len, read); 528c42deffdSMicky Ching else 529c42deffdSMicky Ching sg_count = host->next_data.sg_count; 530c42deffdSMicky Ching 531c42deffdSMicky Ching if (next) { 532c42deffdSMicky Ching next->sg_count = sg_count; 533c42deffdSMicky Ching if (++next->cookie < 0) 534c42deffdSMicky Ching next->cookie = 1; 535c42deffdSMicky Ching data->host_cookie = next->cookie; 536c42deffdSMicky Ching } 537c42deffdSMicky Ching 538c42deffdSMicky Ching return sg_count; 539c42deffdSMicky Ching } 540c42deffdSMicky Ching 541c42deffdSMicky Ching static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 542c42deffdSMicky Ching bool is_first_req) 543c42deffdSMicky Ching { 544c42deffdSMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 545c42deffdSMicky Ching struct mmc_data *data = mrq->data; 546c42deffdSMicky Ching 547c42deffdSMicky Ching if (data->host_cookie) { 548c42deffdSMicky Ching dev_err(sdmmc_dev(host), 549c42deffdSMicky Ching "error: descard already cookie data[%d]\n", 550c42deffdSMicky Ching data->host_cookie); 551c42deffdSMicky Ching data->host_cookie = 0; 552c42deffdSMicky Ching } 553c42deffdSMicky Ching 554c42deffdSMicky Ching dev_dbg(sdmmc_dev(host), "dma sg prepared: %d\n", 555c42deffdSMicky Ching sd_pre_dma_transfer(host, data, &host->next_data)); 556c42deffdSMicky Ching } 557c42deffdSMicky Ching 558c42deffdSMicky Ching static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 559c42deffdSMicky Ching int err) 560c42deffdSMicky Ching { 561c42deffdSMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 562c42deffdSMicky Ching struct rtsx_pcr *pcr = host->pcr; 563c42deffdSMicky Ching struct mmc_data *data = mrq->data; 564c42deffdSMicky Ching int read = data->flags & MMC_DATA_READ; 565c42deffdSMicky Ching 566c42deffdSMicky Ching rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); 567c42deffdSMicky Ching data->host_cookie = 0; 568c42deffdSMicky Ching } 569c42deffdSMicky Ching 570c42deffdSMicky Ching static int sd_start_multi_rw(struct realtek_pci_sdmmc *host, 571c42deffdSMicky Ching struct mmc_request *mrq) 572ff984e57SWei WANG { 573ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 574ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 575ff984e57SWei WANG struct mmc_card *card = mmc->card; 576ff984e57SWei WANG struct mmc_data *data = mrq->data; 57771ef1ea4SJackey Shen int uhs = mmc_card_uhs(card); 578c42deffdSMicky Ching int read = data->flags & MMC_DATA_READ; 579ff984e57SWei WANG u8 cfg2, trans_mode; 580ff984e57SWei WANG int err; 581ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 582ff984e57SWei WANG 583c42deffdSMicky Ching if (host->data) 584c42deffdSMicky Ching dev_err(sdmmc_dev(host), "error: data already exist\n"); 585c42deffdSMicky Ching 586c42deffdSMicky Ching host->data = data; 587c42deffdSMicky Ching 588ff984e57SWei WANG if (read) { 589ff984e57SWei WANG cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 590ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0; 591ff984e57SWei WANG trans_mode = SD_TM_AUTO_READ_3; 592ff984e57SWei WANG } else { 593ff984e57SWei WANG cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 594ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 595ff984e57SWei WANG trans_mode = SD_TM_AUTO_WRITE_3; 596ff984e57SWei WANG } 597ff984e57SWei WANG 598ff984e57SWei WANG if (!uhs) 599ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 600ff984e57SWei WANG 601ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 602ff984e57SWei WANG 603ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00); 604ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02); 605ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 606ff984e57SWei WANG 0xFF, (u8)data->blocks); 607ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 608ff984e57SWei WANG 0xFF, (u8)(data->blocks >> 8)); 609ff984e57SWei WANG 610ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 611ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 612ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 613ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 614ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 615ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 616ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 617ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 618ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 619ff984e57SWei WANG if (read) { 620ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 621ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 622ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 623ff984e57SWei WANG } else { 624ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 625ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 626ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 627ff984e57SWei WANG } 628ff984e57SWei WANG 629ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 630ff984e57SWei WANG 0x01, RING_BUFFER); 631ff984e57SWei WANG 63238d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 633ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 634ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 635ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 636ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 637ff984e57SWei WANG 638c42deffdSMicky Ching mod_timer(&host->timer, jiffies + 10 * HZ); 639ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 640ff984e57SWei WANG 641c42deffdSMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, read); 642ff984e57SWei WANG if (err < 0) { 643c42deffdSMicky Ching data->error = err; 644c42deffdSMicky Ching tasklet_schedule(&host->finish_tasklet); 645c42deffdSMicky Ching } 646c42deffdSMicky Ching return 0; 647ff984e57SWei WANG } 648ff984e57SWei WANG 649c42deffdSMicky Ching static void sd_finish_multi_rw(unsigned long host_addr) 650c42deffdSMicky Ching { 651c42deffdSMicky Ching struct realtek_pci_sdmmc *host = (struct realtek_pci_sdmmc *)host_addr; 652c42deffdSMicky Ching struct rtsx_pcr *pcr = host->pcr; 653c42deffdSMicky Ching struct mmc_data *data; 654c42deffdSMicky Ching int err = 0; 655c42deffdSMicky Ching unsigned long flags; 656c42deffdSMicky Ching 657c42deffdSMicky Ching spin_lock_irqsave(&host->lock, flags); 658c42deffdSMicky Ching 659c42deffdSMicky Ching if (!host->data) { 660c42deffdSMicky Ching dev_err(sdmmc_dev(host), "error: no data exist\n"); 661c42deffdSMicky Ching goto out; 662c42deffdSMicky Ching } 663c42deffdSMicky Ching 664c42deffdSMicky Ching data = host->data; 665c42deffdSMicky Ching host->data = NULL; 666c42deffdSMicky Ching 667c42deffdSMicky Ching if (pcr->trans_result == TRANS_NO_DEVICE) 668c42deffdSMicky Ching err = -ENODEV; 669c42deffdSMicky Ching else if (pcr->trans_result != TRANS_RESULT_OK) 670c42deffdSMicky Ching err = -EINVAL; 671c42deffdSMicky Ching 672c42deffdSMicky Ching if (err < 0) { 673c42deffdSMicky Ching data->error = err; 674c42deffdSMicky Ching goto out; 675c42deffdSMicky Ching } 676c42deffdSMicky Ching 677c42deffdSMicky Ching if (!host->mrq->sbc && data->stop) { 678c42deffdSMicky Ching sd_send_cmd(host, data->stop); 679c42deffdSMicky Ching spin_unlock_irqrestore(&host->lock, flags); 680c42deffdSMicky Ching return; 681c42deffdSMicky Ching } 682c42deffdSMicky Ching 683c42deffdSMicky Ching out: 684c42deffdSMicky Ching tasklet_schedule(&host->finish_tasklet); 685c42deffdSMicky Ching spin_unlock_irqrestore(&host->lock, flags); 686ff984e57SWei WANG } 687ff984e57SWei WANG 688ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 689ff984e57SWei WANG { 690ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 691ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 692ff984e57SWei WANG } 693ff984e57SWei WANG 694ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 695ff984e57SWei WANG { 696ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 697ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 698ff984e57SWei WANG } 699ff984e57SWei WANG 700ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 701ff984e57SWei WANG struct mmc_request *mrq) 702ff984e57SWei WANG { 703ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 704ff984e57SWei WANG struct mmc_data *data = mrq->data; 705ff984e57SWei WANG u8 _cmd[5], *buf; 706ff984e57SWei WANG 707ff984e57SWei WANG _cmd[0] = 0x40 | (u8)cmd->opcode; 708ff984e57SWei WANG put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1])); 709ff984e57SWei WANG 710ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 711ff984e57SWei WANG if (!buf) { 712ff984e57SWei WANG cmd->error = -ENOMEM; 713ff984e57SWei WANG return; 714ff984e57SWei WANG } 715ff984e57SWei WANG 716ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 717ff984e57SWei WANG if (host->initial_mode) 718ff984e57SWei WANG sd_disable_initial_mode(host); 719ff984e57SWei WANG 720ff984e57SWei WANG cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf, 721ff984e57SWei WANG data->blksz, 200); 722ff984e57SWei WANG 723ff984e57SWei WANG if (host->initial_mode) 724ff984e57SWei WANG sd_enable_initial_mode(host); 725ff984e57SWei WANG 726ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 727ff984e57SWei WANG } else { 728ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 729ff984e57SWei WANG 730ff984e57SWei WANG cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf, 731ff984e57SWei WANG data->blksz, 200); 732ff984e57SWei WANG } 733ff984e57SWei WANG 734ff984e57SWei WANG kfree(buf); 735ff984e57SWei WANG } 736ff984e57SWei WANG 73784d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, 73884d72f9cSWei WANG u8 sample_point, bool rx) 739ff984e57SWei WANG { 740ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 741ff984e57SWei WANG int err; 742ff984e57SWei WANG 74384d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 74484d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point); 745ff984e57SWei WANG 746ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 747ff984e57SWei WANG 748ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 74984d72f9cSWei WANG if (rx) 75084d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 75184d72f9cSWei WANG SD_VPRX_CTL, 0x1F, sample_point); 75284d72f9cSWei WANG else 75384d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 75484d72f9cSWei WANG SD_VPTX_CTL, 0x1F, sample_point); 755ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); 756ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 757ff984e57SWei WANG PHASE_NOT_RESET, PHASE_NOT_RESET); 758ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); 759ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 760ff984e57SWei WANG 761ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 762ff984e57SWei WANG if (err < 0) 763ff984e57SWei WANG return err; 764ff984e57SWei WANG 765ff984e57SWei WANG return 0; 766ff984e57SWei WANG } 767ff984e57SWei WANG 768abcc6b29SMicky Ching static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 769abcc6b29SMicky Ching { 770abcc6b29SMicky Ching bit %= RTSX_PHASE_MAX; 771abcc6b29SMicky Ching return phase_map & (1 << bit); 772abcc6b29SMicky Ching } 773abcc6b29SMicky Ching 774abcc6b29SMicky Ching static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 775abcc6b29SMicky Ching { 776abcc6b29SMicky Ching int i; 777abcc6b29SMicky Ching 778abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 779abcc6b29SMicky Ching if (test_phase_bit(phase_map, start_bit + i) == 0) 780abcc6b29SMicky Ching return i; 781abcc6b29SMicky Ching } 782abcc6b29SMicky Ching return RTSX_PHASE_MAX; 783abcc6b29SMicky Ching } 784abcc6b29SMicky Ching 785ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 786ff984e57SWei WANG { 787abcc6b29SMicky Ching int start = 0, len = 0; 788abcc6b29SMicky Ching int start_final = 0, len_final = 0; 789ff984e57SWei WANG u8 final_phase = 0xFF; 790ff984e57SWei WANG 791abcc6b29SMicky Ching if (phase_map == 0) { 792abcc6b29SMicky Ching dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 793abcc6b29SMicky Ching return final_phase; 794ff984e57SWei WANG } 795ff984e57SWei WANG 796abcc6b29SMicky Ching while (start < RTSX_PHASE_MAX) { 797abcc6b29SMicky Ching len = sd_get_phase_len(phase_map, start); 798abcc6b29SMicky Ching if (len_final < len) { 799abcc6b29SMicky Ching start_final = start; 800abcc6b29SMicky Ching len_final = len; 801abcc6b29SMicky Ching } 802abcc6b29SMicky Ching start += len ? len : 1; 803ff984e57SWei WANG } 804ff984e57SWei WANG 805abcc6b29SMicky Ching final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 806abcc6b29SMicky Ching dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 807abcc6b29SMicky Ching phase_map, len_final, final_phase); 808ff984e57SWei WANG 809ff984e57SWei WANG return final_phase; 810ff984e57SWei WANG } 811ff984e57SWei WANG 812ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 813ff984e57SWei WANG { 814ff984e57SWei WANG int err, i; 815ff984e57SWei WANG u8 val = 0; 816ff984e57SWei WANG 817ff984e57SWei WANG for (i = 0; i < 100; i++) { 818ff984e57SWei WANG err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 819ff984e57SWei WANG if (val & SD_DATA_IDLE) 820ff984e57SWei WANG return; 821ff984e57SWei WANG 822ff984e57SWei WANG udelay(100); 823ff984e57SWei WANG } 824ff984e57SWei WANG } 825ff984e57SWei WANG 826ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 827ff984e57SWei WANG u8 opcode, u8 sample_point) 828ff984e57SWei WANG { 829ff984e57SWei WANG int err; 830ff984e57SWei WANG u8 cmd[5] = {0}; 831ff984e57SWei WANG 83284d72f9cSWei WANG err = sd_change_phase(host, sample_point, true); 833ff984e57SWei WANG if (err < 0) 834ff984e57SWei WANG return err; 835ff984e57SWei WANG 836ff984e57SWei WANG cmd[0] = 0x40 | opcode; 837ff984e57SWei WANG err = sd_read_data(host, cmd, 0x40, NULL, 0, 100); 838ff984e57SWei WANG if (err < 0) { 839ff984e57SWei WANG /* Wait till SD DATA IDLE */ 840ff984e57SWei WANG sd_wait_data_idle(host); 841ff984e57SWei WANG sd_clear_error(host); 842ff984e57SWei WANG return err; 843ff984e57SWei WANG } 844ff984e57SWei WANG 845ff984e57SWei WANG return 0; 846ff984e57SWei WANG } 847ff984e57SWei WANG 848ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 849ff984e57SWei WANG u8 opcode, u32 *phase_map) 850ff984e57SWei WANG { 851ff984e57SWei WANG int err, i; 852ff984e57SWei WANG u32 raw_phase_map = 0; 853ff984e57SWei WANG 854abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 855ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 856ff984e57SWei WANG if (err == 0) 857ff984e57SWei WANG raw_phase_map |= 1 << i; 858ff984e57SWei WANG } 859ff984e57SWei WANG 860ff984e57SWei WANG if (phase_map) 861ff984e57SWei WANG *phase_map = raw_phase_map; 862ff984e57SWei WANG 863ff984e57SWei WANG return 0; 864ff984e57SWei WANG } 865ff984e57SWei WANG 866ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 867ff984e57SWei WANG { 868ff984e57SWei WANG int err, i; 869ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 870ff984e57SWei WANG u8 final_phase; 871ff984e57SWei WANG 872ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 873ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 874ff984e57SWei WANG if (err < 0) 875ff984e57SWei WANG return err; 876ff984e57SWei WANG 877ff984e57SWei WANG if (raw_phase_map[i] == 0) 878ff984e57SWei WANG break; 879ff984e57SWei WANG } 880ff984e57SWei WANG 881ff984e57SWei WANG phase_map = 0xFFFFFFFF; 882ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 883ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 884ff984e57SWei WANG i, raw_phase_map[i]); 885ff984e57SWei WANG phase_map &= raw_phase_map[i]; 886ff984e57SWei WANG } 887ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 888ff984e57SWei WANG 889ff984e57SWei WANG if (phase_map) { 890ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 891ff984e57SWei WANG if (final_phase == 0xFF) 892ff984e57SWei WANG return -EINVAL; 893ff984e57SWei WANG 89484d72f9cSWei WANG err = sd_change_phase(host, final_phase, true); 895ff984e57SWei WANG if (err < 0) 896ff984e57SWei WANG return err; 897ff984e57SWei WANG } else { 898ff984e57SWei WANG return -EINVAL; 899ff984e57SWei WANG } 900ff984e57SWei WANG 901ff984e57SWei WANG return 0; 902ff984e57SWei WANG } 903ff984e57SWei WANG 904c42deffdSMicky Ching static inline bool sd_use_muti_rw(struct mmc_command *cmd) 905c42deffdSMicky Ching { 906c42deffdSMicky Ching return mmc_op_multi(cmd->opcode) || 907c42deffdSMicky Ching (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 908c42deffdSMicky Ching (cmd->opcode == MMC_WRITE_BLOCK); 909c42deffdSMicky Ching } 910c42deffdSMicky Ching 911ff984e57SWei WANG static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 912ff984e57SWei WANG { 913ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 914ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 915ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 916ff984e57SWei WANG struct mmc_data *data = mrq->data; 917ff984e57SWei WANG unsigned int data_size = 0; 918c3481955SWei WANG int err; 919c42deffdSMicky Ching unsigned long flags; 920c42deffdSMicky Ching 921c42deffdSMicky Ching mutex_lock(&pcr->pcr_mutex); 922c42deffdSMicky Ching spin_lock_irqsave(&host->lock, flags); 923c42deffdSMicky Ching 924c42deffdSMicky Ching if (host->mrq) 925c42deffdSMicky Ching dev_err(sdmmc_dev(host), "error: request already exist\n"); 926c42deffdSMicky Ching host->mrq = mrq; 927ff984e57SWei WANG 928ff984e57SWei WANG if (host->eject) { 929ff984e57SWei WANG cmd->error = -ENOMEDIUM; 930ff984e57SWei WANG goto finish; 931ff984e57SWei WANG } 932ff984e57SWei WANG 933c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 934c3481955SWei WANG if (err) { 935c3481955SWei WANG cmd->error = err; 936c3481955SWei WANG goto finish; 937c3481955SWei WANG } 938c3481955SWei WANG 939ff984e57SWei WANG rtsx_pci_start_run(pcr); 940ff984e57SWei WANG 941ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 942ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 943ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 944ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 945ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 946ff984e57SWei WANG 947ff984e57SWei WANG if (mrq->data) 948ff984e57SWei WANG data_size = data->blocks * data->blksz; 949ff984e57SWei WANG 950c42deffdSMicky Ching if (sd_use_muti_rw(cmd)) 951c42deffdSMicky Ching host->sg_count = sd_pre_dma_transfer(host, data, NULL); 952ff984e57SWei WANG 953c42deffdSMicky Ching if (!data_size || sd_use_muti_rw(cmd)) { 954c42deffdSMicky Ching if (mrq->sbc) 955c42deffdSMicky Ching sd_send_cmd(host, mrq->sbc); 956ff984e57SWei WANG else 957c42deffdSMicky Ching sd_send_cmd(host, cmd); 958c42deffdSMicky Ching spin_unlock_irqrestore(&host->lock, flags); 959c42deffdSMicky Ching } else { 960c42deffdSMicky Ching spin_unlock_irqrestore(&host->lock, flags); 961c42deffdSMicky Ching sd_normal_rw(host, mrq); 962c42deffdSMicky Ching tasklet_schedule(&host->finish_tasklet); 963ff984e57SWei WANG } 964c42deffdSMicky Ching return; 965ff984e57SWei WANG 966ff984e57SWei WANG finish: 967c42deffdSMicky Ching tasklet_schedule(&host->finish_tasklet); 968c42deffdSMicky Ching spin_unlock_irqrestore(&host->lock, flags); 969ff984e57SWei WANG } 970ff984e57SWei WANG 971ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 972ff984e57SWei WANG unsigned char bus_width) 973ff984e57SWei WANG { 974ff984e57SWei WANG int err = 0; 975ff984e57SWei WANG u8 width[] = { 976ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 977ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 978ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 979ff984e57SWei WANG }; 980ff984e57SWei WANG 981ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 982ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 983ff984e57SWei WANG 0x03, width[bus_width]); 984ff984e57SWei WANG 985ff984e57SWei WANG return err; 986ff984e57SWei WANG } 987ff984e57SWei WANG 988ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 989ff984e57SWei WANG { 990ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 991ff984e57SWei WANG int err; 992ff984e57SWei WANG 993d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 994d88691beSWei WANG return 0; 995d88691beSWei WANG 996ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 997ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 998ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 999ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 1000ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 1001ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 1002ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 1003ff984e57SWei WANG if (err < 0) 1004ff984e57SWei WANG return err; 1005ff984e57SWei WANG 1006ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 1007ff984e57SWei WANG if (err < 0) 1008ff984e57SWei WANG return err; 1009ff984e57SWei WANG 1010ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 1011ff984e57SWei WANG if (err < 0) 1012ff984e57SWei WANG return err; 1013ff984e57SWei WANG 1014ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 1015ff984e57SWei WANG if (err < 0) 1016ff984e57SWei WANG return err; 1017ff984e57SWei WANG 1018d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 1019ff984e57SWei WANG return 0; 1020ff984e57SWei WANG } 1021ff984e57SWei WANG 1022ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 1023ff984e57SWei WANG { 1024ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1025ff984e57SWei WANG int err; 1026ff984e57SWei WANG 1027d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 1028d88691beSWei WANG 1029ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 1030ff984e57SWei WANG 1031ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 1032ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 1033ff984e57SWei WANG 1034ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 1035ff984e57SWei WANG if (err < 0) 1036ff984e57SWei WANG return err; 1037ff984e57SWei WANG 1038ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 1039ff984e57SWei WANG if (err < 0) 1040ff984e57SWei WANG return err; 1041ff984e57SWei WANG 1042ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 1043ff984e57SWei WANG } 1044ff984e57SWei WANG 1045ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 1046ff984e57SWei WANG unsigned char power_mode) 1047ff984e57SWei WANG { 1048ff984e57SWei WANG int err; 1049ff984e57SWei WANG 1050ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 1051ff984e57SWei WANG err = sd_power_off(host); 1052ff984e57SWei WANG else 1053ff984e57SWei WANG err = sd_power_on(host); 1054ff984e57SWei WANG 1055ff984e57SWei WANG return err; 1056ff984e57SWei WANG } 1057ff984e57SWei WANG 105884d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 1059ff984e57SWei WANG { 1060ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1061ff984e57SWei WANG int err = 0; 1062ff984e57SWei WANG 1063ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 1064ff984e57SWei WANG 1065ff984e57SWei WANG switch (timing) { 1066ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1067ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1068ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1069ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 1070ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 1071ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1072ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1073ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1074ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 1075ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1076ff984e57SWei WANG break; 1077ff984e57SWei WANG 1078ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1079ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1080ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 1081ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 1082ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1083ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1084ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1085ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 1086ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1087ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1088ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 1089ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1090ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 1091ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 1092ff984e57SWei WANG break; 1093ff984e57SWei WANG 1094ff984e57SWei WANG case MMC_TIMING_MMC_HS: 1095ff984e57SWei WANG case MMC_TIMING_SD_HS: 1096ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1097ff984e57SWei WANG 0x0C, SD_20_MODE); 1098ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1099ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1100ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1101ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1102ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1103ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1104ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 1105ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1106ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 1107ff984e57SWei WANG break; 1108ff984e57SWei WANG 1109ff984e57SWei WANG default: 1110ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1111ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 1112ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1113ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1114ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1115ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1116ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1117ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1118ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 1119ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1120ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 1121ff984e57SWei WANG break; 1122ff984e57SWei WANG } 1123ff984e57SWei WANG 1124ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 1125ff984e57SWei WANG 1126ff984e57SWei WANG return err; 1127ff984e57SWei WANG } 1128ff984e57SWei WANG 1129ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1130ff984e57SWei WANG { 1131ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1132ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1133ff984e57SWei WANG 1134ff984e57SWei WANG if (host->eject) 1135ff984e57SWei WANG return; 1136ff984e57SWei WANG 1137c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 1138c3481955SWei WANG return; 1139c3481955SWei WANG 1140ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1141ff984e57SWei WANG 1142ff984e57SWei WANG rtsx_pci_start_run(pcr); 1143ff984e57SWei WANG 1144ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 1145ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 114684d72f9cSWei WANG sd_set_timing(host, ios->timing); 1147ff984e57SWei WANG 1148ff984e57SWei WANG host->vpclk = false; 1149ff984e57SWei WANG host->double_clk = true; 1150ff984e57SWei WANG 1151ff984e57SWei WANG switch (ios->timing) { 1152ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1153ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1154ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 1155ff984e57SWei WANG host->vpclk = true; 1156ff984e57SWei WANG host->double_clk = false; 1157ff984e57SWei WANG break; 1158ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1159ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 1160ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 1161ff984e57SWei WANG break; 1162ff984e57SWei WANG default: 1163ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 1164ff984e57SWei WANG break; 1165ff984e57SWei WANG } 1166ff984e57SWei WANG 1167ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 1168ff984e57SWei WANG 1169ff984e57SWei WANG host->clock = ios->clock; 1170ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 1171ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 1172ff984e57SWei WANG 1173ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1174ff984e57SWei WANG } 1175ff984e57SWei WANG 1176ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 1177ff984e57SWei WANG { 1178ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1179ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1180ff984e57SWei WANG int ro = 0; 1181ff984e57SWei WANG u32 val; 1182ff984e57SWei WANG 1183ff984e57SWei WANG if (host->eject) 1184ff984e57SWei WANG return -ENOMEDIUM; 1185ff984e57SWei WANG 1186ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1187ff984e57SWei WANG 1188ff984e57SWei WANG rtsx_pci_start_run(pcr); 1189ff984e57SWei WANG 1190ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 1191ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 1192ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1193ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 1194ff984e57SWei WANG ro = 1; 1195ff984e57SWei WANG 1196ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1197ff984e57SWei WANG 1198ff984e57SWei WANG return ro; 1199ff984e57SWei WANG } 1200ff984e57SWei WANG 1201ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 1202ff984e57SWei WANG { 1203ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1204ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1205ff984e57SWei WANG int cd = 0; 1206ff984e57SWei WANG u32 val; 1207ff984e57SWei WANG 1208ff984e57SWei WANG if (host->eject) 1209ff984e57SWei WANG return -ENOMEDIUM; 1210ff984e57SWei WANG 1211ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1212ff984e57SWei WANG 1213ff984e57SWei WANG rtsx_pci_start_run(pcr); 1214ff984e57SWei WANG 1215ff984e57SWei WANG /* Check SD card detect */ 1216ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 1217ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1218ff984e57SWei WANG if (val & SD_EXIST) 1219ff984e57SWei WANG cd = 1; 1220ff984e57SWei WANG 1221ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1222ff984e57SWei WANG 1223ff984e57SWei WANG return cd; 1224ff984e57SWei WANG } 1225ff984e57SWei WANG 1226ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1227ff984e57SWei WANG { 1228ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1229ff984e57SWei WANG int err; 1230ff984e57SWei WANG u8 stat; 1231ff984e57SWei WANG 1232ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 1233ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 1234ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 1235ff984e57SWei WANG */ 1236ff984e57SWei WANG mdelay(1); 1237ff984e57SWei WANG 1238ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1239ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 1240ff984e57SWei WANG * abort the voltage switch sequence; 1241ff984e57SWei WANG */ 1242ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1243ff984e57SWei WANG if (err < 0) 1244ff984e57SWei WANG return err; 1245ff984e57SWei WANG 1246ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1247ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 1248ff984e57SWei WANG return -EINVAL; 1249ff984e57SWei WANG 1250ff984e57SWei WANG /* Stop toggle SD clock */ 1251ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1252ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 1253ff984e57SWei WANG if (err < 0) 1254ff984e57SWei WANG return err; 1255ff984e57SWei WANG 1256ff984e57SWei WANG return 0; 1257ff984e57SWei WANG } 1258ff984e57SWei WANG 1259ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1260ff984e57SWei WANG { 1261ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1262ff984e57SWei WANG int err; 1263ff984e57SWei WANG u8 stat, mask, val; 1264ff984e57SWei WANG 1265ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1266ff984e57SWei WANG msleep(50); 1267ff984e57SWei WANG 1268ff984e57SWei WANG /* Toggle SD clock again */ 1269ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1270ff984e57SWei WANG if (err < 0) 1271ff984e57SWei WANG return err; 1272ff984e57SWei WANG 1273ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1274ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1275ff984e57SWei WANG */ 1276ff984e57SWei WANG msleep(20); 1277ff984e57SWei WANG 1278ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1279ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1280ff984e57SWei WANG if (err < 0) 1281ff984e57SWei WANG return err; 1282ff984e57SWei WANG 1283ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1284ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1285ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1286ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1287ff984e57SWei WANG if ((stat & mask) != val) { 1288ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1289ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1290ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1291ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1292ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1293ff984e57SWei WANG return -EINVAL; 1294ff984e57SWei WANG } 1295ff984e57SWei WANG 1296ff984e57SWei WANG return 0; 1297ff984e57SWei WANG } 1298ff984e57SWei WANG 1299ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1300ff984e57SWei WANG { 1301ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1302ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1303ff984e57SWei WANG int err = 0; 1304ff984e57SWei WANG u8 voltage; 1305ff984e57SWei WANG 1306ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1307ff984e57SWei WANG __func__, ios->signal_voltage); 1308ff984e57SWei WANG 1309ff984e57SWei WANG if (host->eject) 1310ff984e57SWei WANG return -ENOMEDIUM; 1311ff984e57SWei WANG 1312c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1313c3481955SWei WANG if (err) 1314c3481955SWei WANG return err; 1315c3481955SWei WANG 1316ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1317ff984e57SWei WANG 1318ff984e57SWei WANG rtsx_pci_start_run(pcr); 1319ff984e57SWei WANG 1320ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1321ef85e736SWei WANG voltage = OUTPUT_3V3; 1322ff984e57SWei WANG else 1323ef85e736SWei WANG voltage = OUTPUT_1V8; 1324ff984e57SWei WANG 1325ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1326ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1327ff984e57SWei WANG if (err < 0) 1328ff984e57SWei WANG goto out; 1329ff984e57SWei WANG } 1330ff984e57SWei WANG 1331ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1332ff984e57SWei WANG if (err < 0) 1333ff984e57SWei WANG goto out; 1334ff984e57SWei WANG 1335ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1336ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1337ff984e57SWei WANG if (err < 0) 1338ff984e57SWei WANG goto out; 1339ff984e57SWei WANG } 1340ff984e57SWei WANG 13411b8055b4SWei WANG out: 1342ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1343ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1344ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1345ff984e57SWei WANG 1346ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1347ff984e57SWei WANG 1348ff984e57SWei WANG return err; 1349ff984e57SWei WANG } 1350ff984e57SWei WANG 1351ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1352ff984e57SWei WANG { 1353ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1354ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1355ff984e57SWei WANG int err = 0; 1356ff984e57SWei WANG 1357ff984e57SWei WANG if (host->eject) 1358ff984e57SWei WANG return -ENOMEDIUM; 1359ff984e57SWei WANG 1360c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1361c3481955SWei WANG if (err) 1362c3481955SWei WANG return err; 1363c3481955SWei WANG 1364ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1365ff984e57SWei WANG 1366ff984e57SWei WANG rtsx_pci_start_run(pcr); 1367ff984e57SWei WANG 136884d72f9cSWei WANG /* Set initial TX phase */ 136984d72f9cSWei WANG switch (mmc->ios.timing) { 137084d72f9cSWei WANG case MMC_TIMING_UHS_SDR104: 137184d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 137284d72f9cSWei WANG break; 1373ff984e57SWei WANG 137484d72f9cSWei WANG case MMC_TIMING_UHS_SDR50: 137584d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 137684d72f9cSWei WANG break; 137784d72f9cSWei WANG 137884d72f9cSWei WANG case MMC_TIMING_UHS_DDR50: 137984d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 138084d72f9cSWei WANG break; 138184d72f9cSWei WANG 138284d72f9cSWei WANG default: 138384d72f9cSWei WANG err = 0; 138484d72f9cSWei WANG } 138584d72f9cSWei WANG 138684d72f9cSWei WANG if (err) 138784d72f9cSWei WANG goto out; 138884d72f9cSWei WANG 138984d72f9cSWei WANG /* Tuning RX phase */ 139084d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 139184d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 139284d72f9cSWei WANG err = sd_tuning_rx(host, opcode); 139384d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 139484d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 139584d72f9cSWei WANG 139684d72f9cSWei WANG out: 1397ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1398ff984e57SWei WANG 1399ff984e57SWei WANG return err; 1400ff984e57SWei WANG } 1401ff984e57SWei WANG 1402ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 1403c42deffdSMicky Ching .pre_req = sdmmc_pre_req, 1404c42deffdSMicky Ching .post_req = sdmmc_post_req, 1405ff984e57SWei WANG .request = sdmmc_request, 1406ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1407ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1408ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1409ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1410ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 1411ff984e57SWei WANG }; 1412ff984e57SWei WANG 1413ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1414ff984e57SWei WANG { 1415ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1416ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1417ff984e57SWei WANG 1418ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1419ff984e57SWei WANG 1420ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1421ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1422ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1423ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1424ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1425ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1426ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1427ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1428ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1429ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1430ff984e57SWei WANG } 1431ff984e57SWei WANG 1432ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1433ff984e57SWei WANG { 1434ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1435ff984e57SWei WANG 1436ff984e57SWei WANG mmc->f_min = 250000; 1437ff984e57SWei WANG mmc->f_max = 208000000; 1438ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1439ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1440ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1441ff984e57SWei WANG MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1442ff984e57SWei WANG mmc->max_current_330 = 400; 1443ff984e57SWei WANG mmc->max_current_180 = 800; 1444ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1445ff984e57SWei WANG 1446ff984e57SWei WANG init_extra_caps(host); 1447ff984e57SWei WANG 1448ff984e57SWei WANG mmc->max_segs = 256; 1449ff984e57SWei WANG mmc->max_seg_size = 65536; 1450ff984e57SWei WANG mmc->max_blk_size = 512; 1451ff984e57SWei WANG mmc->max_blk_count = 65535; 1452ff984e57SWei WANG mmc->max_req_size = 524288; 1453ff984e57SWei WANG } 1454ff984e57SWei WANG 1455ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1456ff984e57SWei WANG { 1457ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1458ff984e57SWei WANG 1459ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1460ff984e57SWei WANG } 1461ff984e57SWei WANG 1462ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1463ff984e57SWei WANG { 1464ff984e57SWei WANG struct mmc_host *mmc; 1465ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1466ff984e57SWei WANG struct rtsx_pcr *pcr; 1467ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1468c42deffdSMicky Ching unsigned long host_addr; 1469ff984e57SWei WANG 1470ff984e57SWei WANG if (!handle) 1471ff984e57SWei WANG return -ENXIO; 1472ff984e57SWei WANG 1473ff984e57SWei WANG pcr = handle->pcr; 1474ff984e57SWei WANG if (!pcr) 1475ff984e57SWei WANG return -ENXIO; 1476ff984e57SWei WANG 1477ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1478ff984e57SWei WANG 1479ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1480ff984e57SWei WANG if (!mmc) 1481ff984e57SWei WANG return -ENOMEM; 1482ff984e57SWei WANG 1483ff984e57SWei WANG host = mmc_priv(mmc); 1484ff984e57SWei WANG host->pcr = pcr; 1485ff984e57SWei WANG host->mmc = mmc; 1486ff984e57SWei WANG host->pdev = pdev; 1487d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 1488ff984e57SWei WANG platform_set_drvdata(pdev, host); 1489ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1490ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1491ff984e57SWei WANG 1492c42deffdSMicky Ching host_addr = (unsigned long)host; 1493c42deffdSMicky Ching host->next_data.cookie = 1; 1494c42deffdSMicky Ching setup_timer(&host->timer, sd_request_timeout, host_addr); 1495c42deffdSMicky Ching tasklet_init(&host->cmd_tasklet, sd_get_rsp, host_addr); 1496c42deffdSMicky Ching tasklet_init(&host->data_tasklet, sd_finish_multi_rw, host_addr); 1497c42deffdSMicky Ching tasklet_init(&host->finish_tasklet, sd_finish_request, host_addr); 1498c42deffdSMicky Ching spin_lock_init(&host->lock); 1499ff984e57SWei WANG 1500c42deffdSMicky Ching pcr->slots[RTSX_SD_CARD].done_transfer = sd_isr_done_transfer; 1501ff984e57SWei WANG realtek_init_host(host); 1502ff984e57SWei WANG 1503ff984e57SWei WANG mmc_add_host(mmc); 1504ff984e57SWei WANG 1505ff984e57SWei WANG return 0; 1506ff984e57SWei WANG } 1507ff984e57SWei WANG 1508ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1509ff984e57SWei WANG { 1510ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1511ff984e57SWei WANG struct rtsx_pcr *pcr; 1512ff984e57SWei WANG struct mmc_host *mmc; 1513c42deffdSMicky Ching struct mmc_request *mrq; 1514c42deffdSMicky Ching unsigned long flags; 1515ff984e57SWei WANG 1516ff984e57SWei WANG if (!host) 1517ff984e57SWei WANG return 0; 1518ff984e57SWei WANG 1519ff984e57SWei WANG pcr = host->pcr; 1520ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1521ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1522c42deffdSMicky Ching pcr->slots[RTSX_SD_CARD].done_transfer = NULL; 1523ff984e57SWei WANG mmc = host->mmc; 1524c42deffdSMicky Ching mrq = host->mrq; 1525ff984e57SWei WANG 1526c42deffdSMicky Ching spin_lock_irqsave(&host->lock, flags); 1527ff984e57SWei WANG if (host->mrq) { 1528ff984e57SWei WANG dev_dbg(&(pdev->dev), 1529ff984e57SWei WANG "%s: Controller removed during transfer\n", 1530ff984e57SWei WANG mmc_hostname(mmc)); 1531ff984e57SWei WANG 1532c42deffdSMicky Ching if (mrq->sbc) 1533c42deffdSMicky Ching mrq->sbc->error = -ENOMEDIUM; 1534c42deffdSMicky Ching if (mrq->cmd) 1535c42deffdSMicky Ching mrq->cmd->error = -ENOMEDIUM; 1536c42deffdSMicky Ching if (mrq->stop) 1537c42deffdSMicky Ching mrq->stop->error = -ENOMEDIUM; 1538c42deffdSMicky Ching if (mrq->data) 1539c42deffdSMicky Ching mrq->data->error = -ENOMEDIUM; 1540ff984e57SWei WANG 1541c42deffdSMicky Ching tasklet_schedule(&host->finish_tasklet); 1542ff984e57SWei WANG } 1543c42deffdSMicky Ching spin_unlock_irqrestore(&host->lock, flags); 1544c42deffdSMicky Ching 1545c42deffdSMicky Ching del_timer_sync(&host->timer); 1546c42deffdSMicky Ching tasklet_kill(&host->cmd_tasklet); 1547c42deffdSMicky Ching tasklet_kill(&host->data_tasklet); 1548c42deffdSMicky Ching tasklet_kill(&host->finish_tasklet); 1549ff984e57SWei WANG 1550ff984e57SWei WANG mmc_remove_host(mmc); 1551640e09bcSMicky Ching host->eject = true; 1552640e09bcSMicky Ching 1553ff984e57SWei WANG mmc_free_host(mmc); 1554ff984e57SWei WANG 1555ff984e57SWei WANG dev_dbg(&(pdev->dev), 1556ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1557ff984e57SWei WANG 1558ff984e57SWei WANG return 0; 1559ff984e57SWei WANG } 1560ff984e57SWei WANG 1561ff984e57SWei WANG static struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1562ff984e57SWei WANG { 1563ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1564ff984e57SWei WANG }, { 1565ff984e57SWei WANG /* sentinel */ 1566ff984e57SWei WANG } 1567ff984e57SWei WANG }; 1568ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1569ff984e57SWei WANG 1570ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1571ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1572ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1573ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1574ff984e57SWei WANG .driver = { 1575ff984e57SWei WANG .owner = THIS_MODULE, 1576ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1577ff984e57SWei WANG }, 1578ff984e57SWei WANG }; 1579ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1580ff984e57SWei WANG 1581ff984e57SWei WANG MODULE_LICENSE("GPL"); 1582ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1583ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1584