1ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 2ff984e57SWei WANG * 362282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4ff984e57SWei WANG * 5ff984e57SWei WANG * This program is free software; you can redistribute it and/or modify it 6ff984e57SWei WANG * under the terms of the GNU General Public License as published by the 7ff984e57SWei WANG * Free Software Foundation; either version 2, or (at your option) any 8ff984e57SWei WANG * later version. 9ff984e57SWei WANG * 10ff984e57SWei WANG * This program is distributed in the hope that it will be useful, but 11ff984e57SWei WANG * WITHOUT ANY WARRANTY; without even the implied warranty of 12ff984e57SWei WANG * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13ff984e57SWei WANG * General Public License for more details. 14ff984e57SWei WANG * 15ff984e57SWei WANG * You should have received a copy of the GNU General Public License along 16ff984e57SWei WANG * with this program; if not, see <http://www.gnu.org/licenses/>. 17ff984e57SWei WANG * 18ff984e57SWei WANG * Author: 19ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 20ff984e57SWei WANG */ 21ff984e57SWei WANG 22ff984e57SWei WANG #include <linux/module.h> 23433e075cSWei WANG #include <linux/slab.h> 24ff984e57SWei WANG #include <linux/highmem.h> 25ff984e57SWei WANG #include <linux/delay.h> 26ff984e57SWei WANG #include <linux/platform_device.h> 276291e715SMicky Ching #include <linux/workqueue.h> 28ff984e57SWei WANG #include <linux/mmc/host.h> 29ff984e57SWei WANG #include <linux/mmc/mmc.h> 30ff984e57SWei WANG #include <linux/mmc/sd.h> 311dcb3579SMicky Ching #include <linux/mmc/sdio.h> 32ff984e57SWei WANG #include <linux/mmc/card.h> 33ff984e57SWei WANG #include <linux/mfd/rtsx_pci.h> 34ff984e57SWei WANG #include <asm/unaligned.h> 35ff984e57SWei WANG 36ff984e57SWei WANG struct realtek_pci_sdmmc { 37ff984e57SWei WANG struct platform_device *pdev; 38ff984e57SWei WANG struct rtsx_pcr *pcr; 39ff984e57SWei WANG struct mmc_host *mmc; 40ff984e57SWei WANG struct mmc_request *mrq; 416291e715SMicky Ching struct workqueue_struct *workq; 426291e715SMicky Ching #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" 43ff984e57SWei WANG 446291e715SMicky Ching struct work_struct work; 4598fcc576SMicky Ching struct mutex host_mutex; 46ff984e57SWei WANG 47ff984e57SWei WANG u8 ssc_depth; 48ff984e57SWei WANG unsigned int clock; 49ff984e57SWei WANG bool vpclk; 50ff984e57SWei WANG bool double_clk; 51ff984e57SWei WANG bool eject; 52ff984e57SWei WANG bool initial_mode; 53d88691beSWei WANG int power_state; 54d88691beSWei WANG #define SDMMC_POWER_ON 1 55d88691beSWei WANG #define SDMMC_POWER_OFF 0 566291e715SMicky Ching 576291e715SMicky Ching unsigned int sg_count; 586291e715SMicky Ching s32 cookie; 596291e715SMicky Ching unsigned int cookie_sg_count; 606291e715SMicky Ching bool using_cookie; 61ff984e57SWei WANG }; 62ff984e57SWei WANG 63ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 64ff984e57SWei WANG { 65ff984e57SWei WANG return &(host->pdev->dev); 66ff984e57SWei WANG } 67ff984e57SWei WANG 68ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 69ff984e57SWei WANG { 70ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 71ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 72ff984e57SWei WANG } 73ff984e57SWei WANG 74ff984e57SWei WANG #ifdef DEBUG 75755987f9SMicky Ching static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end) 76755987f9SMicky Ching { 77755987f9SMicky Ching u16 len = end - start + 1; 78755987f9SMicky Ching int i; 79755987f9SMicky Ching u8 data[8]; 80755987f9SMicky Ching 81755987f9SMicky Ching for (i = 0; i < len; i += 8) { 82755987f9SMicky Ching int j; 83755987f9SMicky Ching int n = min(8, len - i); 84755987f9SMicky Ching 85755987f9SMicky Ching memset(&data, 0, sizeof(data)); 86755987f9SMicky Ching for (j = 0; j < n; j++) 87755987f9SMicky Ching rtsx_pci_read_register(host->pcr, start + i + j, 88755987f9SMicky Ching data + j); 89755987f9SMicky Ching dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n", 90755987f9SMicky Ching start + i, n, data); 91755987f9SMicky Ching } 92755987f9SMicky Ching } 93755987f9SMicky Ching 94ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 95ff984e57SWei WANG { 96755987f9SMicky Ching dump_reg_range(host, 0xFDA0, 0xFDB3); 97755987f9SMicky Ching dump_reg_range(host, 0xFD52, 0xFD69); 98ff984e57SWei WANG } 99ff984e57SWei WANG #else 100ff984e57SWei WANG #define sd_print_debug_regs(host) 101ff984e57SWei WANG #endif /* DEBUG */ 102ff984e57SWei WANG 103b22217f9SMicky Ching static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host) 104b22217f9SMicky Ching { 105b22217f9SMicky Ching return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST; 106b22217f9SMicky Ching } 107b22217f9SMicky Ching 1082d48e5f1SMicky Ching static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd) 1092d48e5f1SMicky Ching { 1102d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 1112d48e5f1SMicky Ching SD_CMD_START | cmd->opcode); 1122d48e5f1SMicky Ching rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg); 1132d48e5f1SMicky Ching } 1142d48e5f1SMicky Ching 1152d48e5f1SMicky Ching static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz) 1162d48e5f1SMicky Ching { 1172d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); 1182d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); 1192d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); 1202d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); 1212d48e5f1SMicky Ching } 1222d48e5f1SMicky Ching 1232d48e5f1SMicky Ching static int sd_response_type(struct mmc_command *cmd) 1242d48e5f1SMicky Ching { 1252d48e5f1SMicky Ching switch (mmc_resp_type(cmd)) { 1262d48e5f1SMicky Ching case MMC_RSP_NONE: 1272d48e5f1SMicky Ching return SD_RSP_TYPE_R0; 1282d48e5f1SMicky Ching case MMC_RSP_R1: 1292d48e5f1SMicky Ching return SD_RSP_TYPE_R1; 1302d48e5f1SMicky Ching case MMC_RSP_R1 & ~MMC_RSP_CRC: 1312d48e5f1SMicky Ching return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; 1322d48e5f1SMicky Ching case MMC_RSP_R1B: 1332d48e5f1SMicky Ching return SD_RSP_TYPE_R1b; 1342d48e5f1SMicky Ching case MMC_RSP_R2: 1352d48e5f1SMicky Ching return SD_RSP_TYPE_R2; 1362d48e5f1SMicky Ching case MMC_RSP_R3: 1372d48e5f1SMicky Ching return SD_RSP_TYPE_R3; 1382d48e5f1SMicky Ching default: 1392d48e5f1SMicky Ching return -EINVAL; 1402d48e5f1SMicky Ching } 1412d48e5f1SMicky Ching } 1422d48e5f1SMicky Ching 1432d48e5f1SMicky Ching static int sd_status_index(int resp_type) 1442d48e5f1SMicky Ching { 1452d48e5f1SMicky Ching if (resp_type == SD_RSP_TYPE_R0) 1462d48e5f1SMicky Ching return 0; 1472d48e5f1SMicky Ching else if (resp_type == SD_RSP_TYPE_R2) 1482d48e5f1SMicky Ching return 16; 1492d48e5f1SMicky Ching 1502d48e5f1SMicky Ching return 5; 1512d48e5f1SMicky Ching } 1526291e715SMicky Ching /* 1536291e715SMicky Ching * sd_pre_dma_transfer - do dma_map_sg() or using cookie 1546291e715SMicky Ching * 1556291e715SMicky Ching * @pre: if called in pre_req() 1566291e715SMicky Ching * return: 1576291e715SMicky Ching * 0 - do dma_map_sg() 1586291e715SMicky Ching * 1 - using cookie 1596291e715SMicky Ching */ 1606291e715SMicky Ching static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, 1616291e715SMicky Ching struct mmc_data *data, bool pre) 1626291e715SMicky Ching { 1636291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 1646291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 1656291e715SMicky Ching int count = 0; 1666291e715SMicky Ching int using_cookie = 0; 1676291e715SMicky Ching 1686291e715SMicky Ching if (!pre && data->host_cookie && data->host_cookie != host->cookie) { 1696291e715SMicky Ching dev_err(sdmmc_dev(host), 1706291e715SMicky Ching "error: data->host_cookie = %d, host->cookie = %d\n", 1716291e715SMicky Ching data->host_cookie, host->cookie); 1726291e715SMicky Ching data->host_cookie = 0; 1736291e715SMicky Ching } 1746291e715SMicky Ching 1756291e715SMicky Ching if (pre || data->host_cookie != host->cookie) { 1766291e715SMicky Ching count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); 1776291e715SMicky Ching } else { 1786291e715SMicky Ching count = host->cookie_sg_count; 1796291e715SMicky Ching using_cookie = 1; 1806291e715SMicky Ching } 1816291e715SMicky Ching 1826291e715SMicky Ching if (pre) { 1836291e715SMicky Ching host->cookie_sg_count = count; 1846291e715SMicky Ching if (++host->cookie < 0) 1856291e715SMicky Ching host->cookie = 1; 1866291e715SMicky Ching data->host_cookie = host->cookie; 1876291e715SMicky Ching } else { 1886291e715SMicky Ching host->sg_count = count; 1896291e715SMicky Ching } 1906291e715SMicky Ching 1916291e715SMicky Ching return using_cookie; 1926291e715SMicky Ching } 1936291e715SMicky Ching 1946291e715SMicky Ching static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 1956291e715SMicky Ching bool is_first_req) 1966291e715SMicky Ching { 1976291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1986291e715SMicky Ching struct mmc_data *data = mrq->data; 1996291e715SMicky Ching 2006291e715SMicky Ching if (data->host_cookie) { 2016291e715SMicky Ching dev_err(sdmmc_dev(host), 2026291e715SMicky Ching "error: reset data->host_cookie = %d\n", 2036291e715SMicky Ching data->host_cookie); 2046291e715SMicky Ching data->host_cookie = 0; 2056291e715SMicky Ching } 2066291e715SMicky Ching 2076291e715SMicky Ching sd_pre_dma_transfer(host, data, true); 2086291e715SMicky Ching dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); 2096291e715SMicky Ching } 2106291e715SMicky Ching 2116291e715SMicky Ching static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2126291e715SMicky Ching int err) 2136291e715SMicky Ching { 2146291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 2156291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 2166291e715SMicky Ching struct mmc_data *data = mrq->data; 2176291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 2186291e715SMicky Ching 2196291e715SMicky Ching rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); 2206291e715SMicky Ching data->host_cookie = 0; 2216291e715SMicky Ching } 2226291e715SMicky Ching 22398fcc576SMicky Ching static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 22498fcc576SMicky Ching struct mmc_command *cmd) 225ff984e57SWei WANG { 226ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 227ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 228ff984e57SWei WANG u32 arg = cmd->arg; 229ff984e57SWei WANG int err = 0; 230ff984e57SWei WANG int timeout = 100; 231ff984e57SWei WANG int i; 23298fcc576SMicky Ching u8 *ptr; 2332d48e5f1SMicky Ching int rsp_type; 2342d48e5f1SMicky Ching int stat_idx; 23598fcc576SMicky Ching bool clock_toggled = false; 236ff984e57SWei WANG 237ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 238ff984e57SWei WANG __func__, cmd_idx, arg); 239ff984e57SWei WANG 2402d48e5f1SMicky Ching rsp_type = sd_response_type(cmd); 2412d48e5f1SMicky Ching if (rsp_type < 0) 242ff984e57SWei WANG goto out; 2432d48e5f1SMicky Ching 2442d48e5f1SMicky Ching stat_idx = sd_status_index(rsp_type); 245ff984e57SWei WANG 246ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 247ff984e57SWei WANG timeout = 3000; 248ff984e57SWei WANG 249ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 250ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 251ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 252ff984e57SWei WANG if (err < 0) 253ff984e57SWei WANG goto out; 25498fcc576SMicky Ching 25598fcc576SMicky Ching clock_toggled = true; 256ff984e57SWei WANG } 257ff984e57SWei WANG 258ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 2592d48e5f1SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 260ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 261ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 262ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 263ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 264ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 265ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 266ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 267ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 268ff984e57SWei WANG 269ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 270ff984e57SWei WANG /* Read data from ping-pong buffer */ 271ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 272ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 273ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 274ff984e57SWei WANG /* Read data from SD_CMDx registers */ 275ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 276ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 277ff984e57SWei WANG } 278ff984e57SWei WANG 279ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 280ff984e57SWei WANG 28198fcc576SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 28298fcc576SMicky Ching if (err < 0) { 28398fcc576SMicky Ching sd_print_debug_regs(host); 28498fcc576SMicky Ching sd_clear_error(host); 28598fcc576SMicky Ching dev_dbg(sdmmc_dev(host), 28698fcc576SMicky Ching "rtsx_pci_send_cmd error (err = %d)\n", err); 287ff984e57SWei WANG goto out; 288ff984e57SWei WANG } 289ff984e57SWei WANG 290ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 291ff984e57SWei WANG err = 0; 292ff984e57SWei WANG goto out; 293ff984e57SWei WANG } 294ff984e57SWei WANG 295ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 296ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 297ff984e57SWei WANG 298ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 299ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 300ff984e57SWei WANG err = -EILSEQ; 301ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 302ff984e57SWei WANG goto out; 303ff984e57SWei WANG } 304ff984e57SWei WANG 305ff984e57SWei WANG /* Check CRC7 */ 306ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 307ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 308ff984e57SWei WANG err = -EILSEQ; 309ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 310ff984e57SWei WANG goto out; 311ff984e57SWei WANG } 312ff984e57SWei WANG } 313ff984e57SWei WANG 314ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 315d1419d50SRoger Tseng /* 316d1419d50SRoger Tseng * The controller offloads the last byte {CRC-7, end bit 1'b1} 317d1419d50SRoger Tseng * of response type R2. Assign dummy CRC, 0, and end bit to the 318d1419d50SRoger Tseng * byte(ptr[16], goes into the LSB of resp[3] later). 319d1419d50SRoger Tseng */ 320d1419d50SRoger Tseng ptr[16] = 1; 321d1419d50SRoger Tseng 322ff984e57SWei WANG for (i = 0; i < 4; i++) { 323ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 324ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 325ff984e57SWei WANG i, cmd->resp[i]); 326ff984e57SWei WANG } 327ff984e57SWei WANG } else { 328ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 329ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 330ff984e57SWei WANG cmd->resp[0]); 331ff984e57SWei WANG } 332ff984e57SWei WANG 333ff984e57SWei WANG out: 334ff984e57SWei WANG cmd->error = err; 3351b8055b4SWei WANG 33698fcc576SMicky Ching if (err && clock_toggled) 33798fcc576SMicky Ching rtsx_pci_write_register(pcr, SD_BUS_STAT, 33898fcc576SMicky Ching SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 339ff984e57SWei WANG } 340ff984e57SWei WANG 34156d1c0d9SMicky Ching static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd, 34256d1c0d9SMicky Ching u16 byte_cnt, u8 *buf, int buf_len, int timeout) 34356d1c0d9SMicky Ching { 34456d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr; 34556d1c0d9SMicky Ching int err; 34656d1c0d9SMicky Ching u8 trans_mode; 34756d1c0d9SMicky Ching 34856d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 34956d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg); 35056d1c0d9SMicky Ching 35156d1c0d9SMicky Ching if (!buf) 35256d1c0d9SMicky Ching buf_len = 0; 35356d1c0d9SMicky Ching 35456d1c0d9SMicky Ching if (cmd->opcode == MMC_SEND_TUNING_BLOCK) 35556d1c0d9SMicky Ching trans_mode = SD_TM_AUTO_TUNING; 35656d1c0d9SMicky Ching else 35756d1c0d9SMicky Ching trans_mode = SD_TM_NORMAL_READ; 35856d1c0d9SMicky Ching 35956d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr); 36056d1c0d9SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 36156d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt); 36256d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 36356d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 36456d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 36556d1c0d9SMicky Ching if (trans_mode != SD_TM_AUTO_TUNING) 36656d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 36756d1c0d9SMicky Ching CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 36856d1c0d9SMicky Ching 36956d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 37056d1c0d9SMicky Ching 0xFF, trans_mode | SD_TRANSFER_START); 37156d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 37256d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 37356d1c0d9SMicky Ching 37456d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 37556d1c0d9SMicky Ching if (err < 0) { 37656d1c0d9SMicky Ching sd_print_debug_regs(host); 37756d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 37856d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err); 37956d1c0d9SMicky Ching return err; 38056d1c0d9SMicky Ching } 38156d1c0d9SMicky Ching 38256d1c0d9SMicky Ching if (buf && buf_len) { 38356d1c0d9SMicky Ching err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 38456d1c0d9SMicky Ching if (err < 0) { 38556d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 38656d1c0d9SMicky Ching "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 38756d1c0d9SMicky Ching return err; 38856d1c0d9SMicky Ching } 38956d1c0d9SMicky Ching } 39056d1c0d9SMicky Ching 39156d1c0d9SMicky Ching return 0; 39256d1c0d9SMicky Ching } 39356d1c0d9SMicky Ching 39456d1c0d9SMicky Ching static int sd_write_data(struct realtek_pci_sdmmc *host, 39556d1c0d9SMicky Ching struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len, 39656d1c0d9SMicky Ching int timeout) 39756d1c0d9SMicky Ching { 39856d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr; 39956d1c0d9SMicky Ching int err; 40056d1c0d9SMicky Ching 40156d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 40256d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg); 40356d1c0d9SMicky Ching 40456d1c0d9SMicky Ching if (!buf) 40556d1c0d9SMicky Ching buf_len = 0; 40656d1c0d9SMicky Ching 40756d1c0d9SMicky Ching sd_send_cmd_get_rsp(host, cmd); 40856d1c0d9SMicky Ching if (cmd->error) 40956d1c0d9SMicky Ching return cmd->error; 41056d1c0d9SMicky Ching 41156d1c0d9SMicky Ching if (buf && buf_len) { 41256d1c0d9SMicky Ching err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 41356d1c0d9SMicky Ching if (err < 0) { 41456d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 41556d1c0d9SMicky Ching "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 41656d1c0d9SMicky Ching return err; 41756d1c0d9SMicky Ching } 41856d1c0d9SMicky Ching } 41956d1c0d9SMicky Ching 42056d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr); 42156d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt); 42256d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 42356d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 42456d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0); 42556d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 42656d1c0d9SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 42756d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 42856d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 42956d1c0d9SMicky Ching 43056d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 43156d1c0d9SMicky Ching if (err < 0) { 43256d1c0d9SMicky Ching sd_print_debug_regs(host); 43356d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 43456d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err); 43556d1c0d9SMicky Ching return err; 43656d1c0d9SMicky Ching } 43756d1c0d9SMicky Ching 43856d1c0d9SMicky Ching return 0; 43956d1c0d9SMicky Ching } 44056d1c0d9SMicky Ching 4411dcb3579SMicky Ching static int sd_read_long_data(struct realtek_pci_sdmmc *host, 4421dcb3579SMicky Ching struct mmc_request *mrq) 443ff984e57SWei WANG { 444ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 445ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 446ff984e57SWei WANG struct mmc_card *card = mmc->card; 4471dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd; 448ff984e57SWei WANG struct mmc_data *data = mrq->data; 44971ef1ea4SJackey Shen int uhs = mmc_card_uhs(card); 4501dcb3579SMicky Ching u8 cfg2 = 0; 451ff984e57SWei WANG int err; 4521dcb3579SMicky Ching int resp_type; 453ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 454ff984e57SWei WANG 4551dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 4561dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg); 4571dcb3579SMicky Ching 4581dcb3579SMicky Ching resp_type = sd_response_type(cmd); 4591dcb3579SMicky Ching if (resp_type < 0) 4601dcb3579SMicky Ching return resp_type; 461ff984e57SWei WANG 462ff984e57SWei WANG if (!uhs) 463ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 464ff984e57SWei WANG 465ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 4661dcb3579SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 4671dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 468ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 469ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 470ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 471ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 472ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 473ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 474ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 475ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 476ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 477ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 478ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 479ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 4801dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 4811dcb3579SMicky Ching 0x01, RING_BUFFER); 4821dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); 4831dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 4841dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_READ_2); 4851dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 4861dcb3579SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 4871dcb3579SMicky Ching rtsx_pci_send_cmd_no_wait(pcr); 4881dcb3579SMicky Ching 4891dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000); 4901dcb3579SMicky Ching if (err < 0) { 4911dcb3579SMicky Ching sd_print_debug_regs(host); 4921dcb3579SMicky Ching sd_clear_error(host); 4931dcb3579SMicky Ching return err; 4941dcb3579SMicky Ching } 4951dcb3579SMicky Ching 4961dcb3579SMicky Ching return 0; 4971dcb3579SMicky Ching } 4981dcb3579SMicky Ching 4991dcb3579SMicky Ching static int sd_write_long_data(struct realtek_pci_sdmmc *host, 5001dcb3579SMicky Ching struct mmc_request *mrq) 5011dcb3579SMicky Ching { 5021dcb3579SMicky Ching struct rtsx_pcr *pcr = host->pcr; 5031dcb3579SMicky Ching struct mmc_host *mmc = host->mmc; 5041dcb3579SMicky Ching struct mmc_card *card = mmc->card; 5051dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd; 5061dcb3579SMicky Ching struct mmc_data *data = mrq->data; 5071dcb3579SMicky Ching int uhs = mmc_card_uhs(card); 5081dcb3579SMicky Ching u8 cfg2; 5091dcb3579SMicky Ching int err; 5101dcb3579SMicky Ching size_t data_len = data->blksz * data->blocks; 5111dcb3579SMicky Ching 5121dcb3579SMicky Ching sd_send_cmd_get_rsp(host, cmd); 5131dcb3579SMicky Ching if (cmd->error) 5141dcb3579SMicky Ching return cmd->error; 5151dcb3579SMicky Ching 5161dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 5171dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg); 5181dcb3579SMicky Ching 5191dcb3579SMicky Ching cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 5201dcb3579SMicky Ching SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 5211dcb3579SMicky Ching 5221dcb3579SMicky Ching if (!uhs) 5231dcb3579SMicky Ching cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 5241dcb3579SMicky Ching 5251dcb3579SMicky Ching rtsx_pci_init_cmd(pcr); 5261dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 5271dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 5281dcb3579SMicky Ching DMA_DONE_INT, DMA_DONE_INT); 5291dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 5301dcb3579SMicky Ching 0xFF, (u8)(data_len >> 24)); 5311dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 5321dcb3579SMicky Ching 0xFF, (u8)(data_len >> 16)); 5331dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 5341dcb3579SMicky Ching 0xFF, (u8)(data_len >> 8)); 5351dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 536ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 537ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 538ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 539ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 540ff984e57SWei WANG 0x01, RING_BUFFER); 54138d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 542ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 5431dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 544ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 545ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 546ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 5471dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000); 548ff984e57SWei WANG if (err < 0) { 54998fcc576SMicky Ching sd_clear_error(host); 55098fcc576SMicky Ching return err; 551c42deffdSMicky Ching } 55298fcc576SMicky Ching 553c42deffdSMicky Ching return 0; 554ff984e57SWei WANG } 555ff984e57SWei WANG 5561dcb3579SMicky Ching static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 5571dcb3579SMicky Ching { 5581dcb3579SMicky Ching struct mmc_data *data = mrq->data; 5591dcb3579SMicky Ching 5601dcb3579SMicky Ching if (data->flags & MMC_DATA_READ) 5611dcb3579SMicky Ching return sd_read_long_data(host, mrq); 5621dcb3579SMicky Ching 5631dcb3579SMicky Ching return sd_write_long_data(host, mrq); 5641dcb3579SMicky Ching } 5651dcb3579SMicky Ching 566ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 567ff984e57SWei WANG { 568ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 569ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 570ff984e57SWei WANG } 571ff984e57SWei WANG 572ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 573ff984e57SWei WANG { 574ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 575ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 576ff984e57SWei WANG } 577ff984e57SWei WANG 578ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 579ff984e57SWei WANG struct mmc_request *mrq) 580ff984e57SWei WANG { 581ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 582ff984e57SWei WANG struct mmc_data *data = mrq->data; 5831dcb3579SMicky Ching u8 *buf; 584ff984e57SWei WANG 585ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 586ff984e57SWei WANG if (!buf) { 587ff984e57SWei WANG cmd->error = -ENOMEM; 588ff984e57SWei WANG return; 589ff984e57SWei WANG } 590ff984e57SWei WANG 591ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 592ff984e57SWei WANG if (host->initial_mode) 593ff984e57SWei WANG sd_disable_initial_mode(host); 594ff984e57SWei WANG 5951dcb3579SMicky Ching cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf, 596ff984e57SWei WANG data->blksz, 200); 597ff984e57SWei WANG 598ff984e57SWei WANG if (host->initial_mode) 599ff984e57SWei WANG sd_enable_initial_mode(host); 600ff984e57SWei WANG 601ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 602ff984e57SWei WANG } else { 603ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 604ff984e57SWei WANG 6051dcb3579SMicky Ching cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf, 606ff984e57SWei WANG data->blksz, 200); 607ff984e57SWei WANG } 608ff984e57SWei WANG 609ff984e57SWei WANG kfree(buf); 610ff984e57SWei WANG } 611ff984e57SWei WANG 61284d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, 61384d72f9cSWei WANG u8 sample_point, bool rx) 614ff984e57SWei WANG { 615ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 616ff984e57SWei WANG int err; 617ff984e57SWei WANG 61884d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 61984d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point); 620ff984e57SWei WANG 621ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 622ff984e57SWei WANG 623ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 62484d72f9cSWei WANG if (rx) 62584d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 62684d72f9cSWei WANG SD_VPRX_CTL, 0x1F, sample_point); 62784d72f9cSWei WANG else 62884d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 62984d72f9cSWei WANG SD_VPTX_CTL, 0x1F, sample_point); 630ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); 631ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 632ff984e57SWei WANG PHASE_NOT_RESET, PHASE_NOT_RESET); 633ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); 634ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 635ff984e57SWei WANG 636ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 637ff984e57SWei WANG if (err < 0) 638ff984e57SWei WANG return err; 639ff984e57SWei WANG 640ff984e57SWei WANG return 0; 641ff984e57SWei WANG } 642ff984e57SWei WANG 643abcc6b29SMicky Ching static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 644abcc6b29SMicky Ching { 645abcc6b29SMicky Ching bit %= RTSX_PHASE_MAX; 646abcc6b29SMicky Ching return phase_map & (1 << bit); 647abcc6b29SMicky Ching } 648abcc6b29SMicky Ching 649abcc6b29SMicky Ching static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 650abcc6b29SMicky Ching { 651abcc6b29SMicky Ching int i; 652abcc6b29SMicky Ching 653abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 654abcc6b29SMicky Ching if (test_phase_bit(phase_map, start_bit + i) == 0) 655abcc6b29SMicky Ching return i; 656abcc6b29SMicky Ching } 657abcc6b29SMicky Ching return RTSX_PHASE_MAX; 658abcc6b29SMicky Ching } 659abcc6b29SMicky Ching 660ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 661ff984e57SWei WANG { 662abcc6b29SMicky Ching int start = 0, len = 0; 663abcc6b29SMicky Ching int start_final = 0, len_final = 0; 664ff984e57SWei WANG u8 final_phase = 0xFF; 665ff984e57SWei WANG 666abcc6b29SMicky Ching if (phase_map == 0) { 667abcc6b29SMicky Ching dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 668abcc6b29SMicky Ching return final_phase; 669ff984e57SWei WANG } 670ff984e57SWei WANG 671abcc6b29SMicky Ching while (start < RTSX_PHASE_MAX) { 672abcc6b29SMicky Ching len = sd_get_phase_len(phase_map, start); 673abcc6b29SMicky Ching if (len_final < len) { 674abcc6b29SMicky Ching start_final = start; 675abcc6b29SMicky Ching len_final = len; 676abcc6b29SMicky Ching } 677abcc6b29SMicky Ching start += len ? len : 1; 678ff984e57SWei WANG } 679ff984e57SWei WANG 680abcc6b29SMicky Ching final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 681abcc6b29SMicky Ching dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 682abcc6b29SMicky Ching phase_map, len_final, final_phase); 683ff984e57SWei WANG 684ff984e57SWei WANG return final_phase; 685ff984e57SWei WANG } 686ff984e57SWei WANG 687ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 688ff984e57SWei WANG { 689ff984e57SWei WANG int err, i; 690ff984e57SWei WANG u8 val = 0; 691ff984e57SWei WANG 692ff984e57SWei WANG for (i = 0; i < 100; i++) { 693ff984e57SWei WANG err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 694ff984e57SWei WANG if (val & SD_DATA_IDLE) 695ff984e57SWei WANG return; 696ff984e57SWei WANG 697ff984e57SWei WANG udelay(100); 698ff984e57SWei WANG } 699ff984e57SWei WANG } 700ff984e57SWei WANG 701ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 702ff984e57SWei WANG u8 opcode, u8 sample_point) 703ff984e57SWei WANG { 704ff984e57SWei WANG int err; 7051dcb3579SMicky Ching struct mmc_command cmd = {0}; 706ff984e57SWei WANG 70784d72f9cSWei WANG err = sd_change_phase(host, sample_point, true); 708ff984e57SWei WANG if (err < 0) 709ff984e57SWei WANG return err; 710ff984e57SWei WANG 7111dcb3579SMicky Ching cmd.opcode = opcode; 7121dcb3579SMicky Ching err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100); 713ff984e57SWei WANG if (err < 0) { 714ff984e57SWei WANG /* Wait till SD DATA IDLE */ 715ff984e57SWei WANG sd_wait_data_idle(host); 716ff984e57SWei WANG sd_clear_error(host); 717ff984e57SWei WANG return err; 718ff984e57SWei WANG } 719ff984e57SWei WANG 720ff984e57SWei WANG return 0; 721ff984e57SWei WANG } 722ff984e57SWei WANG 723ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 724ff984e57SWei WANG u8 opcode, u32 *phase_map) 725ff984e57SWei WANG { 726ff984e57SWei WANG int err, i; 727ff984e57SWei WANG u32 raw_phase_map = 0; 728ff984e57SWei WANG 729abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 730ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 731ff984e57SWei WANG if (err == 0) 732ff984e57SWei WANG raw_phase_map |= 1 << i; 733ff984e57SWei WANG } 734ff984e57SWei WANG 735ff984e57SWei WANG if (phase_map) 736ff984e57SWei WANG *phase_map = raw_phase_map; 737ff984e57SWei WANG 738ff984e57SWei WANG return 0; 739ff984e57SWei WANG } 740ff984e57SWei WANG 741ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 742ff984e57SWei WANG { 743ff984e57SWei WANG int err, i; 744ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 745ff984e57SWei WANG u8 final_phase; 746ff984e57SWei WANG 747ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 748ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 749ff984e57SWei WANG if (err < 0) 750ff984e57SWei WANG return err; 751ff984e57SWei WANG 752ff984e57SWei WANG if (raw_phase_map[i] == 0) 753ff984e57SWei WANG break; 754ff984e57SWei WANG } 755ff984e57SWei WANG 756ff984e57SWei WANG phase_map = 0xFFFFFFFF; 757ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 758ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 759ff984e57SWei WANG i, raw_phase_map[i]); 760ff984e57SWei WANG phase_map &= raw_phase_map[i]; 761ff984e57SWei WANG } 762ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 763ff984e57SWei WANG 764ff984e57SWei WANG if (phase_map) { 765ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 766ff984e57SWei WANG if (final_phase == 0xFF) 767ff984e57SWei WANG return -EINVAL; 768ff984e57SWei WANG 76984d72f9cSWei WANG err = sd_change_phase(host, final_phase, true); 770ff984e57SWei WANG if (err < 0) 771ff984e57SWei WANG return err; 772ff984e57SWei WANG } else { 773ff984e57SWei WANG return -EINVAL; 774ff984e57SWei WANG } 775ff984e57SWei WANG 776ff984e57SWei WANG return 0; 777ff984e57SWei WANG } 778ff984e57SWei WANG 7791dcb3579SMicky Ching static inline int sdio_extblock_cmd(struct mmc_command *cmd, 7801dcb3579SMicky Ching struct mmc_data *data) 7811dcb3579SMicky Ching { 7821dcb3579SMicky Ching return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512); 7831dcb3579SMicky Ching } 7841dcb3579SMicky Ching 7856291e715SMicky Ching static inline int sd_rw_cmd(struct mmc_command *cmd) 786ff984e57SWei WANG { 7876291e715SMicky Ching return mmc_op_multi(cmd->opcode) || 7886291e715SMicky Ching (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 7896291e715SMicky Ching (cmd->opcode == MMC_WRITE_BLOCK); 7906291e715SMicky Ching } 7916291e715SMicky Ching 7926291e715SMicky Ching static void sd_request(struct work_struct *work) 7936291e715SMicky Ching { 7946291e715SMicky Ching struct realtek_pci_sdmmc *host = container_of(work, 7956291e715SMicky Ching struct realtek_pci_sdmmc, work); 796ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 7976291e715SMicky Ching 7986291e715SMicky Ching struct mmc_host *mmc = host->mmc; 7996291e715SMicky Ching struct mmc_request *mrq = host->mrq; 800ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 801ff984e57SWei WANG struct mmc_data *data = mrq->data; 8026291e715SMicky Ching 803ff984e57SWei WANG unsigned int data_size = 0; 804c3481955SWei WANG int err; 805ff984e57SWei WANG 806b22217f9SMicky Ching if (host->eject || !sd_get_cd_int(host)) { 807ff984e57SWei WANG cmd->error = -ENOMEDIUM; 808ff984e57SWei WANG goto finish; 809ff984e57SWei WANG } 810ff984e57SWei WANG 811c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 812c3481955SWei WANG if (err) { 813c3481955SWei WANG cmd->error = err; 814c3481955SWei WANG goto finish; 815c3481955SWei WANG } 816c3481955SWei WANG 81798fcc576SMicky Ching mutex_lock(&pcr->pcr_mutex); 81898fcc576SMicky Ching 819ff984e57SWei WANG rtsx_pci_start_run(pcr); 820ff984e57SWei WANG 821ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 822ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 823ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 824ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 825ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 826ff984e57SWei WANG 82798fcc576SMicky Ching mutex_lock(&host->host_mutex); 82898fcc576SMicky Ching host->mrq = mrq; 82998fcc576SMicky Ching mutex_unlock(&host->host_mutex); 83098fcc576SMicky Ching 831ff984e57SWei WANG if (mrq->data) 832ff984e57SWei WANG data_size = data->blocks * data->blksz; 833ff984e57SWei WANG 8341dcb3579SMicky Ching if (!data_size) { 83598fcc576SMicky Ching sd_send_cmd_get_rsp(host, cmd); 8361dcb3579SMicky Ching } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) { 8371dcb3579SMicky Ching cmd->error = sd_rw_multi(host, mrq); 8386291e715SMicky Ching if (!host->using_cookie) 8396291e715SMicky Ching sdmmc_post_req(host->mmc, host->mrq, 0); 84098fcc576SMicky Ching 84198fcc576SMicky Ching if (mmc_op_multi(cmd->opcode) && mrq->stop) 84298fcc576SMicky Ching sd_send_cmd_get_rsp(host, mrq->stop); 84398fcc576SMicky Ching } else { 84498fcc576SMicky Ching sd_normal_rw(host, mrq); 84598fcc576SMicky Ching } 84698fcc576SMicky Ching 84798fcc576SMicky Ching if (mrq->data) { 84898fcc576SMicky Ching if (cmd->error || data->error) 84998fcc576SMicky Ching data->bytes_xfered = 0; 85098fcc576SMicky Ching else 85198fcc576SMicky Ching data->bytes_xfered = data->blocks * data->blksz; 85298fcc576SMicky Ching } 85398fcc576SMicky Ching 85498fcc576SMicky Ching mutex_unlock(&pcr->pcr_mutex); 855ff984e57SWei WANG 856ff984e57SWei WANG finish: 8571dcb3579SMicky Ching if (cmd->error) { 8581dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n", 8591dcb3579SMicky Ching cmd->opcode, cmd->arg, cmd->error); 8601dcb3579SMicky Ching } 86198fcc576SMicky Ching 86298fcc576SMicky Ching mutex_lock(&host->host_mutex); 86398fcc576SMicky Ching host->mrq = NULL; 86498fcc576SMicky Ching mutex_unlock(&host->host_mutex); 86598fcc576SMicky Ching 86698fcc576SMicky Ching mmc_request_done(mmc, mrq); 867ff984e57SWei WANG } 868ff984e57SWei WANG 8696291e715SMicky Ching static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 8706291e715SMicky Ching { 8716291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 8726291e715SMicky Ching struct mmc_data *data = mrq->data; 8736291e715SMicky Ching 8746291e715SMicky Ching mutex_lock(&host->host_mutex); 8756291e715SMicky Ching host->mrq = mrq; 8766291e715SMicky Ching mutex_unlock(&host->host_mutex); 8776291e715SMicky Ching 8781dcb3579SMicky Ching if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data)) 8796291e715SMicky Ching host->using_cookie = sd_pre_dma_transfer(host, data, false); 8806291e715SMicky Ching 8816291e715SMicky Ching queue_work(host->workq, &host->work); 8826291e715SMicky Ching } 8836291e715SMicky Ching 884ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 885ff984e57SWei WANG unsigned char bus_width) 886ff984e57SWei WANG { 887ff984e57SWei WANG int err = 0; 888ff984e57SWei WANG u8 width[] = { 889ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 890ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 891ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 892ff984e57SWei WANG }; 893ff984e57SWei WANG 894ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 895ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 896ff984e57SWei WANG 0x03, width[bus_width]); 897ff984e57SWei WANG 898ff984e57SWei WANG return err; 899ff984e57SWei WANG } 900ff984e57SWei WANG 901ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 902ff984e57SWei WANG { 903ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 904ff984e57SWei WANG int err; 905ff984e57SWei WANG 906d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 907d88691beSWei WANG return 0; 908d88691beSWei WANG 909ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 910ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 911ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 912ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 913ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 914ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 915ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 916ff984e57SWei WANG if (err < 0) 917ff984e57SWei WANG return err; 918ff984e57SWei WANG 919ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 920ff984e57SWei WANG if (err < 0) 921ff984e57SWei WANG return err; 922ff984e57SWei WANG 923ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 924ff984e57SWei WANG if (err < 0) 925ff984e57SWei WANG return err; 926ff984e57SWei WANG 927ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 928ff984e57SWei WANG if (err < 0) 929ff984e57SWei WANG return err; 930ff984e57SWei WANG 931d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 932ff984e57SWei WANG return 0; 933ff984e57SWei WANG } 934ff984e57SWei WANG 935ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 936ff984e57SWei WANG { 937ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 938ff984e57SWei WANG int err; 939ff984e57SWei WANG 940d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 941d88691beSWei WANG 942ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 943ff984e57SWei WANG 944ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 945ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 946ff984e57SWei WANG 947ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 948ff984e57SWei WANG if (err < 0) 949ff984e57SWei WANG return err; 950ff984e57SWei WANG 951ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 952ff984e57SWei WANG if (err < 0) 953ff984e57SWei WANG return err; 954ff984e57SWei WANG 955ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 956ff984e57SWei WANG } 957ff984e57SWei WANG 958ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 959ff984e57SWei WANG unsigned char power_mode) 960ff984e57SWei WANG { 961ff984e57SWei WANG int err; 962ff984e57SWei WANG 963ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 964ff984e57SWei WANG err = sd_power_off(host); 965ff984e57SWei WANG else 966ff984e57SWei WANG err = sd_power_on(host); 967ff984e57SWei WANG 968ff984e57SWei WANG return err; 969ff984e57SWei WANG } 970ff984e57SWei WANG 97184d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 972ff984e57SWei WANG { 973ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 974ff984e57SWei WANG int err = 0; 975ff984e57SWei WANG 976ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 977ff984e57SWei WANG 978ff984e57SWei WANG switch (timing) { 979ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 980ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 981ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 982ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 983ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 984ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 985ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 986ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 987ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 988ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 989ff984e57SWei WANG break; 990ff984e57SWei WANG 9911a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 992ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 993ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 994ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 995ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 996ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 997ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 998ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 999ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 1000ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1001ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1002ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 1003ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1004ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 1005ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 1006ff984e57SWei WANG break; 1007ff984e57SWei WANG 1008ff984e57SWei WANG case MMC_TIMING_MMC_HS: 1009ff984e57SWei WANG case MMC_TIMING_SD_HS: 1010ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1011ff984e57SWei WANG 0x0C, SD_20_MODE); 1012ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1013ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1014ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1015ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1016ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1017ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1018ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 1019ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1020ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 1021ff984e57SWei WANG break; 1022ff984e57SWei WANG 1023ff984e57SWei WANG default: 1024ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1025ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 1026ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1027ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1028ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1029ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1030ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1031ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1032ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 1033ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1034ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 1035ff984e57SWei WANG break; 1036ff984e57SWei WANG } 1037ff984e57SWei WANG 1038ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 1039ff984e57SWei WANG 1040ff984e57SWei WANG return err; 1041ff984e57SWei WANG } 1042ff984e57SWei WANG 1043ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1044ff984e57SWei WANG { 1045ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1046ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1047ff984e57SWei WANG 1048ff984e57SWei WANG if (host->eject) 1049ff984e57SWei WANG return; 1050ff984e57SWei WANG 1051c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 1052c3481955SWei WANG return; 1053c3481955SWei WANG 1054ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1055ff984e57SWei WANG 1056ff984e57SWei WANG rtsx_pci_start_run(pcr); 1057ff984e57SWei WANG 1058ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 1059ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 106084d72f9cSWei WANG sd_set_timing(host, ios->timing); 1061ff984e57SWei WANG 1062ff984e57SWei WANG host->vpclk = false; 1063ff984e57SWei WANG host->double_clk = true; 1064ff984e57SWei WANG 1065ff984e57SWei WANG switch (ios->timing) { 1066ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1067ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1068ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 1069ff984e57SWei WANG host->vpclk = true; 1070ff984e57SWei WANG host->double_clk = false; 1071ff984e57SWei WANG break; 10721a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 1073ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1074ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 1075ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 1076ff984e57SWei WANG break; 1077ff984e57SWei WANG default: 1078ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 1079ff984e57SWei WANG break; 1080ff984e57SWei WANG } 1081ff984e57SWei WANG 1082ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 1083ff984e57SWei WANG 1084ff984e57SWei WANG host->clock = ios->clock; 1085ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 1086ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 1087ff984e57SWei WANG 1088ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1089ff984e57SWei WANG } 1090ff984e57SWei WANG 1091ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 1092ff984e57SWei WANG { 1093ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1094ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1095ff984e57SWei WANG int ro = 0; 1096ff984e57SWei WANG u32 val; 1097ff984e57SWei WANG 1098ff984e57SWei WANG if (host->eject) 1099ff984e57SWei WANG return -ENOMEDIUM; 1100ff984e57SWei WANG 1101ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1102ff984e57SWei WANG 1103ff984e57SWei WANG rtsx_pci_start_run(pcr); 1104ff984e57SWei WANG 1105ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 1106ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 1107ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1108ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 1109ff984e57SWei WANG ro = 1; 1110ff984e57SWei WANG 1111ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1112ff984e57SWei WANG 1113ff984e57SWei WANG return ro; 1114ff984e57SWei WANG } 1115ff984e57SWei WANG 1116ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 1117ff984e57SWei WANG { 1118ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1119ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1120ff984e57SWei WANG int cd = 0; 1121ff984e57SWei WANG u32 val; 1122ff984e57SWei WANG 1123ff984e57SWei WANG if (host->eject) 1124b22217f9SMicky Ching return cd; 1125ff984e57SWei WANG 1126ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1127ff984e57SWei WANG 1128ff984e57SWei WANG rtsx_pci_start_run(pcr); 1129ff984e57SWei WANG 1130ff984e57SWei WANG /* Check SD card detect */ 1131ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 1132ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1133ff984e57SWei WANG if (val & SD_EXIST) 1134ff984e57SWei WANG cd = 1; 1135ff984e57SWei WANG 1136ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1137ff984e57SWei WANG 1138ff984e57SWei WANG return cd; 1139ff984e57SWei WANG } 1140ff984e57SWei WANG 1141ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1142ff984e57SWei WANG { 1143ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1144ff984e57SWei WANG int err; 1145ff984e57SWei WANG u8 stat; 1146ff984e57SWei WANG 1147ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 1148ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 1149ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 1150ff984e57SWei WANG */ 1151ff984e57SWei WANG mdelay(1); 1152ff984e57SWei WANG 1153ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1154ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 1155ff984e57SWei WANG * abort the voltage switch sequence; 1156ff984e57SWei WANG */ 1157ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1158ff984e57SWei WANG if (err < 0) 1159ff984e57SWei WANG return err; 1160ff984e57SWei WANG 1161ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1162ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 1163ff984e57SWei WANG return -EINVAL; 1164ff984e57SWei WANG 1165ff984e57SWei WANG /* Stop toggle SD clock */ 1166ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1167ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 1168ff984e57SWei WANG if (err < 0) 1169ff984e57SWei WANG return err; 1170ff984e57SWei WANG 1171ff984e57SWei WANG return 0; 1172ff984e57SWei WANG } 1173ff984e57SWei WANG 1174ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1175ff984e57SWei WANG { 1176ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1177ff984e57SWei WANG int err; 1178ff984e57SWei WANG u8 stat, mask, val; 1179ff984e57SWei WANG 1180ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1181ff984e57SWei WANG msleep(50); 1182ff984e57SWei WANG 1183ff984e57SWei WANG /* Toggle SD clock again */ 1184ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1185ff984e57SWei WANG if (err < 0) 1186ff984e57SWei WANG return err; 1187ff984e57SWei WANG 1188ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1189ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1190ff984e57SWei WANG */ 1191ff984e57SWei WANG msleep(20); 1192ff984e57SWei WANG 1193ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1194ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1195ff984e57SWei WANG if (err < 0) 1196ff984e57SWei WANG return err; 1197ff984e57SWei WANG 1198ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1199ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1200ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1201ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1202ff984e57SWei WANG if ((stat & mask) != val) { 1203ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1204ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1205ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1206ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1207ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1208ff984e57SWei WANG return -EINVAL; 1209ff984e57SWei WANG } 1210ff984e57SWei WANG 1211ff984e57SWei WANG return 0; 1212ff984e57SWei WANG } 1213ff984e57SWei WANG 1214ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1215ff984e57SWei WANG { 1216ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1217ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1218ff984e57SWei WANG int err = 0; 1219ff984e57SWei WANG u8 voltage; 1220ff984e57SWei WANG 1221ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1222ff984e57SWei WANG __func__, ios->signal_voltage); 1223ff984e57SWei WANG 1224ff984e57SWei WANG if (host->eject) 1225ff984e57SWei WANG return -ENOMEDIUM; 1226ff984e57SWei WANG 1227c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1228c3481955SWei WANG if (err) 1229c3481955SWei WANG return err; 1230c3481955SWei WANG 1231ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1232ff984e57SWei WANG 1233ff984e57SWei WANG rtsx_pci_start_run(pcr); 1234ff984e57SWei WANG 1235ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1236ef85e736SWei WANG voltage = OUTPUT_3V3; 1237ff984e57SWei WANG else 1238ef85e736SWei WANG voltage = OUTPUT_1V8; 1239ff984e57SWei WANG 1240ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1241ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1242ff984e57SWei WANG if (err < 0) 1243ff984e57SWei WANG goto out; 1244ff984e57SWei WANG } 1245ff984e57SWei WANG 1246ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1247ff984e57SWei WANG if (err < 0) 1248ff984e57SWei WANG goto out; 1249ff984e57SWei WANG 1250ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1251ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1252ff984e57SWei WANG if (err < 0) 1253ff984e57SWei WANG goto out; 1254ff984e57SWei WANG } 1255ff984e57SWei WANG 12561b8055b4SWei WANG out: 1257ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1258ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1259ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1260ff984e57SWei WANG 1261ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1262ff984e57SWei WANG 1263ff984e57SWei WANG return err; 1264ff984e57SWei WANG } 1265ff984e57SWei WANG 1266ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1267ff984e57SWei WANG { 1268ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1269ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1270ff984e57SWei WANG int err = 0; 1271ff984e57SWei WANG 1272ff984e57SWei WANG if (host->eject) 1273ff984e57SWei WANG return -ENOMEDIUM; 1274ff984e57SWei WANG 1275c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1276c3481955SWei WANG if (err) 1277c3481955SWei WANG return err; 1278c3481955SWei WANG 1279ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1280ff984e57SWei WANG 1281ff984e57SWei WANG rtsx_pci_start_run(pcr); 1282ff984e57SWei WANG 128384d72f9cSWei WANG /* Set initial TX phase */ 128484d72f9cSWei WANG switch (mmc->ios.timing) { 128584d72f9cSWei WANG case MMC_TIMING_UHS_SDR104: 128684d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 128784d72f9cSWei WANG break; 1288ff984e57SWei WANG 128984d72f9cSWei WANG case MMC_TIMING_UHS_SDR50: 129084d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 129184d72f9cSWei WANG break; 129284d72f9cSWei WANG 129384d72f9cSWei WANG case MMC_TIMING_UHS_DDR50: 129484d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 129584d72f9cSWei WANG break; 129684d72f9cSWei WANG 129784d72f9cSWei WANG default: 129884d72f9cSWei WANG err = 0; 129984d72f9cSWei WANG } 130084d72f9cSWei WANG 130184d72f9cSWei WANG if (err) 130284d72f9cSWei WANG goto out; 130384d72f9cSWei WANG 130484d72f9cSWei WANG /* Tuning RX phase */ 130584d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 130684d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 130784d72f9cSWei WANG err = sd_tuning_rx(host, opcode); 130884d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 130984d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 131084d72f9cSWei WANG 131184d72f9cSWei WANG out: 1312ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1313ff984e57SWei WANG 1314ff984e57SWei WANG return err; 1315ff984e57SWei WANG } 1316ff984e57SWei WANG 1317ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 13186291e715SMicky Ching .pre_req = sdmmc_pre_req, 13196291e715SMicky Ching .post_req = sdmmc_post_req, 1320ff984e57SWei WANG .request = sdmmc_request, 1321ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1322ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1323ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1324ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1325ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 1326ff984e57SWei WANG }; 1327ff984e57SWei WANG 1328ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1329ff984e57SWei WANG { 1330ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1331ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1332ff984e57SWei WANG 1333ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1334ff984e57SWei WANG 1335ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1336ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1337ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1338ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1339ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1340ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1341ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1342ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1343ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1344ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1345ff984e57SWei WANG } 1346ff984e57SWei WANG 1347ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1348ff984e57SWei WANG { 1349ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1350ff984e57SWei WANG 1351ff984e57SWei WANG mmc->f_min = 250000; 1352ff984e57SWei WANG mmc->f_max = 208000000; 1353ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1354ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1355ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1356ff984e57SWei WANG MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1357517bf80fSRoger Tseng mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE; 1358ff984e57SWei WANG mmc->max_current_330 = 400; 1359ff984e57SWei WANG mmc->max_current_180 = 800; 1360ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1361ff984e57SWei WANG 1362ff984e57SWei WANG init_extra_caps(host); 1363ff984e57SWei WANG 1364ff984e57SWei WANG mmc->max_segs = 256; 1365ff984e57SWei WANG mmc->max_seg_size = 65536; 1366ff984e57SWei WANG mmc->max_blk_size = 512; 1367ff984e57SWei WANG mmc->max_blk_count = 65535; 1368ff984e57SWei WANG mmc->max_req_size = 524288; 1369ff984e57SWei WANG } 1370ff984e57SWei WANG 1371ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1372ff984e57SWei WANG { 1373ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1374ff984e57SWei WANG 13752057647fSMicky Ching host->cookie = -1; 1376ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1377ff984e57SWei WANG } 1378ff984e57SWei WANG 1379ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1380ff984e57SWei WANG { 1381ff984e57SWei WANG struct mmc_host *mmc; 1382ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1383ff984e57SWei WANG struct rtsx_pcr *pcr; 1384ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1385ff984e57SWei WANG 1386ff984e57SWei WANG if (!handle) 1387ff984e57SWei WANG return -ENXIO; 1388ff984e57SWei WANG 1389ff984e57SWei WANG pcr = handle->pcr; 1390ff984e57SWei WANG if (!pcr) 1391ff984e57SWei WANG return -ENXIO; 1392ff984e57SWei WANG 1393ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1394ff984e57SWei WANG 1395ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1396ff984e57SWei WANG if (!mmc) 1397ff984e57SWei WANG return -ENOMEM; 1398ff984e57SWei WANG 1399ff984e57SWei WANG host = mmc_priv(mmc); 14006291e715SMicky Ching host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME); 14016291e715SMicky Ching if (!host->workq) { 14026291e715SMicky Ching mmc_free_host(mmc); 14036291e715SMicky Ching return -ENOMEM; 14046291e715SMicky Ching } 1405ff984e57SWei WANG host->pcr = pcr; 1406ff984e57SWei WANG host->mmc = mmc; 1407ff984e57SWei WANG host->pdev = pdev; 14082057647fSMicky Ching host->cookie = -1; 1409d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 14106291e715SMicky Ching INIT_WORK(&host->work, sd_request); 1411ff984e57SWei WANG platform_set_drvdata(pdev, host); 1412ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1413ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1414ff984e57SWei WANG 141598fcc576SMicky Ching mutex_init(&host->host_mutex); 1416ff984e57SWei WANG 1417ff984e57SWei WANG realtek_init_host(host); 1418ff984e57SWei WANG 1419ff984e57SWei WANG mmc_add_host(mmc); 1420ff984e57SWei WANG 1421ff984e57SWei WANG return 0; 1422ff984e57SWei WANG } 1423ff984e57SWei WANG 1424ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1425ff984e57SWei WANG { 1426ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1427ff984e57SWei WANG struct rtsx_pcr *pcr; 1428ff984e57SWei WANG struct mmc_host *mmc; 1429ff984e57SWei WANG 1430ff984e57SWei WANG if (!host) 1431ff984e57SWei WANG return 0; 1432ff984e57SWei WANG 1433ff984e57SWei WANG pcr = host->pcr; 1434ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1435ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1436ff984e57SWei WANG mmc = host->mmc; 1437ff984e57SWei WANG 14386291e715SMicky Ching cancel_work_sync(&host->work); 14396291e715SMicky Ching 144098fcc576SMicky Ching mutex_lock(&host->host_mutex); 1441ff984e57SWei WANG if (host->mrq) { 1442ff984e57SWei WANG dev_dbg(&(pdev->dev), 1443ff984e57SWei WANG "%s: Controller removed during transfer\n", 1444ff984e57SWei WANG mmc_hostname(mmc)); 1445ff984e57SWei WANG 144698fcc576SMicky Ching rtsx_pci_complete_unfinished_transfer(pcr); 1447ff984e57SWei WANG 144898fcc576SMicky Ching host->mrq->cmd->error = -ENOMEDIUM; 144998fcc576SMicky Ching if (host->mrq->stop) 145098fcc576SMicky Ching host->mrq->stop->error = -ENOMEDIUM; 145198fcc576SMicky Ching mmc_request_done(mmc, host->mrq); 1452ff984e57SWei WANG } 145398fcc576SMicky Ching mutex_unlock(&host->host_mutex); 1454ff984e57SWei WANG 1455ff984e57SWei WANG mmc_remove_host(mmc); 1456640e09bcSMicky Ching host->eject = true; 1457640e09bcSMicky Ching 14586291e715SMicky Ching flush_workqueue(host->workq); 14596291e715SMicky Ching destroy_workqueue(host->workq); 14606291e715SMicky Ching host->workq = NULL; 14616291e715SMicky Ching 1462ff984e57SWei WANG mmc_free_host(mmc); 1463ff984e57SWei WANG 1464ff984e57SWei WANG dev_dbg(&(pdev->dev), 1465ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1466ff984e57SWei WANG 1467ff984e57SWei WANG return 0; 1468ff984e57SWei WANG } 1469ff984e57SWei WANG 1470ff984e57SWei WANG static struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1471ff984e57SWei WANG { 1472ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1473ff984e57SWei WANG }, { 1474ff984e57SWei WANG /* sentinel */ 1475ff984e57SWei WANG } 1476ff984e57SWei WANG }; 1477ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1478ff984e57SWei WANG 1479ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1480ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1481ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1482ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1483ff984e57SWei WANG .driver = { 1484ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1485ff984e57SWei WANG }, 1486ff984e57SWei WANG }; 1487ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1488ff984e57SWei WANG 1489ff984e57SWei WANG MODULE_LICENSE("GPL"); 1490ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1491ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1492