1ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 2ff984e57SWei WANG * 362282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4ff984e57SWei WANG * 5ff984e57SWei WANG * This program is free software; you can redistribute it and/or modify it 6ff984e57SWei WANG * under the terms of the GNU General Public License as published by the 7ff984e57SWei WANG * Free Software Foundation; either version 2, or (at your option) any 8ff984e57SWei WANG * later version. 9ff984e57SWei WANG * 10ff984e57SWei WANG * This program is distributed in the hope that it will be useful, but 11ff984e57SWei WANG * WITHOUT ANY WARRANTY; without even the implied warranty of 12ff984e57SWei WANG * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13ff984e57SWei WANG * General Public License for more details. 14ff984e57SWei WANG * 15ff984e57SWei WANG * You should have received a copy of the GNU General Public License along 16ff984e57SWei WANG * with this program; if not, see <http://www.gnu.org/licenses/>. 17ff984e57SWei WANG * 18ff984e57SWei WANG * Author: 19ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 20ff984e57SWei WANG */ 21ff984e57SWei WANG 22ff984e57SWei WANG #include <linux/module.h> 23433e075cSWei WANG #include <linux/slab.h> 24ff984e57SWei WANG #include <linux/highmem.h> 25ff984e57SWei WANG #include <linux/delay.h> 26ff984e57SWei WANG #include <linux/platform_device.h> 27ff984e57SWei WANG #include <linux/mmc/host.h> 28ff984e57SWei WANG #include <linux/mmc/mmc.h> 29ff984e57SWei WANG #include <linux/mmc/sd.h> 30ff984e57SWei WANG #include <linux/mmc/card.h> 31ff984e57SWei WANG #include <linux/mfd/rtsx_pci.h> 32ff984e57SWei WANG #include <asm/unaligned.h> 33ff984e57SWei WANG 34ff984e57SWei WANG struct realtek_pci_sdmmc { 35ff984e57SWei WANG struct platform_device *pdev; 36ff984e57SWei WANG struct rtsx_pcr *pcr; 37ff984e57SWei WANG struct mmc_host *mmc; 38ff984e57SWei WANG struct mmc_request *mrq; 39ff984e57SWei WANG 40ff984e57SWei WANG struct mutex host_mutex; 41ff984e57SWei WANG 42ff984e57SWei WANG u8 ssc_depth; 43ff984e57SWei WANG unsigned int clock; 44ff984e57SWei WANG bool vpclk; 45ff984e57SWei WANG bool double_clk; 46ff984e57SWei WANG bool eject; 47ff984e57SWei WANG bool initial_mode; 48d88691beSWei WANG int power_state; 49d88691beSWei WANG #define SDMMC_POWER_ON 1 50d88691beSWei WANG #define SDMMC_POWER_OFF 0 51ff984e57SWei WANG }; 52ff984e57SWei WANG 53ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 54ff984e57SWei WANG { 55ff984e57SWei WANG return &(host->pdev->dev); 56ff984e57SWei WANG } 57ff984e57SWei WANG 58ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 59ff984e57SWei WANG { 60ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 61ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 62ff984e57SWei WANG } 63ff984e57SWei WANG 64ff984e57SWei WANG #ifdef DEBUG 65ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 66ff984e57SWei WANG { 67ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 68ff984e57SWei WANG u16 i; 69ff984e57SWei WANG u8 *ptr; 70ff984e57SWei WANG 71ff984e57SWei WANG /* Print SD host internal registers */ 72ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 73ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 74ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 75ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 76ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 77ff984e57SWei WANG rtsx_pci_send_cmd(pcr, 100); 78ff984e57SWei WANG 79ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr); 80ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 81ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 82ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 83ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 84ff984e57SWei WANG } 85ff984e57SWei WANG #else 86ff984e57SWei WANG #define sd_print_debug_regs(host) 87ff984e57SWei WANG #endif /* DEBUG */ 88ff984e57SWei WANG 89ff984e57SWei WANG static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 90ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 91ff984e57SWei WANG { 92ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 93ff984e57SWei WANG int err, i; 94ff984e57SWei WANG u8 trans_mode; 95ff984e57SWei WANG 96ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40); 97ff984e57SWei WANG 98ff984e57SWei WANG if (!buf) 99ff984e57SWei WANG buf_len = 0; 100ff984e57SWei WANG 101ff984e57SWei WANG if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK) 102ff984e57SWei WANG trans_mode = SD_TM_AUTO_TUNING; 103ff984e57SWei WANG else 104ff984e57SWei WANG trans_mode = SD_TM_NORMAL_READ; 105ff984e57SWei WANG 106ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 107ff984e57SWei WANG 108ff984e57SWei WANG for (i = 0; i < 5; i++) 109ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]); 110ff984e57SWei WANG 111ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 112ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 113ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 114ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 115ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 116ff984e57SWei WANG 117ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 118ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 119ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 120ff984e57SWei WANG if (trans_mode != SD_TM_AUTO_TUNING) 121ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 122ff984e57SWei WANG CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 123ff984e57SWei WANG 124ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 125ff984e57SWei WANG 0xFF, trans_mode | SD_TRANSFER_START); 126ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 127ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 128ff984e57SWei WANG 129ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 130ff984e57SWei WANG if (err < 0) { 131ff984e57SWei WANG sd_print_debug_regs(host); 132ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 133ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 134ff984e57SWei WANG return err; 135ff984e57SWei WANG } 136ff984e57SWei WANG 137ff984e57SWei WANG if (buf && buf_len) { 138ff984e57SWei WANG err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 139ff984e57SWei WANG if (err < 0) { 140ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 141ff984e57SWei WANG "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 142ff984e57SWei WANG return err; 143ff984e57SWei WANG } 144ff984e57SWei WANG } 145ff984e57SWei WANG 146ff984e57SWei WANG return 0; 147ff984e57SWei WANG } 148ff984e57SWei WANG 149ff984e57SWei WANG static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 150ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 151ff984e57SWei WANG { 152ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 153ff984e57SWei WANG int err, i; 154ff984e57SWei WANG u8 trans_mode; 155ff984e57SWei WANG 156ff984e57SWei WANG if (!buf) 157ff984e57SWei WANG buf_len = 0; 158ff984e57SWei WANG 159ff984e57SWei WANG if (buf && buf_len) { 160ff984e57SWei WANG err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 161ff984e57SWei WANG if (err < 0) { 162ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 163ff984e57SWei WANG "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 164ff984e57SWei WANG return err; 165ff984e57SWei WANG } 166ff984e57SWei WANG } 167ff984e57SWei WANG 168ff984e57SWei WANG trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3; 169ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 170ff984e57SWei WANG 171ff984e57SWei WANG if (cmd) { 172ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__, 173ff984e57SWei WANG cmd[0] - 0x40); 174ff984e57SWei WANG 175ff984e57SWei WANG for (i = 0; i < 5; i++) 176ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 177ff984e57SWei WANG SD_CMD0 + i, 0xFF, cmd[i]); 178ff984e57SWei WANG } 179ff984e57SWei WANG 180ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 181ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 182ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 183ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 184ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 185ff984e57SWei WANG 186ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 187ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 188ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 189ff984e57SWei WANG 190ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 191ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 192ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 193ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 194ff984e57SWei WANG 195ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 196ff984e57SWei WANG if (err < 0) { 197ff984e57SWei WANG sd_print_debug_regs(host); 198ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 199ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 200ff984e57SWei WANG return err; 201ff984e57SWei WANG } 202ff984e57SWei WANG 203ff984e57SWei WANG return 0; 204ff984e57SWei WANG } 205ff984e57SWei WANG 206ff984e57SWei WANG static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 207ff984e57SWei WANG struct mmc_command *cmd) 208ff984e57SWei WANG { 209ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 210ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 211ff984e57SWei WANG u32 arg = cmd->arg; 212ff984e57SWei WANG int err = 0; 213ff984e57SWei WANG int timeout = 100; 214ff984e57SWei WANG int i; 215ff984e57SWei WANG u8 *ptr; 216ff984e57SWei WANG int stat_idx = 0; 217ff984e57SWei WANG u8 rsp_type; 218ff984e57SWei WANG int rsp_len = 5; 2191b8055b4SWei WANG bool clock_toggled = false; 220ff984e57SWei WANG 221ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 222ff984e57SWei WANG __func__, cmd_idx, arg); 223ff984e57SWei WANG 224ff984e57SWei WANG /* Response type: 225ff984e57SWei WANG * R0 226ff984e57SWei WANG * R1, R5, R6, R7 227ff984e57SWei WANG * R1b 228ff984e57SWei WANG * R2 229ff984e57SWei WANG * R3, R4 230ff984e57SWei WANG */ 231ff984e57SWei WANG switch (mmc_resp_type(cmd)) { 232ff984e57SWei WANG case MMC_RSP_NONE: 233ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R0; 234ff984e57SWei WANG rsp_len = 0; 235ff984e57SWei WANG break; 236ff984e57SWei WANG case MMC_RSP_R1: 237ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1; 238ff984e57SWei WANG break; 239ff984e57SWei WANG case MMC_RSP_R1B: 240ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1b; 241ff984e57SWei WANG break; 242ff984e57SWei WANG case MMC_RSP_R2: 243ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R2; 244ff984e57SWei WANG rsp_len = 16; 245ff984e57SWei WANG break; 246ff984e57SWei WANG case MMC_RSP_R3: 247ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R3; 248ff984e57SWei WANG break; 249ff984e57SWei WANG default: 250ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n"); 251ff984e57SWei WANG err = -EINVAL; 252ff984e57SWei WANG goto out; 253ff984e57SWei WANG } 254ff984e57SWei WANG 255ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 256ff984e57SWei WANG timeout = 3000; 257ff984e57SWei WANG 258ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 259ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 260ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 261ff984e57SWei WANG if (err < 0) 262ff984e57SWei WANG goto out; 2631b8055b4SWei WANG 2641b8055b4SWei WANG clock_toggled = true; 265ff984e57SWei WANG } 266ff984e57SWei WANG 267ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 268ff984e57SWei WANG 269ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx); 270ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24)); 271ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16)); 272ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8)); 273ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg); 274ff984e57SWei WANG 275ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 276ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 277ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 278ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 279ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 280ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 281ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 282ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 283ff984e57SWei WANG 284ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 285ff984e57SWei WANG /* Read data from ping-pong buffer */ 286ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 287ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 288ff984e57SWei WANG stat_idx = 16; 289ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 290ff984e57SWei WANG /* Read data from SD_CMDx registers */ 291ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 292ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 293ff984e57SWei WANG stat_idx = 5; 294ff984e57SWei WANG } 295ff984e57SWei WANG 296ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 297ff984e57SWei WANG 298ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 299ff984e57SWei WANG if (err < 0) { 300ff984e57SWei WANG sd_print_debug_regs(host); 301ff984e57SWei WANG sd_clear_error(host); 302ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 303ff984e57SWei WANG "rtsx_pci_send_cmd error (err = %d)\n", err); 304ff984e57SWei WANG goto out; 305ff984e57SWei WANG } 306ff984e57SWei WANG 307ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 308ff984e57SWei WANG err = 0; 309ff984e57SWei WANG goto out; 310ff984e57SWei WANG } 311ff984e57SWei WANG 312ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 313ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 314ff984e57SWei WANG 315ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 316ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 317ff984e57SWei WANG err = -EILSEQ; 318ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 319ff984e57SWei WANG goto out; 320ff984e57SWei WANG } 321ff984e57SWei WANG 322ff984e57SWei WANG /* Check CRC7 */ 323ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 324ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 325ff984e57SWei WANG err = -EILSEQ; 326ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 327ff984e57SWei WANG goto out; 328ff984e57SWei WANG } 329ff984e57SWei WANG } 330ff984e57SWei WANG 331ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 332ff984e57SWei WANG for (i = 0; i < 4; i++) { 333ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 334ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 335ff984e57SWei WANG i, cmd->resp[i]); 336ff984e57SWei WANG } 337ff984e57SWei WANG } else { 338ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 339ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 340ff984e57SWei WANG cmd->resp[0]); 341ff984e57SWei WANG } 342ff984e57SWei WANG 343ff984e57SWei WANG out: 344ff984e57SWei WANG cmd->error = err; 3451b8055b4SWei WANG 3461b8055b4SWei WANG if (err && clock_toggled) 3471b8055b4SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 3481b8055b4SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 349ff984e57SWei WANG } 350ff984e57SWei WANG 351ff984e57SWei WANG static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 352ff984e57SWei WANG { 353ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 354ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 355ff984e57SWei WANG struct mmc_card *card = mmc->card; 356ff984e57SWei WANG struct mmc_data *data = mrq->data; 35771ef1ea4SJackey Shen int uhs = mmc_card_uhs(card); 358ff984e57SWei WANG int read = (data->flags & MMC_DATA_READ) ? 1 : 0; 359ff984e57SWei WANG u8 cfg2, trans_mode; 360ff984e57SWei WANG int err; 361ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 362ff984e57SWei WANG 363ff984e57SWei WANG if (read) { 364ff984e57SWei WANG cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 365ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0; 366ff984e57SWei WANG trans_mode = SD_TM_AUTO_READ_3; 367ff984e57SWei WANG } else { 368ff984e57SWei WANG cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 369ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 370ff984e57SWei WANG trans_mode = SD_TM_AUTO_WRITE_3; 371ff984e57SWei WANG } 372ff984e57SWei WANG 373ff984e57SWei WANG if (!uhs) 374ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 375ff984e57SWei WANG 376ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 377ff984e57SWei WANG 378ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00); 379ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02); 380ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 381ff984e57SWei WANG 0xFF, (u8)data->blocks); 382ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 383ff984e57SWei WANG 0xFF, (u8)(data->blocks >> 8)); 384ff984e57SWei WANG 385ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 386ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 387ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 388ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 389ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 390ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 391ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 392ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 393ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 394ff984e57SWei WANG if (read) { 395ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 396ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 397ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 398ff984e57SWei WANG } else { 399ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 400ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 401ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 402ff984e57SWei WANG } 403ff984e57SWei WANG 404ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 405ff984e57SWei WANG 0x01, RING_BUFFER); 406ff984e57SWei WANG 40738d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 408ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 409ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 410ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 411ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 412ff984e57SWei WANG 413ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 414ff984e57SWei WANG 415ff984e57SWei WANG err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000); 416ff984e57SWei WANG if (err < 0) { 417ff984e57SWei WANG sd_clear_error(host); 418ff984e57SWei WANG return err; 419ff984e57SWei WANG } 420ff984e57SWei WANG 421ff984e57SWei WANG return 0; 422ff984e57SWei WANG } 423ff984e57SWei WANG 424ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 425ff984e57SWei WANG { 426ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 427ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 428ff984e57SWei WANG } 429ff984e57SWei WANG 430ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 431ff984e57SWei WANG { 432ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 433ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 434ff984e57SWei WANG } 435ff984e57SWei WANG 436ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 437ff984e57SWei WANG struct mmc_request *mrq) 438ff984e57SWei WANG { 439ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 440ff984e57SWei WANG struct mmc_data *data = mrq->data; 441ff984e57SWei WANG u8 _cmd[5], *buf; 442ff984e57SWei WANG 443ff984e57SWei WANG _cmd[0] = 0x40 | (u8)cmd->opcode; 444ff984e57SWei WANG put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1])); 445ff984e57SWei WANG 446ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 447ff984e57SWei WANG if (!buf) { 448ff984e57SWei WANG cmd->error = -ENOMEM; 449ff984e57SWei WANG return; 450ff984e57SWei WANG } 451ff984e57SWei WANG 452ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 453ff984e57SWei WANG if (host->initial_mode) 454ff984e57SWei WANG sd_disable_initial_mode(host); 455ff984e57SWei WANG 456ff984e57SWei WANG cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf, 457ff984e57SWei WANG data->blksz, 200); 458ff984e57SWei WANG 459ff984e57SWei WANG if (host->initial_mode) 460ff984e57SWei WANG sd_enable_initial_mode(host); 461ff984e57SWei WANG 462ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 463ff984e57SWei WANG } else { 464ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 465ff984e57SWei WANG 466ff984e57SWei WANG cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf, 467ff984e57SWei WANG data->blksz, 200); 468ff984e57SWei WANG } 469ff984e57SWei WANG 470ff984e57SWei WANG kfree(buf); 471ff984e57SWei WANG } 472ff984e57SWei WANG 47384d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, 47484d72f9cSWei WANG u8 sample_point, bool rx) 475ff984e57SWei WANG { 476ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 477ff984e57SWei WANG int err; 478ff984e57SWei WANG 47984d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 48084d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point); 481ff984e57SWei WANG 482ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 483ff984e57SWei WANG 484ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 48584d72f9cSWei WANG if (rx) 48684d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 48784d72f9cSWei WANG SD_VPRX_CTL, 0x1F, sample_point); 48884d72f9cSWei WANG else 48984d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 49084d72f9cSWei WANG SD_VPTX_CTL, 0x1F, sample_point); 491ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); 492ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 493ff984e57SWei WANG PHASE_NOT_RESET, PHASE_NOT_RESET); 494ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); 495ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 496ff984e57SWei WANG 497ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 498ff984e57SWei WANG if (err < 0) 499ff984e57SWei WANG return err; 500ff984e57SWei WANG 501ff984e57SWei WANG return 0; 502ff984e57SWei WANG } 503ff984e57SWei WANG 504abcc6b29SMicky Ching static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 505abcc6b29SMicky Ching { 506abcc6b29SMicky Ching bit %= RTSX_PHASE_MAX; 507abcc6b29SMicky Ching return phase_map & (1 << bit); 508abcc6b29SMicky Ching } 509abcc6b29SMicky Ching 510abcc6b29SMicky Ching static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 511abcc6b29SMicky Ching { 512abcc6b29SMicky Ching int i; 513abcc6b29SMicky Ching 514abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 515abcc6b29SMicky Ching if (test_phase_bit(phase_map, start_bit + i) == 0) 516abcc6b29SMicky Ching return i; 517abcc6b29SMicky Ching } 518abcc6b29SMicky Ching return RTSX_PHASE_MAX; 519abcc6b29SMicky Ching } 520abcc6b29SMicky Ching 521ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 522ff984e57SWei WANG { 523abcc6b29SMicky Ching int start = 0, len = 0; 524abcc6b29SMicky Ching int start_final = 0, len_final = 0; 525ff984e57SWei WANG u8 final_phase = 0xFF; 526ff984e57SWei WANG 527abcc6b29SMicky Ching if (phase_map == 0) { 528abcc6b29SMicky Ching dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 529abcc6b29SMicky Ching return final_phase; 530ff984e57SWei WANG } 531ff984e57SWei WANG 532abcc6b29SMicky Ching while (start < RTSX_PHASE_MAX) { 533abcc6b29SMicky Ching len = sd_get_phase_len(phase_map, start); 534abcc6b29SMicky Ching if (len_final < len) { 535abcc6b29SMicky Ching start_final = start; 536abcc6b29SMicky Ching len_final = len; 537abcc6b29SMicky Ching } 538abcc6b29SMicky Ching start += len ? len : 1; 539ff984e57SWei WANG } 540ff984e57SWei WANG 541abcc6b29SMicky Ching final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 542abcc6b29SMicky Ching dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 543abcc6b29SMicky Ching phase_map, len_final, final_phase); 544ff984e57SWei WANG 545ff984e57SWei WANG return final_phase; 546ff984e57SWei WANG } 547ff984e57SWei WANG 548ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 549ff984e57SWei WANG { 550ff984e57SWei WANG int err, i; 551ff984e57SWei WANG u8 val = 0; 552ff984e57SWei WANG 553ff984e57SWei WANG for (i = 0; i < 100; i++) { 554ff984e57SWei WANG err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 555ff984e57SWei WANG if (val & SD_DATA_IDLE) 556ff984e57SWei WANG return; 557ff984e57SWei WANG 558ff984e57SWei WANG udelay(100); 559ff984e57SWei WANG } 560ff984e57SWei WANG } 561ff984e57SWei WANG 562ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 563ff984e57SWei WANG u8 opcode, u8 sample_point) 564ff984e57SWei WANG { 565ff984e57SWei WANG int err; 566ff984e57SWei WANG u8 cmd[5] = {0}; 567ff984e57SWei WANG 56884d72f9cSWei WANG err = sd_change_phase(host, sample_point, true); 569ff984e57SWei WANG if (err < 0) 570ff984e57SWei WANG return err; 571ff984e57SWei WANG 572ff984e57SWei WANG cmd[0] = 0x40 | opcode; 573ff984e57SWei WANG err = sd_read_data(host, cmd, 0x40, NULL, 0, 100); 574ff984e57SWei WANG if (err < 0) { 575ff984e57SWei WANG /* Wait till SD DATA IDLE */ 576ff984e57SWei WANG sd_wait_data_idle(host); 577ff984e57SWei WANG sd_clear_error(host); 578ff984e57SWei WANG return err; 579ff984e57SWei WANG } 580ff984e57SWei WANG 581ff984e57SWei WANG return 0; 582ff984e57SWei WANG } 583ff984e57SWei WANG 584ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 585ff984e57SWei WANG u8 opcode, u32 *phase_map) 586ff984e57SWei WANG { 587ff984e57SWei WANG int err, i; 588ff984e57SWei WANG u32 raw_phase_map = 0; 589ff984e57SWei WANG 590abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 591ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 592ff984e57SWei WANG if (err == 0) 593ff984e57SWei WANG raw_phase_map |= 1 << i; 594ff984e57SWei WANG } 595ff984e57SWei WANG 596ff984e57SWei WANG if (phase_map) 597ff984e57SWei WANG *phase_map = raw_phase_map; 598ff984e57SWei WANG 599ff984e57SWei WANG return 0; 600ff984e57SWei WANG } 601ff984e57SWei WANG 602ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 603ff984e57SWei WANG { 604ff984e57SWei WANG int err, i; 605ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 606ff984e57SWei WANG u8 final_phase; 607ff984e57SWei WANG 608ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 609ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 610ff984e57SWei WANG if (err < 0) 611ff984e57SWei WANG return err; 612ff984e57SWei WANG 613ff984e57SWei WANG if (raw_phase_map[i] == 0) 614ff984e57SWei WANG break; 615ff984e57SWei WANG } 616ff984e57SWei WANG 617ff984e57SWei WANG phase_map = 0xFFFFFFFF; 618ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 619ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 620ff984e57SWei WANG i, raw_phase_map[i]); 621ff984e57SWei WANG phase_map &= raw_phase_map[i]; 622ff984e57SWei WANG } 623ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 624ff984e57SWei WANG 625ff984e57SWei WANG if (phase_map) { 626ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 627ff984e57SWei WANG if (final_phase == 0xFF) 628ff984e57SWei WANG return -EINVAL; 629ff984e57SWei WANG 63084d72f9cSWei WANG err = sd_change_phase(host, final_phase, true); 631ff984e57SWei WANG if (err < 0) 632ff984e57SWei WANG return err; 633ff984e57SWei WANG } else { 634ff984e57SWei WANG return -EINVAL; 635ff984e57SWei WANG } 636ff984e57SWei WANG 637ff984e57SWei WANG return 0; 638ff984e57SWei WANG } 639ff984e57SWei WANG 640ff984e57SWei WANG static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 641ff984e57SWei WANG { 642ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 643ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 644ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 645ff984e57SWei WANG struct mmc_data *data = mrq->data; 646ff984e57SWei WANG unsigned int data_size = 0; 647c3481955SWei WANG int err; 648ff984e57SWei WANG 649ff984e57SWei WANG if (host->eject) { 650ff984e57SWei WANG cmd->error = -ENOMEDIUM; 651ff984e57SWei WANG goto finish; 652ff984e57SWei WANG } 653ff984e57SWei WANG 654c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 655c3481955SWei WANG if (err) { 656c3481955SWei WANG cmd->error = err; 657c3481955SWei WANG goto finish; 658c3481955SWei WANG } 659c3481955SWei WANG 660ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 661ff984e57SWei WANG 662ff984e57SWei WANG rtsx_pci_start_run(pcr); 663ff984e57SWei WANG 664ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 665ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 666ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 667ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 668ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 669ff984e57SWei WANG 670ff984e57SWei WANG mutex_lock(&host->host_mutex); 671ff984e57SWei WANG host->mrq = mrq; 672ff984e57SWei WANG mutex_unlock(&host->host_mutex); 673ff984e57SWei WANG 674ff984e57SWei WANG if (mrq->data) 675ff984e57SWei WANG data_size = data->blocks * data->blksz; 676ff984e57SWei WANG 677ff984e57SWei WANG if (!data_size || mmc_op_multi(cmd->opcode) || 678ff984e57SWei WANG (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 679ff984e57SWei WANG (cmd->opcode == MMC_WRITE_BLOCK)) { 680ff984e57SWei WANG sd_send_cmd_get_rsp(host, cmd); 681ff984e57SWei WANG 682ff984e57SWei WANG if (!cmd->error && data_size) { 683ff984e57SWei WANG sd_rw_multi(host, mrq); 684ff984e57SWei WANG 685ff984e57SWei WANG if (mmc_op_multi(cmd->opcode) && mrq->stop) 686ff984e57SWei WANG sd_send_cmd_get_rsp(host, mrq->stop); 687ff984e57SWei WANG } 688ff984e57SWei WANG } else { 689ff984e57SWei WANG sd_normal_rw(host, mrq); 690ff984e57SWei WANG } 691ff984e57SWei WANG 692ff984e57SWei WANG if (mrq->data) { 693ff984e57SWei WANG if (cmd->error || data->error) 694ff984e57SWei WANG data->bytes_xfered = 0; 695ff984e57SWei WANG else 696ff984e57SWei WANG data->bytes_xfered = data->blocks * data->blksz; 697ff984e57SWei WANG } 698ff984e57SWei WANG 699ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 700ff984e57SWei WANG 701ff984e57SWei WANG finish: 702ff984e57SWei WANG if (cmd->error) 703ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error); 704ff984e57SWei WANG 705ff984e57SWei WANG mutex_lock(&host->host_mutex); 706ff984e57SWei WANG host->mrq = NULL; 707ff984e57SWei WANG mutex_unlock(&host->host_mutex); 708ff984e57SWei WANG 709ff984e57SWei WANG mmc_request_done(mmc, mrq); 710ff984e57SWei WANG } 711ff984e57SWei WANG 712ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 713ff984e57SWei WANG unsigned char bus_width) 714ff984e57SWei WANG { 715ff984e57SWei WANG int err = 0; 716ff984e57SWei WANG u8 width[] = { 717ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 718ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 719ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 720ff984e57SWei WANG }; 721ff984e57SWei WANG 722ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 723ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 724ff984e57SWei WANG 0x03, width[bus_width]); 725ff984e57SWei WANG 726ff984e57SWei WANG return err; 727ff984e57SWei WANG } 728ff984e57SWei WANG 729ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 730ff984e57SWei WANG { 731ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 732ff984e57SWei WANG int err; 733ff984e57SWei WANG 734d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 735d88691beSWei WANG return 0; 736d88691beSWei WANG 737ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 738ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 739ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 740ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 741ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 742ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 743ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 744ff984e57SWei WANG if (err < 0) 745ff984e57SWei WANG return err; 746ff984e57SWei WANG 747ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 748ff984e57SWei WANG if (err < 0) 749ff984e57SWei WANG return err; 750ff984e57SWei WANG 751ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 752ff984e57SWei WANG if (err < 0) 753ff984e57SWei WANG return err; 754ff984e57SWei WANG 755ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 756ff984e57SWei WANG if (err < 0) 757ff984e57SWei WANG return err; 758ff984e57SWei WANG 759d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 760ff984e57SWei WANG return 0; 761ff984e57SWei WANG } 762ff984e57SWei WANG 763ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 764ff984e57SWei WANG { 765ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 766ff984e57SWei WANG int err; 767ff984e57SWei WANG 768d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 769d88691beSWei WANG 770ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 771ff984e57SWei WANG 772ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 773ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 774ff984e57SWei WANG 775ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 776ff984e57SWei WANG if (err < 0) 777ff984e57SWei WANG return err; 778ff984e57SWei WANG 779ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 780ff984e57SWei WANG if (err < 0) 781ff984e57SWei WANG return err; 782ff984e57SWei WANG 783ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 784ff984e57SWei WANG } 785ff984e57SWei WANG 786ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 787ff984e57SWei WANG unsigned char power_mode) 788ff984e57SWei WANG { 789ff984e57SWei WANG int err; 790ff984e57SWei WANG 791ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 792ff984e57SWei WANG err = sd_power_off(host); 793ff984e57SWei WANG else 794ff984e57SWei WANG err = sd_power_on(host); 795ff984e57SWei WANG 796ff984e57SWei WANG return err; 797ff984e57SWei WANG } 798ff984e57SWei WANG 79984d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 800ff984e57SWei WANG { 801ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 802ff984e57SWei WANG int err = 0; 803ff984e57SWei WANG 804ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 805ff984e57SWei WANG 806ff984e57SWei WANG switch (timing) { 807ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 808ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 809ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 810ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 811ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 812ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 813ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 814ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 815ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 816ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 817ff984e57SWei WANG break; 818ff984e57SWei WANG 819ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 820ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 821ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 822ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 823ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 824ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 825ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 826ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 827ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 828ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 829ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 830ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 831ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 832ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 833ff984e57SWei WANG break; 834ff984e57SWei WANG 835ff984e57SWei WANG case MMC_TIMING_MMC_HS: 836ff984e57SWei WANG case MMC_TIMING_SD_HS: 837ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 838ff984e57SWei WANG 0x0C, SD_20_MODE); 839ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 840ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 841ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 842ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 843ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 844ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 845ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 846ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 847ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 848ff984e57SWei WANG break; 849ff984e57SWei WANG 850ff984e57SWei WANG default: 851ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 852ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 853ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 854ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 855ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 856ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 857ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 858ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 859ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 860ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 861ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 862ff984e57SWei WANG break; 863ff984e57SWei WANG } 864ff984e57SWei WANG 865ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 866ff984e57SWei WANG 867ff984e57SWei WANG return err; 868ff984e57SWei WANG } 869ff984e57SWei WANG 870ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 871ff984e57SWei WANG { 872ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 873ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 874ff984e57SWei WANG 875ff984e57SWei WANG if (host->eject) 876ff984e57SWei WANG return; 877ff984e57SWei WANG 878c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 879c3481955SWei WANG return; 880c3481955SWei WANG 881ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 882ff984e57SWei WANG 883ff984e57SWei WANG rtsx_pci_start_run(pcr); 884ff984e57SWei WANG 885ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 886ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 88784d72f9cSWei WANG sd_set_timing(host, ios->timing); 888ff984e57SWei WANG 889ff984e57SWei WANG host->vpclk = false; 890ff984e57SWei WANG host->double_clk = true; 891ff984e57SWei WANG 892ff984e57SWei WANG switch (ios->timing) { 893ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 894ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 895ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 896ff984e57SWei WANG host->vpclk = true; 897ff984e57SWei WANG host->double_clk = false; 898ff984e57SWei WANG break; 899ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 900ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 901ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 902ff984e57SWei WANG break; 903ff984e57SWei WANG default: 904ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 905ff984e57SWei WANG break; 906ff984e57SWei WANG } 907ff984e57SWei WANG 908ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 909ff984e57SWei WANG 910ff984e57SWei WANG host->clock = ios->clock; 911ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 912ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 913ff984e57SWei WANG 914ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 915ff984e57SWei WANG } 916ff984e57SWei WANG 917ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 918ff984e57SWei WANG { 919ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 920ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 921ff984e57SWei WANG int ro = 0; 922ff984e57SWei WANG u32 val; 923ff984e57SWei WANG 924ff984e57SWei WANG if (host->eject) 925ff984e57SWei WANG return -ENOMEDIUM; 926ff984e57SWei WANG 927ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 928ff984e57SWei WANG 929ff984e57SWei WANG rtsx_pci_start_run(pcr); 930ff984e57SWei WANG 931ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 932ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 933ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 934ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 935ff984e57SWei WANG ro = 1; 936ff984e57SWei WANG 937ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 938ff984e57SWei WANG 939ff984e57SWei WANG return ro; 940ff984e57SWei WANG } 941ff984e57SWei WANG 942ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 943ff984e57SWei WANG { 944ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 945ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 946ff984e57SWei WANG int cd = 0; 947ff984e57SWei WANG u32 val; 948ff984e57SWei WANG 949ff984e57SWei WANG if (host->eject) 950ff984e57SWei WANG return -ENOMEDIUM; 951ff984e57SWei WANG 952ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 953ff984e57SWei WANG 954ff984e57SWei WANG rtsx_pci_start_run(pcr); 955ff984e57SWei WANG 956ff984e57SWei WANG /* Check SD card detect */ 957ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 958ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 959ff984e57SWei WANG if (val & SD_EXIST) 960ff984e57SWei WANG cd = 1; 961ff984e57SWei WANG 962ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 963ff984e57SWei WANG 964ff984e57SWei WANG return cd; 965ff984e57SWei WANG } 966ff984e57SWei WANG 967ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 968ff984e57SWei WANG { 969ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 970ff984e57SWei WANG int err; 971ff984e57SWei WANG u8 stat; 972ff984e57SWei WANG 973ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 974ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 975ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 976ff984e57SWei WANG */ 977ff984e57SWei WANG mdelay(1); 978ff984e57SWei WANG 979ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 980ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 981ff984e57SWei WANG * abort the voltage switch sequence; 982ff984e57SWei WANG */ 983ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 984ff984e57SWei WANG if (err < 0) 985ff984e57SWei WANG return err; 986ff984e57SWei WANG 987ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 988ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 989ff984e57SWei WANG return -EINVAL; 990ff984e57SWei WANG 991ff984e57SWei WANG /* Stop toggle SD clock */ 992ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 993ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 994ff984e57SWei WANG if (err < 0) 995ff984e57SWei WANG return err; 996ff984e57SWei WANG 997ff984e57SWei WANG return 0; 998ff984e57SWei WANG } 999ff984e57SWei WANG 1000ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1001ff984e57SWei WANG { 1002ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1003ff984e57SWei WANG int err; 1004ff984e57SWei WANG u8 stat, mask, val; 1005ff984e57SWei WANG 1006ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1007ff984e57SWei WANG msleep(50); 1008ff984e57SWei WANG 1009ff984e57SWei WANG /* Toggle SD clock again */ 1010ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1011ff984e57SWei WANG if (err < 0) 1012ff984e57SWei WANG return err; 1013ff984e57SWei WANG 1014ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1015ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1016ff984e57SWei WANG */ 1017ff984e57SWei WANG msleep(20); 1018ff984e57SWei WANG 1019ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1020ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1021ff984e57SWei WANG if (err < 0) 1022ff984e57SWei WANG return err; 1023ff984e57SWei WANG 1024ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1025ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1026ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1027ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1028ff984e57SWei WANG if ((stat & mask) != val) { 1029ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1030ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1031ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1032ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1033ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1034ff984e57SWei WANG return -EINVAL; 1035ff984e57SWei WANG } 1036ff984e57SWei WANG 1037ff984e57SWei WANG return 0; 1038ff984e57SWei WANG } 1039ff984e57SWei WANG 1040ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1041ff984e57SWei WANG { 1042ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1043ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1044ff984e57SWei WANG int err = 0; 1045ff984e57SWei WANG u8 voltage; 1046ff984e57SWei WANG 1047ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1048ff984e57SWei WANG __func__, ios->signal_voltage); 1049ff984e57SWei WANG 1050ff984e57SWei WANG if (host->eject) 1051ff984e57SWei WANG return -ENOMEDIUM; 1052ff984e57SWei WANG 1053c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1054c3481955SWei WANG if (err) 1055c3481955SWei WANG return err; 1056c3481955SWei WANG 1057ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1058ff984e57SWei WANG 1059ff984e57SWei WANG rtsx_pci_start_run(pcr); 1060ff984e57SWei WANG 1061ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1062ef85e736SWei WANG voltage = OUTPUT_3V3; 1063ff984e57SWei WANG else 1064ef85e736SWei WANG voltage = OUTPUT_1V8; 1065ff984e57SWei WANG 1066ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1067ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1068ff984e57SWei WANG if (err < 0) 1069ff984e57SWei WANG goto out; 1070ff984e57SWei WANG } 1071ff984e57SWei WANG 1072ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1073ff984e57SWei WANG if (err < 0) 1074ff984e57SWei WANG goto out; 1075ff984e57SWei WANG 1076ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1077ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1078ff984e57SWei WANG if (err < 0) 1079ff984e57SWei WANG goto out; 1080ff984e57SWei WANG } 1081ff984e57SWei WANG 10821b8055b4SWei WANG out: 1083ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1084ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1085ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1086ff984e57SWei WANG 1087ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1088ff984e57SWei WANG 1089ff984e57SWei WANG return err; 1090ff984e57SWei WANG } 1091ff984e57SWei WANG 1092ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1093ff984e57SWei WANG { 1094ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1095ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1096ff984e57SWei WANG int err = 0; 1097ff984e57SWei WANG 1098ff984e57SWei WANG if (host->eject) 1099ff984e57SWei WANG return -ENOMEDIUM; 1100ff984e57SWei WANG 1101c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1102c3481955SWei WANG if (err) 1103c3481955SWei WANG return err; 1104c3481955SWei WANG 1105ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1106ff984e57SWei WANG 1107ff984e57SWei WANG rtsx_pci_start_run(pcr); 1108ff984e57SWei WANG 110984d72f9cSWei WANG /* Set initial TX phase */ 111084d72f9cSWei WANG switch (mmc->ios.timing) { 111184d72f9cSWei WANG case MMC_TIMING_UHS_SDR104: 111284d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 111384d72f9cSWei WANG break; 1114ff984e57SWei WANG 111584d72f9cSWei WANG case MMC_TIMING_UHS_SDR50: 111684d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 111784d72f9cSWei WANG break; 111884d72f9cSWei WANG 111984d72f9cSWei WANG case MMC_TIMING_UHS_DDR50: 112084d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 112184d72f9cSWei WANG break; 112284d72f9cSWei WANG 112384d72f9cSWei WANG default: 112484d72f9cSWei WANG err = 0; 112584d72f9cSWei WANG } 112684d72f9cSWei WANG 112784d72f9cSWei WANG if (err) 112884d72f9cSWei WANG goto out; 112984d72f9cSWei WANG 113084d72f9cSWei WANG /* Tuning RX phase */ 113184d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 113284d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 113384d72f9cSWei WANG err = sd_tuning_rx(host, opcode); 113484d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 113584d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 113684d72f9cSWei WANG 113784d72f9cSWei WANG out: 1138ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1139ff984e57SWei WANG 1140ff984e57SWei WANG return err; 1141ff984e57SWei WANG } 1142ff984e57SWei WANG 1143ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 1144ff984e57SWei WANG .request = sdmmc_request, 1145ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1146ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1147ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1148ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1149ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 1150ff984e57SWei WANG }; 1151ff984e57SWei WANG 1152ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1153ff984e57SWei WANG { 1154ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1155ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1156ff984e57SWei WANG 1157ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1158ff984e57SWei WANG 1159ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1160ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1161ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1162ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1163ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1164ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1165ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1166ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1167ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1168ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1169ff984e57SWei WANG } 1170ff984e57SWei WANG 1171ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1172ff984e57SWei WANG { 1173ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1174ff984e57SWei WANG 1175ff984e57SWei WANG mmc->f_min = 250000; 1176ff984e57SWei WANG mmc->f_max = 208000000; 1177ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1178ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1179ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1180ff984e57SWei WANG MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1181ff984e57SWei WANG mmc->max_current_330 = 400; 1182ff984e57SWei WANG mmc->max_current_180 = 800; 1183ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1184ff984e57SWei WANG 1185ff984e57SWei WANG init_extra_caps(host); 1186ff984e57SWei WANG 1187ff984e57SWei WANG mmc->max_segs = 256; 1188ff984e57SWei WANG mmc->max_seg_size = 65536; 1189ff984e57SWei WANG mmc->max_blk_size = 512; 1190ff984e57SWei WANG mmc->max_blk_count = 65535; 1191ff984e57SWei WANG mmc->max_req_size = 524288; 1192ff984e57SWei WANG } 1193ff984e57SWei WANG 1194ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1195ff984e57SWei WANG { 1196ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1197ff984e57SWei WANG 1198ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1199ff984e57SWei WANG } 1200ff984e57SWei WANG 1201ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1202ff984e57SWei WANG { 1203ff984e57SWei WANG struct mmc_host *mmc; 1204ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1205ff984e57SWei WANG struct rtsx_pcr *pcr; 1206ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1207ff984e57SWei WANG 1208ff984e57SWei WANG if (!handle) 1209ff984e57SWei WANG return -ENXIO; 1210ff984e57SWei WANG 1211ff984e57SWei WANG pcr = handle->pcr; 1212ff984e57SWei WANG if (!pcr) 1213ff984e57SWei WANG return -ENXIO; 1214ff984e57SWei WANG 1215ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1216ff984e57SWei WANG 1217ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1218ff984e57SWei WANG if (!mmc) 1219ff984e57SWei WANG return -ENOMEM; 1220ff984e57SWei WANG 1221ff984e57SWei WANG host = mmc_priv(mmc); 1222ff984e57SWei WANG host->pcr = pcr; 1223ff984e57SWei WANG host->mmc = mmc; 1224ff984e57SWei WANG host->pdev = pdev; 1225d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 1226ff984e57SWei WANG platform_set_drvdata(pdev, host); 1227ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1228ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1229ff984e57SWei WANG 1230ff984e57SWei WANG mutex_init(&host->host_mutex); 1231ff984e57SWei WANG 1232ff984e57SWei WANG realtek_init_host(host); 1233ff984e57SWei WANG 1234ff984e57SWei WANG mmc_add_host(mmc); 1235ff984e57SWei WANG 1236ff984e57SWei WANG return 0; 1237ff984e57SWei WANG } 1238ff984e57SWei WANG 1239ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1240ff984e57SWei WANG { 1241ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1242ff984e57SWei WANG struct rtsx_pcr *pcr; 1243ff984e57SWei WANG struct mmc_host *mmc; 1244ff984e57SWei WANG 1245ff984e57SWei WANG if (!host) 1246ff984e57SWei WANG return 0; 1247ff984e57SWei WANG 1248ff984e57SWei WANG pcr = host->pcr; 1249ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1250ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1251ff984e57SWei WANG mmc = host->mmc; 1252ff984e57SWei WANG 1253ff984e57SWei WANG mutex_lock(&host->host_mutex); 1254ff984e57SWei WANG if (host->mrq) { 1255ff984e57SWei WANG dev_dbg(&(pdev->dev), 1256ff984e57SWei WANG "%s: Controller removed during transfer\n", 1257ff984e57SWei WANG mmc_hostname(mmc)); 1258ff984e57SWei WANG 1259ff984e57SWei WANG rtsx_pci_complete_unfinished_transfer(pcr); 1260ff984e57SWei WANG 1261ff984e57SWei WANG host->mrq->cmd->error = -ENOMEDIUM; 1262ff984e57SWei WANG if (host->mrq->stop) 1263ff984e57SWei WANG host->mrq->stop->error = -ENOMEDIUM; 1264ff984e57SWei WANG mmc_request_done(mmc, host->mrq); 1265ff984e57SWei WANG } 1266ff984e57SWei WANG mutex_unlock(&host->host_mutex); 1267ff984e57SWei WANG 1268ff984e57SWei WANG mmc_remove_host(mmc); 1269640e09bcSMicky Ching host->eject = true; 1270640e09bcSMicky Ching 1271ff984e57SWei WANG mmc_free_host(mmc); 1272ff984e57SWei WANG 1273ff984e57SWei WANG dev_dbg(&(pdev->dev), 1274ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1275ff984e57SWei WANG 1276ff984e57SWei WANG return 0; 1277ff984e57SWei WANG } 1278ff984e57SWei WANG 1279ff984e57SWei WANG static struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1280ff984e57SWei WANG { 1281ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1282ff984e57SWei WANG }, { 1283ff984e57SWei WANG /* sentinel */ 1284ff984e57SWei WANG } 1285ff984e57SWei WANG }; 1286ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1287ff984e57SWei WANG 1288ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1289ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1290ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1291ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1292ff984e57SWei WANG .driver = { 1293ff984e57SWei WANG .owner = THIS_MODULE, 1294ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1295ff984e57SWei WANG }, 1296ff984e57SWei WANG }; 1297ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1298ff984e57SWei WANG 1299ff984e57SWei WANG MODULE_LICENSE("GPL"); 1300ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1301ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1302