1aaf4989bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 3ff984e57SWei WANG * 462282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5ff984e57SWei WANG * 6ff984e57SWei WANG * Author: 7ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 8ff984e57SWei WANG */ 9ff984e57SWei WANG 10ff984e57SWei WANG #include <linux/module.h> 11433e075cSWei WANG #include <linux/slab.h> 12ff984e57SWei WANG #include <linux/highmem.h> 13ff984e57SWei WANG #include <linux/delay.h> 14ff984e57SWei WANG #include <linux/platform_device.h> 156291e715SMicky Ching #include <linux/workqueue.h> 16ff984e57SWei WANG #include <linux/mmc/host.h> 17ff984e57SWei WANG #include <linux/mmc/mmc.h> 18ff984e57SWei WANG #include <linux/mmc/sd.h> 191dcb3579SMicky Ching #include <linux/mmc/sdio.h> 20ff984e57SWei WANG #include <linux/mmc/card.h> 21e455b69dSRui Feng #include <linux/rtsx_pci.h> 22ff984e57SWei WANG #include <asm/unaligned.h> 23ff984e57SWei WANG 24ff984e57SWei WANG struct realtek_pci_sdmmc { 25ff984e57SWei WANG struct platform_device *pdev; 26ff984e57SWei WANG struct rtsx_pcr *pcr; 27ff984e57SWei WANG struct mmc_host *mmc; 28ff984e57SWei WANG struct mmc_request *mrq; 296291e715SMicky Ching #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" 30ff984e57SWei WANG 316291e715SMicky Ching struct work_struct work; 3298fcc576SMicky Ching struct mutex host_mutex; 33ff984e57SWei WANG 34ff984e57SWei WANG u8 ssc_depth; 35ff984e57SWei WANG unsigned int clock; 36ff984e57SWei WANG bool vpclk; 37ff984e57SWei WANG bool double_clk; 38ff984e57SWei WANG bool eject; 39ff984e57SWei WANG bool initial_mode; 40d88691beSWei WANG int power_state; 41d88691beSWei WANG #define SDMMC_POWER_ON 1 42d88691beSWei WANG #define SDMMC_POWER_OFF 0 436291e715SMicky Ching 44be186ad5SMicky Ching int sg_count; 456291e715SMicky Ching s32 cookie; 46be186ad5SMicky Ching int cookie_sg_count; 476291e715SMicky Ching bool using_cookie; 48ff984e57SWei WANG }; 49ff984e57SWei WANG 50ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 51ff984e57SWei WANG { 52ff984e57SWei WANG return &(host->pdev->dev); 53ff984e57SWei WANG } 54ff984e57SWei WANG 55ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 56ff984e57SWei WANG { 57ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 58ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 59ff984e57SWei WANG } 60ff984e57SWei WANG 61ff984e57SWei WANG #ifdef DEBUG 62755987f9SMicky Ching static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end) 63755987f9SMicky Ching { 64755987f9SMicky Ching u16 len = end - start + 1; 65755987f9SMicky Ching int i; 66755987f9SMicky Ching u8 data[8]; 67755987f9SMicky Ching 68755987f9SMicky Ching for (i = 0; i < len; i += 8) { 69755987f9SMicky Ching int j; 70755987f9SMicky Ching int n = min(8, len - i); 71755987f9SMicky Ching 72755987f9SMicky Ching memset(&data, 0, sizeof(data)); 73755987f9SMicky Ching for (j = 0; j < n; j++) 74755987f9SMicky Ching rtsx_pci_read_register(host->pcr, start + i + j, 75755987f9SMicky Ching data + j); 76755987f9SMicky Ching dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n", 77755987f9SMicky Ching start + i, n, data); 78755987f9SMicky Ching } 79755987f9SMicky Ching } 80755987f9SMicky Ching 81ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 82ff984e57SWei WANG { 83755987f9SMicky Ching dump_reg_range(host, 0xFDA0, 0xFDB3); 84755987f9SMicky Ching dump_reg_range(host, 0xFD52, 0xFD69); 85ff984e57SWei WANG } 86ff984e57SWei WANG #else 87ff984e57SWei WANG #define sd_print_debug_regs(host) 88ff984e57SWei WANG #endif /* DEBUG */ 89ff984e57SWei WANG 90b22217f9SMicky Ching static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host) 91b22217f9SMicky Ching { 92b22217f9SMicky Ching return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST; 93b22217f9SMicky Ching } 94b22217f9SMicky Ching 952d48e5f1SMicky Ching static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd) 962d48e5f1SMicky Ching { 972d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 982d48e5f1SMicky Ching SD_CMD_START | cmd->opcode); 992d48e5f1SMicky Ching rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg); 1002d48e5f1SMicky Ching } 1012d48e5f1SMicky Ching 1022d48e5f1SMicky Ching static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz) 1032d48e5f1SMicky Ching { 1042d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); 1052d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); 1062d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); 1072d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); 1082d48e5f1SMicky Ching } 1092d48e5f1SMicky Ching 1102d48e5f1SMicky Ching static int sd_response_type(struct mmc_command *cmd) 1112d48e5f1SMicky Ching { 1122d48e5f1SMicky Ching switch (mmc_resp_type(cmd)) { 1132d48e5f1SMicky Ching case MMC_RSP_NONE: 1142d48e5f1SMicky Ching return SD_RSP_TYPE_R0; 1152d48e5f1SMicky Ching case MMC_RSP_R1: 1162d48e5f1SMicky Ching return SD_RSP_TYPE_R1; 1178c8d0ecbSWolfram Sang case MMC_RSP_R1_NO_CRC: 1182d48e5f1SMicky Ching return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; 1192d48e5f1SMicky Ching case MMC_RSP_R1B: 1202d48e5f1SMicky Ching return SD_RSP_TYPE_R1b; 1212d48e5f1SMicky Ching case MMC_RSP_R2: 1222d48e5f1SMicky Ching return SD_RSP_TYPE_R2; 1232d48e5f1SMicky Ching case MMC_RSP_R3: 1242d48e5f1SMicky Ching return SD_RSP_TYPE_R3; 1252d48e5f1SMicky Ching default: 1262d48e5f1SMicky Ching return -EINVAL; 1272d48e5f1SMicky Ching } 1282d48e5f1SMicky Ching } 1292d48e5f1SMicky Ching 1302d48e5f1SMicky Ching static int sd_status_index(int resp_type) 1312d48e5f1SMicky Ching { 1322d48e5f1SMicky Ching if (resp_type == SD_RSP_TYPE_R0) 1332d48e5f1SMicky Ching return 0; 1342d48e5f1SMicky Ching else if (resp_type == SD_RSP_TYPE_R2) 1352d48e5f1SMicky Ching return 16; 1362d48e5f1SMicky Ching 1372d48e5f1SMicky Ching return 5; 1382d48e5f1SMicky Ching } 1396291e715SMicky Ching /* 1406291e715SMicky Ching * sd_pre_dma_transfer - do dma_map_sg() or using cookie 1416291e715SMicky Ching * 1426291e715SMicky Ching * @pre: if called in pre_req() 1436291e715SMicky Ching * return: 1446291e715SMicky Ching * 0 - do dma_map_sg() 1456291e715SMicky Ching * 1 - using cookie 1466291e715SMicky Ching */ 1476291e715SMicky Ching static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, 1486291e715SMicky Ching struct mmc_data *data, bool pre) 1496291e715SMicky Ching { 1506291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 1516291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 1526291e715SMicky Ching int count = 0; 1536291e715SMicky Ching int using_cookie = 0; 1546291e715SMicky Ching 1556291e715SMicky Ching if (!pre && data->host_cookie && data->host_cookie != host->cookie) { 1566291e715SMicky Ching dev_err(sdmmc_dev(host), 1576291e715SMicky Ching "error: data->host_cookie = %d, host->cookie = %d\n", 1586291e715SMicky Ching data->host_cookie, host->cookie); 1596291e715SMicky Ching data->host_cookie = 0; 1606291e715SMicky Ching } 1616291e715SMicky Ching 1626291e715SMicky Ching if (pre || data->host_cookie != host->cookie) { 1636291e715SMicky Ching count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); 1646291e715SMicky Ching } else { 1656291e715SMicky Ching count = host->cookie_sg_count; 1666291e715SMicky Ching using_cookie = 1; 1676291e715SMicky Ching } 1686291e715SMicky Ching 1696291e715SMicky Ching if (pre) { 1706291e715SMicky Ching host->cookie_sg_count = count; 1716291e715SMicky Ching if (++host->cookie < 0) 1726291e715SMicky Ching host->cookie = 1; 1736291e715SMicky Ching data->host_cookie = host->cookie; 1746291e715SMicky Ching } else { 1756291e715SMicky Ching host->sg_count = count; 1766291e715SMicky Ching } 1776291e715SMicky Ching 1786291e715SMicky Ching return using_cookie; 1796291e715SMicky Ching } 1806291e715SMicky Ching 181d3c6aac3SLinus Walleij static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1826291e715SMicky Ching { 1836291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1846291e715SMicky Ching struct mmc_data *data = mrq->data; 1856291e715SMicky Ching 1866291e715SMicky Ching if (data->host_cookie) { 1876291e715SMicky Ching dev_err(sdmmc_dev(host), 1886291e715SMicky Ching "error: reset data->host_cookie = %d\n", 1896291e715SMicky Ching data->host_cookie); 1906291e715SMicky Ching data->host_cookie = 0; 1916291e715SMicky Ching } 1926291e715SMicky Ching 1936291e715SMicky Ching sd_pre_dma_transfer(host, data, true); 1946291e715SMicky Ching dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); 1956291e715SMicky Ching } 1966291e715SMicky Ching 1976291e715SMicky Ching static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1986291e715SMicky Ching int err) 1996291e715SMicky Ching { 2006291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 2016291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 2026291e715SMicky Ching struct mmc_data *data = mrq->data; 2036291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 2046291e715SMicky Ching 2056291e715SMicky Ching rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); 2066291e715SMicky Ching data->host_cookie = 0; 2076291e715SMicky Ching } 2086291e715SMicky Ching 20998fcc576SMicky Ching static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 21098fcc576SMicky Ching struct mmc_command *cmd) 211ff984e57SWei WANG { 212ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 213ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 214ff984e57SWei WANG u32 arg = cmd->arg; 215ff984e57SWei WANG int err = 0; 216ff984e57SWei WANG int timeout = 100; 217ff984e57SWei WANG int i; 21898fcc576SMicky Ching u8 *ptr; 2192d48e5f1SMicky Ching int rsp_type; 2202d48e5f1SMicky Ching int stat_idx; 22198fcc576SMicky Ching bool clock_toggled = false; 222ff984e57SWei WANG 223ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 224ff984e57SWei WANG __func__, cmd_idx, arg); 225ff984e57SWei WANG 2262d48e5f1SMicky Ching rsp_type = sd_response_type(cmd); 2272d48e5f1SMicky Ching if (rsp_type < 0) 228ff984e57SWei WANG goto out; 2292d48e5f1SMicky Ching 2302d48e5f1SMicky Ching stat_idx = sd_status_index(rsp_type); 231ff984e57SWei WANG 232ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 23327f4bf7dSUlf Hansson timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000; 234ff984e57SWei WANG 235ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 236ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 237ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 238ff984e57SWei WANG if (err < 0) 239ff984e57SWei WANG goto out; 24098fcc576SMicky Ching 24198fcc576SMicky Ching clock_toggled = true; 242ff984e57SWei WANG } 243ff984e57SWei WANG 244ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 2452d48e5f1SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 246ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 247ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 248ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 249ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 250ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 251ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 252ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 253ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 254ff984e57SWei WANG 255ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 256ff984e57SWei WANG /* Read data from ping-pong buffer */ 257ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 258ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 259ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 260ff984e57SWei WANG /* Read data from SD_CMDx registers */ 261ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 262ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 263ff984e57SWei WANG } 264ff984e57SWei WANG 265ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 266ff984e57SWei WANG 26798fcc576SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 26898fcc576SMicky Ching if (err < 0) { 26998fcc576SMicky Ching sd_print_debug_regs(host); 27098fcc576SMicky Ching sd_clear_error(host); 27198fcc576SMicky Ching dev_dbg(sdmmc_dev(host), 27298fcc576SMicky Ching "rtsx_pci_send_cmd error (err = %d)\n", err); 273ff984e57SWei WANG goto out; 274ff984e57SWei WANG } 275ff984e57SWei WANG 276ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 277ff984e57SWei WANG err = 0; 278ff984e57SWei WANG goto out; 279ff984e57SWei WANG } 280ff984e57SWei WANG 281ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 282ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 283ff984e57SWei WANG 284ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 285ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 286ff984e57SWei WANG err = -EILSEQ; 287ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 288ff984e57SWei WANG goto out; 289ff984e57SWei WANG } 290ff984e57SWei WANG 291ff984e57SWei WANG /* Check CRC7 */ 292ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 293ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 294ff984e57SWei WANG err = -EILSEQ; 295ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 296ff984e57SWei WANG goto out; 297ff984e57SWei WANG } 298ff984e57SWei WANG } 299ff984e57SWei WANG 300ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 301d1419d50SRoger Tseng /* 302d1419d50SRoger Tseng * The controller offloads the last byte {CRC-7, end bit 1'b1} 303d1419d50SRoger Tseng * of response type R2. Assign dummy CRC, 0, and end bit to the 304d1419d50SRoger Tseng * byte(ptr[16], goes into the LSB of resp[3] later). 305d1419d50SRoger Tseng */ 306d1419d50SRoger Tseng ptr[16] = 1; 307d1419d50SRoger Tseng 308ff984e57SWei WANG for (i = 0; i < 4; i++) { 309ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 310ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 311ff984e57SWei WANG i, cmd->resp[i]); 312ff984e57SWei WANG } 313ff984e57SWei WANG } else { 314ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 315ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 316ff984e57SWei WANG cmd->resp[0]); 317ff984e57SWei WANG } 318ff984e57SWei WANG 319ff984e57SWei WANG out: 320ff984e57SWei WANG cmd->error = err; 3211b8055b4SWei WANG 32298fcc576SMicky Ching if (err && clock_toggled) 32398fcc576SMicky Ching rtsx_pci_write_register(pcr, SD_BUS_STAT, 32498fcc576SMicky Ching SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 325ff984e57SWei WANG } 326ff984e57SWei WANG 32756d1c0d9SMicky Ching static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd, 32856d1c0d9SMicky Ching u16 byte_cnt, u8 *buf, int buf_len, int timeout) 32956d1c0d9SMicky Ching { 33056d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr; 33156d1c0d9SMicky Ching int err; 33256d1c0d9SMicky Ching u8 trans_mode; 33356d1c0d9SMicky Ching 33456d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 33556d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg); 33656d1c0d9SMicky Ching 33756d1c0d9SMicky Ching if (!buf) 33856d1c0d9SMicky Ching buf_len = 0; 33956d1c0d9SMicky Ching 34056d1c0d9SMicky Ching if (cmd->opcode == MMC_SEND_TUNING_BLOCK) 34156d1c0d9SMicky Ching trans_mode = SD_TM_AUTO_TUNING; 34256d1c0d9SMicky Ching else 34356d1c0d9SMicky Ching trans_mode = SD_TM_NORMAL_READ; 34456d1c0d9SMicky Ching 34556d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr); 34656d1c0d9SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 34756d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt); 34856d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 34956d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 35056d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 35156d1c0d9SMicky Ching if (trans_mode != SD_TM_AUTO_TUNING) 35256d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 35356d1c0d9SMicky Ching CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 35456d1c0d9SMicky Ching 35556d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 35656d1c0d9SMicky Ching 0xFF, trans_mode | SD_TRANSFER_START); 35756d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 35856d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 35956d1c0d9SMicky Ching 36056d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 36156d1c0d9SMicky Ching if (err < 0) { 36256d1c0d9SMicky Ching sd_print_debug_regs(host); 36356d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 36456d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err); 36556d1c0d9SMicky Ching return err; 36656d1c0d9SMicky Ching } 36756d1c0d9SMicky Ching 36856d1c0d9SMicky Ching if (buf && buf_len) { 36956d1c0d9SMicky Ching err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 37056d1c0d9SMicky Ching if (err < 0) { 37156d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 37256d1c0d9SMicky Ching "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 37356d1c0d9SMicky Ching return err; 37456d1c0d9SMicky Ching } 37556d1c0d9SMicky Ching } 37656d1c0d9SMicky Ching 37756d1c0d9SMicky Ching return 0; 37856d1c0d9SMicky Ching } 37956d1c0d9SMicky Ching 38056d1c0d9SMicky Ching static int sd_write_data(struct realtek_pci_sdmmc *host, 38156d1c0d9SMicky Ching struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len, 38256d1c0d9SMicky Ching int timeout) 38356d1c0d9SMicky Ching { 38456d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr; 38556d1c0d9SMicky Ching int err; 38656d1c0d9SMicky Ching 38756d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 38856d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg); 38956d1c0d9SMicky Ching 39056d1c0d9SMicky Ching if (!buf) 39156d1c0d9SMicky Ching buf_len = 0; 39256d1c0d9SMicky Ching 39356d1c0d9SMicky Ching sd_send_cmd_get_rsp(host, cmd); 39456d1c0d9SMicky Ching if (cmd->error) 39556d1c0d9SMicky Ching return cmd->error; 39656d1c0d9SMicky Ching 39756d1c0d9SMicky Ching if (buf && buf_len) { 39856d1c0d9SMicky Ching err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 39956d1c0d9SMicky Ching if (err < 0) { 40056d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 40156d1c0d9SMicky Ching "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 40256d1c0d9SMicky Ching return err; 40356d1c0d9SMicky Ching } 40456d1c0d9SMicky Ching } 40556d1c0d9SMicky Ching 40656d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr); 40756d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt); 40856d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 40956d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 41056d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0); 41156d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 41256d1c0d9SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 41356d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 41456d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 41556d1c0d9SMicky Ching 41656d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 41756d1c0d9SMicky Ching if (err < 0) { 41856d1c0d9SMicky Ching sd_print_debug_regs(host); 41956d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 42056d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err); 42156d1c0d9SMicky Ching return err; 42256d1c0d9SMicky Ching } 42356d1c0d9SMicky Ching 42456d1c0d9SMicky Ching return 0; 42556d1c0d9SMicky Ching } 42656d1c0d9SMicky Ching 4271dcb3579SMicky Ching static int sd_read_long_data(struct realtek_pci_sdmmc *host, 4281dcb3579SMicky Ching struct mmc_request *mrq) 429ff984e57SWei WANG { 430ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 431ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 432ff984e57SWei WANG struct mmc_card *card = mmc->card; 4331dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd; 434ff984e57SWei WANG struct mmc_data *data = mrq->data; 43571ef1ea4SJackey Shen int uhs = mmc_card_uhs(card); 4361dcb3579SMicky Ching u8 cfg2 = 0; 437ff984e57SWei WANG int err; 4381dcb3579SMicky Ching int resp_type; 439ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 440ff984e57SWei WANG 4411dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 4421dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg); 4431dcb3579SMicky Ching 4441dcb3579SMicky Ching resp_type = sd_response_type(cmd); 4451dcb3579SMicky Ching if (resp_type < 0) 4461dcb3579SMicky Ching return resp_type; 447ff984e57SWei WANG 448ff984e57SWei WANG if (!uhs) 449ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 450ff984e57SWei WANG 451ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 4521dcb3579SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 4531dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 454ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 455ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 456ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 457ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 458ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 459ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 460ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 461ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 462ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 463ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 464ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 465ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 4661dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 4671dcb3579SMicky Ching 0x01, RING_BUFFER); 4681dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); 4691dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 4701dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_READ_2); 4711dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 4721dcb3579SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 4731dcb3579SMicky Ching rtsx_pci_send_cmd_no_wait(pcr); 4741dcb3579SMicky Ching 4751dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000); 4761dcb3579SMicky Ching if (err < 0) { 4771dcb3579SMicky Ching sd_print_debug_regs(host); 4781dcb3579SMicky Ching sd_clear_error(host); 4791dcb3579SMicky Ching return err; 4801dcb3579SMicky Ching } 4811dcb3579SMicky Ching 4821dcb3579SMicky Ching return 0; 4831dcb3579SMicky Ching } 4841dcb3579SMicky Ching 4851dcb3579SMicky Ching static int sd_write_long_data(struct realtek_pci_sdmmc *host, 4861dcb3579SMicky Ching struct mmc_request *mrq) 4871dcb3579SMicky Ching { 4881dcb3579SMicky Ching struct rtsx_pcr *pcr = host->pcr; 4891dcb3579SMicky Ching struct mmc_host *mmc = host->mmc; 4901dcb3579SMicky Ching struct mmc_card *card = mmc->card; 4911dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd; 4921dcb3579SMicky Ching struct mmc_data *data = mrq->data; 4931dcb3579SMicky Ching int uhs = mmc_card_uhs(card); 4941dcb3579SMicky Ching u8 cfg2; 4951dcb3579SMicky Ching int err; 4961dcb3579SMicky Ching size_t data_len = data->blksz * data->blocks; 4971dcb3579SMicky Ching 4981dcb3579SMicky Ching sd_send_cmd_get_rsp(host, cmd); 4991dcb3579SMicky Ching if (cmd->error) 5001dcb3579SMicky Ching return cmd->error; 5011dcb3579SMicky Ching 5021dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 5031dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg); 5041dcb3579SMicky Ching 5051dcb3579SMicky Ching cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 5061dcb3579SMicky Ching SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 5071dcb3579SMicky Ching 5081dcb3579SMicky Ching if (!uhs) 5091dcb3579SMicky Ching cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 5101dcb3579SMicky Ching 5111dcb3579SMicky Ching rtsx_pci_init_cmd(pcr); 5121dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 5131dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 5141dcb3579SMicky Ching DMA_DONE_INT, DMA_DONE_INT); 5151dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 5161dcb3579SMicky Ching 0xFF, (u8)(data_len >> 24)); 5171dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 5181dcb3579SMicky Ching 0xFF, (u8)(data_len >> 16)); 5191dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 5201dcb3579SMicky Ching 0xFF, (u8)(data_len >> 8)); 5211dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 522ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 523ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 524ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 525ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 526ff984e57SWei WANG 0x01, RING_BUFFER); 52738d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 528ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 5291dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 530ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 531ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 532ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 5331dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000); 534ff984e57SWei WANG if (err < 0) { 53598fcc576SMicky Ching sd_clear_error(host); 53698fcc576SMicky Ching return err; 537c42deffdSMicky Ching } 53898fcc576SMicky Ching 539c42deffdSMicky Ching return 0; 540ff984e57SWei WANG } 541ff984e57SWei WANG 5421dcb3579SMicky Ching static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 5431dcb3579SMicky Ching { 5441dcb3579SMicky Ching struct mmc_data *data = mrq->data; 5451dcb3579SMicky Ching 546be186ad5SMicky Ching if (host->sg_count < 0) { 547be186ad5SMicky Ching data->error = host->sg_count; 548be186ad5SMicky Ching dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n", 549be186ad5SMicky Ching __func__, host->sg_count); 550be186ad5SMicky Ching return data->error; 551be186ad5SMicky Ching } 552be186ad5SMicky Ching 5531dcb3579SMicky Ching if (data->flags & MMC_DATA_READ) 5541dcb3579SMicky Ching return sd_read_long_data(host, mrq); 5551dcb3579SMicky Ching 5561dcb3579SMicky Ching return sd_write_long_data(host, mrq); 5571dcb3579SMicky Ching } 5581dcb3579SMicky Ching 559ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 560ff984e57SWei WANG { 561ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 562ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 563ff984e57SWei WANG } 564ff984e57SWei WANG 565ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 566ff984e57SWei WANG { 567ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 568ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 569ff984e57SWei WANG } 570ff984e57SWei WANG 571ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 572ff984e57SWei WANG struct mmc_request *mrq) 573ff984e57SWei WANG { 574ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 575ff984e57SWei WANG struct mmc_data *data = mrq->data; 5761dcb3579SMicky Ching u8 *buf; 577ff984e57SWei WANG 578ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 579ff984e57SWei WANG if (!buf) { 580ff984e57SWei WANG cmd->error = -ENOMEM; 581ff984e57SWei WANG return; 582ff984e57SWei WANG } 583ff984e57SWei WANG 584ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 585ff984e57SWei WANG if (host->initial_mode) 586ff984e57SWei WANG sd_disable_initial_mode(host); 587ff984e57SWei WANG 5881dcb3579SMicky Ching cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf, 589ff984e57SWei WANG data->blksz, 200); 590ff984e57SWei WANG 591ff984e57SWei WANG if (host->initial_mode) 592ff984e57SWei WANG sd_enable_initial_mode(host); 593ff984e57SWei WANG 594ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 595ff984e57SWei WANG } else { 596ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 597ff984e57SWei WANG 5981dcb3579SMicky Ching cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf, 599ff984e57SWei WANG data->blksz, 200); 600ff984e57SWei WANG } 601ff984e57SWei WANG 602ff984e57SWei WANG kfree(buf); 603ff984e57SWei WANG } 604ff984e57SWei WANG 60584d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, 60684d72f9cSWei WANG u8 sample_point, bool rx) 607ff984e57SWei WANG { 608ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 609ff984e57SWei WANG 61084d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 61184d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point); 612ff984e57SWei WANG 613563be8b6Srui_feng rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 61484d72f9cSWei WANG if (rx) 615563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_VPRX_CTL, 616563be8b6Srui_feng PHASE_SELECT_MASK, sample_point); 61784d72f9cSWei WANG else 618563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_VPTX_CTL, 619563be8b6Srui_feng PHASE_SELECT_MASK, sample_point); 620563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); 621563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET, 622563be8b6Srui_feng PHASE_NOT_RESET); 623563be8b6Srui_feng rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0); 624563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 625ff984e57SWei WANG 626ff984e57SWei WANG return 0; 627ff984e57SWei WANG } 628ff984e57SWei WANG 629abcc6b29SMicky Ching static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 630abcc6b29SMicky Ching { 631abcc6b29SMicky Ching bit %= RTSX_PHASE_MAX; 632abcc6b29SMicky Ching return phase_map & (1 << bit); 633abcc6b29SMicky Ching } 634abcc6b29SMicky Ching 635abcc6b29SMicky Ching static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 636abcc6b29SMicky Ching { 637abcc6b29SMicky Ching int i; 638abcc6b29SMicky Ching 639abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 640abcc6b29SMicky Ching if (test_phase_bit(phase_map, start_bit + i) == 0) 641abcc6b29SMicky Ching return i; 642abcc6b29SMicky Ching } 643abcc6b29SMicky Ching return RTSX_PHASE_MAX; 644abcc6b29SMicky Ching } 645abcc6b29SMicky Ching 646ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 647ff984e57SWei WANG { 648abcc6b29SMicky Ching int start = 0, len = 0; 649abcc6b29SMicky Ching int start_final = 0, len_final = 0; 650ff984e57SWei WANG u8 final_phase = 0xFF; 651ff984e57SWei WANG 652abcc6b29SMicky Ching if (phase_map == 0) { 653abcc6b29SMicky Ching dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 654abcc6b29SMicky Ching return final_phase; 655ff984e57SWei WANG } 656ff984e57SWei WANG 657abcc6b29SMicky Ching while (start < RTSX_PHASE_MAX) { 658abcc6b29SMicky Ching len = sd_get_phase_len(phase_map, start); 659abcc6b29SMicky Ching if (len_final < len) { 660abcc6b29SMicky Ching start_final = start; 661abcc6b29SMicky Ching len_final = len; 662abcc6b29SMicky Ching } 663abcc6b29SMicky Ching start += len ? len : 1; 664ff984e57SWei WANG } 665ff984e57SWei WANG 666abcc6b29SMicky Ching final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 667abcc6b29SMicky Ching dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 668abcc6b29SMicky Ching phase_map, len_final, final_phase); 669ff984e57SWei WANG 670ff984e57SWei WANG return final_phase; 671ff984e57SWei WANG } 672ff984e57SWei WANG 673ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 674ff984e57SWei WANG { 675ff984e57SWei WANG int err, i; 676ff984e57SWei WANG u8 val = 0; 677ff984e57SWei WANG 678ff984e57SWei WANG for (i = 0; i < 100; i++) { 679ff984e57SWei WANG err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 680ff984e57SWei WANG if (val & SD_DATA_IDLE) 681ff984e57SWei WANG return; 682ff984e57SWei WANG 683ff984e57SWei WANG udelay(100); 684ff984e57SWei WANG } 685ff984e57SWei WANG } 686ff984e57SWei WANG 687ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 688ff984e57SWei WANG u8 opcode, u8 sample_point) 689ff984e57SWei WANG { 690ff984e57SWei WANG int err; 691c7836d15SMasahiro Yamada struct mmc_command cmd = {}; 692563be8b6Srui_feng struct rtsx_pcr *pcr = host->pcr; 693ff984e57SWei WANG 694563be8b6Srui_feng sd_change_phase(host, sample_point, true); 695563be8b6Srui_feng 696563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 697563be8b6Srui_feng SD_RSP_80CLK_TIMEOUT_EN); 698ff984e57SWei WANG 6991dcb3579SMicky Ching cmd.opcode = opcode; 7001dcb3579SMicky Ching err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100); 701ff984e57SWei WANG if (err < 0) { 702ff984e57SWei WANG /* Wait till SD DATA IDLE */ 703ff984e57SWei WANG sd_wait_data_idle(host); 704ff984e57SWei WANG sd_clear_error(host); 705563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3, 706563be8b6Srui_feng SD_RSP_80CLK_TIMEOUT_EN, 0); 707ff984e57SWei WANG return err; 708ff984e57SWei WANG } 709ff984e57SWei WANG 710563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); 711ff984e57SWei WANG return 0; 712ff984e57SWei WANG } 713ff984e57SWei WANG 714ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 715ff984e57SWei WANG u8 opcode, u32 *phase_map) 716ff984e57SWei WANG { 717ff984e57SWei WANG int err, i; 718ff984e57SWei WANG u32 raw_phase_map = 0; 719ff984e57SWei WANG 720abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 721ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 722ff984e57SWei WANG if (err == 0) 723ff984e57SWei WANG raw_phase_map |= 1 << i; 724ff984e57SWei WANG } 725ff984e57SWei WANG 726ff984e57SWei WANG if (phase_map) 727ff984e57SWei WANG *phase_map = raw_phase_map; 728ff984e57SWei WANG 729ff984e57SWei WANG return 0; 730ff984e57SWei WANG } 731ff984e57SWei WANG 732ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 733ff984e57SWei WANG { 734ff984e57SWei WANG int err, i; 735ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 736ff984e57SWei WANG u8 final_phase; 737ff984e57SWei WANG 738ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 739ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 740ff984e57SWei WANG if (err < 0) 741ff984e57SWei WANG return err; 742ff984e57SWei WANG 743ff984e57SWei WANG if (raw_phase_map[i] == 0) 744ff984e57SWei WANG break; 745ff984e57SWei WANG } 746ff984e57SWei WANG 747ff984e57SWei WANG phase_map = 0xFFFFFFFF; 748ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 749ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 750ff984e57SWei WANG i, raw_phase_map[i]); 751ff984e57SWei WANG phase_map &= raw_phase_map[i]; 752ff984e57SWei WANG } 753ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 754ff984e57SWei WANG 755ff984e57SWei WANG if (phase_map) { 756ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 757ff984e57SWei WANG if (final_phase == 0xFF) 758ff984e57SWei WANG return -EINVAL; 759ff984e57SWei WANG 76084d72f9cSWei WANG err = sd_change_phase(host, final_phase, true); 761ff984e57SWei WANG if (err < 0) 762ff984e57SWei WANG return err; 763ff984e57SWei WANG } else { 764ff984e57SWei WANG return -EINVAL; 765ff984e57SWei WANG } 766ff984e57SWei WANG 767ff984e57SWei WANG return 0; 768ff984e57SWei WANG } 769ff984e57SWei WANG 7701dcb3579SMicky Ching static inline int sdio_extblock_cmd(struct mmc_command *cmd, 7711dcb3579SMicky Ching struct mmc_data *data) 7721dcb3579SMicky Ching { 7731dcb3579SMicky Ching return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512); 7741dcb3579SMicky Ching } 7751dcb3579SMicky Ching 7766291e715SMicky Ching static inline int sd_rw_cmd(struct mmc_command *cmd) 777ff984e57SWei WANG { 7786291e715SMicky Ching return mmc_op_multi(cmd->opcode) || 7796291e715SMicky Ching (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 7806291e715SMicky Ching (cmd->opcode == MMC_WRITE_BLOCK); 7816291e715SMicky Ching } 7826291e715SMicky Ching 7836291e715SMicky Ching static void sd_request(struct work_struct *work) 7846291e715SMicky Ching { 7856291e715SMicky Ching struct realtek_pci_sdmmc *host = container_of(work, 7866291e715SMicky Ching struct realtek_pci_sdmmc, work); 787ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 7886291e715SMicky Ching 7896291e715SMicky Ching struct mmc_host *mmc = host->mmc; 7906291e715SMicky Ching struct mmc_request *mrq = host->mrq; 791ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 792ff984e57SWei WANG struct mmc_data *data = mrq->data; 7936291e715SMicky Ching 794ff984e57SWei WANG unsigned int data_size = 0; 795c3481955SWei WANG int err; 796ff984e57SWei WANG 797b22217f9SMicky Ching if (host->eject || !sd_get_cd_int(host)) { 798ff984e57SWei WANG cmd->error = -ENOMEDIUM; 799ff984e57SWei WANG goto finish; 800ff984e57SWei WANG } 801ff984e57SWei WANG 802c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 803c3481955SWei WANG if (err) { 804c3481955SWei WANG cmd->error = err; 805c3481955SWei WANG goto finish; 806c3481955SWei WANG } 807c3481955SWei WANG 80898fcc576SMicky Ching mutex_lock(&pcr->pcr_mutex); 80998fcc576SMicky Ching 810ff984e57SWei WANG rtsx_pci_start_run(pcr); 811ff984e57SWei WANG 812ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 813ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 814ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 815ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 816ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 817ff984e57SWei WANG 81898fcc576SMicky Ching mutex_lock(&host->host_mutex); 81998fcc576SMicky Ching host->mrq = mrq; 82098fcc576SMicky Ching mutex_unlock(&host->host_mutex); 82198fcc576SMicky Ching 822ff984e57SWei WANG if (mrq->data) 823ff984e57SWei WANG data_size = data->blocks * data->blksz; 824ff984e57SWei WANG 8251dcb3579SMicky Ching if (!data_size) { 82698fcc576SMicky Ching sd_send_cmd_get_rsp(host, cmd); 8271dcb3579SMicky Ching } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) { 8281dcb3579SMicky Ching cmd->error = sd_rw_multi(host, mrq); 8296291e715SMicky Ching if (!host->using_cookie) 8306291e715SMicky Ching sdmmc_post_req(host->mmc, host->mrq, 0); 83198fcc576SMicky Ching 83298fcc576SMicky Ching if (mmc_op_multi(cmd->opcode) && mrq->stop) 83398fcc576SMicky Ching sd_send_cmd_get_rsp(host, mrq->stop); 83498fcc576SMicky Ching } else { 83598fcc576SMicky Ching sd_normal_rw(host, mrq); 83698fcc576SMicky Ching } 83798fcc576SMicky Ching 83898fcc576SMicky Ching if (mrq->data) { 83998fcc576SMicky Ching if (cmd->error || data->error) 84098fcc576SMicky Ching data->bytes_xfered = 0; 84198fcc576SMicky Ching else 84298fcc576SMicky Ching data->bytes_xfered = data->blocks * data->blksz; 84398fcc576SMicky Ching } 84498fcc576SMicky Ching 84598fcc576SMicky Ching mutex_unlock(&pcr->pcr_mutex); 846ff984e57SWei WANG 847ff984e57SWei WANG finish: 8481dcb3579SMicky Ching if (cmd->error) { 8491dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n", 8501dcb3579SMicky Ching cmd->opcode, cmd->arg, cmd->error); 8511dcb3579SMicky Ching } 85298fcc576SMicky Ching 85398fcc576SMicky Ching mutex_lock(&host->host_mutex); 85498fcc576SMicky Ching host->mrq = NULL; 85598fcc576SMicky Ching mutex_unlock(&host->host_mutex); 85698fcc576SMicky Ching 85798fcc576SMicky Ching mmc_request_done(mmc, mrq); 858ff984e57SWei WANG } 859ff984e57SWei WANG 8606291e715SMicky Ching static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 8616291e715SMicky Ching { 8626291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 8636291e715SMicky Ching struct mmc_data *data = mrq->data; 8646291e715SMicky Ching 8656291e715SMicky Ching mutex_lock(&host->host_mutex); 8666291e715SMicky Ching host->mrq = mrq; 8676291e715SMicky Ching mutex_unlock(&host->host_mutex); 8686291e715SMicky Ching 8691dcb3579SMicky Ching if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data)) 8706291e715SMicky Ching host->using_cookie = sd_pre_dma_transfer(host, data, false); 8716291e715SMicky Ching 8726ea62579SBhaktipriya Shridhar schedule_work(&host->work); 8736291e715SMicky Ching } 8746291e715SMicky Ching 875ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 876ff984e57SWei WANG unsigned char bus_width) 877ff984e57SWei WANG { 878ff984e57SWei WANG int err = 0; 879ff984e57SWei WANG u8 width[] = { 880ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 881ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 882ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 883ff984e57SWei WANG }; 884ff984e57SWei WANG 885ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 886ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 887ff984e57SWei WANG 0x03, width[bus_width]); 888ff984e57SWei WANG 889ff984e57SWei WANG return err; 890ff984e57SWei WANG } 891ff984e57SWei WANG 892ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 893ff984e57SWei WANG { 894ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 895ff984e57SWei WANG int err; 896ff984e57SWei WANG 897d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 898d88691beSWei WANG return 0; 899d88691beSWei WANG 900ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 901ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 902ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 903ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 904ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 905ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 906ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 907ff984e57SWei WANG if (err < 0) 908ff984e57SWei WANG return err; 909ff984e57SWei WANG 910ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 911ff984e57SWei WANG if (err < 0) 912ff984e57SWei WANG return err; 913ff984e57SWei WANG 914ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 915ff984e57SWei WANG if (err < 0) 916ff984e57SWei WANG return err; 917ff984e57SWei WANG 918ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 919ff984e57SWei WANG if (err < 0) 920ff984e57SWei WANG return err; 921ff984e57SWei WANG 922d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 923ff984e57SWei WANG return 0; 924ff984e57SWei WANG } 925ff984e57SWei WANG 926ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 927ff984e57SWei WANG { 928ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 929ff984e57SWei WANG int err; 930ff984e57SWei WANG 931d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 932d88691beSWei WANG 933ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 934ff984e57SWei WANG 935ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 936ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 937ff984e57SWei WANG 938ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 939ff984e57SWei WANG if (err < 0) 940ff984e57SWei WANG return err; 941ff984e57SWei WANG 942ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 943ff984e57SWei WANG if (err < 0) 944ff984e57SWei WANG return err; 945ff984e57SWei WANG 946ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 947ff984e57SWei WANG } 948ff984e57SWei WANG 949ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 950ff984e57SWei WANG unsigned char power_mode) 951ff984e57SWei WANG { 952ff984e57SWei WANG int err; 953ff984e57SWei WANG 954ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 955ff984e57SWei WANG err = sd_power_off(host); 956ff984e57SWei WANG else 957ff984e57SWei WANG err = sd_power_on(host); 958ff984e57SWei WANG 959ff984e57SWei WANG return err; 960ff984e57SWei WANG } 961ff984e57SWei WANG 96284d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 963ff984e57SWei WANG { 964ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 965ff984e57SWei WANG int err = 0; 966ff984e57SWei WANG 967ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 968ff984e57SWei WANG 969ff984e57SWei WANG switch (timing) { 970ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 971ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 972ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 973ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 974ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 975ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 976ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 977ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 978ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 979ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 980ff984e57SWei WANG break; 981ff984e57SWei WANG 9821a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 983ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 984ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 985ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 986ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 987ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 988ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 989ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 990ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 991ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 992ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 993ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 994ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 995ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 996ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 997ff984e57SWei WANG break; 998ff984e57SWei WANG 999ff984e57SWei WANG case MMC_TIMING_MMC_HS: 1000ff984e57SWei WANG case MMC_TIMING_SD_HS: 1001ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1002ff984e57SWei WANG 0x0C, SD_20_MODE); 1003ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1004ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1005ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1006ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1007ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1008ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1009ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 1010ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1011ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 1012ff984e57SWei WANG break; 1013ff984e57SWei WANG 1014ff984e57SWei WANG default: 1015ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1016ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 1017ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1018ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1019ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1020ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1021ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1022ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1023ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 1024ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1025ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 1026ff984e57SWei WANG break; 1027ff984e57SWei WANG } 1028ff984e57SWei WANG 1029ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 1030ff984e57SWei WANG 1031ff984e57SWei WANG return err; 1032ff984e57SWei WANG } 1033ff984e57SWei WANG 1034ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1035ff984e57SWei WANG { 1036ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1037ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1038ff984e57SWei WANG 1039ff984e57SWei WANG if (host->eject) 1040ff984e57SWei WANG return; 1041ff984e57SWei WANG 1042c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 1043c3481955SWei WANG return; 1044c3481955SWei WANG 1045ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1046ff984e57SWei WANG 1047ff984e57SWei WANG rtsx_pci_start_run(pcr); 1048ff984e57SWei WANG 1049ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 1050ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 105184d72f9cSWei WANG sd_set_timing(host, ios->timing); 1052ff984e57SWei WANG 1053ff984e57SWei WANG host->vpclk = false; 1054ff984e57SWei WANG host->double_clk = true; 1055ff984e57SWei WANG 1056ff984e57SWei WANG switch (ios->timing) { 1057ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1058ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1059ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 1060ff984e57SWei WANG host->vpclk = true; 1061ff984e57SWei WANG host->double_clk = false; 1062ff984e57SWei WANG break; 10631a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 1064ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1065ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 1066ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 1067ff984e57SWei WANG break; 1068ff984e57SWei WANG default: 1069ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 1070ff984e57SWei WANG break; 1071ff984e57SWei WANG } 1072ff984e57SWei WANG 1073ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 1074ff984e57SWei WANG 1075ff984e57SWei WANG host->clock = ios->clock; 1076ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 1077ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 1078ff984e57SWei WANG 1079ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1080ff984e57SWei WANG } 1081ff984e57SWei WANG 1082ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 1083ff984e57SWei WANG { 1084ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1085ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1086ff984e57SWei WANG int ro = 0; 1087ff984e57SWei WANG u32 val; 1088ff984e57SWei WANG 1089ff984e57SWei WANG if (host->eject) 1090ff984e57SWei WANG return -ENOMEDIUM; 1091ff984e57SWei WANG 1092ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1093ff984e57SWei WANG 1094ff984e57SWei WANG rtsx_pci_start_run(pcr); 1095ff984e57SWei WANG 1096ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 1097ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 1098ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1099ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 1100ff984e57SWei WANG ro = 1; 1101ff984e57SWei WANG 1102ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1103ff984e57SWei WANG 1104ff984e57SWei WANG return ro; 1105ff984e57SWei WANG } 1106ff984e57SWei WANG 1107ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 1108ff984e57SWei WANG { 1109ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1110ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1111ff984e57SWei WANG int cd = 0; 1112ff984e57SWei WANG u32 val; 1113ff984e57SWei WANG 1114ff984e57SWei WANG if (host->eject) 1115b22217f9SMicky Ching return cd; 1116ff984e57SWei WANG 1117ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1118ff984e57SWei WANG 1119ff984e57SWei WANG rtsx_pci_start_run(pcr); 1120ff984e57SWei WANG 1121ff984e57SWei WANG /* Check SD card detect */ 1122ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 1123ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1124ff984e57SWei WANG if (val & SD_EXIST) 1125ff984e57SWei WANG cd = 1; 1126ff984e57SWei WANG 1127ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1128ff984e57SWei WANG 1129ff984e57SWei WANG return cd; 1130ff984e57SWei WANG } 1131ff984e57SWei WANG 1132ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1133ff984e57SWei WANG { 1134ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1135ff984e57SWei WANG int err; 1136ff984e57SWei WANG u8 stat; 1137ff984e57SWei WANG 1138ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 1139ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 1140ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 1141ff984e57SWei WANG */ 1142ff984e57SWei WANG mdelay(1); 1143ff984e57SWei WANG 1144ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1145ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 1146ff984e57SWei WANG * abort the voltage switch sequence; 1147ff984e57SWei WANG */ 1148ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1149ff984e57SWei WANG if (err < 0) 1150ff984e57SWei WANG return err; 1151ff984e57SWei WANG 1152ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1153ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 1154ff984e57SWei WANG return -EINVAL; 1155ff984e57SWei WANG 1156ff984e57SWei WANG /* Stop toggle SD clock */ 1157ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1158ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 1159ff984e57SWei WANG if (err < 0) 1160ff984e57SWei WANG return err; 1161ff984e57SWei WANG 1162ff984e57SWei WANG return 0; 1163ff984e57SWei WANG } 1164ff984e57SWei WANG 1165ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1166ff984e57SWei WANG { 1167ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1168ff984e57SWei WANG int err; 1169ff984e57SWei WANG u8 stat, mask, val; 1170ff984e57SWei WANG 1171ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1172ff984e57SWei WANG msleep(50); 1173ff984e57SWei WANG 1174ff984e57SWei WANG /* Toggle SD clock again */ 1175ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1176ff984e57SWei WANG if (err < 0) 1177ff984e57SWei WANG return err; 1178ff984e57SWei WANG 1179ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1180ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1181ff984e57SWei WANG */ 1182ff984e57SWei WANG msleep(20); 1183ff984e57SWei WANG 1184ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1185ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1186ff984e57SWei WANG if (err < 0) 1187ff984e57SWei WANG return err; 1188ff984e57SWei WANG 1189ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1190ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1191ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1192ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1193ff984e57SWei WANG if ((stat & mask) != val) { 1194ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1195ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1196ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1197ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1198ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1199ff984e57SWei WANG return -EINVAL; 1200ff984e57SWei WANG } 1201ff984e57SWei WANG 1202ff984e57SWei WANG return 0; 1203ff984e57SWei WANG } 1204ff984e57SWei WANG 1205ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1206ff984e57SWei WANG { 1207ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1208ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1209ff984e57SWei WANG int err = 0; 1210ff984e57SWei WANG u8 voltage; 1211ff984e57SWei WANG 1212ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1213ff984e57SWei WANG __func__, ios->signal_voltage); 1214ff984e57SWei WANG 1215ff984e57SWei WANG if (host->eject) 1216ff984e57SWei WANG return -ENOMEDIUM; 1217ff984e57SWei WANG 1218c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1219c3481955SWei WANG if (err) 1220c3481955SWei WANG return err; 1221c3481955SWei WANG 1222ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1223ff984e57SWei WANG 1224ff984e57SWei WANG rtsx_pci_start_run(pcr); 1225ff984e57SWei WANG 1226ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1227ef85e736SWei WANG voltage = OUTPUT_3V3; 1228ff984e57SWei WANG else 1229ef85e736SWei WANG voltage = OUTPUT_1V8; 1230ff984e57SWei WANG 1231ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1232ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1233ff984e57SWei WANG if (err < 0) 1234ff984e57SWei WANG goto out; 1235ff984e57SWei WANG } 1236ff984e57SWei WANG 1237ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1238ff984e57SWei WANG if (err < 0) 1239ff984e57SWei WANG goto out; 1240ff984e57SWei WANG 1241ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1242ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1243ff984e57SWei WANG if (err < 0) 1244ff984e57SWei WANG goto out; 1245ff984e57SWei WANG } 1246ff984e57SWei WANG 12471b8055b4SWei WANG out: 1248ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1249ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1250ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1251ff984e57SWei WANG 1252ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1253ff984e57SWei WANG 1254ff984e57SWei WANG return err; 1255ff984e57SWei WANG } 1256ff984e57SWei WANG 1257ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1258ff984e57SWei WANG { 1259ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1260ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1261ff984e57SWei WANG int err = 0; 1262ff984e57SWei WANG 1263ff984e57SWei WANG if (host->eject) 1264ff984e57SWei WANG return -ENOMEDIUM; 1265ff984e57SWei WANG 1266c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1267c3481955SWei WANG if (err) 1268c3481955SWei WANG return err; 1269c3481955SWei WANG 1270ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1271ff984e57SWei WANG 1272ff984e57SWei WANG rtsx_pci_start_run(pcr); 1273ff984e57SWei WANG 127484d72f9cSWei WANG /* Set initial TX phase */ 127584d72f9cSWei WANG switch (mmc->ios.timing) { 127684d72f9cSWei WANG case MMC_TIMING_UHS_SDR104: 127784d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 127884d72f9cSWei WANG break; 1279ff984e57SWei WANG 128084d72f9cSWei WANG case MMC_TIMING_UHS_SDR50: 128184d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 128284d72f9cSWei WANG break; 128384d72f9cSWei WANG 128484d72f9cSWei WANG case MMC_TIMING_UHS_DDR50: 128584d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 128684d72f9cSWei WANG break; 128784d72f9cSWei WANG 128884d72f9cSWei WANG default: 128984d72f9cSWei WANG err = 0; 129084d72f9cSWei WANG } 129184d72f9cSWei WANG 129284d72f9cSWei WANG if (err) 129384d72f9cSWei WANG goto out; 129484d72f9cSWei WANG 129584d72f9cSWei WANG /* Tuning RX phase */ 129684d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 129784d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 129884d72f9cSWei WANG err = sd_tuning_rx(host, opcode); 129984d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 130084d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 130184d72f9cSWei WANG 130284d72f9cSWei WANG out: 1303ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1304ff984e57SWei WANG 1305ff984e57SWei WANG return err; 1306ff984e57SWei WANG } 1307ff984e57SWei WANG 1308ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 13096291e715SMicky Ching .pre_req = sdmmc_pre_req, 13106291e715SMicky Ching .post_req = sdmmc_post_req, 1311ff984e57SWei WANG .request = sdmmc_request, 1312ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1313ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1314ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1315ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1316ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 1317ff984e57SWei WANG }; 1318ff984e57SWei WANG 1319ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1320ff984e57SWei WANG { 1321ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1322ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1323ff984e57SWei WANG 1324ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1325ff984e57SWei WANG 1326ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1327ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1328ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1329ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1330ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1331ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1332ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1333ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1334ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1335ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1336ff984e57SWei WANG } 1337ff984e57SWei WANG 1338ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1339ff984e57SWei WANG { 1340ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1341ff984e57SWei WANG 1342ff984e57SWei WANG mmc->f_min = 250000; 1343ff984e57SWei WANG mmc->f_max = 208000000; 1344ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1345ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1346ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 13479bce7fd6SUlf Hansson MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE; 1348517bf80fSRoger Tseng mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE; 1349ff984e57SWei WANG mmc->max_current_330 = 400; 1350ff984e57SWei WANG mmc->max_current_180 = 800; 1351ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1352ff984e57SWei WANG 1353ff984e57SWei WANG init_extra_caps(host); 1354ff984e57SWei WANG 1355ff984e57SWei WANG mmc->max_segs = 256; 1356ff984e57SWei WANG mmc->max_seg_size = 65536; 1357ff984e57SWei WANG mmc->max_blk_size = 512; 1358ff984e57SWei WANG mmc->max_blk_count = 65535; 1359ff984e57SWei WANG mmc->max_req_size = 524288; 1360ff984e57SWei WANG } 1361ff984e57SWei WANG 1362ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1363ff984e57SWei WANG { 1364ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1365ff984e57SWei WANG 13662057647fSMicky Ching host->cookie = -1; 1367ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1368ff984e57SWei WANG } 1369ff984e57SWei WANG 1370ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1371ff984e57SWei WANG { 1372ff984e57SWei WANG struct mmc_host *mmc; 1373ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1374ff984e57SWei WANG struct rtsx_pcr *pcr; 1375ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1376ff984e57SWei WANG 1377ff984e57SWei WANG if (!handle) 1378ff984e57SWei WANG return -ENXIO; 1379ff984e57SWei WANG 1380ff984e57SWei WANG pcr = handle->pcr; 1381ff984e57SWei WANG if (!pcr) 1382ff984e57SWei WANG return -ENXIO; 1383ff984e57SWei WANG 1384ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1385ff984e57SWei WANG 1386ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1387ff984e57SWei WANG if (!mmc) 1388ff984e57SWei WANG return -ENOMEM; 1389ff984e57SWei WANG 1390ff984e57SWei WANG host = mmc_priv(mmc); 1391ff984e57SWei WANG host->pcr = pcr; 1392ff984e57SWei WANG host->mmc = mmc; 1393ff984e57SWei WANG host->pdev = pdev; 13942057647fSMicky Ching host->cookie = -1; 1395d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 13966291e715SMicky Ching INIT_WORK(&host->work, sd_request); 1397ff984e57SWei WANG platform_set_drvdata(pdev, host); 1398ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1399ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1400ff984e57SWei WANG 140198fcc576SMicky Ching mutex_init(&host->host_mutex); 1402ff984e57SWei WANG 1403ff984e57SWei WANG realtek_init_host(host); 1404ff984e57SWei WANG 1405ff984e57SWei WANG mmc_add_host(mmc); 1406ff984e57SWei WANG 1407ff984e57SWei WANG return 0; 1408ff984e57SWei WANG } 1409ff984e57SWei WANG 1410ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1411ff984e57SWei WANG { 1412ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1413ff984e57SWei WANG struct rtsx_pcr *pcr; 1414ff984e57SWei WANG struct mmc_host *mmc; 1415ff984e57SWei WANG 1416ff984e57SWei WANG if (!host) 1417ff984e57SWei WANG return 0; 1418ff984e57SWei WANG 1419ff984e57SWei WANG pcr = host->pcr; 1420ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1421ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1422ff984e57SWei WANG mmc = host->mmc; 1423ff984e57SWei WANG 14246291e715SMicky Ching cancel_work_sync(&host->work); 14256291e715SMicky Ching 142698fcc576SMicky Ching mutex_lock(&host->host_mutex); 1427ff984e57SWei WANG if (host->mrq) { 1428ff984e57SWei WANG dev_dbg(&(pdev->dev), 1429ff984e57SWei WANG "%s: Controller removed during transfer\n", 1430ff984e57SWei WANG mmc_hostname(mmc)); 1431ff984e57SWei WANG 143298fcc576SMicky Ching rtsx_pci_complete_unfinished_transfer(pcr); 1433ff984e57SWei WANG 143498fcc576SMicky Ching host->mrq->cmd->error = -ENOMEDIUM; 143598fcc576SMicky Ching if (host->mrq->stop) 143698fcc576SMicky Ching host->mrq->stop->error = -ENOMEDIUM; 143798fcc576SMicky Ching mmc_request_done(mmc, host->mrq); 1438ff984e57SWei WANG } 143998fcc576SMicky Ching mutex_unlock(&host->host_mutex); 1440ff984e57SWei WANG 1441ff984e57SWei WANG mmc_remove_host(mmc); 1442640e09bcSMicky Ching host->eject = true; 1443640e09bcSMicky Ching 14446ea62579SBhaktipriya Shridhar flush_work(&host->work); 14456291e715SMicky Ching 1446ff984e57SWei WANG mmc_free_host(mmc); 1447ff984e57SWei WANG 1448ff984e57SWei WANG dev_dbg(&(pdev->dev), 1449ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1450ff984e57SWei WANG 1451ff984e57SWei WANG return 0; 1452ff984e57SWei WANG } 1453ff984e57SWei WANG 1454f2483b0dSKrzysztof Kozlowski static const struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1455ff984e57SWei WANG { 1456ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1457ff984e57SWei WANG }, { 1458ff984e57SWei WANG /* sentinel */ 1459ff984e57SWei WANG } 1460ff984e57SWei WANG }; 1461ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1462ff984e57SWei WANG 1463ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1464ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1465ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1466ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1467ff984e57SWei WANG .driver = { 1468ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1469ff984e57SWei WANG }, 1470ff984e57SWei WANG }; 1471ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1472ff984e57SWei WANG 1473ff984e57SWei WANG MODULE_LICENSE("GPL"); 1474ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1475ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1476