1ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 2ff984e57SWei WANG * 362282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4ff984e57SWei WANG * 5ff984e57SWei WANG * This program is free software; you can redistribute it and/or modify it 6ff984e57SWei WANG * under the terms of the GNU General Public License as published by the 7ff984e57SWei WANG * Free Software Foundation; either version 2, or (at your option) any 8ff984e57SWei WANG * later version. 9ff984e57SWei WANG * 10ff984e57SWei WANG * This program is distributed in the hope that it will be useful, but 11ff984e57SWei WANG * WITHOUT ANY WARRANTY; without even the implied warranty of 12ff984e57SWei WANG * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13ff984e57SWei WANG * General Public License for more details. 14ff984e57SWei WANG * 15ff984e57SWei WANG * You should have received a copy of the GNU General Public License along 16ff984e57SWei WANG * with this program; if not, see <http://www.gnu.org/licenses/>. 17ff984e57SWei WANG * 18ff984e57SWei WANG * Author: 19ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 20ff984e57SWei WANG */ 21ff984e57SWei WANG 22ff984e57SWei WANG #include <linux/module.h> 23433e075cSWei WANG #include <linux/slab.h> 24ff984e57SWei WANG #include <linux/highmem.h> 25ff984e57SWei WANG #include <linux/delay.h> 26ff984e57SWei WANG #include <linux/platform_device.h> 27ff984e57SWei WANG #include <linux/mmc/host.h> 28ff984e57SWei WANG #include <linux/mmc/mmc.h> 29ff984e57SWei WANG #include <linux/mmc/sd.h> 30ff984e57SWei WANG #include <linux/mmc/card.h> 31ff984e57SWei WANG #include <linux/mfd/rtsx_pci.h> 32ff984e57SWei WANG #include <asm/unaligned.h> 33ff984e57SWei WANG 34ff984e57SWei WANG /* SD Tuning Data Structure 35ff984e57SWei WANG * Record continuous timing phase path 36ff984e57SWei WANG */ 37ff984e57SWei WANG struct timing_phase_path { 38ff984e57SWei WANG int start; 39ff984e57SWei WANG int end; 40ff984e57SWei WANG int mid; 41ff984e57SWei WANG int len; 42ff984e57SWei WANG }; 43ff984e57SWei WANG 44ff984e57SWei WANG struct realtek_pci_sdmmc { 45ff984e57SWei WANG struct platform_device *pdev; 46ff984e57SWei WANG struct rtsx_pcr *pcr; 47ff984e57SWei WANG struct mmc_host *mmc; 48ff984e57SWei WANG struct mmc_request *mrq; 49ff984e57SWei WANG 50ff984e57SWei WANG struct mutex host_mutex; 51ff984e57SWei WANG 52ff984e57SWei WANG u8 ssc_depth; 53ff984e57SWei WANG unsigned int clock; 54ff984e57SWei WANG bool vpclk; 55ff984e57SWei WANG bool double_clk; 56ff984e57SWei WANG bool eject; 57ff984e57SWei WANG bool initial_mode; 58d88691beSWei WANG int power_state; 59d88691beSWei WANG #define SDMMC_POWER_ON 1 60d88691beSWei WANG #define SDMMC_POWER_OFF 0 61ff984e57SWei WANG }; 62ff984e57SWei WANG 63ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 64ff984e57SWei WANG { 65ff984e57SWei WANG return &(host->pdev->dev); 66ff984e57SWei WANG } 67ff984e57SWei WANG 68ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 69ff984e57SWei WANG { 70ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 71ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 72ff984e57SWei WANG } 73ff984e57SWei WANG 74ff984e57SWei WANG #ifdef DEBUG 75ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 76ff984e57SWei WANG { 77ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 78ff984e57SWei WANG u16 i; 79ff984e57SWei WANG u8 *ptr; 80ff984e57SWei WANG 81ff984e57SWei WANG /* Print SD host internal registers */ 82ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 83ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 84ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 85ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 86ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 87ff984e57SWei WANG rtsx_pci_send_cmd(pcr, 100); 88ff984e57SWei WANG 89ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr); 90ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 91ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 92ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 93ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 94ff984e57SWei WANG } 95ff984e57SWei WANG #else 96ff984e57SWei WANG #define sd_print_debug_regs(host) 97ff984e57SWei WANG #endif /* DEBUG */ 98ff984e57SWei WANG 99ff984e57SWei WANG static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 100ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 101ff984e57SWei WANG { 102ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 103ff984e57SWei WANG int err, i; 104ff984e57SWei WANG u8 trans_mode; 105ff984e57SWei WANG 106ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40); 107ff984e57SWei WANG 108ff984e57SWei WANG if (!buf) 109ff984e57SWei WANG buf_len = 0; 110ff984e57SWei WANG 111ff984e57SWei WANG if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK) 112ff984e57SWei WANG trans_mode = SD_TM_AUTO_TUNING; 113ff984e57SWei WANG else 114ff984e57SWei WANG trans_mode = SD_TM_NORMAL_READ; 115ff984e57SWei WANG 116ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 117ff984e57SWei WANG 118ff984e57SWei WANG for (i = 0; i < 5; i++) 119ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]); 120ff984e57SWei WANG 121ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 122ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 123ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 124ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 125ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 126ff984e57SWei WANG 127ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 128ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 129ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 130ff984e57SWei WANG if (trans_mode != SD_TM_AUTO_TUNING) 131ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 132ff984e57SWei WANG CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 133ff984e57SWei WANG 134ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 135ff984e57SWei WANG 0xFF, trans_mode | SD_TRANSFER_START); 136ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 137ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 138ff984e57SWei WANG 139ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 140ff984e57SWei WANG if (err < 0) { 141ff984e57SWei WANG sd_print_debug_regs(host); 142ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 143ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 144ff984e57SWei WANG return err; 145ff984e57SWei WANG } 146ff984e57SWei WANG 147ff984e57SWei WANG if (buf && buf_len) { 148ff984e57SWei WANG err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 149ff984e57SWei WANG if (err < 0) { 150ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 151ff984e57SWei WANG "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 152ff984e57SWei WANG return err; 153ff984e57SWei WANG } 154ff984e57SWei WANG } 155ff984e57SWei WANG 156ff984e57SWei WANG return 0; 157ff984e57SWei WANG } 158ff984e57SWei WANG 159ff984e57SWei WANG static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 160ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 161ff984e57SWei WANG { 162ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 163ff984e57SWei WANG int err, i; 164ff984e57SWei WANG u8 trans_mode; 165ff984e57SWei WANG 166ff984e57SWei WANG if (!buf) 167ff984e57SWei WANG buf_len = 0; 168ff984e57SWei WANG 169ff984e57SWei WANG if (buf && buf_len) { 170ff984e57SWei WANG err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 171ff984e57SWei WANG if (err < 0) { 172ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 173ff984e57SWei WANG "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 174ff984e57SWei WANG return err; 175ff984e57SWei WANG } 176ff984e57SWei WANG } 177ff984e57SWei WANG 178ff984e57SWei WANG trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3; 179ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 180ff984e57SWei WANG 181ff984e57SWei WANG if (cmd) { 182ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__, 183ff984e57SWei WANG cmd[0] - 0x40); 184ff984e57SWei WANG 185ff984e57SWei WANG for (i = 0; i < 5; i++) 186ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 187ff984e57SWei WANG SD_CMD0 + i, 0xFF, cmd[i]); 188ff984e57SWei WANG } 189ff984e57SWei WANG 190ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 191ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 192ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 193ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 194ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 195ff984e57SWei WANG 196ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 197ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 198ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 199ff984e57SWei WANG 200ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 201ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 202ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 203ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 204ff984e57SWei WANG 205ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 206ff984e57SWei WANG if (err < 0) { 207ff984e57SWei WANG sd_print_debug_regs(host); 208ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 209ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 210ff984e57SWei WANG return err; 211ff984e57SWei WANG } 212ff984e57SWei WANG 213ff984e57SWei WANG return 0; 214ff984e57SWei WANG } 215ff984e57SWei WANG 216ff984e57SWei WANG static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 217ff984e57SWei WANG struct mmc_command *cmd) 218ff984e57SWei WANG { 219ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 220ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 221ff984e57SWei WANG u32 arg = cmd->arg; 222ff984e57SWei WANG int err = 0; 223ff984e57SWei WANG int timeout = 100; 224ff984e57SWei WANG int i; 225ff984e57SWei WANG u8 *ptr; 226ff984e57SWei WANG int stat_idx = 0; 227ff984e57SWei WANG u8 rsp_type; 228ff984e57SWei WANG int rsp_len = 5; 2291b8055b4SWei WANG bool clock_toggled = false; 230ff984e57SWei WANG 231ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 232ff984e57SWei WANG __func__, cmd_idx, arg); 233ff984e57SWei WANG 234ff984e57SWei WANG /* Response type: 235ff984e57SWei WANG * R0 236ff984e57SWei WANG * R1, R5, R6, R7 237ff984e57SWei WANG * R1b 238ff984e57SWei WANG * R2 239ff984e57SWei WANG * R3, R4 240ff984e57SWei WANG */ 241ff984e57SWei WANG switch (mmc_resp_type(cmd)) { 242ff984e57SWei WANG case MMC_RSP_NONE: 243ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R0; 244ff984e57SWei WANG rsp_len = 0; 245ff984e57SWei WANG break; 246ff984e57SWei WANG case MMC_RSP_R1: 247ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1; 248ff984e57SWei WANG break; 249ff984e57SWei WANG case MMC_RSP_R1B: 250ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1b; 251ff984e57SWei WANG break; 252ff984e57SWei WANG case MMC_RSP_R2: 253ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R2; 254ff984e57SWei WANG rsp_len = 16; 255ff984e57SWei WANG break; 256ff984e57SWei WANG case MMC_RSP_R3: 257ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R3; 258ff984e57SWei WANG break; 259ff984e57SWei WANG default: 260ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n"); 261ff984e57SWei WANG err = -EINVAL; 262ff984e57SWei WANG goto out; 263ff984e57SWei WANG } 264ff984e57SWei WANG 265ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 266ff984e57SWei WANG timeout = 3000; 267ff984e57SWei WANG 268ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 269ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 270ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 271ff984e57SWei WANG if (err < 0) 272ff984e57SWei WANG goto out; 2731b8055b4SWei WANG 2741b8055b4SWei WANG clock_toggled = true; 275ff984e57SWei WANG } 276ff984e57SWei WANG 277ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 278ff984e57SWei WANG 279ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx); 280ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24)); 281ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16)); 282ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8)); 283ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg); 284ff984e57SWei WANG 285ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 286ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 287ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 288ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 289ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 290ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 291ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 292ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 293ff984e57SWei WANG 294ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 295ff984e57SWei WANG /* Read data from ping-pong buffer */ 296ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 297ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 298ff984e57SWei WANG stat_idx = 16; 299ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 300ff984e57SWei WANG /* Read data from SD_CMDx registers */ 301ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 302ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 303ff984e57SWei WANG stat_idx = 5; 304ff984e57SWei WANG } 305ff984e57SWei WANG 306ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 307ff984e57SWei WANG 308ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 309ff984e57SWei WANG if (err < 0) { 310ff984e57SWei WANG sd_print_debug_regs(host); 311ff984e57SWei WANG sd_clear_error(host); 312ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 313ff984e57SWei WANG "rtsx_pci_send_cmd error (err = %d)\n", err); 314ff984e57SWei WANG goto out; 315ff984e57SWei WANG } 316ff984e57SWei WANG 317ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 318ff984e57SWei WANG err = 0; 319ff984e57SWei WANG goto out; 320ff984e57SWei WANG } 321ff984e57SWei WANG 322ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 323ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 324ff984e57SWei WANG 325ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 326ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 327ff984e57SWei WANG err = -EILSEQ; 328ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 329ff984e57SWei WANG goto out; 330ff984e57SWei WANG } 331ff984e57SWei WANG 332ff984e57SWei WANG /* Check CRC7 */ 333ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 334ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 335ff984e57SWei WANG err = -EILSEQ; 336ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 337ff984e57SWei WANG goto out; 338ff984e57SWei WANG } 339ff984e57SWei WANG } 340ff984e57SWei WANG 341ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 342ff984e57SWei WANG for (i = 0; i < 4; i++) { 343ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 344ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 345ff984e57SWei WANG i, cmd->resp[i]); 346ff984e57SWei WANG } 347ff984e57SWei WANG } else { 348ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 349ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 350ff984e57SWei WANG cmd->resp[0]); 351ff984e57SWei WANG } 352ff984e57SWei WANG 353ff984e57SWei WANG out: 354ff984e57SWei WANG cmd->error = err; 3551b8055b4SWei WANG 3561b8055b4SWei WANG if (err && clock_toggled) 3571b8055b4SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 3581b8055b4SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 359ff984e57SWei WANG } 360ff984e57SWei WANG 361ff984e57SWei WANG static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 362ff984e57SWei WANG { 363ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 364ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 365ff984e57SWei WANG struct mmc_card *card = mmc->card; 366ff984e57SWei WANG struct mmc_data *data = mrq->data; 36771ef1ea4SJackey Shen int uhs = mmc_card_uhs(card); 368ff984e57SWei WANG int read = (data->flags & MMC_DATA_READ) ? 1 : 0; 369ff984e57SWei WANG u8 cfg2, trans_mode; 370ff984e57SWei WANG int err; 371ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 372ff984e57SWei WANG 373ff984e57SWei WANG if (read) { 374ff984e57SWei WANG cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 375ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0; 376ff984e57SWei WANG trans_mode = SD_TM_AUTO_READ_3; 377ff984e57SWei WANG } else { 378ff984e57SWei WANG cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 379ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 380ff984e57SWei WANG trans_mode = SD_TM_AUTO_WRITE_3; 381ff984e57SWei WANG } 382ff984e57SWei WANG 383ff984e57SWei WANG if (!uhs) 384ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 385ff984e57SWei WANG 386ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 387ff984e57SWei WANG 388ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00); 389ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02); 390ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 391ff984e57SWei WANG 0xFF, (u8)data->blocks); 392ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 393ff984e57SWei WANG 0xFF, (u8)(data->blocks >> 8)); 394ff984e57SWei WANG 395ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 396ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 397ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 398ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 399ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 400ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 401ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 402ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 403ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 404ff984e57SWei WANG if (read) { 405ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 406ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 407ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 408ff984e57SWei WANG } else { 409ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 410ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 411ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 412ff984e57SWei WANG } 413ff984e57SWei WANG 414ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 415ff984e57SWei WANG 0x01, RING_BUFFER); 416ff984e57SWei WANG 41738d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 418ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 419ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 420ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 421ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 422ff984e57SWei WANG 423ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 424ff984e57SWei WANG 425ff984e57SWei WANG err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000); 426ff984e57SWei WANG if (err < 0) { 427ff984e57SWei WANG sd_clear_error(host); 428ff984e57SWei WANG return err; 429ff984e57SWei WANG } 430ff984e57SWei WANG 431ff984e57SWei WANG return 0; 432ff984e57SWei WANG } 433ff984e57SWei WANG 434ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 435ff984e57SWei WANG { 436ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 437ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 438ff984e57SWei WANG } 439ff984e57SWei WANG 440ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 441ff984e57SWei WANG { 442ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 443ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 444ff984e57SWei WANG } 445ff984e57SWei WANG 446ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 447ff984e57SWei WANG struct mmc_request *mrq) 448ff984e57SWei WANG { 449ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 450ff984e57SWei WANG struct mmc_data *data = mrq->data; 451ff984e57SWei WANG u8 _cmd[5], *buf; 452ff984e57SWei WANG 453ff984e57SWei WANG _cmd[0] = 0x40 | (u8)cmd->opcode; 454ff984e57SWei WANG put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1])); 455ff984e57SWei WANG 456ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 457ff984e57SWei WANG if (!buf) { 458ff984e57SWei WANG cmd->error = -ENOMEM; 459ff984e57SWei WANG return; 460ff984e57SWei WANG } 461ff984e57SWei WANG 462ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 463ff984e57SWei WANG if (host->initial_mode) 464ff984e57SWei WANG sd_disable_initial_mode(host); 465ff984e57SWei WANG 466ff984e57SWei WANG cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf, 467ff984e57SWei WANG data->blksz, 200); 468ff984e57SWei WANG 469ff984e57SWei WANG if (host->initial_mode) 470ff984e57SWei WANG sd_enable_initial_mode(host); 471ff984e57SWei WANG 472ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 473ff984e57SWei WANG } else { 474ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 475ff984e57SWei WANG 476ff984e57SWei WANG cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf, 477ff984e57SWei WANG data->blksz, 200); 478ff984e57SWei WANG } 479ff984e57SWei WANG 480ff984e57SWei WANG kfree(buf); 481ff984e57SWei WANG } 482ff984e57SWei WANG 48384d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, 48484d72f9cSWei WANG u8 sample_point, bool rx) 485ff984e57SWei WANG { 486ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 487ff984e57SWei WANG int err; 488ff984e57SWei WANG 48984d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 49084d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point); 491ff984e57SWei WANG 492ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 493ff984e57SWei WANG 494ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 49584d72f9cSWei WANG if (rx) 49684d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 49784d72f9cSWei WANG SD_VPRX_CTL, 0x1F, sample_point); 49884d72f9cSWei WANG else 49984d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 50084d72f9cSWei WANG SD_VPTX_CTL, 0x1F, sample_point); 501ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); 502ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 503ff984e57SWei WANG PHASE_NOT_RESET, PHASE_NOT_RESET); 504ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); 505ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 506ff984e57SWei WANG 507ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 508ff984e57SWei WANG if (err < 0) 509ff984e57SWei WANG return err; 510ff984e57SWei WANG 511ff984e57SWei WANG return 0; 512ff984e57SWei WANG } 513ff984e57SWei WANG 514ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 515ff984e57SWei WANG { 516ff984e57SWei WANG struct timing_phase_path path[MAX_PHASE + 1]; 517ff984e57SWei WANG int i, j, cont_path_cnt; 518ff984e57SWei WANG int new_block, max_len, final_path_idx; 519ff984e57SWei WANG u8 final_phase = 0xFF; 520ff984e57SWei WANG 521ff984e57SWei WANG /* Parse phase_map, take it as a bit-ring */ 522ff984e57SWei WANG cont_path_cnt = 0; 523ff984e57SWei WANG new_block = 1; 524ff984e57SWei WANG j = 0; 525ff984e57SWei WANG for (i = 0; i < MAX_PHASE + 1; i++) { 526ff984e57SWei WANG if (phase_map & (1 << i)) { 527ff984e57SWei WANG if (new_block) { 528ff984e57SWei WANG new_block = 0; 529ff984e57SWei WANG j = cont_path_cnt++; 530ff984e57SWei WANG path[j].start = i; 531ff984e57SWei WANG path[j].end = i; 532ff984e57SWei WANG } else { 533ff984e57SWei WANG path[j].end = i; 534ff984e57SWei WANG } 535ff984e57SWei WANG } else { 536ff984e57SWei WANG new_block = 1; 537ff984e57SWei WANG if (cont_path_cnt) { 538ff984e57SWei WANG /* Calculate path length and middle point */ 539ff984e57SWei WANG int idx = cont_path_cnt - 1; 540ff984e57SWei WANG path[idx].len = 541ff984e57SWei WANG path[idx].end - path[idx].start + 1; 542ff984e57SWei WANG path[idx].mid = 543ff984e57SWei WANG path[idx].start + path[idx].len / 2; 544ff984e57SWei WANG } 545ff984e57SWei WANG } 546ff984e57SWei WANG } 547ff984e57SWei WANG 548ff984e57SWei WANG if (cont_path_cnt == 0) { 549ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "No continuous phase path\n"); 550ff984e57SWei WANG goto finish; 551ff984e57SWei WANG } else { 552ff984e57SWei WANG /* Calculate last continuous path length and middle point */ 553ff984e57SWei WANG int idx = cont_path_cnt - 1; 554ff984e57SWei WANG path[idx].len = path[idx].end - path[idx].start + 1; 555ff984e57SWei WANG path[idx].mid = path[idx].start + path[idx].len / 2; 556ff984e57SWei WANG } 557ff984e57SWei WANG 558ff984e57SWei WANG /* Connect the first and last continuous paths if they are adjacent */ 559ff984e57SWei WANG if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) { 560ff984e57SWei WANG /* Using negative index */ 561ff984e57SWei WANG path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1; 562ff984e57SWei WANG path[0].len += path[cont_path_cnt - 1].len; 563ff984e57SWei WANG path[0].mid = path[0].start + path[0].len / 2; 564ff984e57SWei WANG /* Convert negative middle point index to positive one */ 565ff984e57SWei WANG if (path[0].mid < 0) 566ff984e57SWei WANG path[0].mid += MAX_PHASE + 1; 567ff984e57SWei WANG cont_path_cnt--; 568ff984e57SWei WANG } 569ff984e57SWei WANG 570ff984e57SWei WANG /* Choose the longest continuous phase path */ 571ff984e57SWei WANG max_len = 0; 572ff984e57SWei WANG final_phase = 0; 573ff984e57SWei WANG final_path_idx = 0; 574ff984e57SWei WANG for (i = 0; i < cont_path_cnt; i++) { 575ff984e57SWei WANG if (path[i].len > max_len) { 576ff984e57SWei WANG max_len = path[i].len; 577ff984e57SWei WANG final_phase = (u8)path[i].mid; 578ff984e57SWei WANG final_path_idx = i; 579ff984e57SWei WANG } 580ff984e57SWei WANG 581ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n", 582ff984e57SWei WANG i, path[i].start); 583ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n", 584ff984e57SWei WANG i, path[i].end); 585ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n", 586ff984e57SWei WANG i, path[i].len); 587ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n", 588ff984e57SWei WANG i, path[i].mid); 589ff984e57SWei WANG } 590ff984e57SWei WANG 591ff984e57SWei WANG finish: 592ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase); 593ff984e57SWei WANG return final_phase; 594ff984e57SWei WANG } 595ff984e57SWei WANG 596ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 597ff984e57SWei WANG { 598ff984e57SWei WANG int err, i; 599ff984e57SWei WANG u8 val = 0; 600ff984e57SWei WANG 601ff984e57SWei WANG for (i = 0; i < 100; i++) { 602ff984e57SWei WANG err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 603ff984e57SWei WANG if (val & SD_DATA_IDLE) 604ff984e57SWei WANG return; 605ff984e57SWei WANG 606ff984e57SWei WANG udelay(100); 607ff984e57SWei WANG } 608ff984e57SWei WANG } 609ff984e57SWei WANG 610ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 611ff984e57SWei WANG u8 opcode, u8 sample_point) 612ff984e57SWei WANG { 613ff984e57SWei WANG int err; 614ff984e57SWei WANG u8 cmd[5] = {0}; 615ff984e57SWei WANG 61684d72f9cSWei WANG err = sd_change_phase(host, sample_point, true); 617ff984e57SWei WANG if (err < 0) 618ff984e57SWei WANG return err; 619ff984e57SWei WANG 620ff984e57SWei WANG cmd[0] = 0x40 | opcode; 621ff984e57SWei WANG err = sd_read_data(host, cmd, 0x40, NULL, 0, 100); 622ff984e57SWei WANG if (err < 0) { 623ff984e57SWei WANG /* Wait till SD DATA IDLE */ 624ff984e57SWei WANG sd_wait_data_idle(host); 625ff984e57SWei WANG sd_clear_error(host); 626ff984e57SWei WANG return err; 627ff984e57SWei WANG } 628ff984e57SWei WANG 629ff984e57SWei WANG return 0; 630ff984e57SWei WANG } 631ff984e57SWei WANG 632ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 633ff984e57SWei WANG u8 opcode, u32 *phase_map) 634ff984e57SWei WANG { 635ff984e57SWei WANG int err, i; 636ff984e57SWei WANG u32 raw_phase_map = 0; 637ff984e57SWei WANG 638ff984e57SWei WANG for (i = MAX_PHASE; i >= 0; i--) { 639ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 640ff984e57SWei WANG if (err == 0) 641ff984e57SWei WANG raw_phase_map |= 1 << i; 642ff984e57SWei WANG } 643ff984e57SWei WANG 644ff984e57SWei WANG if (phase_map) 645ff984e57SWei WANG *phase_map = raw_phase_map; 646ff984e57SWei WANG 647ff984e57SWei WANG return 0; 648ff984e57SWei WANG } 649ff984e57SWei WANG 650ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 651ff984e57SWei WANG { 652ff984e57SWei WANG int err, i; 653ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 654ff984e57SWei WANG u8 final_phase; 655ff984e57SWei WANG 656ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 657ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 658ff984e57SWei WANG if (err < 0) 659ff984e57SWei WANG return err; 660ff984e57SWei WANG 661ff984e57SWei WANG if (raw_phase_map[i] == 0) 662ff984e57SWei WANG break; 663ff984e57SWei WANG } 664ff984e57SWei WANG 665ff984e57SWei WANG phase_map = 0xFFFFFFFF; 666ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 667ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 668ff984e57SWei WANG i, raw_phase_map[i]); 669ff984e57SWei WANG phase_map &= raw_phase_map[i]; 670ff984e57SWei WANG } 671ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 672ff984e57SWei WANG 673ff984e57SWei WANG if (phase_map) { 674ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 675ff984e57SWei WANG if (final_phase == 0xFF) 676ff984e57SWei WANG return -EINVAL; 677ff984e57SWei WANG 67884d72f9cSWei WANG err = sd_change_phase(host, final_phase, true); 679ff984e57SWei WANG if (err < 0) 680ff984e57SWei WANG return err; 681ff984e57SWei WANG } else { 682ff984e57SWei WANG return -EINVAL; 683ff984e57SWei WANG } 684ff984e57SWei WANG 685ff984e57SWei WANG return 0; 686ff984e57SWei WANG } 687ff984e57SWei WANG 688ff984e57SWei WANG static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 689ff984e57SWei WANG { 690ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 691ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 692ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 693ff984e57SWei WANG struct mmc_data *data = mrq->data; 694ff984e57SWei WANG unsigned int data_size = 0; 695c3481955SWei WANG int err; 696ff984e57SWei WANG 697ff984e57SWei WANG if (host->eject) { 698ff984e57SWei WANG cmd->error = -ENOMEDIUM; 699ff984e57SWei WANG goto finish; 700ff984e57SWei WANG } 701ff984e57SWei WANG 702c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 703c3481955SWei WANG if (err) { 704c3481955SWei WANG cmd->error = err; 705c3481955SWei WANG goto finish; 706c3481955SWei WANG } 707c3481955SWei WANG 708ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 709ff984e57SWei WANG 710ff984e57SWei WANG rtsx_pci_start_run(pcr); 711ff984e57SWei WANG 712ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 713ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 714ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 715ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 716ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 717ff984e57SWei WANG 718ff984e57SWei WANG mutex_lock(&host->host_mutex); 719ff984e57SWei WANG host->mrq = mrq; 720ff984e57SWei WANG mutex_unlock(&host->host_mutex); 721ff984e57SWei WANG 722ff984e57SWei WANG if (mrq->data) 723ff984e57SWei WANG data_size = data->blocks * data->blksz; 724ff984e57SWei WANG 725ff984e57SWei WANG if (!data_size || mmc_op_multi(cmd->opcode) || 726ff984e57SWei WANG (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 727ff984e57SWei WANG (cmd->opcode == MMC_WRITE_BLOCK)) { 728ff984e57SWei WANG sd_send_cmd_get_rsp(host, cmd); 729ff984e57SWei WANG 730ff984e57SWei WANG if (!cmd->error && data_size) { 731ff984e57SWei WANG sd_rw_multi(host, mrq); 732ff984e57SWei WANG 733ff984e57SWei WANG if (mmc_op_multi(cmd->opcode) && mrq->stop) 734ff984e57SWei WANG sd_send_cmd_get_rsp(host, mrq->stop); 735ff984e57SWei WANG } 736ff984e57SWei WANG } else { 737ff984e57SWei WANG sd_normal_rw(host, mrq); 738ff984e57SWei WANG } 739ff984e57SWei WANG 740ff984e57SWei WANG if (mrq->data) { 741ff984e57SWei WANG if (cmd->error || data->error) 742ff984e57SWei WANG data->bytes_xfered = 0; 743ff984e57SWei WANG else 744ff984e57SWei WANG data->bytes_xfered = data->blocks * data->blksz; 745ff984e57SWei WANG } 746ff984e57SWei WANG 747ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 748ff984e57SWei WANG 749ff984e57SWei WANG finish: 750ff984e57SWei WANG if (cmd->error) 751ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error); 752ff984e57SWei WANG 753ff984e57SWei WANG mutex_lock(&host->host_mutex); 754ff984e57SWei WANG host->mrq = NULL; 755ff984e57SWei WANG mutex_unlock(&host->host_mutex); 756ff984e57SWei WANG 757ff984e57SWei WANG mmc_request_done(mmc, mrq); 758ff984e57SWei WANG } 759ff984e57SWei WANG 760ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 761ff984e57SWei WANG unsigned char bus_width) 762ff984e57SWei WANG { 763ff984e57SWei WANG int err = 0; 764ff984e57SWei WANG u8 width[] = { 765ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 766ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 767ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 768ff984e57SWei WANG }; 769ff984e57SWei WANG 770ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 771ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 772ff984e57SWei WANG 0x03, width[bus_width]); 773ff984e57SWei WANG 774ff984e57SWei WANG return err; 775ff984e57SWei WANG } 776ff984e57SWei WANG 777ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 778ff984e57SWei WANG { 779ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 780ff984e57SWei WANG int err; 781ff984e57SWei WANG 782d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 783d88691beSWei WANG return 0; 784d88691beSWei WANG 785ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 786ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 787ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 788ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 789ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 790ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 791ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 792ff984e57SWei WANG if (err < 0) 793ff984e57SWei WANG return err; 794ff984e57SWei WANG 795ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 796ff984e57SWei WANG if (err < 0) 797ff984e57SWei WANG return err; 798ff984e57SWei WANG 799ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 800ff984e57SWei WANG if (err < 0) 801ff984e57SWei WANG return err; 802ff984e57SWei WANG 803ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 804ff984e57SWei WANG if (err < 0) 805ff984e57SWei WANG return err; 806ff984e57SWei WANG 807d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 808ff984e57SWei WANG return 0; 809ff984e57SWei WANG } 810ff984e57SWei WANG 811ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 812ff984e57SWei WANG { 813ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 814ff984e57SWei WANG int err; 815ff984e57SWei WANG 816d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 817d88691beSWei WANG 818ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 819ff984e57SWei WANG 820ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 821ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 822ff984e57SWei WANG 823ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 824ff984e57SWei WANG if (err < 0) 825ff984e57SWei WANG return err; 826ff984e57SWei WANG 827ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 828ff984e57SWei WANG if (err < 0) 829ff984e57SWei WANG return err; 830ff984e57SWei WANG 831ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 832ff984e57SWei WANG } 833ff984e57SWei WANG 834ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 835ff984e57SWei WANG unsigned char power_mode) 836ff984e57SWei WANG { 837ff984e57SWei WANG int err; 838ff984e57SWei WANG 839ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 840ff984e57SWei WANG err = sd_power_off(host); 841ff984e57SWei WANG else 842ff984e57SWei WANG err = sd_power_on(host); 843ff984e57SWei WANG 844ff984e57SWei WANG return err; 845ff984e57SWei WANG } 846ff984e57SWei WANG 84784d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 848ff984e57SWei WANG { 849ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 850ff984e57SWei WANG int err = 0; 851ff984e57SWei WANG 852ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 853ff984e57SWei WANG 854ff984e57SWei WANG switch (timing) { 855ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 856ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 857ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 858ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 859ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 860ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 861ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 862ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 863ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 864ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 865ff984e57SWei WANG break; 866ff984e57SWei WANG 867ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 868ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 869ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 870ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 871ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 872ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 873ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 874ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 875ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 876ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 877ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 878ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 879ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 880ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 881ff984e57SWei WANG break; 882ff984e57SWei WANG 883ff984e57SWei WANG case MMC_TIMING_MMC_HS: 884ff984e57SWei WANG case MMC_TIMING_SD_HS: 885ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 886ff984e57SWei WANG 0x0C, SD_20_MODE); 887ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 888ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 889ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 890ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 891ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 892ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 893ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 894ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 895ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 896ff984e57SWei WANG break; 897ff984e57SWei WANG 898ff984e57SWei WANG default: 899ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 900ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 901ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 902ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 903ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 904ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 905ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 906ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 907ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 908ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 909ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 910ff984e57SWei WANG break; 911ff984e57SWei WANG } 912ff984e57SWei WANG 913ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 914ff984e57SWei WANG 915ff984e57SWei WANG return err; 916ff984e57SWei WANG } 917ff984e57SWei WANG 918ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 919ff984e57SWei WANG { 920ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 921ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 922ff984e57SWei WANG 923ff984e57SWei WANG if (host->eject) 924ff984e57SWei WANG return; 925ff984e57SWei WANG 926c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 927c3481955SWei WANG return; 928c3481955SWei WANG 929ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 930ff984e57SWei WANG 931ff984e57SWei WANG rtsx_pci_start_run(pcr); 932ff984e57SWei WANG 933ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 934ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 93584d72f9cSWei WANG sd_set_timing(host, ios->timing); 936ff984e57SWei WANG 937ff984e57SWei WANG host->vpclk = false; 938ff984e57SWei WANG host->double_clk = true; 939ff984e57SWei WANG 940ff984e57SWei WANG switch (ios->timing) { 941ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 942ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 943ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 944ff984e57SWei WANG host->vpclk = true; 945ff984e57SWei WANG host->double_clk = false; 946ff984e57SWei WANG break; 947ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 948ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 949ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 950ff984e57SWei WANG break; 951ff984e57SWei WANG default: 952ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 953ff984e57SWei WANG break; 954ff984e57SWei WANG } 955ff984e57SWei WANG 956ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 957ff984e57SWei WANG 958ff984e57SWei WANG host->clock = ios->clock; 959ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 960ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 961ff984e57SWei WANG 962ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 963ff984e57SWei WANG } 964ff984e57SWei WANG 965ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 966ff984e57SWei WANG { 967ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 968ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 969ff984e57SWei WANG int ro = 0; 970ff984e57SWei WANG u32 val; 971ff984e57SWei WANG 972ff984e57SWei WANG if (host->eject) 973ff984e57SWei WANG return -ENOMEDIUM; 974ff984e57SWei WANG 975ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 976ff984e57SWei WANG 977ff984e57SWei WANG rtsx_pci_start_run(pcr); 978ff984e57SWei WANG 979ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 980ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 981ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 982ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 983ff984e57SWei WANG ro = 1; 984ff984e57SWei WANG 985ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 986ff984e57SWei WANG 987ff984e57SWei WANG return ro; 988ff984e57SWei WANG } 989ff984e57SWei WANG 990ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 991ff984e57SWei WANG { 992ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 993ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 994ff984e57SWei WANG int cd = 0; 995ff984e57SWei WANG u32 val; 996ff984e57SWei WANG 997ff984e57SWei WANG if (host->eject) 998ff984e57SWei WANG return -ENOMEDIUM; 999ff984e57SWei WANG 1000ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1001ff984e57SWei WANG 1002ff984e57SWei WANG rtsx_pci_start_run(pcr); 1003ff984e57SWei WANG 1004ff984e57SWei WANG /* Check SD card detect */ 1005ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 1006ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1007ff984e57SWei WANG if (val & SD_EXIST) 1008ff984e57SWei WANG cd = 1; 1009ff984e57SWei WANG 1010ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1011ff984e57SWei WANG 1012ff984e57SWei WANG return cd; 1013ff984e57SWei WANG } 1014ff984e57SWei WANG 1015ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1016ff984e57SWei WANG { 1017ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1018ff984e57SWei WANG int err; 1019ff984e57SWei WANG u8 stat; 1020ff984e57SWei WANG 1021ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 1022ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 1023ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 1024ff984e57SWei WANG */ 1025ff984e57SWei WANG mdelay(1); 1026ff984e57SWei WANG 1027ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1028ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 1029ff984e57SWei WANG * abort the voltage switch sequence; 1030ff984e57SWei WANG */ 1031ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1032ff984e57SWei WANG if (err < 0) 1033ff984e57SWei WANG return err; 1034ff984e57SWei WANG 1035ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1036ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 1037ff984e57SWei WANG return -EINVAL; 1038ff984e57SWei WANG 1039ff984e57SWei WANG /* Stop toggle SD clock */ 1040ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1041ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 1042ff984e57SWei WANG if (err < 0) 1043ff984e57SWei WANG return err; 1044ff984e57SWei WANG 1045ff984e57SWei WANG return 0; 1046ff984e57SWei WANG } 1047ff984e57SWei WANG 1048ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1049ff984e57SWei WANG { 1050ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1051ff984e57SWei WANG int err; 1052ff984e57SWei WANG u8 stat, mask, val; 1053ff984e57SWei WANG 1054ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1055ff984e57SWei WANG msleep(50); 1056ff984e57SWei WANG 1057ff984e57SWei WANG /* Toggle SD clock again */ 1058ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1059ff984e57SWei WANG if (err < 0) 1060ff984e57SWei WANG return err; 1061ff984e57SWei WANG 1062ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1063ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1064ff984e57SWei WANG */ 1065ff984e57SWei WANG msleep(20); 1066ff984e57SWei WANG 1067ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1068ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1069ff984e57SWei WANG if (err < 0) 1070ff984e57SWei WANG return err; 1071ff984e57SWei WANG 1072ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1073ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1074ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1075ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1076ff984e57SWei WANG if ((stat & mask) != val) { 1077ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1078ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1079ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1080ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1081ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1082ff984e57SWei WANG return -EINVAL; 1083ff984e57SWei WANG } 1084ff984e57SWei WANG 1085ff984e57SWei WANG return 0; 1086ff984e57SWei WANG } 1087ff984e57SWei WANG 1088ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1089ff984e57SWei WANG { 1090ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1091ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1092ff984e57SWei WANG int err = 0; 1093ff984e57SWei WANG u8 voltage; 1094ff984e57SWei WANG 1095ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1096ff984e57SWei WANG __func__, ios->signal_voltage); 1097ff984e57SWei WANG 1098ff984e57SWei WANG if (host->eject) 1099ff984e57SWei WANG return -ENOMEDIUM; 1100ff984e57SWei WANG 1101c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1102c3481955SWei WANG if (err) 1103c3481955SWei WANG return err; 1104c3481955SWei WANG 1105ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1106ff984e57SWei WANG 1107ff984e57SWei WANG rtsx_pci_start_run(pcr); 1108ff984e57SWei WANG 1109ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1110ef85e736SWei WANG voltage = OUTPUT_3V3; 1111ff984e57SWei WANG else 1112ef85e736SWei WANG voltage = OUTPUT_1V8; 1113ff984e57SWei WANG 1114ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1115ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1116ff984e57SWei WANG if (err < 0) 1117ff984e57SWei WANG goto out; 1118ff984e57SWei WANG } 1119ff984e57SWei WANG 1120ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1121ff984e57SWei WANG if (err < 0) 1122ff984e57SWei WANG goto out; 1123ff984e57SWei WANG 1124ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1125ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1126ff984e57SWei WANG if (err < 0) 1127ff984e57SWei WANG goto out; 1128ff984e57SWei WANG } 1129ff984e57SWei WANG 11301b8055b4SWei WANG out: 1131ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1132ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1133ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1134ff984e57SWei WANG 1135ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1136ff984e57SWei WANG 1137ff984e57SWei WANG return err; 1138ff984e57SWei WANG } 1139ff984e57SWei WANG 1140ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1141ff984e57SWei WANG { 1142ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1143ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1144ff984e57SWei WANG int err = 0; 1145ff984e57SWei WANG 1146ff984e57SWei WANG if (host->eject) 1147ff984e57SWei WANG return -ENOMEDIUM; 1148ff984e57SWei WANG 1149c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1150c3481955SWei WANG if (err) 1151c3481955SWei WANG return err; 1152c3481955SWei WANG 1153ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1154ff984e57SWei WANG 1155ff984e57SWei WANG rtsx_pci_start_run(pcr); 1156ff984e57SWei WANG 115784d72f9cSWei WANG /* Set initial TX phase */ 115884d72f9cSWei WANG switch (mmc->ios.timing) { 115984d72f9cSWei WANG case MMC_TIMING_UHS_SDR104: 116084d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 116184d72f9cSWei WANG break; 1162ff984e57SWei WANG 116384d72f9cSWei WANG case MMC_TIMING_UHS_SDR50: 116484d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 116584d72f9cSWei WANG break; 116684d72f9cSWei WANG 116784d72f9cSWei WANG case MMC_TIMING_UHS_DDR50: 116884d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 116984d72f9cSWei WANG break; 117084d72f9cSWei WANG 117184d72f9cSWei WANG default: 117284d72f9cSWei WANG err = 0; 117384d72f9cSWei WANG } 117484d72f9cSWei WANG 117584d72f9cSWei WANG if (err) 117684d72f9cSWei WANG goto out; 117784d72f9cSWei WANG 117884d72f9cSWei WANG /* Tuning RX phase */ 117984d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 118084d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 118184d72f9cSWei WANG err = sd_tuning_rx(host, opcode); 118284d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 118384d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 118484d72f9cSWei WANG 118584d72f9cSWei WANG out: 1186ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1187ff984e57SWei WANG 1188ff984e57SWei WANG return err; 1189ff984e57SWei WANG } 1190ff984e57SWei WANG 1191ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 1192ff984e57SWei WANG .request = sdmmc_request, 1193ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1194ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1195ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1196ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1197ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 1198ff984e57SWei WANG }; 1199ff984e57SWei WANG 1200ff984e57SWei WANG #ifdef CONFIG_PM 1201ff984e57SWei WANG static int rtsx_pci_sdmmc_suspend(struct platform_device *pdev, 1202ff984e57SWei WANG pm_message_t state) 1203ff984e57SWei WANG { 1204ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1205ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1206ff984e57SWei WANG int err; 1207ff984e57SWei WANG 1208ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "--> %s\n", __func__); 1209ff984e57SWei WANG 1210ff984e57SWei WANG err = mmc_suspend_host(mmc); 1211ff984e57SWei WANG if (err) 1212ff984e57SWei WANG return err; 1213ff984e57SWei WANG 1214ff984e57SWei WANG return 0; 1215ff984e57SWei WANG } 1216ff984e57SWei WANG 1217ff984e57SWei WANG static int rtsx_pci_sdmmc_resume(struct platform_device *pdev) 1218ff984e57SWei WANG { 1219ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1220ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1221ff984e57SWei WANG 1222ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "--> %s\n", __func__); 1223ff984e57SWei WANG 1224ff984e57SWei WANG return mmc_resume_host(mmc); 1225ff984e57SWei WANG } 1226ff984e57SWei WANG #else /* CONFIG_PM */ 1227ff984e57SWei WANG #define rtsx_pci_sdmmc_suspend NULL 1228ff984e57SWei WANG #define rtsx_pci_sdmmc_resume NULL 1229ff984e57SWei WANG #endif /* CONFIG_PM */ 1230ff984e57SWei WANG 1231ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1232ff984e57SWei WANG { 1233ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1234ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1235ff984e57SWei WANG 1236ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1237ff984e57SWei WANG 1238ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1239ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1240ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1241ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1242ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1243ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1244ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1245ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1246ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1247ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1248ff984e57SWei WANG } 1249ff984e57SWei WANG 1250ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1251ff984e57SWei WANG { 1252ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1253ff984e57SWei WANG 1254ff984e57SWei WANG mmc->f_min = 250000; 1255ff984e57SWei WANG mmc->f_max = 208000000; 1256ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1257ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1258ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1259ff984e57SWei WANG MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1260ff984e57SWei WANG mmc->max_current_330 = 400; 1261ff984e57SWei WANG mmc->max_current_180 = 800; 1262ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1263ff984e57SWei WANG 1264ff984e57SWei WANG init_extra_caps(host); 1265ff984e57SWei WANG 1266ff984e57SWei WANG mmc->max_segs = 256; 1267ff984e57SWei WANG mmc->max_seg_size = 65536; 1268ff984e57SWei WANG mmc->max_blk_size = 512; 1269ff984e57SWei WANG mmc->max_blk_count = 65535; 1270ff984e57SWei WANG mmc->max_req_size = 524288; 1271ff984e57SWei WANG } 1272ff984e57SWei WANG 1273ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1274ff984e57SWei WANG { 1275ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1276ff984e57SWei WANG 1277ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1278ff984e57SWei WANG } 1279ff984e57SWei WANG 1280ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1281ff984e57SWei WANG { 1282ff984e57SWei WANG struct mmc_host *mmc; 1283ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1284ff984e57SWei WANG struct rtsx_pcr *pcr; 1285ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1286ff984e57SWei WANG 1287ff984e57SWei WANG if (!handle) 1288ff984e57SWei WANG return -ENXIO; 1289ff984e57SWei WANG 1290ff984e57SWei WANG pcr = handle->pcr; 1291ff984e57SWei WANG if (!pcr) 1292ff984e57SWei WANG return -ENXIO; 1293ff984e57SWei WANG 1294ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1295ff984e57SWei WANG 1296ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1297ff984e57SWei WANG if (!mmc) 1298ff984e57SWei WANG return -ENOMEM; 1299ff984e57SWei WANG 1300ff984e57SWei WANG host = mmc_priv(mmc); 1301ff984e57SWei WANG host->pcr = pcr; 1302ff984e57SWei WANG host->mmc = mmc; 1303ff984e57SWei WANG host->pdev = pdev; 1304d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 1305ff984e57SWei WANG platform_set_drvdata(pdev, host); 1306ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1307ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1308ff984e57SWei WANG 1309ff984e57SWei WANG mutex_init(&host->host_mutex); 1310ff984e57SWei WANG 1311ff984e57SWei WANG realtek_init_host(host); 1312ff984e57SWei WANG 1313ff984e57SWei WANG mmc_add_host(mmc); 1314ff984e57SWei WANG 1315ff984e57SWei WANG return 0; 1316ff984e57SWei WANG } 1317ff984e57SWei WANG 1318ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1319ff984e57SWei WANG { 1320ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1321ff984e57SWei WANG struct rtsx_pcr *pcr; 1322ff984e57SWei WANG struct mmc_host *mmc; 1323ff984e57SWei WANG 1324ff984e57SWei WANG if (!host) 1325ff984e57SWei WANG return 0; 1326ff984e57SWei WANG 1327ff984e57SWei WANG pcr = host->pcr; 1328ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1329ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1330ff984e57SWei WANG mmc = host->mmc; 1331ff984e57SWei WANG host->eject = true; 1332ff984e57SWei WANG 1333ff984e57SWei WANG mutex_lock(&host->host_mutex); 1334ff984e57SWei WANG if (host->mrq) { 1335ff984e57SWei WANG dev_dbg(&(pdev->dev), 1336ff984e57SWei WANG "%s: Controller removed during transfer\n", 1337ff984e57SWei WANG mmc_hostname(mmc)); 1338ff984e57SWei WANG 1339ff984e57SWei WANG rtsx_pci_complete_unfinished_transfer(pcr); 1340ff984e57SWei WANG 1341ff984e57SWei WANG host->mrq->cmd->error = -ENOMEDIUM; 1342ff984e57SWei WANG if (host->mrq->stop) 1343ff984e57SWei WANG host->mrq->stop->error = -ENOMEDIUM; 1344ff984e57SWei WANG mmc_request_done(mmc, host->mrq); 1345ff984e57SWei WANG } 1346ff984e57SWei WANG mutex_unlock(&host->host_mutex); 1347ff984e57SWei WANG 1348ff984e57SWei WANG mmc_remove_host(mmc); 1349ff984e57SWei WANG mmc_free_host(mmc); 1350ff984e57SWei WANG 1351ff984e57SWei WANG dev_dbg(&(pdev->dev), 1352ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1353ff984e57SWei WANG 1354ff984e57SWei WANG return 0; 1355ff984e57SWei WANG } 1356ff984e57SWei WANG 1357ff984e57SWei WANG static struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1358ff984e57SWei WANG { 1359ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1360ff984e57SWei WANG }, { 1361ff984e57SWei WANG /* sentinel */ 1362ff984e57SWei WANG } 1363ff984e57SWei WANG }; 1364ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1365ff984e57SWei WANG 1366ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1367ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1368ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1369ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1370ff984e57SWei WANG .suspend = rtsx_pci_sdmmc_suspend, 1371ff984e57SWei WANG .resume = rtsx_pci_sdmmc_resume, 1372ff984e57SWei WANG .driver = { 1373ff984e57SWei WANG .owner = THIS_MODULE, 1374ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1375ff984e57SWei WANG }, 1376ff984e57SWei WANG }; 1377ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1378ff984e57SWei WANG 1379ff984e57SWei WANG MODULE_LICENSE("GPL"); 1380ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1381ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1382