1aaf4989bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 3ff984e57SWei WANG * 462282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5ff984e57SWei WANG * 6ff984e57SWei WANG * Author: 7ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 8ff984e57SWei WANG */ 9ff984e57SWei WANG 10ff984e57SWei WANG #include <linux/module.h> 11433e075cSWei WANG #include <linux/slab.h> 12ff984e57SWei WANG #include <linux/highmem.h> 13ff984e57SWei WANG #include <linux/delay.h> 14ff984e57SWei WANG #include <linux/platform_device.h> 156291e715SMicky Ching #include <linux/workqueue.h> 16ff984e57SWei WANG #include <linux/mmc/host.h> 17ff984e57SWei WANG #include <linux/mmc/mmc.h> 18ff984e57SWei WANG #include <linux/mmc/sd.h> 191dcb3579SMicky Ching #include <linux/mmc/sdio.h> 20ff984e57SWei WANG #include <linux/mmc/card.h> 21e455b69dSRui Feng #include <linux/rtsx_pci.h> 22ff984e57SWei WANG #include <asm/unaligned.h> 23ff984e57SWei WANG 24ff984e57SWei WANG struct realtek_pci_sdmmc { 25ff984e57SWei WANG struct platform_device *pdev; 26ff984e57SWei WANG struct rtsx_pcr *pcr; 27ff984e57SWei WANG struct mmc_host *mmc; 28ff984e57SWei WANG struct mmc_request *mrq; 296291e715SMicky Ching #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" 30ff984e57SWei WANG 316291e715SMicky Ching struct work_struct work; 3298fcc576SMicky Ching struct mutex host_mutex; 33ff984e57SWei WANG 34ff984e57SWei WANG u8 ssc_depth; 35ff984e57SWei WANG unsigned int clock; 36ff984e57SWei WANG bool vpclk; 37ff984e57SWei WANG bool double_clk; 38ff984e57SWei WANG bool eject; 39ff984e57SWei WANG bool initial_mode; 40d88691beSWei WANG int power_state; 41d88691beSWei WANG #define SDMMC_POWER_ON 1 42d88691beSWei WANG #define SDMMC_POWER_OFF 0 436291e715SMicky Ching 44be186ad5SMicky Ching int sg_count; 456291e715SMicky Ching s32 cookie; 46be186ad5SMicky Ching int cookie_sg_count; 476291e715SMicky Ching bool using_cookie; 48ff984e57SWei WANG }; 49ff984e57SWei WANG 50*6b7b58f4SRui Feng static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios); 51*6b7b58f4SRui Feng 52ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 53ff984e57SWei WANG { 54ff984e57SWei WANG return &(host->pdev->dev); 55ff984e57SWei WANG } 56ff984e57SWei WANG 57ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 58ff984e57SWei WANG { 59ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 60ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 61ff984e57SWei WANG } 62ff984e57SWei WANG 63ff984e57SWei WANG #ifdef DEBUG 64755987f9SMicky Ching static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end) 65755987f9SMicky Ching { 66755987f9SMicky Ching u16 len = end - start + 1; 67755987f9SMicky Ching int i; 68755987f9SMicky Ching u8 data[8]; 69755987f9SMicky Ching 70755987f9SMicky Ching for (i = 0; i < len; i += 8) { 71755987f9SMicky Ching int j; 72755987f9SMicky Ching int n = min(8, len - i); 73755987f9SMicky Ching 74755987f9SMicky Ching memset(&data, 0, sizeof(data)); 75755987f9SMicky Ching for (j = 0; j < n; j++) 76755987f9SMicky Ching rtsx_pci_read_register(host->pcr, start + i + j, 77755987f9SMicky Ching data + j); 78755987f9SMicky Ching dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n", 79755987f9SMicky Ching start + i, n, data); 80755987f9SMicky Ching } 81755987f9SMicky Ching } 82755987f9SMicky Ching 83ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 84ff984e57SWei WANG { 85755987f9SMicky Ching dump_reg_range(host, 0xFDA0, 0xFDB3); 86755987f9SMicky Ching dump_reg_range(host, 0xFD52, 0xFD69); 87ff984e57SWei WANG } 88ff984e57SWei WANG #else 89ff984e57SWei WANG #define sd_print_debug_regs(host) 90ff984e57SWei WANG #endif /* DEBUG */ 91ff984e57SWei WANG 92b22217f9SMicky Ching static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host) 93b22217f9SMicky Ching { 94b22217f9SMicky Ching return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST; 95b22217f9SMicky Ching } 96b22217f9SMicky Ching 972d48e5f1SMicky Ching static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd) 982d48e5f1SMicky Ching { 992d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 1002d48e5f1SMicky Ching SD_CMD_START | cmd->opcode); 1012d48e5f1SMicky Ching rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg); 1022d48e5f1SMicky Ching } 1032d48e5f1SMicky Ching 1042d48e5f1SMicky Ching static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz) 1052d48e5f1SMicky Ching { 1062d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); 1072d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); 1082d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); 1092d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); 1102d48e5f1SMicky Ching } 1112d48e5f1SMicky Ching 1122d48e5f1SMicky Ching static int sd_response_type(struct mmc_command *cmd) 1132d48e5f1SMicky Ching { 1142d48e5f1SMicky Ching switch (mmc_resp_type(cmd)) { 1152d48e5f1SMicky Ching case MMC_RSP_NONE: 1162d48e5f1SMicky Ching return SD_RSP_TYPE_R0; 1172d48e5f1SMicky Ching case MMC_RSP_R1: 1182d48e5f1SMicky Ching return SD_RSP_TYPE_R1; 1198c8d0ecbSWolfram Sang case MMC_RSP_R1_NO_CRC: 1202d48e5f1SMicky Ching return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; 1212d48e5f1SMicky Ching case MMC_RSP_R1B: 1222d48e5f1SMicky Ching return SD_RSP_TYPE_R1b; 1232d48e5f1SMicky Ching case MMC_RSP_R2: 1242d48e5f1SMicky Ching return SD_RSP_TYPE_R2; 1252d48e5f1SMicky Ching case MMC_RSP_R3: 1262d48e5f1SMicky Ching return SD_RSP_TYPE_R3; 1272d48e5f1SMicky Ching default: 1282d48e5f1SMicky Ching return -EINVAL; 1292d48e5f1SMicky Ching } 1302d48e5f1SMicky Ching } 1312d48e5f1SMicky Ching 1322d48e5f1SMicky Ching static int sd_status_index(int resp_type) 1332d48e5f1SMicky Ching { 1342d48e5f1SMicky Ching if (resp_type == SD_RSP_TYPE_R0) 1352d48e5f1SMicky Ching return 0; 1362d48e5f1SMicky Ching else if (resp_type == SD_RSP_TYPE_R2) 1372d48e5f1SMicky Ching return 16; 1382d48e5f1SMicky Ching 1392d48e5f1SMicky Ching return 5; 1402d48e5f1SMicky Ching } 1416291e715SMicky Ching /* 1426291e715SMicky Ching * sd_pre_dma_transfer - do dma_map_sg() or using cookie 1436291e715SMicky Ching * 1446291e715SMicky Ching * @pre: if called in pre_req() 1456291e715SMicky Ching * return: 1466291e715SMicky Ching * 0 - do dma_map_sg() 1476291e715SMicky Ching * 1 - using cookie 1486291e715SMicky Ching */ 1496291e715SMicky Ching static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, 1506291e715SMicky Ching struct mmc_data *data, bool pre) 1516291e715SMicky Ching { 1526291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 1536291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 1546291e715SMicky Ching int count = 0; 1556291e715SMicky Ching int using_cookie = 0; 1566291e715SMicky Ching 1576291e715SMicky Ching if (!pre && data->host_cookie && data->host_cookie != host->cookie) { 1586291e715SMicky Ching dev_err(sdmmc_dev(host), 1596291e715SMicky Ching "error: data->host_cookie = %d, host->cookie = %d\n", 1606291e715SMicky Ching data->host_cookie, host->cookie); 1616291e715SMicky Ching data->host_cookie = 0; 1626291e715SMicky Ching } 1636291e715SMicky Ching 1646291e715SMicky Ching if (pre || data->host_cookie != host->cookie) { 1656291e715SMicky Ching count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); 1666291e715SMicky Ching } else { 1676291e715SMicky Ching count = host->cookie_sg_count; 1686291e715SMicky Ching using_cookie = 1; 1696291e715SMicky Ching } 1706291e715SMicky Ching 1716291e715SMicky Ching if (pre) { 1726291e715SMicky Ching host->cookie_sg_count = count; 1736291e715SMicky Ching if (++host->cookie < 0) 1746291e715SMicky Ching host->cookie = 1; 1756291e715SMicky Ching data->host_cookie = host->cookie; 1766291e715SMicky Ching } else { 1776291e715SMicky Ching host->sg_count = count; 1786291e715SMicky Ching } 1796291e715SMicky Ching 1806291e715SMicky Ching return using_cookie; 1816291e715SMicky Ching } 1826291e715SMicky Ching 183d3c6aac3SLinus Walleij static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1846291e715SMicky Ching { 1856291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1866291e715SMicky Ching struct mmc_data *data = mrq->data; 1876291e715SMicky Ching 1886291e715SMicky Ching if (data->host_cookie) { 1896291e715SMicky Ching dev_err(sdmmc_dev(host), 1906291e715SMicky Ching "error: reset data->host_cookie = %d\n", 1916291e715SMicky Ching data->host_cookie); 1926291e715SMicky Ching data->host_cookie = 0; 1936291e715SMicky Ching } 1946291e715SMicky Ching 1956291e715SMicky Ching sd_pre_dma_transfer(host, data, true); 1966291e715SMicky Ching dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); 1976291e715SMicky Ching } 1986291e715SMicky Ching 1996291e715SMicky Ching static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2006291e715SMicky Ching int err) 2016291e715SMicky Ching { 2026291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 2036291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 2046291e715SMicky Ching struct mmc_data *data = mrq->data; 2056291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 2066291e715SMicky Ching 2076291e715SMicky Ching rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); 2086291e715SMicky Ching data->host_cookie = 0; 2096291e715SMicky Ching } 2106291e715SMicky Ching 21198fcc576SMicky Ching static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 21298fcc576SMicky Ching struct mmc_command *cmd) 213ff984e57SWei WANG { 214ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 215ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 216ff984e57SWei WANG u32 arg = cmd->arg; 217ff984e57SWei WANG int err = 0; 218ff984e57SWei WANG int timeout = 100; 219ff984e57SWei WANG int i; 22098fcc576SMicky Ching u8 *ptr; 2212d48e5f1SMicky Ching int rsp_type; 2222d48e5f1SMicky Ching int stat_idx; 22398fcc576SMicky Ching bool clock_toggled = false; 224ff984e57SWei WANG 225ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 226ff984e57SWei WANG __func__, cmd_idx, arg); 227ff984e57SWei WANG 2282d48e5f1SMicky Ching rsp_type = sd_response_type(cmd); 2292d48e5f1SMicky Ching if (rsp_type < 0) 230ff984e57SWei WANG goto out; 2312d48e5f1SMicky Ching 2322d48e5f1SMicky Ching stat_idx = sd_status_index(rsp_type); 233ff984e57SWei WANG 234ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 23527f4bf7dSUlf Hansson timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000; 236ff984e57SWei WANG 237ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 238ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 239ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 240ff984e57SWei WANG if (err < 0) 241ff984e57SWei WANG goto out; 24298fcc576SMicky Ching 24398fcc576SMicky Ching clock_toggled = true; 244ff984e57SWei WANG } 245ff984e57SWei WANG 246ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 2472d48e5f1SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 248ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 249ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 250ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 251ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 252ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 253ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 254ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 255ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 256ff984e57SWei WANG 257ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 258ff984e57SWei WANG /* Read data from ping-pong buffer */ 259ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 260ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 261ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 262ff984e57SWei WANG /* Read data from SD_CMDx registers */ 263ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 264ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 265ff984e57SWei WANG } 266ff984e57SWei WANG 267ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 268ff984e57SWei WANG 26998fcc576SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 27098fcc576SMicky Ching if (err < 0) { 27198fcc576SMicky Ching sd_print_debug_regs(host); 27298fcc576SMicky Ching sd_clear_error(host); 27398fcc576SMicky Ching dev_dbg(sdmmc_dev(host), 27498fcc576SMicky Ching "rtsx_pci_send_cmd error (err = %d)\n", err); 275ff984e57SWei WANG goto out; 276ff984e57SWei WANG } 277ff984e57SWei WANG 278ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 279ff984e57SWei WANG err = 0; 280ff984e57SWei WANG goto out; 281ff984e57SWei WANG } 282ff984e57SWei WANG 283ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 284ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 285ff984e57SWei WANG 286ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 287ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 288ff984e57SWei WANG err = -EILSEQ; 289ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 290ff984e57SWei WANG goto out; 291ff984e57SWei WANG } 292ff984e57SWei WANG 293ff984e57SWei WANG /* Check CRC7 */ 294ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 295ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 296ff984e57SWei WANG err = -EILSEQ; 297ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 298ff984e57SWei WANG goto out; 299ff984e57SWei WANG } 300ff984e57SWei WANG } 301ff984e57SWei WANG 302ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 303d1419d50SRoger Tseng /* 304d1419d50SRoger Tseng * The controller offloads the last byte {CRC-7, end bit 1'b1} 305d1419d50SRoger Tseng * of response type R2. Assign dummy CRC, 0, and end bit to the 306d1419d50SRoger Tseng * byte(ptr[16], goes into the LSB of resp[3] later). 307d1419d50SRoger Tseng */ 308d1419d50SRoger Tseng ptr[16] = 1; 309d1419d50SRoger Tseng 310ff984e57SWei WANG for (i = 0; i < 4; i++) { 311ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 312ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 313ff984e57SWei WANG i, cmd->resp[i]); 314ff984e57SWei WANG } 315ff984e57SWei WANG } else { 316ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 317ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 318ff984e57SWei WANG cmd->resp[0]); 319ff984e57SWei WANG } 320ff984e57SWei WANG 321ff984e57SWei WANG out: 322ff984e57SWei WANG cmd->error = err; 3231b8055b4SWei WANG 32498fcc576SMicky Ching if (err && clock_toggled) 32598fcc576SMicky Ching rtsx_pci_write_register(pcr, SD_BUS_STAT, 32698fcc576SMicky Ching SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 327ff984e57SWei WANG } 328ff984e57SWei WANG 32956d1c0d9SMicky Ching static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd, 33056d1c0d9SMicky Ching u16 byte_cnt, u8 *buf, int buf_len, int timeout) 33156d1c0d9SMicky Ching { 33256d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr; 33356d1c0d9SMicky Ching int err; 33456d1c0d9SMicky Ching u8 trans_mode; 33556d1c0d9SMicky Ching 33656d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 33756d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg); 33856d1c0d9SMicky Ching 33956d1c0d9SMicky Ching if (!buf) 34056d1c0d9SMicky Ching buf_len = 0; 34156d1c0d9SMicky Ching 34256d1c0d9SMicky Ching if (cmd->opcode == MMC_SEND_TUNING_BLOCK) 34356d1c0d9SMicky Ching trans_mode = SD_TM_AUTO_TUNING; 34456d1c0d9SMicky Ching else 34556d1c0d9SMicky Ching trans_mode = SD_TM_NORMAL_READ; 34656d1c0d9SMicky Ching 34756d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr); 34856d1c0d9SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 34956d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt); 35056d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 35156d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 35256d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 35356d1c0d9SMicky Ching if (trans_mode != SD_TM_AUTO_TUNING) 35456d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 35556d1c0d9SMicky Ching CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 35656d1c0d9SMicky Ching 35756d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 35856d1c0d9SMicky Ching 0xFF, trans_mode | SD_TRANSFER_START); 35956d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 36056d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 36156d1c0d9SMicky Ching 36256d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 36356d1c0d9SMicky Ching if (err < 0) { 36456d1c0d9SMicky Ching sd_print_debug_regs(host); 36556d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 36656d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err); 36756d1c0d9SMicky Ching return err; 36856d1c0d9SMicky Ching } 36956d1c0d9SMicky Ching 37056d1c0d9SMicky Ching if (buf && buf_len) { 37156d1c0d9SMicky Ching err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 37256d1c0d9SMicky Ching if (err < 0) { 37356d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 37456d1c0d9SMicky Ching "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 37556d1c0d9SMicky Ching return err; 37656d1c0d9SMicky Ching } 37756d1c0d9SMicky Ching } 37856d1c0d9SMicky Ching 37956d1c0d9SMicky Ching return 0; 38056d1c0d9SMicky Ching } 38156d1c0d9SMicky Ching 38256d1c0d9SMicky Ching static int sd_write_data(struct realtek_pci_sdmmc *host, 38356d1c0d9SMicky Ching struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len, 38456d1c0d9SMicky Ching int timeout) 38556d1c0d9SMicky Ching { 38656d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr; 38756d1c0d9SMicky Ching int err; 38856d1c0d9SMicky Ching 38956d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 39056d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg); 39156d1c0d9SMicky Ching 39256d1c0d9SMicky Ching if (!buf) 39356d1c0d9SMicky Ching buf_len = 0; 39456d1c0d9SMicky Ching 39556d1c0d9SMicky Ching sd_send_cmd_get_rsp(host, cmd); 39656d1c0d9SMicky Ching if (cmd->error) 39756d1c0d9SMicky Ching return cmd->error; 39856d1c0d9SMicky Ching 39956d1c0d9SMicky Ching if (buf && buf_len) { 40056d1c0d9SMicky Ching err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 40156d1c0d9SMicky Ching if (err < 0) { 40256d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 40356d1c0d9SMicky Ching "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 40456d1c0d9SMicky Ching return err; 40556d1c0d9SMicky Ching } 40656d1c0d9SMicky Ching } 40756d1c0d9SMicky Ching 40856d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr); 40956d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt); 41056d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 41156d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 41256d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0); 41356d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 41456d1c0d9SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 41556d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 41656d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 41756d1c0d9SMicky Ching 41856d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 41956d1c0d9SMicky Ching if (err < 0) { 42056d1c0d9SMicky Ching sd_print_debug_regs(host); 42156d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 42256d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err); 42356d1c0d9SMicky Ching return err; 42456d1c0d9SMicky Ching } 42556d1c0d9SMicky Ching 42656d1c0d9SMicky Ching return 0; 42756d1c0d9SMicky Ching } 42856d1c0d9SMicky Ching 4291dcb3579SMicky Ching static int sd_read_long_data(struct realtek_pci_sdmmc *host, 4301dcb3579SMicky Ching struct mmc_request *mrq) 431ff984e57SWei WANG { 432ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 433ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 434ff984e57SWei WANG struct mmc_card *card = mmc->card; 4351dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd; 436ff984e57SWei WANG struct mmc_data *data = mrq->data; 43771ef1ea4SJackey Shen int uhs = mmc_card_uhs(card); 4381dcb3579SMicky Ching u8 cfg2 = 0; 439ff984e57SWei WANG int err; 4401dcb3579SMicky Ching int resp_type; 441ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 442ff984e57SWei WANG 4431dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 4441dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg); 4451dcb3579SMicky Ching 4461dcb3579SMicky Ching resp_type = sd_response_type(cmd); 4471dcb3579SMicky Ching if (resp_type < 0) 4481dcb3579SMicky Ching return resp_type; 449ff984e57SWei WANG 450ff984e57SWei WANG if (!uhs) 451ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 452ff984e57SWei WANG 453ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 4541dcb3579SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 4551dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 456ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 457ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 458ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 459ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 460ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 461ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 462ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 463ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 464ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 465ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 466ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 467ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 4681dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 4691dcb3579SMicky Ching 0x01, RING_BUFFER); 4701dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); 4711dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 4721dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_READ_2); 4731dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 4741dcb3579SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 4751dcb3579SMicky Ching rtsx_pci_send_cmd_no_wait(pcr); 4761dcb3579SMicky Ching 4771dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000); 4781dcb3579SMicky Ching if (err < 0) { 4791dcb3579SMicky Ching sd_print_debug_regs(host); 4801dcb3579SMicky Ching sd_clear_error(host); 4811dcb3579SMicky Ching return err; 4821dcb3579SMicky Ching } 4831dcb3579SMicky Ching 4841dcb3579SMicky Ching return 0; 4851dcb3579SMicky Ching } 4861dcb3579SMicky Ching 4871dcb3579SMicky Ching static int sd_write_long_data(struct realtek_pci_sdmmc *host, 4881dcb3579SMicky Ching struct mmc_request *mrq) 4891dcb3579SMicky Ching { 4901dcb3579SMicky Ching struct rtsx_pcr *pcr = host->pcr; 4911dcb3579SMicky Ching struct mmc_host *mmc = host->mmc; 4921dcb3579SMicky Ching struct mmc_card *card = mmc->card; 4931dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd; 4941dcb3579SMicky Ching struct mmc_data *data = mrq->data; 4951dcb3579SMicky Ching int uhs = mmc_card_uhs(card); 4961dcb3579SMicky Ching u8 cfg2; 4971dcb3579SMicky Ching int err; 4981dcb3579SMicky Ching size_t data_len = data->blksz * data->blocks; 4991dcb3579SMicky Ching 5001dcb3579SMicky Ching sd_send_cmd_get_rsp(host, cmd); 5011dcb3579SMicky Ching if (cmd->error) 5021dcb3579SMicky Ching return cmd->error; 5031dcb3579SMicky Ching 5041dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 5051dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg); 5061dcb3579SMicky Ching 5071dcb3579SMicky Ching cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 5081dcb3579SMicky Ching SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 5091dcb3579SMicky Ching 5101dcb3579SMicky Ching if (!uhs) 5111dcb3579SMicky Ching cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 5121dcb3579SMicky Ching 5131dcb3579SMicky Ching rtsx_pci_init_cmd(pcr); 5141dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 5151dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 5161dcb3579SMicky Ching DMA_DONE_INT, DMA_DONE_INT); 5171dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 5181dcb3579SMicky Ching 0xFF, (u8)(data_len >> 24)); 5191dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 5201dcb3579SMicky Ching 0xFF, (u8)(data_len >> 16)); 5211dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 5221dcb3579SMicky Ching 0xFF, (u8)(data_len >> 8)); 5231dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 524ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 525ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 526ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 527ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 528ff984e57SWei WANG 0x01, RING_BUFFER); 52938d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 530ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 5311dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 532ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 533ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 534ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 5351dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000); 536ff984e57SWei WANG if (err < 0) { 53798fcc576SMicky Ching sd_clear_error(host); 53898fcc576SMicky Ching return err; 539c42deffdSMicky Ching } 54098fcc576SMicky Ching 541c42deffdSMicky Ching return 0; 542ff984e57SWei WANG } 543ff984e57SWei WANG 5441dcb3579SMicky Ching static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 5451dcb3579SMicky Ching { 5461dcb3579SMicky Ching struct mmc_data *data = mrq->data; 5471dcb3579SMicky Ching 548be186ad5SMicky Ching if (host->sg_count < 0) { 549be186ad5SMicky Ching data->error = host->sg_count; 550be186ad5SMicky Ching dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n", 551be186ad5SMicky Ching __func__, host->sg_count); 552be186ad5SMicky Ching return data->error; 553be186ad5SMicky Ching } 554be186ad5SMicky Ching 5551dcb3579SMicky Ching if (data->flags & MMC_DATA_READ) 5561dcb3579SMicky Ching return sd_read_long_data(host, mrq); 5571dcb3579SMicky Ching 5581dcb3579SMicky Ching return sd_write_long_data(host, mrq); 5591dcb3579SMicky Ching } 5601dcb3579SMicky Ching 561ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 562ff984e57SWei WANG { 563ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 564ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 565ff984e57SWei WANG } 566ff984e57SWei WANG 567ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 568ff984e57SWei WANG { 569ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 570ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 571ff984e57SWei WANG } 572ff984e57SWei WANG 573ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 574ff984e57SWei WANG struct mmc_request *mrq) 575ff984e57SWei WANG { 576ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 577ff984e57SWei WANG struct mmc_data *data = mrq->data; 5781dcb3579SMicky Ching u8 *buf; 579ff984e57SWei WANG 580ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 581ff984e57SWei WANG if (!buf) { 582ff984e57SWei WANG cmd->error = -ENOMEM; 583ff984e57SWei WANG return; 584ff984e57SWei WANG } 585ff984e57SWei WANG 586ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 587ff984e57SWei WANG if (host->initial_mode) 588ff984e57SWei WANG sd_disable_initial_mode(host); 589ff984e57SWei WANG 5901dcb3579SMicky Ching cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf, 591ff984e57SWei WANG data->blksz, 200); 592ff984e57SWei WANG 593ff984e57SWei WANG if (host->initial_mode) 594ff984e57SWei WANG sd_enable_initial_mode(host); 595ff984e57SWei WANG 596ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 597ff984e57SWei WANG } else { 598ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 599ff984e57SWei WANG 6001dcb3579SMicky Ching cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf, 601ff984e57SWei WANG data->blksz, 200); 602ff984e57SWei WANG } 603ff984e57SWei WANG 604ff984e57SWei WANG kfree(buf); 605ff984e57SWei WANG } 606ff984e57SWei WANG 60784d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, 60884d72f9cSWei WANG u8 sample_point, bool rx) 609ff984e57SWei WANG { 610ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 6114686392cSRicky Wu u16 SD_VP_CTL = 0; 61284d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 61384d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point); 614ff984e57SWei WANG 615563be8b6Srui_feng rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 6164686392cSRicky Wu if (rx) { 6174686392cSRicky Wu SD_VP_CTL = SD_VPRX_CTL; 618563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_VPRX_CTL, 619563be8b6Srui_feng PHASE_SELECT_MASK, sample_point); 6204686392cSRicky Wu } else { 6214686392cSRicky Wu SD_VP_CTL = SD_VPTX_CTL; 622563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_VPTX_CTL, 623563be8b6Srui_feng PHASE_SELECT_MASK, sample_point); 6244686392cSRicky Wu } 6254686392cSRicky Wu rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0); 6264686392cSRicky Wu rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 627563be8b6Srui_feng PHASE_NOT_RESET); 628563be8b6Srui_feng rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0); 629563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 630ff984e57SWei WANG 631ff984e57SWei WANG return 0; 632ff984e57SWei WANG } 633ff984e57SWei WANG 634abcc6b29SMicky Ching static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 635abcc6b29SMicky Ching { 636abcc6b29SMicky Ching bit %= RTSX_PHASE_MAX; 637abcc6b29SMicky Ching return phase_map & (1 << bit); 638abcc6b29SMicky Ching } 639abcc6b29SMicky Ching 640abcc6b29SMicky Ching static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 641abcc6b29SMicky Ching { 642abcc6b29SMicky Ching int i; 643abcc6b29SMicky Ching 644abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 645abcc6b29SMicky Ching if (test_phase_bit(phase_map, start_bit + i) == 0) 646abcc6b29SMicky Ching return i; 647abcc6b29SMicky Ching } 648abcc6b29SMicky Ching return RTSX_PHASE_MAX; 649abcc6b29SMicky Ching } 650abcc6b29SMicky Ching 651ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 652ff984e57SWei WANG { 653abcc6b29SMicky Ching int start = 0, len = 0; 654abcc6b29SMicky Ching int start_final = 0, len_final = 0; 655ff984e57SWei WANG u8 final_phase = 0xFF; 656ff984e57SWei WANG 657abcc6b29SMicky Ching if (phase_map == 0) { 658abcc6b29SMicky Ching dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 659abcc6b29SMicky Ching return final_phase; 660ff984e57SWei WANG } 661ff984e57SWei WANG 662abcc6b29SMicky Ching while (start < RTSX_PHASE_MAX) { 663abcc6b29SMicky Ching len = sd_get_phase_len(phase_map, start); 664abcc6b29SMicky Ching if (len_final < len) { 665abcc6b29SMicky Ching start_final = start; 666abcc6b29SMicky Ching len_final = len; 667abcc6b29SMicky Ching } 668abcc6b29SMicky Ching start += len ? len : 1; 669ff984e57SWei WANG } 670ff984e57SWei WANG 671abcc6b29SMicky Ching final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 672abcc6b29SMicky Ching dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 673abcc6b29SMicky Ching phase_map, len_final, final_phase); 674ff984e57SWei WANG 675ff984e57SWei WANG return final_phase; 676ff984e57SWei WANG } 677ff984e57SWei WANG 678ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 679ff984e57SWei WANG { 680679209b3SLee Jones int i; 681ff984e57SWei WANG u8 val = 0; 682ff984e57SWei WANG 683ff984e57SWei WANG for (i = 0; i < 100; i++) { 684679209b3SLee Jones rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 685ff984e57SWei WANG if (val & SD_DATA_IDLE) 686ff984e57SWei WANG return; 687ff984e57SWei WANG 688ff984e57SWei WANG udelay(100); 689ff984e57SWei WANG } 690ff984e57SWei WANG } 691ff984e57SWei WANG 692ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 693ff984e57SWei WANG u8 opcode, u8 sample_point) 694ff984e57SWei WANG { 695ff984e57SWei WANG int err; 696c7836d15SMasahiro Yamada struct mmc_command cmd = {}; 697563be8b6Srui_feng struct rtsx_pcr *pcr = host->pcr; 698ff984e57SWei WANG 699563be8b6Srui_feng sd_change_phase(host, sample_point, true); 700563be8b6Srui_feng 701563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 702563be8b6Srui_feng SD_RSP_80CLK_TIMEOUT_EN); 703ff984e57SWei WANG 7041dcb3579SMicky Ching cmd.opcode = opcode; 7051dcb3579SMicky Ching err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100); 706ff984e57SWei WANG if (err < 0) { 707ff984e57SWei WANG /* Wait till SD DATA IDLE */ 708ff984e57SWei WANG sd_wait_data_idle(host); 709ff984e57SWei WANG sd_clear_error(host); 710563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3, 711563be8b6Srui_feng SD_RSP_80CLK_TIMEOUT_EN, 0); 712ff984e57SWei WANG return err; 713ff984e57SWei WANG } 714ff984e57SWei WANG 715563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); 716ff984e57SWei WANG return 0; 717ff984e57SWei WANG } 718ff984e57SWei WANG 719ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 720ff984e57SWei WANG u8 opcode, u32 *phase_map) 721ff984e57SWei WANG { 722ff984e57SWei WANG int err, i; 723ff984e57SWei WANG u32 raw_phase_map = 0; 724ff984e57SWei WANG 725abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 726ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 727ff984e57SWei WANG if (err == 0) 728ff984e57SWei WANG raw_phase_map |= 1 << i; 729ff984e57SWei WANG } 730ff984e57SWei WANG 731ff984e57SWei WANG if (phase_map) 732ff984e57SWei WANG *phase_map = raw_phase_map; 733ff984e57SWei WANG 734ff984e57SWei WANG return 0; 735ff984e57SWei WANG } 736ff984e57SWei WANG 737ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 738ff984e57SWei WANG { 739ff984e57SWei WANG int err, i; 740ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 741ff984e57SWei WANG u8 final_phase; 742ff984e57SWei WANG 743ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 744ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 745ff984e57SWei WANG if (err < 0) 746ff984e57SWei WANG return err; 747ff984e57SWei WANG 748ff984e57SWei WANG if (raw_phase_map[i] == 0) 749ff984e57SWei WANG break; 750ff984e57SWei WANG } 751ff984e57SWei WANG 752ff984e57SWei WANG phase_map = 0xFFFFFFFF; 753ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 754ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 755ff984e57SWei WANG i, raw_phase_map[i]); 756ff984e57SWei WANG phase_map &= raw_phase_map[i]; 757ff984e57SWei WANG } 758ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 759ff984e57SWei WANG 760ff984e57SWei WANG if (phase_map) { 761ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 762ff984e57SWei WANG if (final_phase == 0xFF) 763ff984e57SWei WANG return -EINVAL; 764ff984e57SWei WANG 76584d72f9cSWei WANG err = sd_change_phase(host, final_phase, true); 766ff984e57SWei WANG if (err < 0) 767ff984e57SWei WANG return err; 768ff984e57SWei WANG } else { 769ff984e57SWei WANG return -EINVAL; 770ff984e57SWei WANG } 771ff984e57SWei WANG 772ff984e57SWei WANG return 0; 773ff984e57SWei WANG } 774ff984e57SWei WANG 7751dcb3579SMicky Ching static inline int sdio_extblock_cmd(struct mmc_command *cmd, 7761dcb3579SMicky Ching struct mmc_data *data) 7771dcb3579SMicky Ching { 7781dcb3579SMicky Ching return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512); 7791dcb3579SMicky Ching } 7801dcb3579SMicky Ching 7816291e715SMicky Ching static inline int sd_rw_cmd(struct mmc_command *cmd) 782ff984e57SWei WANG { 7836291e715SMicky Ching return mmc_op_multi(cmd->opcode) || 7846291e715SMicky Ching (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 7856291e715SMicky Ching (cmd->opcode == MMC_WRITE_BLOCK); 7866291e715SMicky Ching } 7876291e715SMicky Ching 7886291e715SMicky Ching static void sd_request(struct work_struct *work) 7896291e715SMicky Ching { 7906291e715SMicky Ching struct realtek_pci_sdmmc *host = container_of(work, 7916291e715SMicky Ching struct realtek_pci_sdmmc, work); 792ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 7936291e715SMicky Ching 7946291e715SMicky Ching struct mmc_host *mmc = host->mmc; 7956291e715SMicky Ching struct mmc_request *mrq = host->mrq; 796ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 797ff984e57SWei WANG struct mmc_data *data = mrq->data; 7986291e715SMicky Ching 799ff984e57SWei WANG unsigned int data_size = 0; 800c3481955SWei WANG int err; 801ff984e57SWei WANG 802b22217f9SMicky Ching if (host->eject || !sd_get_cd_int(host)) { 803ff984e57SWei WANG cmd->error = -ENOMEDIUM; 804ff984e57SWei WANG goto finish; 805ff984e57SWei WANG } 806ff984e57SWei WANG 807c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 808c3481955SWei WANG if (err) { 809c3481955SWei WANG cmd->error = err; 810c3481955SWei WANG goto finish; 811c3481955SWei WANG } 812c3481955SWei WANG 81398fcc576SMicky Ching mutex_lock(&pcr->pcr_mutex); 81498fcc576SMicky Ching 815ff984e57SWei WANG rtsx_pci_start_run(pcr); 816ff984e57SWei WANG 817ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 818ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 819ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 820ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 821ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 822ff984e57SWei WANG 82398fcc576SMicky Ching mutex_lock(&host->host_mutex); 82498fcc576SMicky Ching host->mrq = mrq; 82598fcc576SMicky Ching mutex_unlock(&host->host_mutex); 82698fcc576SMicky Ching 827ff984e57SWei WANG if (mrq->data) 828ff984e57SWei WANG data_size = data->blocks * data->blksz; 829ff984e57SWei WANG 8301dcb3579SMicky Ching if (!data_size) { 83198fcc576SMicky Ching sd_send_cmd_get_rsp(host, cmd); 8321dcb3579SMicky Ching } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) { 8331dcb3579SMicky Ching cmd->error = sd_rw_multi(host, mrq); 8346291e715SMicky Ching if (!host->using_cookie) 8356291e715SMicky Ching sdmmc_post_req(host->mmc, host->mrq, 0); 83698fcc576SMicky Ching 83798fcc576SMicky Ching if (mmc_op_multi(cmd->opcode) && mrq->stop) 83898fcc576SMicky Ching sd_send_cmd_get_rsp(host, mrq->stop); 83998fcc576SMicky Ching } else { 84098fcc576SMicky Ching sd_normal_rw(host, mrq); 84198fcc576SMicky Ching } 84298fcc576SMicky Ching 84398fcc576SMicky Ching if (mrq->data) { 84498fcc576SMicky Ching if (cmd->error || data->error) 84598fcc576SMicky Ching data->bytes_xfered = 0; 84698fcc576SMicky Ching else 84798fcc576SMicky Ching data->bytes_xfered = data->blocks * data->blksz; 84898fcc576SMicky Ching } 84998fcc576SMicky Ching 85098fcc576SMicky Ching mutex_unlock(&pcr->pcr_mutex); 851ff984e57SWei WANG 852ff984e57SWei WANG finish: 8531dcb3579SMicky Ching if (cmd->error) { 8541dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n", 8551dcb3579SMicky Ching cmd->opcode, cmd->arg, cmd->error); 8561dcb3579SMicky Ching } 85798fcc576SMicky Ching 85898fcc576SMicky Ching mutex_lock(&host->host_mutex); 85998fcc576SMicky Ching host->mrq = NULL; 86098fcc576SMicky Ching mutex_unlock(&host->host_mutex); 86198fcc576SMicky Ching 86298fcc576SMicky Ching mmc_request_done(mmc, mrq); 863ff984e57SWei WANG } 864ff984e57SWei WANG 8656291e715SMicky Ching static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 8666291e715SMicky Ching { 8676291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 8686291e715SMicky Ching struct mmc_data *data = mrq->data; 8696291e715SMicky Ching 8706291e715SMicky Ching mutex_lock(&host->host_mutex); 8716291e715SMicky Ching host->mrq = mrq; 8726291e715SMicky Ching mutex_unlock(&host->host_mutex); 8736291e715SMicky Ching 8741dcb3579SMicky Ching if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data)) 8756291e715SMicky Ching host->using_cookie = sd_pre_dma_transfer(host, data, false); 8766291e715SMicky Ching 8776ea62579SBhaktipriya Shridhar schedule_work(&host->work); 8786291e715SMicky Ching } 8796291e715SMicky Ching 880ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 881ff984e57SWei WANG unsigned char bus_width) 882ff984e57SWei WANG { 883ff984e57SWei WANG int err = 0; 884ff984e57SWei WANG u8 width[] = { 885ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 886ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 887ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 888ff984e57SWei WANG }; 889ff984e57SWei WANG 890ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 891ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 892ff984e57SWei WANG 0x03, width[bus_width]); 893ff984e57SWei WANG 894ff984e57SWei WANG return err; 895ff984e57SWei WANG } 896ff984e57SWei WANG 897ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 898ff984e57SWei WANG { 899ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 9009ff43c7bSRui Feng struct mmc_host *mmc = host->mmc; 901ff984e57SWei WANG int err; 9029ff43c7bSRui Feng u32 val; 903*6b7b58f4SRui Feng u8 test_mode; 904ff984e57SWei WANG 905d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 906d88691beSWei WANG return 0; 907d88691beSWei WANG 908ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 909ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 910ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 911ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 912ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 913ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 914ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 915ff984e57SWei WANG if (err < 0) 916ff984e57SWei WANG return err; 917ff984e57SWei WANG 918ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 919ff984e57SWei WANG if (err < 0) 920ff984e57SWei WANG return err; 921ff984e57SWei WANG 922ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 923ff984e57SWei WANG if (err < 0) 924ff984e57SWei WANG return err; 925ff984e57SWei WANG 926ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 927ff984e57SWei WANG if (err < 0) 928ff984e57SWei WANG return err; 929ff984e57SWei WANG 9309ff43c7bSRui Feng if (PCI_PID(pcr) == PID_5261) { 931*6b7b58f4SRui Feng /* 932*6b7b58f4SRui Feng * If test mode is set switch to SD Express mandatorily, 933*6b7b58f4SRui Feng * this is only for factory testing. 934*6b7b58f4SRui Feng */ 935*6b7b58f4SRui Feng rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode); 936*6b7b58f4SRui Feng if (test_mode & RTS5261_FW_EXPRESS_TEST_MASK) { 937*6b7b58f4SRui Feng sdmmc_init_sd_express(mmc, NULL); 938*6b7b58f4SRui Feng return 0; 939*6b7b58f4SRui Feng } 9409ff43c7bSRui Feng if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) 9419ff43c7bSRui Feng mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; 9429ff43c7bSRui Feng /* 9439ff43c7bSRui Feng * HW read wp status when resuming from S3/S4, 9449ff43c7bSRui Feng * and then picks SD legacy interface if it's set 9459ff43c7bSRui Feng * in read-only mode. 9469ff43c7bSRui Feng */ 9479ff43c7bSRui Feng val = rtsx_pci_readl(pcr, RTSX_BIPR); 9489ff43c7bSRui Feng if (val & SD_WRITE_PROTECT) { 9499ff43c7bSRui Feng pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS; 9509ff43c7bSRui Feng mmc->caps2 &= ~(MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V); 9519ff43c7bSRui Feng } 9529ff43c7bSRui Feng } 9539ff43c7bSRui Feng 954d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 955ff984e57SWei WANG return 0; 956ff984e57SWei WANG } 957ff984e57SWei WANG 958ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 959ff984e57SWei WANG { 960ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 961ff984e57SWei WANG int err; 962ff984e57SWei WANG 963d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 964d88691beSWei WANG 965ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 966ff984e57SWei WANG 967ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 968ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 969ff984e57SWei WANG 970ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 971ff984e57SWei WANG if (err < 0) 972ff984e57SWei WANG return err; 973ff984e57SWei WANG 974ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 975ff984e57SWei WANG if (err < 0) 976ff984e57SWei WANG return err; 977ff984e57SWei WANG 978ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 979ff984e57SWei WANG } 980ff984e57SWei WANG 981ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 982ff984e57SWei WANG unsigned char power_mode) 983ff984e57SWei WANG { 984ff984e57SWei WANG int err; 985ff984e57SWei WANG 986ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 987ff984e57SWei WANG err = sd_power_off(host); 988ff984e57SWei WANG else 989ff984e57SWei WANG err = sd_power_on(host); 990ff984e57SWei WANG 991ff984e57SWei WANG return err; 992ff984e57SWei WANG } 993ff984e57SWei WANG 99484d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 995ff984e57SWei WANG { 996ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 997ff984e57SWei WANG int err = 0; 998ff984e57SWei WANG 999ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 1000ff984e57SWei WANG 1001ff984e57SWei WANG switch (timing) { 1002ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1003ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1004ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1005ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 1006ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 1007ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1008ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1009ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1010ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 1011ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1012ff984e57SWei WANG break; 1013ff984e57SWei WANG 10141a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 1015ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1016ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1017ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 1018ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 1019ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1020ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1021ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1022ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 1023ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1024ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1025ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 1026ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1027ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 1028ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 1029ff984e57SWei WANG break; 1030ff984e57SWei WANG 1031ff984e57SWei WANG case MMC_TIMING_MMC_HS: 1032ff984e57SWei WANG case MMC_TIMING_SD_HS: 1033ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1034ff984e57SWei WANG 0x0C, SD_20_MODE); 1035ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1036ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1037ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1038ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1039ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1040ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1041ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 1042ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1043ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 1044ff984e57SWei WANG break; 1045ff984e57SWei WANG 1046ff984e57SWei WANG default: 1047ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1048ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 1049ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1050ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1051ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1052ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1053ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1054ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1055ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 1056ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1057ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 1058ff984e57SWei WANG break; 1059ff984e57SWei WANG } 1060ff984e57SWei WANG 1061ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 1062ff984e57SWei WANG 1063ff984e57SWei WANG return err; 1064ff984e57SWei WANG } 1065ff984e57SWei WANG 1066ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1067ff984e57SWei WANG { 1068ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1069ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1070ff984e57SWei WANG 1071ff984e57SWei WANG if (host->eject) 1072ff984e57SWei WANG return; 1073ff984e57SWei WANG 1074c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 1075c3481955SWei WANG return; 1076c3481955SWei WANG 1077ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1078ff984e57SWei WANG 1079ff984e57SWei WANG rtsx_pci_start_run(pcr); 1080ff984e57SWei WANG 1081ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 1082ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 108384d72f9cSWei WANG sd_set_timing(host, ios->timing); 1084ff984e57SWei WANG 1085ff984e57SWei WANG host->vpclk = false; 1086ff984e57SWei WANG host->double_clk = true; 1087ff984e57SWei WANG 1088ff984e57SWei WANG switch (ios->timing) { 1089ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1090ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1091ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 1092ff984e57SWei WANG host->vpclk = true; 1093ff984e57SWei WANG host->double_clk = false; 1094ff984e57SWei WANG break; 10951a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 1096ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1097ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 1098ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 1099ff984e57SWei WANG break; 1100ff984e57SWei WANG default: 1101ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 1102ff984e57SWei WANG break; 1103ff984e57SWei WANG } 1104ff984e57SWei WANG 1105ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 1106ff984e57SWei WANG 1107ff984e57SWei WANG host->clock = ios->clock; 1108ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 1109ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 1110ff984e57SWei WANG 1111ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1112ff984e57SWei WANG } 1113ff984e57SWei WANG 1114ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 1115ff984e57SWei WANG { 1116ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1117ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1118ff984e57SWei WANG int ro = 0; 1119ff984e57SWei WANG u32 val; 1120ff984e57SWei WANG 1121ff984e57SWei WANG if (host->eject) 1122ff984e57SWei WANG return -ENOMEDIUM; 1123ff984e57SWei WANG 1124ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1125ff984e57SWei WANG 1126ff984e57SWei WANG rtsx_pci_start_run(pcr); 1127ff984e57SWei WANG 1128ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 1129ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 1130ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1131ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 1132ff984e57SWei WANG ro = 1; 1133ff984e57SWei WANG 1134ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1135ff984e57SWei WANG 1136ff984e57SWei WANG return ro; 1137ff984e57SWei WANG } 1138ff984e57SWei WANG 1139ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 1140ff984e57SWei WANG { 1141ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1142ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1143ff984e57SWei WANG int cd = 0; 1144ff984e57SWei WANG u32 val; 1145ff984e57SWei WANG 1146ff984e57SWei WANG if (host->eject) 1147b22217f9SMicky Ching return cd; 1148ff984e57SWei WANG 1149ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1150ff984e57SWei WANG 1151ff984e57SWei WANG rtsx_pci_start_run(pcr); 1152ff984e57SWei WANG 1153ff984e57SWei WANG /* Check SD card detect */ 1154ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 1155ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1156ff984e57SWei WANG if (val & SD_EXIST) 1157ff984e57SWei WANG cd = 1; 1158ff984e57SWei WANG 1159ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1160ff984e57SWei WANG 1161ff984e57SWei WANG return cd; 1162ff984e57SWei WANG } 1163ff984e57SWei WANG 1164ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1165ff984e57SWei WANG { 1166ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1167ff984e57SWei WANG int err; 1168ff984e57SWei WANG u8 stat; 1169ff984e57SWei WANG 1170ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 1171ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 1172ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 1173ff984e57SWei WANG */ 1174ff984e57SWei WANG mdelay(1); 1175ff984e57SWei WANG 1176ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1177ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 1178ff984e57SWei WANG * abort the voltage switch sequence; 1179ff984e57SWei WANG */ 1180ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1181ff984e57SWei WANG if (err < 0) 1182ff984e57SWei WANG return err; 1183ff984e57SWei WANG 1184ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1185ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 1186ff984e57SWei WANG return -EINVAL; 1187ff984e57SWei WANG 1188ff984e57SWei WANG /* Stop toggle SD clock */ 1189ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1190ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 1191ff984e57SWei WANG if (err < 0) 1192ff984e57SWei WANG return err; 1193ff984e57SWei WANG 1194ff984e57SWei WANG return 0; 1195ff984e57SWei WANG } 1196ff984e57SWei WANG 1197ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1198ff984e57SWei WANG { 1199ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1200ff984e57SWei WANG int err; 1201ff984e57SWei WANG u8 stat, mask, val; 1202ff984e57SWei WANG 1203ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1204ff984e57SWei WANG msleep(50); 1205ff984e57SWei WANG 1206ff984e57SWei WANG /* Toggle SD clock again */ 1207ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1208ff984e57SWei WANG if (err < 0) 1209ff984e57SWei WANG return err; 1210ff984e57SWei WANG 1211ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1212ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1213ff984e57SWei WANG */ 1214ff984e57SWei WANG msleep(20); 1215ff984e57SWei WANG 1216ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1217ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1218ff984e57SWei WANG if (err < 0) 1219ff984e57SWei WANG return err; 1220ff984e57SWei WANG 1221ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1222ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1223ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1224ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1225ff984e57SWei WANG if ((stat & mask) != val) { 1226ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1227ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1228ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1229ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1230ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1231ff984e57SWei WANG return -EINVAL; 1232ff984e57SWei WANG } 1233ff984e57SWei WANG 1234ff984e57SWei WANG return 0; 1235ff984e57SWei WANG } 1236ff984e57SWei WANG 1237ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1238ff984e57SWei WANG { 1239ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1240ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1241ff984e57SWei WANG int err = 0; 1242ff984e57SWei WANG u8 voltage; 1243ff984e57SWei WANG 1244ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1245ff984e57SWei WANG __func__, ios->signal_voltage); 1246ff984e57SWei WANG 1247ff984e57SWei WANG if (host->eject) 1248ff984e57SWei WANG return -ENOMEDIUM; 1249ff984e57SWei WANG 1250c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1251c3481955SWei WANG if (err) 1252c3481955SWei WANG return err; 1253c3481955SWei WANG 1254ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1255ff984e57SWei WANG 1256ff984e57SWei WANG rtsx_pci_start_run(pcr); 1257ff984e57SWei WANG 1258ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1259ef85e736SWei WANG voltage = OUTPUT_3V3; 1260ff984e57SWei WANG else 1261ef85e736SWei WANG voltage = OUTPUT_1V8; 1262ff984e57SWei WANG 1263ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1264ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1265ff984e57SWei WANG if (err < 0) 1266ff984e57SWei WANG goto out; 1267ff984e57SWei WANG } 1268ff984e57SWei WANG 1269ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1270ff984e57SWei WANG if (err < 0) 1271ff984e57SWei WANG goto out; 1272ff984e57SWei WANG 1273ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1274ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1275ff984e57SWei WANG if (err < 0) 1276ff984e57SWei WANG goto out; 1277ff984e57SWei WANG } 1278ff984e57SWei WANG 12791b8055b4SWei WANG out: 1280ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1281ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1282ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1283ff984e57SWei WANG 1284ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1285ff984e57SWei WANG 1286ff984e57SWei WANG return err; 1287ff984e57SWei WANG } 1288ff984e57SWei WANG 1289ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1290ff984e57SWei WANG { 1291ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1292ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1293ff984e57SWei WANG int err = 0; 1294ff984e57SWei WANG 1295ff984e57SWei WANG if (host->eject) 1296ff984e57SWei WANG return -ENOMEDIUM; 1297ff984e57SWei WANG 1298c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1299c3481955SWei WANG if (err) 1300c3481955SWei WANG return err; 1301c3481955SWei WANG 1302ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1303ff984e57SWei WANG 1304ff984e57SWei WANG rtsx_pci_start_run(pcr); 1305ff984e57SWei WANG 130684d72f9cSWei WANG /* Set initial TX phase */ 130784d72f9cSWei WANG switch (mmc->ios.timing) { 130884d72f9cSWei WANG case MMC_TIMING_UHS_SDR104: 130984d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 131084d72f9cSWei WANG break; 1311ff984e57SWei WANG 131284d72f9cSWei WANG case MMC_TIMING_UHS_SDR50: 131384d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 131484d72f9cSWei WANG break; 131584d72f9cSWei WANG 131684d72f9cSWei WANG case MMC_TIMING_UHS_DDR50: 131784d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 131884d72f9cSWei WANG break; 131984d72f9cSWei WANG 132084d72f9cSWei WANG default: 132184d72f9cSWei WANG err = 0; 132284d72f9cSWei WANG } 132384d72f9cSWei WANG 132484d72f9cSWei WANG if (err) 132584d72f9cSWei WANG goto out; 132684d72f9cSWei WANG 132784d72f9cSWei WANG /* Tuning RX phase */ 132884d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 132984d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 133084d72f9cSWei WANG err = sd_tuning_rx(host, opcode); 133184d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 133284d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 133384d72f9cSWei WANG 133484d72f9cSWei WANG out: 1335ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1336ff984e57SWei WANG 1337ff984e57SWei WANG return err; 1338ff984e57SWei WANG } 1339ff984e57SWei WANG 13409ff43c7bSRui Feng static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) 13419ff43c7bSRui Feng { 13429ff43c7bSRui Feng u32 relink_time; 13439ff43c7bSRui Feng struct realtek_pci_sdmmc *host = mmc_priv(mmc); 13449ff43c7bSRui Feng struct rtsx_pcr *pcr = host->pcr; 13459ff43c7bSRui Feng 13469ff43c7bSRui Feng /* Set relink_time for changing to PCIe card */ 13479ff43c7bSRui Feng relink_time = 0x8FFF; 13489ff43c7bSRui Feng 13499ff43c7bSRui Feng rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time); 13509ff43c7bSRui Feng rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8); 13519ff43c7bSRui Feng rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16); 13529ff43c7bSRui Feng 13539ff43c7bSRui Feng rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80); 13549ff43c7bSRui Feng rtsx_pci_write_register(pcr, LDO_VCC_CFG0, 13559ff43c7bSRui Feng RTS5261_LDO1_OCP_THD_MASK, 13569ff43c7bSRui Feng pcr->option.sd_800mA_ocp_thd); 13579ff43c7bSRui Feng 13589ff43c7bSRui Feng if (pcr->ops->disable_auto_blink) 13599ff43c7bSRui Feng pcr->ops->disable_auto_blink(pcr); 13609ff43c7bSRui Feng 13619ff43c7bSRui Feng /* For PCIe/NVMe mode can't enter delink issue */ 13629ff43c7bSRui Feng pcr->hw_param.interrupt_en &= ~(SD_INT_EN); 13639ff43c7bSRui Feng rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en); 13649ff43c7bSRui Feng 13659ff43c7bSRui Feng rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4, 13669ff43c7bSRui Feng RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN); 13679ff43c7bSRui Feng rtsx_pci_write_register(pcr, RTS5261_FW_CFG0, 13689ff43c7bSRui Feng RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS); 13699ff43c7bSRui Feng rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, 1370*6b7b58f4SRui Feng RTS5261_MCU_CLOCK_GATING, RTS5261_MCU_CLOCK_GATING); 1371*6b7b58f4SRui Feng rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, 13729ff43c7bSRui Feng RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK 1373*6b7b58f4SRui Feng | RTS5261_DRIVER_ENABLE_FW, 1374*6b7b58f4SRui Feng RTS5261_MCU_CLOCK_SEL_16M | RTS5261_DRIVER_ENABLE_FW); 13759ff43c7bSRui Feng host->eject = true; 13769ff43c7bSRui Feng return 0; 13779ff43c7bSRui Feng } 13789ff43c7bSRui Feng 1379ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 13806291e715SMicky Ching .pre_req = sdmmc_pre_req, 13816291e715SMicky Ching .post_req = sdmmc_post_req, 1382ff984e57SWei WANG .request = sdmmc_request, 1383ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1384ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1385ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1386ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1387ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 13889ff43c7bSRui Feng .init_sd_express = sdmmc_init_sd_express, 1389ff984e57SWei WANG }; 1390ff984e57SWei WANG 1391ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1392ff984e57SWei WANG { 1393ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1394ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1395ff984e57SWei WANG 1396ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1397ff984e57SWei WANG 1398ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1399ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1400ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1401ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1402ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1403ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1404ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1405ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1406ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1407ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1408849a9366SRicky Wu if (pcr->extra_caps & EXTRA_CAPS_NO_MMC) 1409849a9366SRicky Wu mmc->caps2 |= MMC_CAP2_NO_MMC; 14109ff43c7bSRui Feng if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) 14119ff43c7bSRui Feng mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; 1412ff984e57SWei WANG } 1413ff984e57SWei WANG 1414ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1415ff984e57SWei WANG { 1416ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1417ff984e57SWei WANG 1418ff984e57SWei WANG mmc->f_min = 250000; 1419ff984e57SWei WANG mmc->f_max = 208000000; 1420ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1421ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1422ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 14231be64c79SUlf Hansson MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1424517bf80fSRoger Tseng mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE; 1425ff984e57SWei WANG mmc->max_current_330 = 400; 1426ff984e57SWei WANG mmc->max_current_180 = 800; 1427ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1428ff984e57SWei WANG 1429ff984e57SWei WANG init_extra_caps(host); 1430ff984e57SWei WANG 1431ff984e57SWei WANG mmc->max_segs = 256; 1432ff984e57SWei WANG mmc->max_seg_size = 65536; 1433ff984e57SWei WANG mmc->max_blk_size = 512; 1434ff984e57SWei WANG mmc->max_blk_count = 65535; 1435ff984e57SWei WANG mmc->max_req_size = 524288; 1436ff984e57SWei WANG } 1437ff984e57SWei WANG 1438ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1439ff984e57SWei WANG { 1440ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1441ff984e57SWei WANG 14422057647fSMicky Ching host->cookie = -1; 1443ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1444ff984e57SWei WANG } 1445ff984e57SWei WANG 1446ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1447ff984e57SWei WANG { 1448ff984e57SWei WANG struct mmc_host *mmc; 1449ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1450ff984e57SWei WANG struct rtsx_pcr *pcr; 1451ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1452ff984e57SWei WANG 1453ff984e57SWei WANG if (!handle) 1454ff984e57SWei WANG return -ENXIO; 1455ff984e57SWei WANG 1456ff984e57SWei WANG pcr = handle->pcr; 1457ff984e57SWei WANG if (!pcr) 1458ff984e57SWei WANG return -ENXIO; 1459ff984e57SWei WANG 1460ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1461ff984e57SWei WANG 1462ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1463ff984e57SWei WANG if (!mmc) 1464ff984e57SWei WANG return -ENOMEM; 1465ff984e57SWei WANG 1466ff984e57SWei WANG host = mmc_priv(mmc); 1467ff984e57SWei WANG host->pcr = pcr; 1468ff984e57SWei WANG host->mmc = mmc; 1469ff984e57SWei WANG host->pdev = pdev; 14702057647fSMicky Ching host->cookie = -1; 1471d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 14726291e715SMicky Ching INIT_WORK(&host->work, sd_request); 1473ff984e57SWei WANG platform_set_drvdata(pdev, host); 1474ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1475ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1476ff984e57SWei WANG 147798fcc576SMicky Ching mutex_init(&host->host_mutex); 1478ff984e57SWei WANG 1479ff984e57SWei WANG realtek_init_host(host); 1480ff984e57SWei WANG 1481ff984e57SWei WANG mmc_add_host(mmc); 1482ff984e57SWei WANG 1483ff984e57SWei WANG return 0; 1484ff984e57SWei WANG } 1485ff984e57SWei WANG 1486ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1487ff984e57SWei WANG { 1488ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1489ff984e57SWei WANG struct rtsx_pcr *pcr; 1490ff984e57SWei WANG struct mmc_host *mmc; 1491ff984e57SWei WANG 1492ff984e57SWei WANG if (!host) 1493ff984e57SWei WANG return 0; 1494ff984e57SWei WANG 1495ff984e57SWei WANG pcr = host->pcr; 1496ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1497ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1498ff984e57SWei WANG mmc = host->mmc; 1499ff984e57SWei WANG 15006291e715SMicky Ching cancel_work_sync(&host->work); 15016291e715SMicky Ching 150298fcc576SMicky Ching mutex_lock(&host->host_mutex); 1503ff984e57SWei WANG if (host->mrq) { 1504ff984e57SWei WANG dev_dbg(&(pdev->dev), 1505ff984e57SWei WANG "%s: Controller removed during transfer\n", 1506ff984e57SWei WANG mmc_hostname(mmc)); 1507ff984e57SWei WANG 150898fcc576SMicky Ching rtsx_pci_complete_unfinished_transfer(pcr); 1509ff984e57SWei WANG 151098fcc576SMicky Ching host->mrq->cmd->error = -ENOMEDIUM; 151198fcc576SMicky Ching if (host->mrq->stop) 151298fcc576SMicky Ching host->mrq->stop->error = -ENOMEDIUM; 151398fcc576SMicky Ching mmc_request_done(mmc, host->mrq); 1514ff984e57SWei WANG } 151598fcc576SMicky Ching mutex_unlock(&host->host_mutex); 1516ff984e57SWei WANG 1517ff984e57SWei WANG mmc_remove_host(mmc); 1518640e09bcSMicky Ching host->eject = true; 1519640e09bcSMicky Ching 15206ea62579SBhaktipriya Shridhar flush_work(&host->work); 15216291e715SMicky Ching 1522ff984e57SWei WANG mmc_free_host(mmc); 1523ff984e57SWei WANG 1524ff984e57SWei WANG dev_dbg(&(pdev->dev), 1525ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1526ff984e57SWei WANG 1527ff984e57SWei WANG return 0; 1528ff984e57SWei WANG } 1529ff984e57SWei WANG 1530f2483b0dSKrzysztof Kozlowski static const struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1531ff984e57SWei WANG { 1532ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1533ff984e57SWei WANG }, { 1534ff984e57SWei WANG /* sentinel */ 1535ff984e57SWei WANG } 1536ff984e57SWei WANG }; 1537ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1538ff984e57SWei WANG 1539ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1540ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1541ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1542ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1543ff984e57SWei WANG .driver = { 1544ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 154521b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1546ff984e57SWei WANG }, 1547ff984e57SWei WANG }; 1548ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1549ff984e57SWei WANG 1550ff984e57SWei WANG MODULE_LICENSE("GPL"); 1551ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1552ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1553