1ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 2ff984e57SWei WANG * 362282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4ff984e57SWei WANG * 5ff984e57SWei WANG * This program is free software; you can redistribute it and/or modify it 6ff984e57SWei WANG * under the terms of the GNU General Public License as published by the 7ff984e57SWei WANG * Free Software Foundation; either version 2, or (at your option) any 8ff984e57SWei WANG * later version. 9ff984e57SWei WANG * 10ff984e57SWei WANG * This program is distributed in the hope that it will be useful, but 11ff984e57SWei WANG * WITHOUT ANY WARRANTY; without even the implied warranty of 12ff984e57SWei WANG * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13ff984e57SWei WANG * General Public License for more details. 14ff984e57SWei WANG * 15ff984e57SWei WANG * You should have received a copy of the GNU General Public License along 16ff984e57SWei WANG * with this program; if not, see <http://www.gnu.org/licenses/>. 17ff984e57SWei WANG * 18ff984e57SWei WANG * Author: 19ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 20ff984e57SWei WANG */ 21ff984e57SWei WANG 22ff984e57SWei WANG #include <linux/module.h> 23433e075cSWei WANG #include <linux/slab.h> 24ff984e57SWei WANG #include <linux/highmem.h> 25ff984e57SWei WANG #include <linux/delay.h> 26ff984e57SWei WANG #include <linux/platform_device.h> 276291e715SMicky Ching #include <linux/workqueue.h> 28ff984e57SWei WANG #include <linux/mmc/host.h> 29ff984e57SWei WANG #include <linux/mmc/mmc.h> 30ff984e57SWei WANG #include <linux/mmc/sd.h> 31ff984e57SWei WANG #include <linux/mmc/card.h> 32ff984e57SWei WANG #include <linux/mfd/rtsx_pci.h> 33ff984e57SWei WANG #include <asm/unaligned.h> 34ff984e57SWei WANG 35ff984e57SWei WANG struct realtek_pci_sdmmc { 36ff984e57SWei WANG struct platform_device *pdev; 37ff984e57SWei WANG struct rtsx_pcr *pcr; 38ff984e57SWei WANG struct mmc_host *mmc; 39ff984e57SWei WANG struct mmc_request *mrq; 406291e715SMicky Ching struct workqueue_struct *workq; 416291e715SMicky Ching #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" 42ff984e57SWei WANG 436291e715SMicky Ching struct work_struct work; 4498fcc576SMicky Ching struct mutex host_mutex; 45ff984e57SWei WANG 46ff984e57SWei WANG u8 ssc_depth; 47ff984e57SWei WANG unsigned int clock; 48ff984e57SWei WANG bool vpclk; 49ff984e57SWei WANG bool double_clk; 50ff984e57SWei WANG bool eject; 51ff984e57SWei WANG bool initial_mode; 52d88691beSWei WANG int power_state; 53d88691beSWei WANG #define SDMMC_POWER_ON 1 54d88691beSWei WANG #define SDMMC_POWER_OFF 0 556291e715SMicky Ching 566291e715SMicky Ching unsigned int sg_count; 576291e715SMicky Ching s32 cookie; 586291e715SMicky Ching unsigned int cookie_sg_count; 596291e715SMicky Ching bool using_cookie; 60ff984e57SWei WANG }; 61ff984e57SWei WANG 62ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 63ff984e57SWei WANG { 64ff984e57SWei WANG return &(host->pdev->dev); 65ff984e57SWei WANG } 66ff984e57SWei WANG 67ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 68ff984e57SWei WANG { 69ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 70ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 71ff984e57SWei WANG } 72ff984e57SWei WANG 73ff984e57SWei WANG #ifdef DEBUG 74ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 75ff984e57SWei WANG { 76ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 77ff984e57SWei WANG u16 i; 78ff984e57SWei WANG u8 *ptr; 79ff984e57SWei WANG 80ff984e57SWei WANG /* Print SD host internal registers */ 81ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 82ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 83ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 84ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 85ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); 86ff984e57SWei WANG rtsx_pci_send_cmd(pcr, 100); 87ff984e57SWei WANG 88ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr); 89ff984e57SWei WANG for (i = 0xFDA0; i <= 0xFDAE; i++) 90ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 91ff984e57SWei WANG for (i = 0xFD52; i <= 0xFD69; i++) 92ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); 93ff984e57SWei WANG } 94ff984e57SWei WANG #else 95ff984e57SWei WANG #define sd_print_debug_regs(host) 96ff984e57SWei WANG #endif /* DEBUG */ 97ff984e57SWei WANG 986291e715SMicky Ching /* 996291e715SMicky Ching * sd_pre_dma_transfer - do dma_map_sg() or using cookie 1006291e715SMicky Ching * 1016291e715SMicky Ching * @pre: if called in pre_req() 1026291e715SMicky Ching * return: 1036291e715SMicky Ching * 0 - do dma_map_sg() 1046291e715SMicky Ching * 1 - using cookie 1056291e715SMicky Ching */ 1066291e715SMicky Ching static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, 1076291e715SMicky Ching struct mmc_data *data, bool pre) 1086291e715SMicky Ching { 1096291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 1106291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 1116291e715SMicky Ching int count = 0; 1126291e715SMicky Ching int using_cookie = 0; 1136291e715SMicky Ching 1146291e715SMicky Ching if (!pre && data->host_cookie && data->host_cookie != host->cookie) { 1156291e715SMicky Ching dev_err(sdmmc_dev(host), 1166291e715SMicky Ching "error: data->host_cookie = %d, host->cookie = %d\n", 1176291e715SMicky Ching data->host_cookie, host->cookie); 1186291e715SMicky Ching data->host_cookie = 0; 1196291e715SMicky Ching } 1206291e715SMicky Ching 1216291e715SMicky Ching if (pre || data->host_cookie != host->cookie) { 1226291e715SMicky Ching count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); 1236291e715SMicky Ching } else { 1246291e715SMicky Ching count = host->cookie_sg_count; 1256291e715SMicky Ching using_cookie = 1; 1266291e715SMicky Ching } 1276291e715SMicky Ching 1286291e715SMicky Ching if (pre) { 1296291e715SMicky Ching host->cookie_sg_count = count; 1306291e715SMicky Ching if (++host->cookie < 0) 1316291e715SMicky Ching host->cookie = 1; 1326291e715SMicky Ching data->host_cookie = host->cookie; 1336291e715SMicky Ching } else { 1346291e715SMicky Ching host->sg_count = count; 1356291e715SMicky Ching } 1366291e715SMicky Ching 1376291e715SMicky Ching return using_cookie; 1386291e715SMicky Ching } 1396291e715SMicky Ching 1406291e715SMicky Ching static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 1416291e715SMicky Ching bool is_first_req) 1426291e715SMicky Ching { 1436291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1446291e715SMicky Ching struct mmc_data *data = mrq->data; 1456291e715SMicky Ching 1466291e715SMicky Ching if (data->host_cookie) { 1476291e715SMicky Ching dev_err(sdmmc_dev(host), 1486291e715SMicky Ching "error: reset data->host_cookie = %d\n", 1496291e715SMicky Ching data->host_cookie); 1506291e715SMicky Ching data->host_cookie = 0; 1516291e715SMicky Ching } 1526291e715SMicky Ching 1536291e715SMicky Ching sd_pre_dma_transfer(host, data, true); 1546291e715SMicky Ching dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); 1556291e715SMicky Ching } 1566291e715SMicky Ching 1576291e715SMicky Ching static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1586291e715SMicky Ching int err) 1596291e715SMicky Ching { 1606291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1616291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 1626291e715SMicky Ching struct mmc_data *data = mrq->data; 1636291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 1646291e715SMicky Ching 1656291e715SMicky Ching rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); 1666291e715SMicky Ching data->host_cookie = 0; 1676291e715SMicky Ching } 1686291e715SMicky Ching 169ff984e57SWei WANG static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 170ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 171ff984e57SWei WANG { 172ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 173ff984e57SWei WANG int err, i; 174ff984e57SWei WANG u8 trans_mode; 175ff984e57SWei WANG 176ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40); 177ff984e57SWei WANG 178ff984e57SWei WANG if (!buf) 179ff984e57SWei WANG buf_len = 0; 180ff984e57SWei WANG 181ff984e57SWei WANG if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK) 182ff984e57SWei WANG trans_mode = SD_TM_AUTO_TUNING; 183ff984e57SWei WANG else 184ff984e57SWei WANG trans_mode = SD_TM_NORMAL_READ; 185ff984e57SWei WANG 186ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 187ff984e57SWei WANG 188ff984e57SWei WANG for (i = 0; i < 5; i++) 189ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]); 190ff984e57SWei WANG 191ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 192ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 193ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 194ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 195ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 196ff984e57SWei WANG 197ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 198ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 199ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 200ff984e57SWei WANG if (trans_mode != SD_TM_AUTO_TUNING) 201ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 202ff984e57SWei WANG CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 203ff984e57SWei WANG 204ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 205ff984e57SWei WANG 0xFF, trans_mode | SD_TRANSFER_START); 206ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 207ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 208ff984e57SWei WANG 209ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 210ff984e57SWei WANG if (err < 0) { 211ff984e57SWei WANG sd_print_debug_regs(host); 212ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 213ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 214ff984e57SWei WANG return err; 215ff984e57SWei WANG } 216ff984e57SWei WANG 217ff984e57SWei WANG if (buf && buf_len) { 218ff984e57SWei WANG err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 219ff984e57SWei WANG if (err < 0) { 220ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 221ff984e57SWei WANG "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 222ff984e57SWei WANG return err; 223ff984e57SWei WANG } 224ff984e57SWei WANG } 225ff984e57SWei WANG 226ff984e57SWei WANG return 0; 227ff984e57SWei WANG } 228ff984e57SWei WANG 229ff984e57SWei WANG static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 230ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 231ff984e57SWei WANG { 232ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 233ff984e57SWei WANG int err, i; 234ff984e57SWei WANG u8 trans_mode; 235ff984e57SWei WANG 236ff984e57SWei WANG if (!buf) 237ff984e57SWei WANG buf_len = 0; 238ff984e57SWei WANG 239ff984e57SWei WANG if (buf && buf_len) { 240ff984e57SWei WANG err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 241ff984e57SWei WANG if (err < 0) { 242ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 243ff984e57SWei WANG "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 244ff984e57SWei WANG return err; 245ff984e57SWei WANG } 246ff984e57SWei WANG } 247ff984e57SWei WANG 248ff984e57SWei WANG trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3; 249ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 250ff984e57SWei WANG 251ff984e57SWei WANG if (cmd) { 252ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__, 253ff984e57SWei WANG cmd[0] - 0x40); 254ff984e57SWei WANG 255ff984e57SWei WANG for (i = 0; i < 5; i++) 256ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 257ff984e57SWei WANG SD_CMD0 + i, 0xFF, cmd[i]); 258ff984e57SWei WANG } 259ff984e57SWei WANG 260ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 261ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 262ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 263ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 264ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 265ff984e57SWei WANG 266ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 267ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 268ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 269ff984e57SWei WANG 270ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 271ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 272ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 273ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 274ff984e57SWei WANG 275ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 276ff984e57SWei WANG if (err < 0) { 277ff984e57SWei WANG sd_print_debug_regs(host); 278ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 279ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 280ff984e57SWei WANG return err; 281ff984e57SWei WANG } 282ff984e57SWei WANG 283ff984e57SWei WANG return 0; 284ff984e57SWei WANG } 285ff984e57SWei WANG 28698fcc576SMicky Ching static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 28798fcc576SMicky Ching struct mmc_command *cmd) 288ff984e57SWei WANG { 289ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 290ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 291ff984e57SWei WANG u32 arg = cmd->arg; 292ff984e57SWei WANG int err = 0; 293ff984e57SWei WANG int timeout = 100; 294ff984e57SWei WANG int i; 29598fcc576SMicky Ching u8 *ptr; 29698fcc576SMicky Ching int stat_idx = 0; 297ff984e57SWei WANG u8 rsp_type; 298ff984e57SWei WANG int rsp_len = 5; 29998fcc576SMicky Ching bool clock_toggled = false; 300ff984e57SWei WANG 301ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 302ff984e57SWei WANG __func__, cmd_idx, arg); 303ff984e57SWei WANG 304ff984e57SWei WANG /* Response type: 305ff984e57SWei WANG * R0 306ff984e57SWei WANG * R1, R5, R6, R7 307ff984e57SWei WANG * R1b 308ff984e57SWei WANG * R2 309ff984e57SWei WANG * R3, R4 310ff984e57SWei WANG */ 311ff984e57SWei WANG switch (mmc_resp_type(cmd)) { 312ff984e57SWei WANG case MMC_RSP_NONE: 313ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R0; 314ff984e57SWei WANG rsp_len = 0; 315ff984e57SWei WANG break; 316ff984e57SWei WANG case MMC_RSP_R1: 317ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1; 318ff984e57SWei WANG break; 3195027251eSMicky Ching case MMC_RSP_R1 & ~MMC_RSP_CRC: 3205027251eSMicky Ching rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; 3215027251eSMicky Ching break; 322ff984e57SWei WANG case MMC_RSP_R1B: 323ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R1b; 324ff984e57SWei WANG break; 325ff984e57SWei WANG case MMC_RSP_R2: 326ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R2; 327ff984e57SWei WANG rsp_len = 16; 328ff984e57SWei WANG break; 329ff984e57SWei WANG case MMC_RSP_R3: 330ff984e57SWei WANG rsp_type = SD_RSP_TYPE_R3; 331ff984e57SWei WANG break; 332ff984e57SWei WANG default: 333ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n"); 334ff984e57SWei WANG err = -EINVAL; 335ff984e57SWei WANG goto out; 336ff984e57SWei WANG } 337ff984e57SWei WANG 338ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 339ff984e57SWei WANG timeout = 3000; 340ff984e57SWei WANG 341ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 342ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 343ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 344ff984e57SWei WANG if (err < 0) 345ff984e57SWei WANG goto out; 34698fcc576SMicky Ching 34798fcc576SMicky Ching clock_toggled = true; 348ff984e57SWei WANG } 349ff984e57SWei WANG 350ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 351ff984e57SWei WANG 352ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx); 353ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24)); 354ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16)); 355ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8)); 356ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg); 357ff984e57SWei WANG 358ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 359ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 360ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 361ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 362ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 363ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 364ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 365ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 366ff984e57SWei WANG 367ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 368ff984e57SWei WANG /* Read data from ping-pong buffer */ 369ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 370ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 37198fcc576SMicky Ching stat_idx = 16; 372ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 373ff984e57SWei WANG /* Read data from SD_CMDx registers */ 374ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 375ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 37698fcc576SMicky Ching stat_idx = 5; 377ff984e57SWei WANG } 378ff984e57SWei WANG 379ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 380ff984e57SWei WANG 38198fcc576SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 38298fcc576SMicky Ching if (err < 0) { 38398fcc576SMicky Ching sd_print_debug_regs(host); 38498fcc576SMicky Ching sd_clear_error(host); 38598fcc576SMicky Ching dev_dbg(sdmmc_dev(host), 38698fcc576SMicky Ching "rtsx_pci_send_cmd error (err = %d)\n", err); 387ff984e57SWei WANG goto out; 388ff984e57SWei WANG } 389ff984e57SWei WANG 390ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 391ff984e57SWei WANG err = 0; 392ff984e57SWei WANG goto out; 393ff984e57SWei WANG } 394ff984e57SWei WANG 395ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 396ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 397ff984e57SWei WANG 398ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 399ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 400ff984e57SWei WANG err = -EILSEQ; 401ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 402ff984e57SWei WANG goto out; 403ff984e57SWei WANG } 404ff984e57SWei WANG 405ff984e57SWei WANG /* Check CRC7 */ 406ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 407ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 408ff984e57SWei WANG err = -EILSEQ; 409ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 410ff984e57SWei WANG goto out; 411ff984e57SWei WANG } 412ff984e57SWei WANG } 413ff984e57SWei WANG 414ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 415ff984e57SWei WANG for (i = 0; i < 4; i++) { 416ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 417ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 418ff984e57SWei WANG i, cmd->resp[i]); 419ff984e57SWei WANG } 420ff984e57SWei WANG } else { 421ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 422ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 423ff984e57SWei WANG cmd->resp[0]); 424ff984e57SWei WANG } 425ff984e57SWei WANG 426ff984e57SWei WANG out: 427ff984e57SWei WANG cmd->error = err; 4281b8055b4SWei WANG 42998fcc576SMicky Ching if (err && clock_toggled) 43098fcc576SMicky Ching rtsx_pci_write_register(pcr, SD_BUS_STAT, 43198fcc576SMicky Ching SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 432ff984e57SWei WANG } 433ff984e57SWei WANG 43498fcc576SMicky Ching static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 435ff984e57SWei WANG { 436ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 437ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 438ff984e57SWei WANG struct mmc_card *card = mmc->card; 439ff984e57SWei WANG struct mmc_data *data = mrq->data; 44071ef1ea4SJackey Shen int uhs = mmc_card_uhs(card); 44198fcc576SMicky Ching int read = (data->flags & MMC_DATA_READ) ? 1 : 0; 442ff984e57SWei WANG u8 cfg2, trans_mode; 443ff984e57SWei WANG int err; 444ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 445ff984e57SWei WANG 446ff984e57SWei WANG if (read) { 447ff984e57SWei WANG cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 448ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0; 449ff984e57SWei WANG trans_mode = SD_TM_AUTO_READ_3; 450ff984e57SWei WANG } else { 451ff984e57SWei WANG cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 452ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 453ff984e57SWei WANG trans_mode = SD_TM_AUTO_WRITE_3; 454ff984e57SWei WANG } 455ff984e57SWei WANG 456ff984e57SWei WANG if (!uhs) 457ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 458ff984e57SWei WANG 459ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 460ff984e57SWei WANG 461ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00); 462ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02); 463ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 464ff984e57SWei WANG 0xFF, (u8)data->blocks); 465ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 466ff984e57SWei WANG 0xFF, (u8)(data->blocks >> 8)); 467ff984e57SWei WANG 468ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 469ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 470ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 471ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 472ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 473ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 474ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 475ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 476ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 477ff984e57SWei WANG if (read) { 478ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 479ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 480ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 481ff984e57SWei WANG } else { 482ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 483ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 484ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 485ff984e57SWei WANG } 486ff984e57SWei WANG 487ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 488ff984e57SWei WANG 0x01, RING_BUFFER); 489ff984e57SWei WANG 49038d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 491ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 492ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 493ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 494ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 495ff984e57SWei WANG 496ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 497ff984e57SWei WANG 4986291e715SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, read, 10000); 499ff984e57SWei WANG if (err < 0) { 50098fcc576SMicky Ching sd_clear_error(host); 50198fcc576SMicky Ching return err; 502c42deffdSMicky Ching } 50398fcc576SMicky Ching 504c42deffdSMicky Ching return 0; 505ff984e57SWei WANG } 506ff984e57SWei WANG 507ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 508ff984e57SWei WANG { 509ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 510ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 511ff984e57SWei WANG } 512ff984e57SWei WANG 513ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 514ff984e57SWei WANG { 515ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 516ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 517ff984e57SWei WANG } 518ff984e57SWei WANG 519ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 520ff984e57SWei WANG struct mmc_request *mrq) 521ff984e57SWei WANG { 522ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 523ff984e57SWei WANG struct mmc_data *data = mrq->data; 524ff984e57SWei WANG u8 _cmd[5], *buf; 525ff984e57SWei WANG 526ff984e57SWei WANG _cmd[0] = 0x40 | (u8)cmd->opcode; 527ff984e57SWei WANG put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1])); 528ff984e57SWei WANG 529ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 530ff984e57SWei WANG if (!buf) { 531ff984e57SWei WANG cmd->error = -ENOMEM; 532ff984e57SWei WANG return; 533ff984e57SWei WANG } 534ff984e57SWei WANG 535ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 536ff984e57SWei WANG if (host->initial_mode) 537ff984e57SWei WANG sd_disable_initial_mode(host); 538ff984e57SWei WANG 539ff984e57SWei WANG cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf, 540ff984e57SWei WANG data->blksz, 200); 541ff984e57SWei WANG 542ff984e57SWei WANG if (host->initial_mode) 543ff984e57SWei WANG sd_enable_initial_mode(host); 544ff984e57SWei WANG 545ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 546ff984e57SWei WANG } else { 547ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 548ff984e57SWei WANG 549ff984e57SWei WANG cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf, 550ff984e57SWei WANG data->blksz, 200); 551ff984e57SWei WANG } 552ff984e57SWei WANG 553ff984e57SWei WANG kfree(buf); 554ff984e57SWei WANG } 555ff984e57SWei WANG 55684d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, 55784d72f9cSWei WANG u8 sample_point, bool rx) 558ff984e57SWei WANG { 559ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 560ff984e57SWei WANG int err; 561ff984e57SWei WANG 56284d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 56384d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point); 564ff984e57SWei WANG 565ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 566ff984e57SWei WANG 567ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 56884d72f9cSWei WANG if (rx) 56984d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 57084d72f9cSWei WANG SD_VPRX_CTL, 0x1F, sample_point); 57184d72f9cSWei WANG else 57284d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 57384d72f9cSWei WANG SD_VPTX_CTL, 0x1F, sample_point); 574ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); 575ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 576ff984e57SWei WANG PHASE_NOT_RESET, PHASE_NOT_RESET); 577ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); 578ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 579ff984e57SWei WANG 580ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 581ff984e57SWei WANG if (err < 0) 582ff984e57SWei WANG return err; 583ff984e57SWei WANG 584ff984e57SWei WANG return 0; 585ff984e57SWei WANG } 586ff984e57SWei WANG 587abcc6b29SMicky Ching static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 588abcc6b29SMicky Ching { 589abcc6b29SMicky Ching bit %= RTSX_PHASE_MAX; 590abcc6b29SMicky Ching return phase_map & (1 << bit); 591abcc6b29SMicky Ching } 592abcc6b29SMicky Ching 593abcc6b29SMicky Ching static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 594abcc6b29SMicky Ching { 595abcc6b29SMicky Ching int i; 596abcc6b29SMicky Ching 597abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 598abcc6b29SMicky Ching if (test_phase_bit(phase_map, start_bit + i) == 0) 599abcc6b29SMicky Ching return i; 600abcc6b29SMicky Ching } 601abcc6b29SMicky Ching return RTSX_PHASE_MAX; 602abcc6b29SMicky Ching } 603abcc6b29SMicky Ching 604ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 605ff984e57SWei WANG { 606abcc6b29SMicky Ching int start = 0, len = 0; 607abcc6b29SMicky Ching int start_final = 0, len_final = 0; 608ff984e57SWei WANG u8 final_phase = 0xFF; 609ff984e57SWei WANG 610abcc6b29SMicky Ching if (phase_map == 0) { 611abcc6b29SMicky Ching dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 612abcc6b29SMicky Ching return final_phase; 613ff984e57SWei WANG } 614ff984e57SWei WANG 615abcc6b29SMicky Ching while (start < RTSX_PHASE_MAX) { 616abcc6b29SMicky Ching len = sd_get_phase_len(phase_map, start); 617abcc6b29SMicky Ching if (len_final < len) { 618abcc6b29SMicky Ching start_final = start; 619abcc6b29SMicky Ching len_final = len; 620abcc6b29SMicky Ching } 621abcc6b29SMicky Ching start += len ? len : 1; 622ff984e57SWei WANG } 623ff984e57SWei WANG 624abcc6b29SMicky Ching final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 625abcc6b29SMicky Ching dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 626abcc6b29SMicky Ching phase_map, len_final, final_phase); 627ff984e57SWei WANG 628ff984e57SWei WANG return final_phase; 629ff984e57SWei WANG } 630ff984e57SWei WANG 631ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 632ff984e57SWei WANG { 633ff984e57SWei WANG int err, i; 634ff984e57SWei WANG u8 val = 0; 635ff984e57SWei WANG 636ff984e57SWei WANG for (i = 0; i < 100; i++) { 637ff984e57SWei WANG err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 638ff984e57SWei WANG if (val & SD_DATA_IDLE) 639ff984e57SWei WANG return; 640ff984e57SWei WANG 641ff984e57SWei WANG udelay(100); 642ff984e57SWei WANG } 643ff984e57SWei WANG } 644ff984e57SWei WANG 645ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 646ff984e57SWei WANG u8 opcode, u8 sample_point) 647ff984e57SWei WANG { 648ff984e57SWei WANG int err; 649ff984e57SWei WANG u8 cmd[5] = {0}; 650ff984e57SWei WANG 65184d72f9cSWei WANG err = sd_change_phase(host, sample_point, true); 652ff984e57SWei WANG if (err < 0) 653ff984e57SWei WANG return err; 654ff984e57SWei WANG 655ff984e57SWei WANG cmd[0] = 0x40 | opcode; 656ff984e57SWei WANG err = sd_read_data(host, cmd, 0x40, NULL, 0, 100); 657ff984e57SWei WANG if (err < 0) { 658ff984e57SWei WANG /* Wait till SD DATA IDLE */ 659ff984e57SWei WANG sd_wait_data_idle(host); 660ff984e57SWei WANG sd_clear_error(host); 661ff984e57SWei WANG return err; 662ff984e57SWei WANG } 663ff984e57SWei WANG 664ff984e57SWei WANG return 0; 665ff984e57SWei WANG } 666ff984e57SWei WANG 667ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 668ff984e57SWei WANG u8 opcode, u32 *phase_map) 669ff984e57SWei WANG { 670ff984e57SWei WANG int err, i; 671ff984e57SWei WANG u32 raw_phase_map = 0; 672ff984e57SWei WANG 673abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 674ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 675ff984e57SWei WANG if (err == 0) 676ff984e57SWei WANG raw_phase_map |= 1 << i; 677ff984e57SWei WANG } 678ff984e57SWei WANG 679ff984e57SWei WANG if (phase_map) 680ff984e57SWei WANG *phase_map = raw_phase_map; 681ff984e57SWei WANG 682ff984e57SWei WANG return 0; 683ff984e57SWei WANG } 684ff984e57SWei WANG 685ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 686ff984e57SWei WANG { 687ff984e57SWei WANG int err, i; 688ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 689ff984e57SWei WANG u8 final_phase; 690ff984e57SWei WANG 691ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 692ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 693ff984e57SWei WANG if (err < 0) 694ff984e57SWei WANG return err; 695ff984e57SWei WANG 696ff984e57SWei WANG if (raw_phase_map[i] == 0) 697ff984e57SWei WANG break; 698ff984e57SWei WANG } 699ff984e57SWei WANG 700ff984e57SWei WANG phase_map = 0xFFFFFFFF; 701ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 702ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 703ff984e57SWei WANG i, raw_phase_map[i]); 704ff984e57SWei WANG phase_map &= raw_phase_map[i]; 705ff984e57SWei WANG } 706ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 707ff984e57SWei WANG 708ff984e57SWei WANG if (phase_map) { 709ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 710ff984e57SWei WANG if (final_phase == 0xFF) 711ff984e57SWei WANG return -EINVAL; 712ff984e57SWei WANG 71384d72f9cSWei WANG err = sd_change_phase(host, final_phase, true); 714ff984e57SWei WANG if (err < 0) 715ff984e57SWei WANG return err; 716ff984e57SWei WANG } else { 717ff984e57SWei WANG return -EINVAL; 718ff984e57SWei WANG } 719ff984e57SWei WANG 720ff984e57SWei WANG return 0; 721ff984e57SWei WANG } 722ff984e57SWei WANG 7236291e715SMicky Ching static inline int sd_rw_cmd(struct mmc_command *cmd) 724ff984e57SWei WANG { 7256291e715SMicky Ching return mmc_op_multi(cmd->opcode) || 7266291e715SMicky Ching (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 7276291e715SMicky Ching (cmd->opcode == MMC_WRITE_BLOCK); 7286291e715SMicky Ching } 7296291e715SMicky Ching 7306291e715SMicky Ching static void sd_request(struct work_struct *work) 7316291e715SMicky Ching { 7326291e715SMicky Ching struct realtek_pci_sdmmc *host = container_of(work, 7336291e715SMicky Ching struct realtek_pci_sdmmc, work); 734ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 7356291e715SMicky Ching 7366291e715SMicky Ching struct mmc_host *mmc = host->mmc; 7376291e715SMicky Ching struct mmc_request *mrq = host->mrq; 738ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 739ff984e57SWei WANG struct mmc_data *data = mrq->data; 7406291e715SMicky Ching 741ff984e57SWei WANG unsigned int data_size = 0; 742c3481955SWei WANG int err; 743ff984e57SWei WANG 744ff984e57SWei WANG if (host->eject) { 745ff984e57SWei WANG cmd->error = -ENOMEDIUM; 746ff984e57SWei WANG goto finish; 747ff984e57SWei WANG } 748ff984e57SWei WANG 749c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 750c3481955SWei WANG if (err) { 751c3481955SWei WANG cmd->error = err; 752c3481955SWei WANG goto finish; 753c3481955SWei WANG } 754c3481955SWei WANG 75598fcc576SMicky Ching mutex_lock(&pcr->pcr_mutex); 75698fcc576SMicky Ching 757ff984e57SWei WANG rtsx_pci_start_run(pcr); 758ff984e57SWei WANG 759ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 760ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 761ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 762ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 763ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 764ff984e57SWei WANG 76598fcc576SMicky Ching mutex_lock(&host->host_mutex); 76698fcc576SMicky Ching host->mrq = mrq; 76798fcc576SMicky Ching mutex_unlock(&host->host_mutex); 76898fcc576SMicky Ching 769ff984e57SWei WANG if (mrq->data) 770ff984e57SWei WANG data_size = data->blocks * data->blksz; 771ff984e57SWei WANG 7726291e715SMicky Ching if (!data_size || sd_rw_cmd(cmd)) { 77398fcc576SMicky Ching sd_send_cmd_get_rsp(host, cmd); 774ff984e57SWei WANG 77598fcc576SMicky Ching if (!cmd->error && data_size) { 77698fcc576SMicky Ching sd_rw_multi(host, mrq); 7776291e715SMicky Ching if (!host->using_cookie) 7786291e715SMicky Ching sdmmc_post_req(host->mmc, host->mrq, 0); 77998fcc576SMicky Ching 78098fcc576SMicky Ching if (mmc_op_multi(cmd->opcode) && mrq->stop) 78198fcc576SMicky Ching sd_send_cmd_get_rsp(host, mrq->stop); 782ff984e57SWei WANG } 78398fcc576SMicky Ching } else { 78498fcc576SMicky Ching sd_normal_rw(host, mrq); 78598fcc576SMicky Ching } 78698fcc576SMicky Ching 78798fcc576SMicky Ching if (mrq->data) { 78898fcc576SMicky Ching if (cmd->error || data->error) 78998fcc576SMicky Ching data->bytes_xfered = 0; 79098fcc576SMicky Ching else 79198fcc576SMicky Ching data->bytes_xfered = data->blocks * data->blksz; 79298fcc576SMicky Ching } 79398fcc576SMicky Ching 79498fcc576SMicky Ching mutex_unlock(&pcr->pcr_mutex); 795ff984e57SWei WANG 796ff984e57SWei WANG finish: 79798fcc576SMicky Ching if (cmd->error) 79898fcc576SMicky Ching dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error); 79998fcc576SMicky Ching 80098fcc576SMicky Ching mutex_lock(&host->host_mutex); 80198fcc576SMicky Ching host->mrq = NULL; 80298fcc576SMicky Ching mutex_unlock(&host->host_mutex); 80398fcc576SMicky Ching 80498fcc576SMicky Ching mmc_request_done(mmc, mrq); 805ff984e57SWei WANG } 806ff984e57SWei WANG 8076291e715SMicky Ching static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 8086291e715SMicky Ching { 8096291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 8106291e715SMicky Ching struct mmc_data *data = mrq->data; 8116291e715SMicky Ching 8126291e715SMicky Ching mutex_lock(&host->host_mutex); 8136291e715SMicky Ching host->mrq = mrq; 8146291e715SMicky Ching mutex_unlock(&host->host_mutex); 8156291e715SMicky Ching 8166291e715SMicky Ching if (sd_rw_cmd(mrq->cmd)) 8176291e715SMicky Ching host->using_cookie = sd_pre_dma_transfer(host, data, false); 8186291e715SMicky Ching 8196291e715SMicky Ching queue_work(host->workq, &host->work); 8206291e715SMicky Ching } 8216291e715SMicky Ching 822ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 823ff984e57SWei WANG unsigned char bus_width) 824ff984e57SWei WANG { 825ff984e57SWei WANG int err = 0; 826ff984e57SWei WANG u8 width[] = { 827ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 828ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 829ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 830ff984e57SWei WANG }; 831ff984e57SWei WANG 832ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 833ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 834ff984e57SWei WANG 0x03, width[bus_width]); 835ff984e57SWei WANG 836ff984e57SWei WANG return err; 837ff984e57SWei WANG } 838ff984e57SWei WANG 839ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 840ff984e57SWei WANG { 841ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 842ff984e57SWei WANG int err; 843ff984e57SWei WANG 844d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 845d88691beSWei WANG return 0; 846d88691beSWei WANG 847ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 848ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 849ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 850ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 851ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 852ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 853ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 854ff984e57SWei WANG if (err < 0) 855ff984e57SWei WANG return err; 856ff984e57SWei WANG 857ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 858ff984e57SWei WANG if (err < 0) 859ff984e57SWei WANG return err; 860ff984e57SWei WANG 861ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 862ff984e57SWei WANG if (err < 0) 863ff984e57SWei WANG return err; 864ff984e57SWei WANG 865ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 866ff984e57SWei WANG if (err < 0) 867ff984e57SWei WANG return err; 868ff984e57SWei WANG 869d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 870ff984e57SWei WANG return 0; 871ff984e57SWei WANG } 872ff984e57SWei WANG 873ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 874ff984e57SWei WANG { 875ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 876ff984e57SWei WANG int err; 877ff984e57SWei WANG 878d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 879d88691beSWei WANG 880ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 881ff984e57SWei WANG 882ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 883ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 884ff984e57SWei WANG 885ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 886ff984e57SWei WANG if (err < 0) 887ff984e57SWei WANG return err; 888ff984e57SWei WANG 889ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 890ff984e57SWei WANG if (err < 0) 891ff984e57SWei WANG return err; 892ff984e57SWei WANG 893ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 894ff984e57SWei WANG } 895ff984e57SWei WANG 896ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 897ff984e57SWei WANG unsigned char power_mode) 898ff984e57SWei WANG { 899ff984e57SWei WANG int err; 900ff984e57SWei WANG 901ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 902ff984e57SWei WANG err = sd_power_off(host); 903ff984e57SWei WANG else 904ff984e57SWei WANG err = sd_power_on(host); 905ff984e57SWei WANG 906ff984e57SWei WANG return err; 907ff984e57SWei WANG } 908ff984e57SWei WANG 90984d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 910ff984e57SWei WANG { 911ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 912ff984e57SWei WANG int err = 0; 913ff984e57SWei WANG 914ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 915ff984e57SWei WANG 916ff984e57SWei WANG switch (timing) { 917ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 918ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 919ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 920ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 921ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 922ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 923ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 924ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 925ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 926ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 927ff984e57SWei WANG break; 928ff984e57SWei WANG 9291a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 930ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 931ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 932ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 933ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 934ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 935ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 936ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 937ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 938ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 939ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 940ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 941ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 942ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 943ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 944ff984e57SWei WANG break; 945ff984e57SWei WANG 946ff984e57SWei WANG case MMC_TIMING_MMC_HS: 947ff984e57SWei WANG case MMC_TIMING_SD_HS: 948ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 949ff984e57SWei WANG 0x0C, SD_20_MODE); 950ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 951ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 952ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 953ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 954ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 955ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 956ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 957ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 958ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 959ff984e57SWei WANG break; 960ff984e57SWei WANG 961ff984e57SWei WANG default: 962ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 963ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 964ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 965ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 966ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 967ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 968ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 969ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 970ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 971ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 972ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 973ff984e57SWei WANG break; 974ff984e57SWei WANG } 975ff984e57SWei WANG 976ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 977ff984e57SWei WANG 978ff984e57SWei WANG return err; 979ff984e57SWei WANG } 980ff984e57SWei WANG 981ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 982ff984e57SWei WANG { 983ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 984ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 985ff984e57SWei WANG 986ff984e57SWei WANG if (host->eject) 987ff984e57SWei WANG return; 988ff984e57SWei WANG 989c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 990c3481955SWei WANG return; 991c3481955SWei WANG 992ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 993ff984e57SWei WANG 994ff984e57SWei WANG rtsx_pci_start_run(pcr); 995ff984e57SWei WANG 996ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 997ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 99884d72f9cSWei WANG sd_set_timing(host, ios->timing); 999ff984e57SWei WANG 1000ff984e57SWei WANG host->vpclk = false; 1001ff984e57SWei WANG host->double_clk = true; 1002ff984e57SWei WANG 1003ff984e57SWei WANG switch (ios->timing) { 1004ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1005ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1006ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 1007ff984e57SWei WANG host->vpclk = true; 1008ff984e57SWei WANG host->double_clk = false; 1009ff984e57SWei WANG break; 10101a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 1011ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1012ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 1013ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 1014ff984e57SWei WANG break; 1015ff984e57SWei WANG default: 1016ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 1017ff984e57SWei WANG break; 1018ff984e57SWei WANG } 1019ff984e57SWei WANG 1020ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 1021ff984e57SWei WANG 1022ff984e57SWei WANG host->clock = ios->clock; 1023ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 1024ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 1025ff984e57SWei WANG 1026ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1027ff984e57SWei WANG } 1028ff984e57SWei WANG 1029ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 1030ff984e57SWei WANG { 1031ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1032ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1033ff984e57SWei WANG int ro = 0; 1034ff984e57SWei WANG u32 val; 1035ff984e57SWei WANG 1036ff984e57SWei WANG if (host->eject) 1037ff984e57SWei WANG return -ENOMEDIUM; 1038ff984e57SWei WANG 1039ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1040ff984e57SWei WANG 1041ff984e57SWei WANG rtsx_pci_start_run(pcr); 1042ff984e57SWei WANG 1043ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 1044ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 1045ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1046ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 1047ff984e57SWei WANG ro = 1; 1048ff984e57SWei WANG 1049ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1050ff984e57SWei WANG 1051ff984e57SWei WANG return ro; 1052ff984e57SWei WANG } 1053ff984e57SWei WANG 1054ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 1055ff984e57SWei WANG { 1056ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1057ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1058ff984e57SWei WANG int cd = 0; 1059ff984e57SWei WANG u32 val; 1060ff984e57SWei WANG 1061ff984e57SWei WANG if (host->eject) 1062ff984e57SWei WANG return -ENOMEDIUM; 1063ff984e57SWei WANG 1064ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1065ff984e57SWei WANG 1066ff984e57SWei WANG rtsx_pci_start_run(pcr); 1067ff984e57SWei WANG 1068ff984e57SWei WANG /* Check SD card detect */ 1069ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 1070ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1071ff984e57SWei WANG if (val & SD_EXIST) 1072ff984e57SWei WANG cd = 1; 1073ff984e57SWei WANG 1074ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1075ff984e57SWei WANG 1076ff984e57SWei WANG return cd; 1077ff984e57SWei WANG } 1078ff984e57SWei WANG 1079ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1080ff984e57SWei WANG { 1081ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1082ff984e57SWei WANG int err; 1083ff984e57SWei WANG u8 stat; 1084ff984e57SWei WANG 1085ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 1086ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 1087ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 1088ff984e57SWei WANG */ 1089ff984e57SWei WANG mdelay(1); 1090ff984e57SWei WANG 1091ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1092ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 1093ff984e57SWei WANG * abort the voltage switch sequence; 1094ff984e57SWei WANG */ 1095ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1096ff984e57SWei WANG if (err < 0) 1097ff984e57SWei WANG return err; 1098ff984e57SWei WANG 1099ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1100ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 1101ff984e57SWei WANG return -EINVAL; 1102ff984e57SWei WANG 1103ff984e57SWei WANG /* Stop toggle SD clock */ 1104ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1105ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 1106ff984e57SWei WANG if (err < 0) 1107ff984e57SWei WANG return err; 1108ff984e57SWei WANG 1109ff984e57SWei WANG return 0; 1110ff984e57SWei WANG } 1111ff984e57SWei WANG 1112ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1113ff984e57SWei WANG { 1114ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1115ff984e57SWei WANG int err; 1116ff984e57SWei WANG u8 stat, mask, val; 1117ff984e57SWei WANG 1118ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1119ff984e57SWei WANG msleep(50); 1120ff984e57SWei WANG 1121ff984e57SWei WANG /* Toggle SD clock again */ 1122ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1123ff984e57SWei WANG if (err < 0) 1124ff984e57SWei WANG return err; 1125ff984e57SWei WANG 1126ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1127ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1128ff984e57SWei WANG */ 1129ff984e57SWei WANG msleep(20); 1130ff984e57SWei WANG 1131ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1132ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1133ff984e57SWei WANG if (err < 0) 1134ff984e57SWei WANG return err; 1135ff984e57SWei WANG 1136ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1137ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1138ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1139ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1140ff984e57SWei WANG if ((stat & mask) != val) { 1141ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1142ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1143ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1144ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1145ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1146ff984e57SWei WANG return -EINVAL; 1147ff984e57SWei WANG } 1148ff984e57SWei WANG 1149ff984e57SWei WANG return 0; 1150ff984e57SWei WANG } 1151ff984e57SWei WANG 1152ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1153ff984e57SWei WANG { 1154ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1155ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1156ff984e57SWei WANG int err = 0; 1157ff984e57SWei WANG u8 voltage; 1158ff984e57SWei WANG 1159ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1160ff984e57SWei WANG __func__, ios->signal_voltage); 1161ff984e57SWei WANG 1162ff984e57SWei WANG if (host->eject) 1163ff984e57SWei WANG return -ENOMEDIUM; 1164ff984e57SWei WANG 1165c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1166c3481955SWei WANG if (err) 1167c3481955SWei WANG return err; 1168c3481955SWei WANG 1169ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1170ff984e57SWei WANG 1171ff984e57SWei WANG rtsx_pci_start_run(pcr); 1172ff984e57SWei WANG 1173ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1174ef85e736SWei WANG voltage = OUTPUT_3V3; 1175ff984e57SWei WANG else 1176ef85e736SWei WANG voltage = OUTPUT_1V8; 1177ff984e57SWei WANG 1178ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1179ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1180ff984e57SWei WANG if (err < 0) 1181ff984e57SWei WANG goto out; 1182ff984e57SWei WANG } 1183ff984e57SWei WANG 1184ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1185ff984e57SWei WANG if (err < 0) 1186ff984e57SWei WANG goto out; 1187ff984e57SWei WANG 1188ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1189ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1190ff984e57SWei WANG if (err < 0) 1191ff984e57SWei WANG goto out; 1192ff984e57SWei WANG } 1193ff984e57SWei WANG 11941b8055b4SWei WANG out: 1195ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1196ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1197ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1198ff984e57SWei WANG 1199ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1200ff984e57SWei WANG 1201ff984e57SWei WANG return err; 1202ff984e57SWei WANG } 1203ff984e57SWei WANG 1204ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1205ff984e57SWei WANG { 1206ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1207ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1208ff984e57SWei WANG int err = 0; 1209ff984e57SWei WANG 1210ff984e57SWei WANG if (host->eject) 1211ff984e57SWei WANG return -ENOMEDIUM; 1212ff984e57SWei WANG 1213c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1214c3481955SWei WANG if (err) 1215c3481955SWei WANG return err; 1216c3481955SWei WANG 1217ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1218ff984e57SWei WANG 1219ff984e57SWei WANG rtsx_pci_start_run(pcr); 1220ff984e57SWei WANG 122184d72f9cSWei WANG /* Set initial TX phase */ 122284d72f9cSWei WANG switch (mmc->ios.timing) { 122384d72f9cSWei WANG case MMC_TIMING_UHS_SDR104: 122484d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 122584d72f9cSWei WANG break; 1226ff984e57SWei WANG 122784d72f9cSWei WANG case MMC_TIMING_UHS_SDR50: 122884d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 122984d72f9cSWei WANG break; 123084d72f9cSWei WANG 123184d72f9cSWei WANG case MMC_TIMING_UHS_DDR50: 123284d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 123384d72f9cSWei WANG break; 123484d72f9cSWei WANG 123584d72f9cSWei WANG default: 123684d72f9cSWei WANG err = 0; 123784d72f9cSWei WANG } 123884d72f9cSWei WANG 123984d72f9cSWei WANG if (err) 124084d72f9cSWei WANG goto out; 124184d72f9cSWei WANG 124284d72f9cSWei WANG /* Tuning RX phase */ 124384d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 124484d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 124584d72f9cSWei WANG err = sd_tuning_rx(host, opcode); 124684d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 124784d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 124884d72f9cSWei WANG 124984d72f9cSWei WANG out: 1250ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1251ff984e57SWei WANG 1252ff984e57SWei WANG return err; 1253ff984e57SWei WANG } 1254ff984e57SWei WANG 1255ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 12566291e715SMicky Ching .pre_req = sdmmc_pre_req, 12576291e715SMicky Ching .post_req = sdmmc_post_req, 1258ff984e57SWei WANG .request = sdmmc_request, 1259ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1260ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1261ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1262ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1263ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 1264ff984e57SWei WANG }; 1265ff984e57SWei WANG 1266ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1267ff984e57SWei WANG { 1268ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1269ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1270ff984e57SWei WANG 1271ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1272ff984e57SWei WANG 1273ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1274ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1275ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1276ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1277ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1278ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1279ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1280ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1281ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1282ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1283ff984e57SWei WANG } 1284ff984e57SWei WANG 1285ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1286ff984e57SWei WANG { 1287ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1288ff984e57SWei WANG 1289ff984e57SWei WANG mmc->f_min = 250000; 1290ff984e57SWei WANG mmc->f_max = 208000000; 1291ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1292ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1293ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1294ff984e57SWei WANG MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1295ff984e57SWei WANG mmc->max_current_330 = 400; 1296ff984e57SWei WANG mmc->max_current_180 = 800; 1297ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1298ff984e57SWei WANG 1299ff984e57SWei WANG init_extra_caps(host); 1300ff984e57SWei WANG 1301ff984e57SWei WANG mmc->max_segs = 256; 1302ff984e57SWei WANG mmc->max_seg_size = 65536; 1303ff984e57SWei WANG mmc->max_blk_size = 512; 1304ff984e57SWei WANG mmc->max_blk_count = 65535; 1305ff984e57SWei WANG mmc->max_req_size = 524288; 1306ff984e57SWei WANG } 1307ff984e57SWei WANG 1308ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1309ff984e57SWei WANG { 1310ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1311ff984e57SWei WANG 1312ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1313ff984e57SWei WANG } 1314ff984e57SWei WANG 1315ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1316ff984e57SWei WANG { 1317ff984e57SWei WANG struct mmc_host *mmc; 1318ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1319ff984e57SWei WANG struct rtsx_pcr *pcr; 1320ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1321ff984e57SWei WANG 1322ff984e57SWei WANG if (!handle) 1323ff984e57SWei WANG return -ENXIO; 1324ff984e57SWei WANG 1325ff984e57SWei WANG pcr = handle->pcr; 1326ff984e57SWei WANG if (!pcr) 1327ff984e57SWei WANG return -ENXIO; 1328ff984e57SWei WANG 1329ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1330ff984e57SWei WANG 1331ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1332ff984e57SWei WANG if (!mmc) 1333ff984e57SWei WANG return -ENOMEM; 1334ff984e57SWei WANG 1335ff984e57SWei WANG host = mmc_priv(mmc); 13366291e715SMicky Ching host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME); 13376291e715SMicky Ching if (!host->workq) { 13386291e715SMicky Ching mmc_free_host(mmc); 13396291e715SMicky Ching return -ENOMEM; 13406291e715SMicky Ching } 1341ff984e57SWei WANG host->pcr = pcr; 1342ff984e57SWei WANG host->mmc = mmc; 1343ff984e57SWei WANG host->pdev = pdev; 1344d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 13456291e715SMicky Ching INIT_WORK(&host->work, sd_request); 1346ff984e57SWei WANG platform_set_drvdata(pdev, host); 1347ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1348ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1349ff984e57SWei WANG 135098fcc576SMicky Ching mutex_init(&host->host_mutex); 1351ff984e57SWei WANG 1352ff984e57SWei WANG realtek_init_host(host); 1353ff984e57SWei WANG 1354ff984e57SWei WANG mmc_add_host(mmc); 1355ff984e57SWei WANG 1356ff984e57SWei WANG return 0; 1357ff984e57SWei WANG } 1358ff984e57SWei WANG 1359ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1360ff984e57SWei WANG { 1361ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1362ff984e57SWei WANG struct rtsx_pcr *pcr; 1363ff984e57SWei WANG struct mmc_host *mmc; 1364ff984e57SWei WANG 1365ff984e57SWei WANG if (!host) 1366ff984e57SWei WANG return 0; 1367ff984e57SWei WANG 1368ff984e57SWei WANG pcr = host->pcr; 1369ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1370ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1371ff984e57SWei WANG mmc = host->mmc; 1372ff984e57SWei WANG 13736291e715SMicky Ching cancel_work_sync(&host->work); 13746291e715SMicky Ching 137598fcc576SMicky Ching mutex_lock(&host->host_mutex); 1376ff984e57SWei WANG if (host->mrq) { 1377ff984e57SWei WANG dev_dbg(&(pdev->dev), 1378ff984e57SWei WANG "%s: Controller removed during transfer\n", 1379ff984e57SWei WANG mmc_hostname(mmc)); 1380ff984e57SWei WANG 138198fcc576SMicky Ching rtsx_pci_complete_unfinished_transfer(pcr); 1382ff984e57SWei WANG 138398fcc576SMicky Ching host->mrq->cmd->error = -ENOMEDIUM; 138498fcc576SMicky Ching if (host->mrq->stop) 138598fcc576SMicky Ching host->mrq->stop->error = -ENOMEDIUM; 138698fcc576SMicky Ching mmc_request_done(mmc, host->mrq); 1387ff984e57SWei WANG } 138898fcc576SMicky Ching mutex_unlock(&host->host_mutex); 1389ff984e57SWei WANG 1390ff984e57SWei WANG mmc_remove_host(mmc); 1391640e09bcSMicky Ching host->eject = true; 1392640e09bcSMicky Ching 13936291e715SMicky Ching flush_workqueue(host->workq); 13946291e715SMicky Ching destroy_workqueue(host->workq); 13956291e715SMicky Ching host->workq = NULL; 13966291e715SMicky Ching 1397ff984e57SWei WANG mmc_free_host(mmc); 1398ff984e57SWei WANG 1399ff984e57SWei WANG dev_dbg(&(pdev->dev), 1400ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1401ff984e57SWei WANG 1402ff984e57SWei WANG return 0; 1403ff984e57SWei WANG } 1404ff984e57SWei WANG 1405ff984e57SWei WANG static struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1406ff984e57SWei WANG { 1407ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1408ff984e57SWei WANG }, { 1409ff984e57SWei WANG /* sentinel */ 1410ff984e57SWei WANG } 1411ff984e57SWei WANG }; 1412ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1413ff984e57SWei WANG 1414ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1415ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1416ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1417ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1418ff984e57SWei WANG .driver = { 1419ff984e57SWei WANG .owner = THIS_MODULE, 1420ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1421ff984e57SWei WANG }, 1422ff984e57SWei WANG }; 1423ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1424ff984e57SWei WANG 1425ff984e57SWei WANG MODULE_LICENSE("GPL"); 1426ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1427ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1428