1ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 2ff984e57SWei WANG * 362282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4ff984e57SWei WANG * 5ff984e57SWei WANG * This program is free software; you can redistribute it and/or modify it 6ff984e57SWei WANG * under the terms of the GNU General Public License as published by the 7ff984e57SWei WANG * Free Software Foundation; either version 2, or (at your option) any 8ff984e57SWei WANG * later version. 9ff984e57SWei WANG * 10ff984e57SWei WANG * This program is distributed in the hope that it will be useful, but 11ff984e57SWei WANG * WITHOUT ANY WARRANTY; without even the implied warranty of 12ff984e57SWei WANG * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13ff984e57SWei WANG * General Public License for more details. 14ff984e57SWei WANG * 15ff984e57SWei WANG * You should have received a copy of the GNU General Public License along 16ff984e57SWei WANG * with this program; if not, see <http://www.gnu.org/licenses/>. 17ff984e57SWei WANG * 18ff984e57SWei WANG * Author: 19ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 20ff984e57SWei WANG */ 21ff984e57SWei WANG 22ff984e57SWei WANG #include <linux/module.h> 23433e075cSWei WANG #include <linux/slab.h> 24ff984e57SWei WANG #include <linux/highmem.h> 25ff984e57SWei WANG #include <linux/delay.h> 26ff984e57SWei WANG #include <linux/platform_device.h> 276291e715SMicky Ching #include <linux/workqueue.h> 28ff984e57SWei WANG #include <linux/mmc/host.h> 29ff984e57SWei WANG #include <linux/mmc/mmc.h> 30ff984e57SWei WANG #include <linux/mmc/sd.h> 311dcb3579SMicky Ching #include <linux/mmc/sdio.h> 32ff984e57SWei WANG #include <linux/mmc/card.h> 33ff984e57SWei WANG #include <linux/mfd/rtsx_pci.h> 34ff984e57SWei WANG #include <asm/unaligned.h> 35ff984e57SWei WANG 36ff984e57SWei WANG struct realtek_pci_sdmmc { 37ff984e57SWei WANG struct platform_device *pdev; 38ff984e57SWei WANG struct rtsx_pcr *pcr; 39ff984e57SWei WANG struct mmc_host *mmc; 40ff984e57SWei WANG struct mmc_request *mrq; 416291e715SMicky Ching struct workqueue_struct *workq; 426291e715SMicky Ching #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" 43ff984e57SWei WANG 446291e715SMicky Ching struct work_struct work; 4598fcc576SMicky Ching struct mutex host_mutex; 46ff984e57SWei WANG 47ff984e57SWei WANG u8 ssc_depth; 48ff984e57SWei WANG unsigned int clock; 49ff984e57SWei WANG bool vpclk; 50ff984e57SWei WANG bool double_clk; 51ff984e57SWei WANG bool eject; 52ff984e57SWei WANG bool initial_mode; 53d88691beSWei WANG int power_state; 54d88691beSWei WANG #define SDMMC_POWER_ON 1 55d88691beSWei WANG #define SDMMC_POWER_OFF 0 566291e715SMicky Ching 576291e715SMicky Ching unsigned int sg_count; 586291e715SMicky Ching s32 cookie; 596291e715SMicky Ching unsigned int cookie_sg_count; 606291e715SMicky Ching bool using_cookie; 61ff984e57SWei WANG }; 62ff984e57SWei WANG 63ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 64ff984e57SWei WANG { 65ff984e57SWei WANG return &(host->pdev->dev); 66ff984e57SWei WANG } 67ff984e57SWei WANG 68ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 69ff984e57SWei WANG { 70ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 71ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 72ff984e57SWei WANG } 73ff984e57SWei WANG 74ff984e57SWei WANG #ifdef DEBUG 75755987f9SMicky Ching static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end) 76755987f9SMicky Ching { 77755987f9SMicky Ching u16 len = end - start + 1; 78755987f9SMicky Ching int i; 79755987f9SMicky Ching u8 data[8]; 80755987f9SMicky Ching 81755987f9SMicky Ching for (i = 0; i < len; i += 8) { 82755987f9SMicky Ching int j; 83755987f9SMicky Ching int n = min(8, len - i); 84755987f9SMicky Ching 85755987f9SMicky Ching memset(&data, 0, sizeof(data)); 86755987f9SMicky Ching for (j = 0; j < n; j++) 87755987f9SMicky Ching rtsx_pci_read_register(host->pcr, start + i + j, 88755987f9SMicky Ching data + j); 89755987f9SMicky Ching dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n", 90755987f9SMicky Ching start + i, n, data); 91755987f9SMicky Ching } 92755987f9SMicky Ching } 93755987f9SMicky Ching 94ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 95ff984e57SWei WANG { 96755987f9SMicky Ching dump_reg_range(host, 0xFDA0, 0xFDB3); 97755987f9SMicky Ching dump_reg_range(host, 0xFD52, 0xFD69); 98ff984e57SWei WANG } 99ff984e57SWei WANG #else 100ff984e57SWei WANG #define sd_print_debug_regs(host) 101ff984e57SWei WANG #endif /* DEBUG */ 102ff984e57SWei WANG 1032d48e5f1SMicky Ching static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd) 1042d48e5f1SMicky Ching { 1052d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 1062d48e5f1SMicky Ching SD_CMD_START | cmd->opcode); 1072d48e5f1SMicky Ching rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg); 1082d48e5f1SMicky Ching } 1092d48e5f1SMicky Ching 1102d48e5f1SMicky Ching static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz) 1112d48e5f1SMicky Ching { 1122d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); 1132d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); 1142d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); 1152d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); 1162d48e5f1SMicky Ching } 1172d48e5f1SMicky Ching 1182d48e5f1SMicky Ching static int sd_response_type(struct mmc_command *cmd) 1192d48e5f1SMicky Ching { 1202d48e5f1SMicky Ching switch (mmc_resp_type(cmd)) { 1212d48e5f1SMicky Ching case MMC_RSP_NONE: 1222d48e5f1SMicky Ching return SD_RSP_TYPE_R0; 1232d48e5f1SMicky Ching case MMC_RSP_R1: 1242d48e5f1SMicky Ching return SD_RSP_TYPE_R1; 1252d48e5f1SMicky Ching case MMC_RSP_R1 & ~MMC_RSP_CRC: 1262d48e5f1SMicky Ching return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; 1272d48e5f1SMicky Ching case MMC_RSP_R1B: 1282d48e5f1SMicky Ching return SD_RSP_TYPE_R1b; 1292d48e5f1SMicky Ching case MMC_RSP_R2: 1302d48e5f1SMicky Ching return SD_RSP_TYPE_R2; 1312d48e5f1SMicky Ching case MMC_RSP_R3: 1322d48e5f1SMicky Ching return SD_RSP_TYPE_R3; 1332d48e5f1SMicky Ching default: 1342d48e5f1SMicky Ching return -EINVAL; 1352d48e5f1SMicky Ching } 1362d48e5f1SMicky Ching } 1372d48e5f1SMicky Ching 1382d48e5f1SMicky Ching static int sd_status_index(int resp_type) 1392d48e5f1SMicky Ching { 1402d48e5f1SMicky Ching if (resp_type == SD_RSP_TYPE_R0) 1412d48e5f1SMicky Ching return 0; 1422d48e5f1SMicky Ching else if (resp_type == SD_RSP_TYPE_R2) 1432d48e5f1SMicky Ching return 16; 1442d48e5f1SMicky Ching 1452d48e5f1SMicky Ching return 5; 1462d48e5f1SMicky Ching } 1476291e715SMicky Ching /* 1486291e715SMicky Ching * sd_pre_dma_transfer - do dma_map_sg() or using cookie 1496291e715SMicky Ching * 1506291e715SMicky Ching * @pre: if called in pre_req() 1516291e715SMicky Ching * return: 1526291e715SMicky Ching * 0 - do dma_map_sg() 1536291e715SMicky Ching * 1 - using cookie 1546291e715SMicky Ching */ 1556291e715SMicky Ching static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, 1566291e715SMicky Ching struct mmc_data *data, bool pre) 1576291e715SMicky Ching { 1586291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 1596291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 1606291e715SMicky Ching int count = 0; 1616291e715SMicky Ching int using_cookie = 0; 1626291e715SMicky Ching 1636291e715SMicky Ching if (!pre && data->host_cookie && data->host_cookie != host->cookie) { 1646291e715SMicky Ching dev_err(sdmmc_dev(host), 1656291e715SMicky Ching "error: data->host_cookie = %d, host->cookie = %d\n", 1666291e715SMicky Ching data->host_cookie, host->cookie); 1676291e715SMicky Ching data->host_cookie = 0; 1686291e715SMicky Ching } 1696291e715SMicky Ching 1706291e715SMicky Ching if (pre || data->host_cookie != host->cookie) { 1716291e715SMicky Ching count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); 1726291e715SMicky Ching } else { 1736291e715SMicky Ching count = host->cookie_sg_count; 1746291e715SMicky Ching using_cookie = 1; 1756291e715SMicky Ching } 1766291e715SMicky Ching 1776291e715SMicky Ching if (pre) { 1786291e715SMicky Ching host->cookie_sg_count = count; 1796291e715SMicky Ching if (++host->cookie < 0) 1806291e715SMicky Ching host->cookie = 1; 1816291e715SMicky Ching data->host_cookie = host->cookie; 1826291e715SMicky Ching } else { 1836291e715SMicky Ching host->sg_count = count; 1846291e715SMicky Ching } 1856291e715SMicky Ching 1866291e715SMicky Ching return using_cookie; 1876291e715SMicky Ching } 1886291e715SMicky Ching 1896291e715SMicky Ching static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 1906291e715SMicky Ching bool is_first_req) 1916291e715SMicky Ching { 1926291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1936291e715SMicky Ching struct mmc_data *data = mrq->data; 1946291e715SMicky Ching 1956291e715SMicky Ching if (data->host_cookie) { 1966291e715SMicky Ching dev_err(sdmmc_dev(host), 1976291e715SMicky Ching "error: reset data->host_cookie = %d\n", 1986291e715SMicky Ching data->host_cookie); 1996291e715SMicky Ching data->host_cookie = 0; 2006291e715SMicky Ching } 2016291e715SMicky Ching 2026291e715SMicky Ching sd_pre_dma_transfer(host, data, true); 2036291e715SMicky Ching dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); 2046291e715SMicky Ching } 2056291e715SMicky Ching 2066291e715SMicky Ching static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2076291e715SMicky Ching int err) 2086291e715SMicky Ching { 2096291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 2106291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 2116291e715SMicky Ching struct mmc_data *data = mrq->data; 2126291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 2136291e715SMicky Ching 2146291e715SMicky Ching rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); 2156291e715SMicky Ching data->host_cookie = 0; 2166291e715SMicky Ching } 2176291e715SMicky Ching 21898fcc576SMicky Ching static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 21998fcc576SMicky Ching struct mmc_command *cmd) 220ff984e57SWei WANG { 221ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 222ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 223ff984e57SWei WANG u32 arg = cmd->arg; 224ff984e57SWei WANG int err = 0; 225ff984e57SWei WANG int timeout = 100; 226ff984e57SWei WANG int i; 22798fcc576SMicky Ching u8 *ptr; 2282d48e5f1SMicky Ching int rsp_type; 2292d48e5f1SMicky Ching int stat_idx; 23098fcc576SMicky Ching bool clock_toggled = false; 231ff984e57SWei WANG 232ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 233ff984e57SWei WANG __func__, cmd_idx, arg); 234ff984e57SWei WANG 2352d48e5f1SMicky Ching rsp_type = sd_response_type(cmd); 2362d48e5f1SMicky Ching if (rsp_type < 0) 237ff984e57SWei WANG goto out; 2382d48e5f1SMicky Ching 2392d48e5f1SMicky Ching stat_idx = sd_status_index(rsp_type); 240ff984e57SWei WANG 241ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 242ff984e57SWei WANG timeout = 3000; 243ff984e57SWei WANG 244ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 245ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 246ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 247ff984e57SWei WANG if (err < 0) 248ff984e57SWei WANG goto out; 24998fcc576SMicky Ching 25098fcc576SMicky Ching clock_toggled = true; 251ff984e57SWei WANG } 252ff984e57SWei WANG 253ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 2542d48e5f1SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 255ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 256ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 257ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 258ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 259ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 260ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 261ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 262ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 263ff984e57SWei WANG 264ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 265ff984e57SWei WANG /* Read data from ping-pong buffer */ 266ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 267ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 268ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 269ff984e57SWei WANG /* Read data from SD_CMDx registers */ 270ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 271ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 272ff984e57SWei WANG } 273ff984e57SWei WANG 274ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 275ff984e57SWei WANG 27698fcc576SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 27798fcc576SMicky Ching if (err < 0) { 27898fcc576SMicky Ching sd_print_debug_regs(host); 27998fcc576SMicky Ching sd_clear_error(host); 28098fcc576SMicky Ching dev_dbg(sdmmc_dev(host), 28198fcc576SMicky Ching "rtsx_pci_send_cmd error (err = %d)\n", err); 282ff984e57SWei WANG goto out; 283ff984e57SWei WANG } 284ff984e57SWei WANG 285ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 286ff984e57SWei WANG err = 0; 287ff984e57SWei WANG goto out; 288ff984e57SWei WANG } 289ff984e57SWei WANG 290ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 291ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 292ff984e57SWei WANG 293ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 294ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 295ff984e57SWei WANG err = -EILSEQ; 296ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 297ff984e57SWei WANG goto out; 298ff984e57SWei WANG } 299ff984e57SWei WANG 300ff984e57SWei WANG /* Check CRC7 */ 301ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 302ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 303ff984e57SWei WANG err = -EILSEQ; 304ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 305ff984e57SWei WANG goto out; 306ff984e57SWei WANG } 307ff984e57SWei WANG } 308ff984e57SWei WANG 309ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 310d1419d50SRoger Tseng /* 311d1419d50SRoger Tseng * The controller offloads the last byte {CRC-7, end bit 1'b1} 312d1419d50SRoger Tseng * of response type R2. Assign dummy CRC, 0, and end bit to the 313d1419d50SRoger Tseng * byte(ptr[16], goes into the LSB of resp[3] later). 314d1419d50SRoger Tseng */ 315d1419d50SRoger Tseng ptr[16] = 1; 316d1419d50SRoger Tseng 317ff984e57SWei WANG for (i = 0; i < 4; i++) { 318ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 319ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 320ff984e57SWei WANG i, cmd->resp[i]); 321ff984e57SWei WANG } 322ff984e57SWei WANG } else { 323ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 324ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 325ff984e57SWei WANG cmd->resp[0]); 326ff984e57SWei WANG } 327ff984e57SWei WANG 328ff984e57SWei WANG out: 329ff984e57SWei WANG cmd->error = err; 3301b8055b4SWei WANG 33198fcc576SMicky Ching if (err && clock_toggled) 33298fcc576SMicky Ching rtsx_pci_write_register(pcr, SD_BUS_STAT, 33398fcc576SMicky Ching SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 334ff984e57SWei WANG } 335ff984e57SWei WANG 33656d1c0d9SMicky Ching static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd, 33756d1c0d9SMicky Ching u16 byte_cnt, u8 *buf, int buf_len, int timeout) 33856d1c0d9SMicky Ching { 33956d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr; 34056d1c0d9SMicky Ching int err; 34156d1c0d9SMicky Ching u8 trans_mode; 34256d1c0d9SMicky Ching 34356d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 34456d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg); 34556d1c0d9SMicky Ching 34656d1c0d9SMicky Ching if (!buf) 34756d1c0d9SMicky Ching buf_len = 0; 34856d1c0d9SMicky Ching 34956d1c0d9SMicky Ching if (cmd->opcode == MMC_SEND_TUNING_BLOCK) 35056d1c0d9SMicky Ching trans_mode = SD_TM_AUTO_TUNING; 35156d1c0d9SMicky Ching else 35256d1c0d9SMicky Ching trans_mode = SD_TM_NORMAL_READ; 35356d1c0d9SMicky Ching 35456d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr); 35556d1c0d9SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 35656d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt); 35756d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 35856d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 35956d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 36056d1c0d9SMicky Ching if (trans_mode != SD_TM_AUTO_TUNING) 36156d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 36256d1c0d9SMicky Ching CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 36356d1c0d9SMicky Ching 36456d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 36556d1c0d9SMicky Ching 0xFF, trans_mode | SD_TRANSFER_START); 36656d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 36756d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 36856d1c0d9SMicky Ching 36956d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 37056d1c0d9SMicky Ching if (err < 0) { 37156d1c0d9SMicky Ching sd_print_debug_regs(host); 37256d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 37356d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err); 37456d1c0d9SMicky Ching return err; 37556d1c0d9SMicky Ching } 37656d1c0d9SMicky Ching 37756d1c0d9SMicky Ching if (buf && buf_len) { 37856d1c0d9SMicky Ching err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 37956d1c0d9SMicky Ching if (err < 0) { 38056d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 38156d1c0d9SMicky Ching "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 38256d1c0d9SMicky Ching return err; 38356d1c0d9SMicky Ching } 38456d1c0d9SMicky Ching } 38556d1c0d9SMicky Ching 38656d1c0d9SMicky Ching return 0; 38756d1c0d9SMicky Ching } 38856d1c0d9SMicky Ching 38956d1c0d9SMicky Ching static int sd_write_data(struct realtek_pci_sdmmc *host, 39056d1c0d9SMicky Ching struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len, 39156d1c0d9SMicky Ching int timeout) 39256d1c0d9SMicky Ching { 39356d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr; 39456d1c0d9SMicky Ching int err; 39556d1c0d9SMicky Ching 39656d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 39756d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg); 39856d1c0d9SMicky Ching 39956d1c0d9SMicky Ching if (!buf) 40056d1c0d9SMicky Ching buf_len = 0; 40156d1c0d9SMicky Ching 40256d1c0d9SMicky Ching sd_send_cmd_get_rsp(host, cmd); 40356d1c0d9SMicky Ching if (cmd->error) 40456d1c0d9SMicky Ching return cmd->error; 40556d1c0d9SMicky Ching 40656d1c0d9SMicky Ching if (buf && buf_len) { 40756d1c0d9SMicky Ching err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 40856d1c0d9SMicky Ching if (err < 0) { 40956d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 41056d1c0d9SMicky Ching "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 41156d1c0d9SMicky Ching return err; 41256d1c0d9SMicky Ching } 41356d1c0d9SMicky Ching } 41456d1c0d9SMicky Ching 41556d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr); 41656d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt); 41756d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 41856d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 41956d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0); 42056d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 42156d1c0d9SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 42256d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 42356d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 42456d1c0d9SMicky Ching 42556d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 42656d1c0d9SMicky Ching if (err < 0) { 42756d1c0d9SMicky Ching sd_print_debug_regs(host); 42856d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 42956d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err); 43056d1c0d9SMicky Ching return err; 43156d1c0d9SMicky Ching } 43256d1c0d9SMicky Ching 43356d1c0d9SMicky Ching return 0; 43456d1c0d9SMicky Ching } 43556d1c0d9SMicky Ching 4361dcb3579SMicky Ching static int sd_read_long_data(struct realtek_pci_sdmmc *host, 4371dcb3579SMicky Ching struct mmc_request *mrq) 438ff984e57SWei WANG { 439ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 440ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 441ff984e57SWei WANG struct mmc_card *card = mmc->card; 4421dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd; 443ff984e57SWei WANG struct mmc_data *data = mrq->data; 44471ef1ea4SJackey Shen int uhs = mmc_card_uhs(card); 4451dcb3579SMicky Ching u8 cfg2 = 0; 446ff984e57SWei WANG int err; 4471dcb3579SMicky Ching int resp_type; 448ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 449ff984e57SWei WANG 4501dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 4511dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg); 4521dcb3579SMicky Ching 4531dcb3579SMicky Ching resp_type = sd_response_type(cmd); 4541dcb3579SMicky Ching if (resp_type < 0) 4551dcb3579SMicky Ching return resp_type; 456ff984e57SWei WANG 457ff984e57SWei WANG if (!uhs) 458ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 459ff984e57SWei WANG 460ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 4611dcb3579SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 4621dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 463ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 464ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 465ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 466ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 467ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 468ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 469ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 470ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 471ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 472ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 473ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 474ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 4751dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 4761dcb3579SMicky Ching 0x01, RING_BUFFER); 4771dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); 4781dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 4791dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_READ_2); 4801dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 4811dcb3579SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 4821dcb3579SMicky Ching rtsx_pci_send_cmd_no_wait(pcr); 4831dcb3579SMicky Ching 4841dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000); 4851dcb3579SMicky Ching if (err < 0) { 4861dcb3579SMicky Ching sd_print_debug_regs(host); 4871dcb3579SMicky Ching sd_clear_error(host); 4881dcb3579SMicky Ching return err; 4891dcb3579SMicky Ching } 4901dcb3579SMicky Ching 4911dcb3579SMicky Ching return 0; 4921dcb3579SMicky Ching } 4931dcb3579SMicky Ching 4941dcb3579SMicky Ching static int sd_write_long_data(struct realtek_pci_sdmmc *host, 4951dcb3579SMicky Ching struct mmc_request *mrq) 4961dcb3579SMicky Ching { 4971dcb3579SMicky Ching struct rtsx_pcr *pcr = host->pcr; 4981dcb3579SMicky Ching struct mmc_host *mmc = host->mmc; 4991dcb3579SMicky Ching struct mmc_card *card = mmc->card; 5001dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd; 5011dcb3579SMicky Ching struct mmc_data *data = mrq->data; 5021dcb3579SMicky Ching int uhs = mmc_card_uhs(card); 5031dcb3579SMicky Ching u8 cfg2; 5041dcb3579SMicky Ching int err; 5051dcb3579SMicky Ching size_t data_len = data->blksz * data->blocks; 5061dcb3579SMicky Ching 5071dcb3579SMicky Ching sd_send_cmd_get_rsp(host, cmd); 5081dcb3579SMicky Ching if (cmd->error) 5091dcb3579SMicky Ching return cmd->error; 5101dcb3579SMicky Ching 5111dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 5121dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg); 5131dcb3579SMicky Ching 5141dcb3579SMicky Ching cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 5151dcb3579SMicky Ching SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 5161dcb3579SMicky Ching 5171dcb3579SMicky Ching if (!uhs) 5181dcb3579SMicky Ching cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 5191dcb3579SMicky Ching 5201dcb3579SMicky Ching rtsx_pci_init_cmd(pcr); 5211dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 5221dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 5231dcb3579SMicky Ching DMA_DONE_INT, DMA_DONE_INT); 5241dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 5251dcb3579SMicky Ching 0xFF, (u8)(data_len >> 24)); 5261dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 5271dcb3579SMicky Ching 0xFF, (u8)(data_len >> 16)); 5281dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 5291dcb3579SMicky Ching 0xFF, (u8)(data_len >> 8)); 5301dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 531ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 532ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 533ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 534ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 535ff984e57SWei WANG 0x01, RING_BUFFER); 53638d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 537ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 5381dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 539ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 540ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 541ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 5421dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000); 543ff984e57SWei WANG if (err < 0) { 54498fcc576SMicky Ching sd_clear_error(host); 54598fcc576SMicky Ching return err; 546c42deffdSMicky Ching } 54798fcc576SMicky Ching 548c42deffdSMicky Ching return 0; 549ff984e57SWei WANG } 550ff984e57SWei WANG 5511dcb3579SMicky Ching static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 5521dcb3579SMicky Ching { 5531dcb3579SMicky Ching struct mmc_data *data = mrq->data; 5541dcb3579SMicky Ching 5551dcb3579SMicky Ching if (data->flags & MMC_DATA_READ) 5561dcb3579SMicky Ching return sd_read_long_data(host, mrq); 5571dcb3579SMicky Ching 5581dcb3579SMicky Ching return sd_write_long_data(host, mrq); 5591dcb3579SMicky Ching } 5601dcb3579SMicky Ching 561ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 562ff984e57SWei WANG { 563ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 564ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 565ff984e57SWei WANG } 566ff984e57SWei WANG 567ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 568ff984e57SWei WANG { 569ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 570ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 571ff984e57SWei WANG } 572ff984e57SWei WANG 573ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 574ff984e57SWei WANG struct mmc_request *mrq) 575ff984e57SWei WANG { 576ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 577ff984e57SWei WANG struct mmc_data *data = mrq->data; 5781dcb3579SMicky Ching u8 *buf; 579ff984e57SWei WANG 580ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 581ff984e57SWei WANG if (!buf) { 582ff984e57SWei WANG cmd->error = -ENOMEM; 583ff984e57SWei WANG return; 584ff984e57SWei WANG } 585ff984e57SWei WANG 586ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 587ff984e57SWei WANG if (host->initial_mode) 588ff984e57SWei WANG sd_disable_initial_mode(host); 589ff984e57SWei WANG 5901dcb3579SMicky Ching cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf, 591ff984e57SWei WANG data->blksz, 200); 592ff984e57SWei WANG 593ff984e57SWei WANG if (host->initial_mode) 594ff984e57SWei WANG sd_enable_initial_mode(host); 595ff984e57SWei WANG 596ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 597ff984e57SWei WANG } else { 598ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 599ff984e57SWei WANG 6001dcb3579SMicky Ching cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf, 601ff984e57SWei WANG data->blksz, 200); 602ff984e57SWei WANG } 603ff984e57SWei WANG 604ff984e57SWei WANG kfree(buf); 605ff984e57SWei WANG } 606ff984e57SWei WANG 60784d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, 60884d72f9cSWei WANG u8 sample_point, bool rx) 609ff984e57SWei WANG { 610ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 611ff984e57SWei WANG int err; 612ff984e57SWei WANG 61384d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 61484d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point); 615ff984e57SWei WANG 616ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 617ff984e57SWei WANG 618ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 61984d72f9cSWei WANG if (rx) 62084d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 62184d72f9cSWei WANG SD_VPRX_CTL, 0x1F, sample_point); 62284d72f9cSWei WANG else 62384d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 62484d72f9cSWei WANG SD_VPTX_CTL, 0x1F, sample_point); 625ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); 626ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 627ff984e57SWei WANG PHASE_NOT_RESET, PHASE_NOT_RESET); 628ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); 629ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 630ff984e57SWei WANG 631ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 632ff984e57SWei WANG if (err < 0) 633ff984e57SWei WANG return err; 634ff984e57SWei WANG 635ff984e57SWei WANG return 0; 636ff984e57SWei WANG } 637ff984e57SWei WANG 638abcc6b29SMicky Ching static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 639abcc6b29SMicky Ching { 640abcc6b29SMicky Ching bit %= RTSX_PHASE_MAX; 641abcc6b29SMicky Ching return phase_map & (1 << bit); 642abcc6b29SMicky Ching } 643abcc6b29SMicky Ching 644abcc6b29SMicky Ching static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 645abcc6b29SMicky Ching { 646abcc6b29SMicky Ching int i; 647abcc6b29SMicky Ching 648abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 649abcc6b29SMicky Ching if (test_phase_bit(phase_map, start_bit + i) == 0) 650abcc6b29SMicky Ching return i; 651abcc6b29SMicky Ching } 652abcc6b29SMicky Ching return RTSX_PHASE_MAX; 653abcc6b29SMicky Ching } 654abcc6b29SMicky Ching 655ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 656ff984e57SWei WANG { 657abcc6b29SMicky Ching int start = 0, len = 0; 658abcc6b29SMicky Ching int start_final = 0, len_final = 0; 659ff984e57SWei WANG u8 final_phase = 0xFF; 660ff984e57SWei WANG 661abcc6b29SMicky Ching if (phase_map == 0) { 662abcc6b29SMicky Ching dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 663abcc6b29SMicky Ching return final_phase; 664ff984e57SWei WANG } 665ff984e57SWei WANG 666abcc6b29SMicky Ching while (start < RTSX_PHASE_MAX) { 667abcc6b29SMicky Ching len = sd_get_phase_len(phase_map, start); 668abcc6b29SMicky Ching if (len_final < len) { 669abcc6b29SMicky Ching start_final = start; 670abcc6b29SMicky Ching len_final = len; 671abcc6b29SMicky Ching } 672abcc6b29SMicky Ching start += len ? len : 1; 673ff984e57SWei WANG } 674ff984e57SWei WANG 675abcc6b29SMicky Ching final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 676abcc6b29SMicky Ching dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 677abcc6b29SMicky Ching phase_map, len_final, final_phase); 678ff984e57SWei WANG 679ff984e57SWei WANG return final_phase; 680ff984e57SWei WANG } 681ff984e57SWei WANG 682ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 683ff984e57SWei WANG { 684ff984e57SWei WANG int err, i; 685ff984e57SWei WANG u8 val = 0; 686ff984e57SWei WANG 687ff984e57SWei WANG for (i = 0; i < 100; i++) { 688ff984e57SWei WANG err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 689ff984e57SWei WANG if (val & SD_DATA_IDLE) 690ff984e57SWei WANG return; 691ff984e57SWei WANG 692ff984e57SWei WANG udelay(100); 693ff984e57SWei WANG } 694ff984e57SWei WANG } 695ff984e57SWei WANG 696ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 697ff984e57SWei WANG u8 opcode, u8 sample_point) 698ff984e57SWei WANG { 699ff984e57SWei WANG int err; 7001dcb3579SMicky Ching struct mmc_command cmd = {0}; 701ff984e57SWei WANG 70284d72f9cSWei WANG err = sd_change_phase(host, sample_point, true); 703ff984e57SWei WANG if (err < 0) 704ff984e57SWei WANG return err; 705ff984e57SWei WANG 7061dcb3579SMicky Ching cmd.opcode = opcode; 7071dcb3579SMicky Ching err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100); 708ff984e57SWei WANG if (err < 0) { 709ff984e57SWei WANG /* Wait till SD DATA IDLE */ 710ff984e57SWei WANG sd_wait_data_idle(host); 711ff984e57SWei WANG sd_clear_error(host); 712ff984e57SWei WANG return err; 713ff984e57SWei WANG } 714ff984e57SWei WANG 715ff984e57SWei WANG return 0; 716ff984e57SWei WANG } 717ff984e57SWei WANG 718ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 719ff984e57SWei WANG u8 opcode, u32 *phase_map) 720ff984e57SWei WANG { 721ff984e57SWei WANG int err, i; 722ff984e57SWei WANG u32 raw_phase_map = 0; 723ff984e57SWei WANG 724abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 725ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 726ff984e57SWei WANG if (err == 0) 727ff984e57SWei WANG raw_phase_map |= 1 << i; 728ff984e57SWei WANG } 729ff984e57SWei WANG 730ff984e57SWei WANG if (phase_map) 731ff984e57SWei WANG *phase_map = raw_phase_map; 732ff984e57SWei WANG 733ff984e57SWei WANG return 0; 734ff984e57SWei WANG } 735ff984e57SWei WANG 736ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 737ff984e57SWei WANG { 738ff984e57SWei WANG int err, i; 739ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 740ff984e57SWei WANG u8 final_phase; 741ff984e57SWei WANG 742ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 743ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 744ff984e57SWei WANG if (err < 0) 745ff984e57SWei WANG return err; 746ff984e57SWei WANG 747ff984e57SWei WANG if (raw_phase_map[i] == 0) 748ff984e57SWei WANG break; 749ff984e57SWei WANG } 750ff984e57SWei WANG 751ff984e57SWei WANG phase_map = 0xFFFFFFFF; 752ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 753ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 754ff984e57SWei WANG i, raw_phase_map[i]); 755ff984e57SWei WANG phase_map &= raw_phase_map[i]; 756ff984e57SWei WANG } 757ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 758ff984e57SWei WANG 759ff984e57SWei WANG if (phase_map) { 760ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 761ff984e57SWei WANG if (final_phase == 0xFF) 762ff984e57SWei WANG return -EINVAL; 763ff984e57SWei WANG 76484d72f9cSWei WANG err = sd_change_phase(host, final_phase, true); 765ff984e57SWei WANG if (err < 0) 766ff984e57SWei WANG return err; 767ff984e57SWei WANG } else { 768ff984e57SWei WANG return -EINVAL; 769ff984e57SWei WANG } 770ff984e57SWei WANG 771ff984e57SWei WANG return 0; 772ff984e57SWei WANG } 773ff984e57SWei WANG 7741dcb3579SMicky Ching static inline int sdio_extblock_cmd(struct mmc_command *cmd, 7751dcb3579SMicky Ching struct mmc_data *data) 7761dcb3579SMicky Ching { 7771dcb3579SMicky Ching return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512); 7781dcb3579SMicky Ching } 7791dcb3579SMicky Ching 7806291e715SMicky Ching static inline int sd_rw_cmd(struct mmc_command *cmd) 781ff984e57SWei WANG { 7826291e715SMicky Ching return mmc_op_multi(cmd->opcode) || 7836291e715SMicky Ching (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 7846291e715SMicky Ching (cmd->opcode == MMC_WRITE_BLOCK); 7856291e715SMicky Ching } 7866291e715SMicky Ching 7876291e715SMicky Ching static void sd_request(struct work_struct *work) 7886291e715SMicky Ching { 7896291e715SMicky Ching struct realtek_pci_sdmmc *host = container_of(work, 7906291e715SMicky Ching struct realtek_pci_sdmmc, work); 791ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 7926291e715SMicky Ching 7936291e715SMicky Ching struct mmc_host *mmc = host->mmc; 7946291e715SMicky Ching struct mmc_request *mrq = host->mrq; 795ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 796ff984e57SWei WANG struct mmc_data *data = mrq->data; 7976291e715SMicky Ching 798ff984e57SWei WANG unsigned int data_size = 0; 799c3481955SWei WANG int err; 800ff984e57SWei WANG 801ff984e57SWei WANG if (host->eject) { 802ff984e57SWei WANG cmd->error = -ENOMEDIUM; 803ff984e57SWei WANG goto finish; 804ff984e57SWei WANG } 805ff984e57SWei WANG 806c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 807c3481955SWei WANG if (err) { 808c3481955SWei WANG cmd->error = err; 809c3481955SWei WANG goto finish; 810c3481955SWei WANG } 811c3481955SWei WANG 81298fcc576SMicky Ching mutex_lock(&pcr->pcr_mutex); 81398fcc576SMicky Ching 814ff984e57SWei WANG rtsx_pci_start_run(pcr); 815ff984e57SWei WANG 816ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 817ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 818ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 819ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 820ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 821ff984e57SWei WANG 82298fcc576SMicky Ching mutex_lock(&host->host_mutex); 82398fcc576SMicky Ching host->mrq = mrq; 82498fcc576SMicky Ching mutex_unlock(&host->host_mutex); 82598fcc576SMicky Ching 826ff984e57SWei WANG if (mrq->data) 827ff984e57SWei WANG data_size = data->blocks * data->blksz; 828ff984e57SWei WANG 8291dcb3579SMicky Ching if (!data_size) { 83098fcc576SMicky Ching sd_send_cmd_get_rsp(host, cmd); 8311dcb3579SMicky Ching } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) { 8321dcb3579SMicky Ching cmd->error = sd_rw_multi(host, mrq); 8336291e715SMicky Ching if (!host->using_cookie) 8346291e715SMicky Ching sdmmc_post_req(host->mmc, host->mrq, 0); 83598fcc576SMicky Ching 83698fcc576SMicky Ching if (mmc_op_multi(cmd->opcode) && mrq->stop) 83798fcc576SMicky Ching sd_send_cmd_get_rsp(host, mrq->stop); 83898fcc576SMicky Ching } else { 83998fcc576SMicky Ching sd_normal_rw(host, mrq); 84098fcc576SMicky Ching } 84198fcc576SMicky Ching 84298fcc576SMicky Ching if (mrq->data) { 84398fcc576SMicky Ching if (cmd->error || data->error) 84498fcc576SMicky Ching data->bytes_xfered = 0; 84598fcc576SMicky Ching else 84698fcc576SMicky Ching data->bytes_xfered = data->blocks * data->blksz; 84798fcc576SMicky Ching } 84898fcc576SMicky Ching 84998fcc576SMicky Ching mutex_unlock(&pcr->pcr_mutex); 850ff984e57SWei WANG 851ff984e57SWei WANG finish: 8521dcb3579SMicky Ching if (cmd->error) { 8531dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n", 8541dcb3579SMicky Ching cmd->opcode, cmd->arg, cmd->error); 8551dcb3579SMicky Ching } 85698fcc576SMicky Ching 85798fcc576SMicky Ching mutex_lock(&host->host_mutex); 85898fcc576SMicky Ching host->mrq = NULL; 85998fcc576SMicky Ching mutex_unlock(&host->host_mutex); 86098fcc576SMicky Ching 86198fcc576SMicky Ching mmc_request_done(mmc, mrq); 862ff984e57SWei WANG } 863ff984e57SWei WANG 8646291e715SMicky Ching static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 8656291e715SMicky Ching { 8666291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 8676291e715SMicky Ching struct mmc_data *data = mrq->data; 8686291e715SMicky Ching 8696291e715SMicky Ching mutex_lock(&host->host_mutex); 8706291e715SMicky Ching host->mrq = mrq; 8716291e715SMicky Ching mutex_unlock(&host->host_mutex); 8726291e715SMicky Ching 8731dcb3579SMicky Ching if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data)) 8746291e715SMicky Ching host->using_cookie = sd_pre_dma_transfer(host, data, false); 8756291e715SMicky Ching 8766291e715SMicky Ching queue_work(host->workq, &host->work); 8776291e715SMicky Ching } 8786291e715SMicky Ching 879ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 880ff984e57SWei WANG unsigned char bus_width) 881ff984e57SWei WANG { 882ff984e57SWei WANG int err = 0; 883ff984e57SWei WANG u8 width[] = { 884ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 885ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 886ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 887ff984e57SWei WANG }; 888ff984e57SWei WANG 889ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 890ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 891ff984e57SWei WANG 0x03, width[bus_width]); 892ff984e57SWei WANG 893ff984e57SWei WANG return err; 894ff984e57SWei WANG } 895ff984e57SWei WANG 896ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 897ff984e57SWei WANG { 898ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 899ff984e57SWei WANG int err; 900ff984e57SWei WANG 901d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 902d88691beSWei WANG return 0; 903d88691beSWei WANG 904ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 905ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 906ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 907ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 908ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 909ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 910ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 911ff984e57SWei WANG if (err < 0) 912ff984e57SWei WANG return err; 913ff984e57SWei WANG 914ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 915ff984e57SWei WANG if (err < 0) 916ff984e57SWei WANG return err; 917ff984e57SWei WANG 918ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 919ff984e57SWei WANG if (err < 0) 920ff984e57SWei WANG return err; 921ff984e57SWei WANG 922ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 923ff984e57SWei WANG if (err < 0) 924ff984e57SWei WANG return err; 925ff984e57SWei WANG 926d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 927ff984e57SWei WANG return 0; 928ff984e57SWei WANG } 929ff984e57SWei WANG 930ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 931ff984e57SWei WANG { 932ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 933ff984e57SWei WANG int err; 934ff984e57SWei WANG 935d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 936d88691beSWei WANG 937ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 938ff984e57SWei WANG 939ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 940ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 941ff984e57SWei WANG 942ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 943ff984e57SWei WANG if (err < 0) 944ff984e57SWei WANG return err; 945ff984e57SWei WANG 946ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 947ff984e57SWei WANG if (err < 0) 948ff984e57SWei WANG return err; 949ff984e57SWei WANG 950ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 951ff984e57SWei WANG } 952ff984e57SWei WANG 953ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 954ff984e57SWei WANG unsigned char power_mode) 955ff984e57SWei WANG { 956ff984e57SWei WANG int err; 957ff984e57SWei WANG 958ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 959ff984e57SWei WANG err = sd_power_off(host); 960ff984e57SWei WANG else 961ff984e57SWei WANG err = sd_power_on(host); 962ff984e57SWei WANG 963ff984e57SWei WANG return err; 964ff984e57SWei WANG } 965ff984e57SWei WANG 96684d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 967ff984e57SWei WANG { 968ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 969ff984e57SWei WANG int err = 0; 970ff984e57SWei WANG 971ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 972ff984e57SWei WANG 973ff984e57SWei WANG switch (timing) { 974ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 975ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 976ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 977ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 978ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 979ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 980ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 981ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 982ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 983ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 984ff984e57SWei WANG break; 985ff984e57SWei WANG 9861a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 987ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 988ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 989ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 990ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 991ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 992ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 993ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 994ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 995ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 996ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 997ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 998ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 999ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 1000ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 1001ff984e57SWei WANG break; 1002ff984e57SWei WANG 1003ff984e57SWei WANG case MMC_TIMING_MMC_HS: 1004ff984e57SWei WANG case MMC_TIMING_SD_HS: 1005ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1006ff984e57SWei WANG 0x0C, SD_20_MODE); 1007ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1008ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1009ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1010ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1011ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1012ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1013ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 1014ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1015ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 1016ff984e57SWei WANG break; 1017ff984e57SWei WANG 1018ff984e57SWei WANG default: 1019ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1020ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 1021ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1022ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1023ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1024ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1025ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1026ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1027ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 1028ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1029ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 1030ff984e57SWei WANG break; 1031ff984e57SWei WANG } 1032ff984e57SWei WANG 1033ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 1034ff984e57SWei WANG 1035ff984e57SWei WANG return err; 1036ff984e57SWei WANG } 1037ff984e57SWei WANG 1038ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1039ff984e57SWei WANG { 1040ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1041ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1042ff984e57SWei WANG 1043ff984e57SWei WANG if (host->eject) 1044ff984e57SWei WANG return; 1045ff984e57SWei WANG 1046c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 1047c3481955SWei WANG return; 1048c3481955SWei WANG 1049ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1050ff984e57SWei WANG 1051ff984e57SWei WANG rtsx_pci_start_run(pcr); 1052ff984e57SWei WANG 1053ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 1054ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 105584d72f9cSWei WANG sd_set_timing(host, ios->timing); 1056ff984e57SWei WANG 1057ff984e57SWei WANG host->vpclk = false; 1058ff984e57SWei WANG host->double_clk = true; 1059ff984e57SWei WANG 1060ff984e57SWei WANG switch (ios->timing) { 1061ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1062ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1063ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 1064ff984e57SWei WANG host->vpclk = true; 1065ff984e57SWei WANG host->double_clk = false; 1066ff984e57SWei WANG break; 10671a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 1068ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1069ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 1070ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 1071ff984e57SWei WANG break; 1072ff984e57SWei WANG default: 1073ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 1074ff984e57SWei WANG break; 1075ff984e57SWei WANG } 1076ff984e57SWei WANG 1077ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 1078ff984e57SWei WANG 1079ff984e57SWei WANG host->clock = ios->clock; 1080ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 1081ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 1082ff984e57SWei WANG 1083ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1084ff984e57SWei WANG } 1085ff984e57SWei WANG 1086ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 1087ff984e57SWei WANG { 1088ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1089ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1090ff984e57SWei WANG int ro = 0; 1091ff984e57SWei WANG u32 val; 1092ff984e57SWei WANG 1093ff984e57SWei WANG if (host->eject) 1094ff984e57SWei WANG return -ENOMEDIUM; 1095ff984e57SWei WANG 1096ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1097ff984e57SWei WANG 1098ff984e57SWei WANG rtsx_pci_start_run(pcr); 1099ff984e57SWei WANG 1100ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 1101ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 1102ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1103ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 1104ff984e57SWei WANG ro = 1; 1105ff984e57SWei WANG 1106ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1107ff984e57SWei WANG 1108ff984e57SWei WANG return ro; 1109ff984e57SWei WANG } 1110ff984e57SWei WANG 1111ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 1112ff984e57SWei WANG { 1113ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1114ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1115ff984e57SWei WANG int cd = 0; 1116ff984e57SWei WANG u32 val; 1117ff984e57SWei WANG 1118ff984e57SWei WANG if (host->eject) 1119ff984e57SWei WANG return -ENOMEDIUM; 1120ff984e57SWei WANG 1121ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1122ff984e57SWei WANG 1123ff984e57SWei WANG rtsx_pci_start_run(pcr); 1124ff984e57SWei WANG 1125ff984e57SWei WANG /* Check SD card detect */ 1126ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 1127ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1128ff984e57SWei WANG if (val & SD_EXIST) 1129ff984e57SWei WANG cd = 1; 1130ff984e57SWei WANG 1131ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1132ff984e57SWei WANG 1133ff984e57SWei WANG return cd; 1134ff984e57SWei WANG } 1135ff984e57SWei WANG 1136ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1137ff984e57SWei WANG { 1138ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1139ff984e57SWei WANG int err; 1140ff984e57SWei WANG u8 stat; 1141ff984e57SWei WANG 1142ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 1143ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 1144ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 1145ff984e57SWei WANG */ 1146ff984e57SWei WANG mdelay(1); 1147ff984e57SWei WANG 1148ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1149ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 1150ff984e57SWei WANG * abort the voltage switch sequence; 1151ff984e57SWei WANG */ 1152ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1153ff984e57SWei WANG if (err < 0) 1154ff984e57SWei WANG return err; 1155ff984e57SWei WANG 1156ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1157ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 1158ff984e57SWei WANG return -EINVAL; 1159ff984e57SWei WANG 1160ff984e57SWei WANG /* Stop toggle SD clock */ 1161ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1162ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 1163ff984e57SWei WANG if (err < 0) 1164ff984e57SWei WANG return err; 1165ff984e57SWei WANG 1166ff984e57SWei WANG return 0; 1167ff984e57SWei WANG } 1168ff984e57SWei WANG 1169ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1170ff984e57SWei WANG { 1171ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1172ff984e57SWei WANG int err; 1173ff984e57SWei WANG u8 stat, mask, val; 1174ff984e57SWei WANG 1175ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1176ff984e57SWei WANG msleep(50); 1177ff984e57SWei WANG 1178ff984e57SWei WANG /* Toggle SD clock again */ 1179ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1180ff984e57SWei WANG if (err < 0) 1181ff984e57SWei WANG return err; 1182ff984e57SWei WANG 1183ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1184ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1185ff984e57SWei WANG */ 1186ff984e57SWei WANG msleep(20); 1187ff984e57SWei WANG 1188ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1189ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1190ff984e57SWei WANG if (err < 0) 1191ff984e57SWei WANG return err; 1192ff984e57SWei WANG 1193ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1194ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1195ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1196ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1197ff984e57SWei WANG if ((stat & mask) != val) { 1198ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1199ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1200ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1201ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1202ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1203ff984e57SWei WANG return -EINVAL; 1204ff984e57SWei WANG } 1205ff984e57SWei WANG 1206ff984e57SWei WANG return 0; 1207ff984e57SWei WANG } 1208ff984e57SWei WANG 1209ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1210ff984e57SWei WANG { 1211ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1212ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1213ff984e57SWei WANG int err = 0; 1214ff984e57SWei WANG u8 voltage; 1215ff984e57SWei WANG 1216ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1217ff984e57SWei WANG __func__, ios->signal_voltage); 1218ff984e57SWei WANG 1219ff984e57SWei WANG if (host->eject) 1220ff984e57SWei WANG return -ENOMEDIUM; 1221ff984e57SWei WANG 1222c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1223c3481955SWei WANG if (err) 1224c3481955SWei WANG return err; 1225c3481955SWei WANG 1226ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1227ff984e57SWei WANG 1228ff984e57SWei WANG rtsx_pci_start_run(pcr); 1229ff984e57SWei WANG 1230ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1231ef85e736SWei WANG voltage = OUTPUT_3V3; 1232ff984e57SWei WANG else 1233ef85e736SWei WANG voltage = OUTPUT_1V8; 1234ff984e57SWei WANG 1235ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1236ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1237ff984e57SWei WANG if (err < 0) 1238ff984e57SWei WANG goto out; 1239ff984e57SWei WANG } 1240ff984e57SWei WANG 1241ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1242ff984e57SWei WANG if (err < 0) 1243ff984e57SWei WANG goto out; 1244ff984e57SWei WANG 1245ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1246ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1247ff984e57SWei WANG if (err < 0) 1248ff984e57SWei WANG goto out; 1249ff984e57SWei WANG } 1250ff984e57SWei WANG 12511b8055b4SWei WANG out: 1252ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1253ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1254ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1255ff984e57SWei WANG 1256ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1257ff984e57SWei WANG 1258ff984e57SWei WANG return err; 1259ff984e57SWei WANG } 1260ff984e57SWei WANG 1261ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1262ff984e57SWei WANG { 1263ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1264ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1265ff984e57SWei WANG int err = 0; 1266ff984e57SWei WANG 1267ff984e57SWei WANG if (host->eject) 1268ff984e57SWei WANG return -ENOMEDIUM; 1269ff984e57SWei WANG 1270c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1271c3481955SWei WANG if (err) 1272c3481955SWei WANG return err; 1273c3481955SWei WANG 1274ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1275ff984e57SWei WANG 1276ff984e57SWei WANG rtsx_pci_start_run(pcr); 1277ff984e57SWei WANG 127884d72f9cSWei WANG /* Set initial TX phase */ 127984d72f9cSWei WANG switch (mmc->ios.timing) { 128084d72f9cSWei WANG case MMC_TIMING_UHS_SDR104: 128184d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 128284d72f9cSWei WANG break; 1283ff984e57SWei WANG 128484d72f9cSWei WANG case MMC_TIMING_UHS_SDR50: 128584d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 128684d72f9cSWei WANG break; 128784d72f9cSWei WANG 128884d72f9cSWei WANG case MMC_TIMING_UHS_DDR50: 128984d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 129084d72f9cSWei WANG break; 129184d72f9cSWei WANG 129284d72f9cSWei WANG default: 129384d72f9cSWei WANG err = 0; 129484d72f9cSWei WANG } 129584d72f9cSWei WANG 129684d72f9cSWei WANG if (err) 129784d72f9cSWei WANG goto out; 129884d72f9cSWei WANG 129984d72f9cSWei WANG /* Tuning RX phase */ 130084d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 130184d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 130284d72f9cSWei WANG err = sd_tuning_rx(host, opcode); 130384d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 130484d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 130584d72f9cSWei WANG 130684d72f9cSWei WANG out: 1307ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1308ff984e57SWei WANG 1309ff984e57SWei WANG return err; 1310ff984e57SWei WANG } 1311ff984e57SWei WANG 1312ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 13136291e715SMicky Ching .pre_req = sdmmc_pre_req, 13146291e715SMicky Ching .post_req = sdmmc_post_req, 1315ff984e57SWei WANG .request = sdmmc_request, 1316ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1317ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1318ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1319ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1320ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 1321ff984e57SWei WANG }; 1322ff984e57SWei WANG 1323ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1324ff984e57SWei WANG { 1325ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1326ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1327ff984e57SWei WANG 1328ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1329ff984e57SWei WANG 1330ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1331ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1332ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1333ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1334ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1335ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1336ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1337ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1338ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1339ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1340ff984e57SWei WANG } 1341ff984e57SWei WANG 1342ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1343ff984e57SWei WANG { 1344ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1345ff984e57SWei WANG 1346ff984e57SWei WANG mmc->f_min = 250000; 1347ff984e57SWei WANG mmc->f_max = 208000000; 1348ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1349ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1350ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1351ff984e57SWei WANG MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1352517bf80fSRoger Tseng mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE; 1353ff984e57SWei WANG mmc->max_current_330 = 400; 1354ff984e57SWei WANG mmc->max_current_180 = 800; 1355ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1356ff984e57SWei WANG 1357ff984e57SWei WANG init_extra_caps(host); 1358ff984e57SWei WANG 1359ff984e57SWei WANG mmc->max_segs = 256; 1360ff984e57SWei WANG mmc->max_seg_size = 65536; 1361ff984e57SWei WANG mmc->max_blk_size = 512; 1362ff984e57SWei WANG mmc->max_blk_count = 65535; 1363ff984e57SWei WANG mmc->max_req_size = 524288; 1364ff984e57SWei WANG } 1365ff984e57SWei WANG 1366ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1367ff984e57SWei WANG { 1368ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1369ff984e57SWei WANG 13702057647fSMicky Ching host->cookie = -1; 1371ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1372ff984e57SWei WANG } 1373ff984e57SWei WANG 1374ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1375ff984e57SWei WANG { 1376ff984e57SWei WANG struct mmc_host *mmc; 1377ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1378ff984e57SWei WANG struct rtsx_pcr *pcr; 1379ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1380ff984e57SWei WANG 1381ff984e57SWei WANG if (!handle) 1382ff984e57SWei WANG return -ENXIO; 1383ff984e57SWei WANG 1384ff984e57SWei WANG pcr = handle->pcr; 1385ff984e57SWei WANG if (!pcr) 1386ff984e57SWei WANG return -ENXIO; 1387ff984e57SWei WANG 1388ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1389ff984e57SWei WANG 1390ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1391ff984e57SWei WANG if (!mmc) 1392ff984e57SWei WANG return -ENOMEM; 1393ff984e57SWei WANG 1394ff984e57SWei WANG host = mmc_priv(mmc); 13956291e715SMicky Ching host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME); 13966291e715SMicky Ching if (!host->workq) { 13976291e715SMicky Ching mmc_free_host(mmc); 13986291e715SMicky Ching return -ENOMEM; 13996291e715SMicky Ching } 1400ff984e57SWei WANG host->pcr = pcr; 1401ff984e57SWei WANG host->mmc = mmc; 1402ff984e57SWei WANG host->pdev = pdev; 14032057647fSMicky Ching host->cookie = -1; 1404d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 14056291e715SMicky Ching INIT_WORK(&host->work, sd_request); 1406ff984e57SWei WANG platform_set_drvdata(pdev, host); 1407ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1408ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1409ff984e57SWei WANG 141098fcc576SMicky Ching mutex_init(&host->host_mutex); 1411ff984e57SWei WANG 1412ff984e57SWei WANG realtek_init_host(host); 1413ff984e57SWei WANG 1414ff984e57SWei WANG mmc_add_host(mmc); 1415ff984e57SWei WANG 1416ff984e57SWei WANG return 0; 1417ff984e57SWei WANG } 1418ff984e57SWei WANG 1419ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1420ff984e57SWei WANG { 1421ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1422ff984e57SWei WANG struct rtsx_pcr *pcr; 1423ff984e57SWei WANG struct mmc_host *mmc; 1424ff984e57SWei WANG 1425ff984e57SWei WANG if (!host) 1426ff984e57SWei WANG return 0; 1427ff984e57SWei WANG 1428ff984e57SWei WANG pcr = host->pcr; 1429ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1430ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1431ff984e57SWei WANG mmc = host->mmc; 1432ff984e57SWei WANG 14336291e715SMicky Ching cancel_work_sync(&host->work); 14346291e715SMicky Ching 143598fcc576SMicky Ching mutex_lock(&host->host_mutex); 1436ff984e57SWei WANG if (host->mrq) { 1437ff984e57SWei WANG dev_dbg(&(pdev->dev), 1438ff984e57SWei WANG "%s: Controller removed during transfer\n", 1439ff984e57SWei WANG mmc_hostname(mmc)); 1440ff984e57SWei WANG 144198fcc576SMicky Ching rtsx_pci_complete_unfinished_transfer(pcr); 1442ff984e57SWei WANG 144398fcc576SMicky Ching host->mrq->cmd->error = -ENOMEDIUM; 144498fcc576SMicky Ching if (host->mrq->stop) 144598fcc576SMicky Ching host->mrq->stop->error = -ENOMEDIUM; 144698fcc576SMicky Ching mmc_request_done(mmc, host->mrq); 1447ff984e57SWei WANG } 144898fcc576SMicky Ching mutex_unlock(&host->host_mutex); 1449ff984e57SWei WANG 1450ff984e57SWei WANG mmc_remove_host(mmc); 1451640e09bcSMicky Ching host->eject = true; 1452640e09bcSMicky Ching 14536291e715SMicky Ching flush_workqueue(host->workq); 14546291e715SMicky Ching destroy_workqueue(host->workq); 14556291e715SMicky Ching host->workq = NULL; 14566291e715SMicky Ching 1457ff984e57SWei WANG mmc_free_host(mmc); 1458ff984e57SWei WANG 1459ff984e57SWei WANG dev_dbg(&(pdev->dev), 1460ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1461ff984e57SWei WANG 1462ff984e57SWei WANG return 0; 1463ff984e57SWei WANG } 1464ff984e57SWei WANG 1465ff984e57SWei WANG static struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1466ff984e57SWei WANG { 1467ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1468ff984e57SWei WANG }, { 1469ff984e57SWei WANG /* sentinel */ 1470ff984e57SWei WANG } 1471ff984e57SWei WANG }; 1472ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1473ff984e57SWei WANG 1474ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1475ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1476ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1477ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1478ff984e57SWei WANG .driver = { 1479ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1480ff984e57SWei WANG }, 1481ff984e57SWei WANG }; 1482ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1483ff984e57SWei WANG 1484ff984e57SWei WANG MODULE_LICENSE("GPL"); 1485ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1486ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1487