1aaf4989bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 3ff984e57SWei WANG * 462282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5ff984e57SWei WANG * 6ff984e57SWei WANG * Author: 7ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 8ff984e57SWei WANG */ 9ff984e57SWei WANG 10ff984e57SWei WANG #include <linux/module.h> 11433e075cSWei WANG #include <linux/slab.h> 12ff984e57SWei WANG #include <linux/highmem.h> 13ff984e57SWei WANG #include <linux/delay.h> 14ff984e57SWei WANG #include <linux/platform_device.h> 156291e715SMicky Ching #include <linux/workqueue.h> 16ff984e57SWei WANG #include <linux/mmc/host.h> 17ff984e57SWei WANG #include <linux/mmc/mmc.h> 18ff984e57SWei WANG #include <linux/mmc/sd.h> 191dcb3579SMicky Ching #include <linux/mmc/sdio.h> 20ff984e57SWei WANG #include <linux/mmc/card.h> 21e455b69dSRui Feng #include <linux/rtsx_pci.h> 22ff984e57SWei WANG #include <asm/unaligned.h> 235b4258f6SRicky Wu #include <linux/pm_runtime.h> 24ff984e57SWei WANG 25ff984e57SWei WANG struct realtek_pci_sdmmc { 26ff984e57SWei WANG struct platform_device *pdev; 27ff984e57SWei WANG struct rtsx_pcr *pcr; 28ff984e57SWei WANG struct mmc_host *mmc; 29ff984e57SWei WANG struct mmc_request *mrq; 306291e715SMicky Ching #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" 31ff984e57SWei WANG 326291e715SMicky Ching struct work_struct work; 3398fcc576SMicky Ching struct mutex host_mutex; 34ff984e57SWei WANG 35ff984e57SWei WANG u8 ssc_depth; 36ff984e57SWei WANG unsigned int clock; 37ff984e57SWei WANG bool vpclk; 38ff984e57SWei WANG bool double_clk; 39ff984e57SWei WANG bool eject; 40ff984e57SWei WANG bool initial_mode; 41d88691beSWei WANG int power_state; 42d88691beSWei WANG #define SDMMC_POWER_ON 1 43d88691beSWei WANG #define SDMMC_POWER_OFF 0 446291e715SMicky Ching 45be186ad5SMicky Ching int sg_count; 466291e715SMicky Ching s32 cookie; 47be186ad5SMicky Ching int cookie_sg_count; 486291e715SMicky Ching bool using_cookie; 49ff984e57SWei WANG }; 50ff984e57SWei WANG 516b7b58f4SRui Feng static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios); 526b7b58f4SRui Feng 53ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 54ff984e57SWei WANG { 55ff984e57SWei WANG return &(host->pdev->dev); 56ff984e57SWei WANG } 57ff984e57SWei WANG 58ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 59ff984e57SWei WANG { 60ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 61ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 62ff984e57SWei WANG } 63ff984e57SWei WANG 64ff984e57SWei WANG #ifdef DEBUG 65755987f9SMicky Ching static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end) 66755987f9SMicky Ching { 67755987f9SMicky Ching u16 len = end - start + 1; 68755987f9SMicky Ching int i; 69755987f9SMicky Ching u8 data[8]; 70755987f9SMicky Ching 71755987f9SMicky Ching for (i = 0; i < len; i += 8) { 72755987f9SMicky Ching int j; 73755987f9SMicky Ching int n = min(8, len - i); 74755987f9SMicky Ching 75755987f9SMicky Ching memset(&data, 0, sizeof(data)); 76755987f9SMicky Ching for (j = 0; j < n; j++) 77755987f9SMicky Ching rtsx_pci_read_register(host->pcr, start + i + j, 78755987f9SMicky Ching data + j); 79755987f9SMicky Ching dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n", 80755987f9SMicky Ching start + i, n, data); 81755987f9SMicky Ching } 82755987f9SMicky Ching } 83755987f9SMicky Ching 84ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 85ff984e57SWei WANG { 86755987f9SMicky Ching dump_reg_range(host, 0xFDA0, 0xFDB3); 87755987f9SMicky Ching dump_reg_range(host, 0xFD52, 0xFD69); 88ff984e57SWei WANG } 89ff984e57SWei WANG #else 90ff984e57SWei WANG #define sd_print_debug_regs(host) 91ff984e57SWei WANG #endif /* DEBUG */ 92ff984e57SWei WANG 93b22217f9SMicky Ching static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host) 94b22217f9SMicky Ching { 95b22217f9SMicky Ching return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST; 96b22217f9SMicky Ching } 97b22217f9SMicky Ching 982d48e5f1SMicky Ching static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd) 992d48e5f1SMicky Ching { 1002d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 1012d48e5f1SMicky Ching SD_CMD_START | cmd->opcode); 1022d48e5f1SMicky Ching rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg); 1032d48e5f1SMicky Ching } 1042d48e5f1SMicky Ching 1052d48e5f1SMicky Ching static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz) 1062d48e5f1SMicky Ching { 1072d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); 1082d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); 1092d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); 1102d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); 1112d48e5f1SMicky Ching } 1122d48e5f1SMicky Ching 1132d48e5f1SMicky Ching static int sd_response_type(struct mmc_command *cmd) 1142d48e5f1SMicky Ching { 1152d48e5f1SMicky Ching switch (mmc_resp_type(cmd)) { 1162d48e5f1SMicky Ching case MMC_RSP_NONE: 1172d48e5f1SMicky Ching return SD_RSP_TYPE_R0; 1182d48e5f1SMicky Ching case MMC_RSP_R1: 1192d48e5f1SMicky Ching return SD_RSP_TYPE_R1; 1208c8d0ecbSWolfram Sang case MMC_RSP_R1_NO_CRC: 1212d48e5f1SMicky Ching return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; 1222d48e5f1SMicky Ching case MMC_RSP_R1B: 1232d48e5f1SMicky Ching return SD_RSP_TYPE_R1b; 1242d48e5f1SMicky Ching case MMC_RSP_R2: 1252d48e5f1SMicky Ching return SD_RSP_TYPE_R2; 1262d48e5f1SMicky Ching case MMC_RSP_R3: 1272d48e5f1SMicky Ching return SD_RSP_TYPE_R3; 1282d48e5f1SMicky Ching default: 1292d48e5f1SMicky Ching return -EINVAL; 1302d48e5f1SMicky Ching } 1312d48e5f1SMicky Ching } 1322d48e5f1SMicky Ching 1332d48e5f1SMicky Ching static int sd_status_index(int resp_type) 1342d48e5f1SMicky Ching { 1352d48e5f1SMicky Ching if (resp_type == SD_RSP_TYPE_R0) 1362d48e5f1SMicky Ching return 0; 1372d48e5f1SMicky Ching else if (resp_type == SD_RSP_TYPE_R2) 1382d48e5f1SMicky Ching return 16; 1392d48e5f1SMicky Ching 1402d48e5f1SMicky Ching return 5; 1412d48e5f1SMicky Ching } 1426291e715SMicky Ching /* 1436291e715SMicky Ching * sd_pre_dma_transfer - do dma_map_sg() or using cookie 1446291e715SMicky Ching * 1456291e715SMicky Ching * @pre: if called in pre_req() 1466291e715SMicky Ching * return: 1476291e715SMicky Ching * 0 - do dma_map_sg() 1486291e715SMicky Ching * 1 - using cookie 1496291e715SMicky Ching */ 1506291e715SMicky Ching static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, 1516291e715SMicky Ching struct mmc_data *data, bool pre) 1526291e715SMicky Ching { 1536291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 1546291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 1556291e715SMicky Ching int count = 0; 1566291e715SMicky Ching int using_cookie = 0; 1576291e715SMicky Ching 1586291e715SMicky Ching if (!pre && data->host_cookie && data->host_cookie != host->cookie) { 1596291e715SMicky Ching dev_err(sdmmc_dev(host), 1606291e715SMicky Ching "error: data->host_cookie = %d, host->cookie = %d\n", 1616291e715SMicky Ching data->host_cookie, host->cookie); 1626291e715SMicky Ching data->host_cookie = 0; 1636291e715SMicky Ching } 1646291e715SMicky Ching 1656291e715SMicky Ching if (pre || data->host_cookie != host->cookie) { 1666291e715SMicky Ching count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); 1676291e715SMicky Ching } else { 1686291e715SMicky Ching count = host->cookie_sg_count; 1696291e715SMicky Ching using_cookie = 1; 1706291e715SMicky Ching } 1716291e715SMicky Ching 1726291e715SMicky Ching if (pre) { 1736291e715SMicky Ching host->cookie_sg_count = count; 1746291e715SMicky Ching if (++host->cookie < 0) 1756291e715SMicky Ching host->cookie = 1; 1766291e715SMicky Ching data->host_cookie = host->cookie; 1776291e715SMicky Ching } else { 1786291e715SMicky Ching host->sg_count = count; 1796291e715SMicky Ching } 1806291e715SMicky Ching 1816291e715SMicky Ching return using_cookie; 1826291e715SMicky Ching } 1836291e715SMicky Ching 184d3c6aac3SLinus Walleij static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1856291e715SMicky Ching { 1866291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1876291e715SMicky Ching struct mmc_data *data = mrq->data; 1886291e715SMicky Ching 1896291e715SMicky Ching if (data->host_cookie) { 1906291e715SMicky Ching dev_err(sdmmc_dev(host), 1916291e715SMicky Ching "error: reset data->host_cookie = %d\n", 1926291e715SMicky Ching data->host_cookie); 1936291e715SMicky Ching data->host_cookie = 0; 1946291e715SMicky Ching } 1956291e715SMicky Ching 1966291e715SMicky Ching sd_pre_dma_transfer(host, data, true); 1976291e715SMicky Ching dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); 1986291e715SMicky Ching } 1996291e715SMicky Ching 2006291e715SMicky Ching static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2016291e715SMicky Ching int err) 2026291e715SMicky Ching { 2036291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 2046291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 2056291e715SMicky Ching struct mmc_data *data = mrq->data; 2066291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 2076291e715SMicky Ching 2086291e715SMicky Ching rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); 2096291e715SMicky Ching data->host_cookie = 0; 2106291e715SMicky Ching } 2116291e715SMicky Ching 21298fcc576SMicky Ching static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 21398fcc576SMicky Ching struct mmc_command *cmd) 214ff984e57SWei WANG { 215ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 216ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 217ff984e57SWei WANG u32 arg = cmd->arg; 218ff984e57SWei WANG int err = 0; 219ff984e57SWei WANG int timeout = 100; 220ff984e57SWei WANG int i; 22198fcc576SMicky Ching u8 *ptr; 2222d48e5f1SMicky Ching int rsp_type; 2232d48e5f1SMicky Ching int stat_idx; 22498fcc576SMicky Ching bool clock_toggled = false; 225ff984e57SWei WANG 226ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 227ff984e57SWei WANG __func__, cmd_idx, arg); 228ff984e57SWei WANG 2292d48e5f1SMicky Ching rsp_type = sd_response_type(cmd); 2302d48e5f1SMicky Ching if (rsp_type < 0) 231ff984e57SWei WANG goto out; 2322d48e5f1SMicky Ching 2332d48e5f1SMicky Ching stat_idx = sd_status_index(rsp_type); 234ff984e57SWei WANG 235ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 23627f4bf7dSUlf Hansson timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000; 237ff984e57SWei WANG 238ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 239ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 240ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 241ff984e57SWei WANG if (err < 0) 242ff984e57SWei WANG goto out; 24398fcc576SMicky Ching 24498fcc576SMicky Ching clock_toggled = true; 245ff984e57SWei WANG } 246ff984e57SWei WANG 247ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 2482d48e5f1SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 249ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 250ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 251ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 252ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 253ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 254ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 255ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 256ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 257ff984e57SWei WANG 258ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 259ff984e57SWei WANG /* Read data from ping-pong buffer */ 260ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 261ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 262ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 263ff984e57SWei WANG /* Read data from SD_CMDx registers */ 264ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 265ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 266ff984e57SWei WANG } 267ff984e57SWei WANG 268ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 269ff984e57SWei WANG 27098fcc576SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 27198fcc576SMicky Ching if (err < 0) { 27298fcc576SMicky Ching sd_print_debug_regs(host); 27398fcc576SMicky Ching sd_clear_error(host); 27498fcc576SMicky Ching dev_dbg(sdmmc_dev(host), 27598fcc576SMicky Ching "rtsx_pci_send_cmd error (err = %d)\n", err); 276ff984e57SWei WANG goto out; 277ff984e57SWei WANG } 278ff984e57SWei WANG 279ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 280ff984e57SWei WANG err = 0; 281ff984e57SWei WANG goto out; 282ff984e57SWei WANG } 283ff984e57SWei WANG 284ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 285ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 286ff984e57SWei WANG 287ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 288ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 289ff984e57SWei WANG err = -EILSEQ; 290ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 291ff984e57SWei WANG goto out; 292ff984e57SWei WANG } 293ff984e57SWei WANG 294ff984e57SWei WANG /* Check CRC7 */ 295ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 296ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 297ff984e57SWei WANG err = -EILSEQ; 298ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 299ff984e57SWei WANG goto out; 300ff984e57SWei WANG } 301ff984e57SWei WANG } 302ff984e57SWei WANG 303ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 304d1419d50SRoger Tseng /* 305d1419d50SRoger Tseng * The controller offloads the last byte {CRC-7, end bit 1'b1} 306d1419d50SRoger Tseng * of response type R2. Assign dummy CRC, 0, and end bit to the 307d1419d50SRoger Tseng * byte(ptr[16], goes into the LSB of resp[3] later). 308d1419d50SRoger Tseng */ 309d1419d50SRoger Tseng ptr[16] = 1; 310d1419d50SRoger Tseng 311ff984e57SWei WANG for (i = 0; i < 4; i++) { 312ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 313ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 314ff984e57SWei WANG i, cmd->resp[i]); 315ff984e57SWei WANG } 316ff984e57SWei WANG } else { 317ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 318ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 319ff984e57SWei WANG cmd->resp[0]); 320ff984e57SWei WANG } 321ff984e57SWei WANG 322ff984e57SWei WANG out: 323ff984e57SWei WANG cmd->error = err; 3241b8055b4SWei WANG 32598fcc576SMicky Ching if (err && clock_toggled) 32698fcc576SMicky Ching rtsx_pci_write_register(pcr, SD_BUS_STAT, 32798fcc576SMicky Ching SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 328ff984e57SWei WANG } 329ff984e57SWei WANG 33056d1c0d9SMicky Ching static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd, 33156d1c0d9SMicky Ching u16 byte_cnt, u8 *buf, int buf_len, int timeout) 33256d1c0d9SMicky Ching { 33356d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr; 33456d1c0d9SMicky Ching int err; 33556d1c0d9SMicky Ching u8 trans_mode; 33656d1c0d9SMicky Ching 33756d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 33856d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg); 33956d1c0d9SMicky Ching 34056d1c0d9SMicky Ching if (!buf) 34156d1c0d9SMicky Ching buf_len = 0; 34256d1c0d9SMicky Ching 34356d1c0d9SMicky Ching if (cmd->opcode == MMC_SEND_TUNING_BLOCK) 34456d1c0d9SMicky Ching trans_mode = SD_TM_AUTO_TUNING; 34556d1c0d9SMicky Ching else 34656d1c0d9SMicky Ching trans_mode = SD_TM_NORMAL_READ; 34756d1c0d9SMicky Ching 34856d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr); 34956d1c0d9SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 35056d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt); 35156d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 35256d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 35356d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 35456d1c0d9SMicky Ching if (trans_mode != SD_TM_AUTO_TUNING) 35556d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 35656d1c0d9SMicky Ching CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 35756d1c0d9SMicky Ching 35856d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 35956d1c0d9SMicky Ching 0xFF, trans_mode | SD_TRANSFER_START); 36056d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 36156d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 36256d1c0d9SMicky Ching 36356d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 36456d1c0d9SMicky Ching if (err < 0) { 36556d1c0d9SMicky Ching sd_print_debug_regs(host); 36656d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 36756d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err); 36856d1c0d9SMicky Ching return err; 36956d1c0d9SMicky Ching } 37056d1c0d9SMicky Ching 37156d1c0d9SMicky Ching if (buf && buf_len) { 37256d1c0d9SMicky Ching err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 37356d1c0d9SMicky Ching if (err < 0) { 37456d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 37556d1c0d9SMicky Ching "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 37656d1c0d9SMicky Ching return err; 37756d1c0d9SMicky Ching } 37856d1c0d9SMicky Ching } 37956d1c0d9SMicky Ching 38056d1c0d9SMicky Ching return 0; 38156d1c0d9SMicky Ching } 38256d1c0d9SMicky Ching 38356d1c0d9SMicky Ching static int sd_write_data(struct realtek_pci_sdmmc *host, 38456d1c0d9SMicky Ching struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len, 38556d1c0d9SMicky Ching int timeout) 38656d1c0d9SMicky Ching { 38756d1c0d9SMicky Ching struct rtsx_pcr *pcr = host->pcr; 38856d1c0d9SMicky Ching int err; 38956d1c0d9SMicky Ching 39056d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 39156d1c0d9SMicky Ching __func__, cmd->opcode, cmd->arg); 39256d1c0d9SMicky Ching 39356d1c0d9SMicky Ching if (!buf) 39456d1c0d9SMicky Ching buf_len = 0; 39556d1c0d9SMicky Ching 39656d1c0d9SMicky Ching sd_send_cmd_get_rsp(host, cmd); 39756d1c0d9SMicky Ching if (cmd->error) 39856d1c0d9SMicky Ching return cmd->error; 39956d1c0d9SMicky Ching 40056d1c0d9SMicky Ching if (buf && buf_len) { 40156d1c0d9SMicky Ching err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 40256d1c0d9SMicky Ching if (err < 0) { 40356d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 40456d1c0d9SMicky Ching "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 40556d1c0d9SMicky Ching return err; 40656d1c0d9SMicky Ching } 40756d1c0d9SMicky Ching } 40856d1c0d9SMicky Ching 40956d1c0d9SMicky Ching rtsx_pci_init_cmd(pcr); 41056d1c0d9SMicky Ching sd_cmd_set_data_len(pcr, 1, byte_cnt); 41156d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 41256d1c0d9SMicky Ching SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 41356d1c0d9SMicky Ching SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0); 41456d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 41556d1c0d9SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 41656d1c0d9SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 41756d1c0d9SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 41856d1c0d9SMicky Ching 41956d1c0d9SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 42056d1c0d9SMicky Ching if (err < 0) { 42156d1c0d9SMicky Ching sd_print_debug_regs(host); 42256d1c0d9SMicky Ching dev_dbg(sdmmc_dev(host), 42356d1c0d9SMicky Ching "rtsx_pci_send_cmd fail (err = %d)\n", err); 42456d1c0d9SMicky Ching return err; 42556d1c0d9SMicky Ching } 42656d1c0d9SMicky Ching 42756d1c0d9SMicky Ching return 0; 42856d1c0d9SMicky Ching } 42956d1c0d9SMicky Ching 4301dcb3579SMicky Ching static int sd_read_long_data(struct realtek_pci_sdmmc *host, 4311dcb3579SMicky Ching struct mmc_request *mrq) 432ff984e57SWei WANG { 433ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 434ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 435ff984e57SWei WANG struct mmc_card *card = mmc->card; 4361dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd; 437ff984e57SWei WANG struct mmc_data *data = mrq->data; 43871ef1ea4SJackey Shen int uhs = mmc_card_uhs(card); 4391dcb3579SMicky Ching u8 cfg2 = 0; 440ff984e57SWei WANG int err; 4411dcb3579SMicky Ching int resp_type; 442ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 443ff984e57SWei WANG 4441dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 4451dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg); 4461dcb3579SMicky Ching 4471dcb3579SMicky Ching resp_type = sd_response_type(cmd); 4481dcb3579SMicky Ching if (resp_type < 0) 4491dcb3579SMicky Ching return resp_type; 450ff984e57SWei WANG 451ff984e57SWei WANG if (!uhs) 452ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 453ff984e57SWei WANG 454ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 4551dcb3579SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 4561dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 457ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 458ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 459ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 460ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 461ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 462ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 463ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 464ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 465ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 466ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 467ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 468ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 4691dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 4701dcb3579SMicky Ching 0x01, RING_BUFFER); 4711dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); 4721dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 4731dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_READ_2); 4741dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 4751dcb3579SMicky Ching SD_TRANSFER_END, SD_TRANSFER_END); 4761dcb3579SMicky Ching rtsx_pci_send_cmd_no_wait(pcr); 4771dcb3579SMicky Ching 4781dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000); 4791dcb3579SMicky Ching if (err < 0) { 4801dcb3579SMicky Ching sd_print_debug_regs(host); 4811dcb3579SMicky Ching sd_clear_error(host); 4821dcb3579SMicky Ching return err; 4831dcb3579SMicky Ching } 4841dcb3579SMicky Ching 4851dcb3579SMicky Ching return 0; 4861dcb3579SMicky Ching } 4871dcb3579SMicky Ching 4881dcb3579SMicky Ching static int sd_write_long_data(struct realtek_pci_sdmmc *host, 4891dcb3579SMicky Ching struct mmc_request *mrq) 4901dcb3579SMicky Ching { 4911dcb3579SMicky Ching struct rtsx_pcr *pcr = host->pcr; 4921dcb3579SMicky Ching struct mmc_host *mmc = host->mmc; 4931dcb3579SMicky Ching struct mmc_card *card = mmc->card; 4941dcb3579SMicky Ching struct mmc_command *cmd = mrq->cmd; 4951dcb3579SMicky Ching struct mmc_data *data = mrq->data; 4961dcb3579SMicky Ching int uhs = mmc_card_uhs(card); 4971dcb3579SMicky Ching u8 cfg2; 4981dcb3579SMicky Ching int err; 4991dcb3579SMicky Ching size_t data_len = data->blksz * data->blocks; 5001dcb3579SMicky Ching 5011dcb3579SMicky Ching sd_send_cmd_get_rsp(host, cmd); 5021dcb3579SMicky Ching if (cmd->error) 5031dcb3579SMicky Ching return cmd->error; 5041dcb3579SMicky Ching 5051dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 5061dcb3579SMicky Ching __func__, cmd->opcode, cmd->arg); 5071dcb3579SMicky Ching 5081dcb3579SMicky Ching cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 5091dcb3579SMicky Ching SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 5101dcb3579SMicky Ching 5111dcb3579SMicky Ching if (!uhs) 5121dcb3579SMicky Ching cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 5131dcb3579SMicky Ching 5141dcb3579SMicky Ching rtsx_pci_init_cmd(pcr); 5151dcb3579SMicky Ching sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 5161dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 5171dcb3579SMicky Ching DMA_DONE_INT, DMA_DONE_INT); 5181dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 5191dcb3579SMicky Ching 0xFF, (u8)(data_len >> 24)); 5201dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 5211dcb3579SMicky Ching 0xFF, (u8)(data_len >> 16)); 5221dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 5231dcb3579SMicky Ching 0xFF, (u8)(data_len >> 8)); 5241dcb3579SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 525ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 526ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 527ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 528ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 529ff984e57SWei WANG 0x01, RING_BUFFER); 53038d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 531ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 5321dcb3579SMicky Ching SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 533ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 534ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 535ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 5361dcb3579SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000); 537ff984e57SWei WANG if (err < 0) { 53898fcc576SMicky Ching sd_clear_error(host); 53998fcc576SMicky Ching return err; 540c42deffdSMicky Ching } 54198fcc576SMicky Ching 542c42deffdSMicky Ching return 0; 543ff984e57SWei WANG } 544ff984e57SWei WANG 545ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 546ff984e57SWei WANG { 547ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 548ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 549ff984e57SWei WANG } 550ff984e57SWei WANG 551ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 552ff984e57SWei WANG { 553ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 554ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 555ff984e57SWei WANG } 556ff984e57SWei WANG 557*3ac5e452SThomas Hebb static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 558*3ac5e452SThomas Hebb { 559*3ac5e452SThomas Hebb struct mmc_data *data = mrq->data; 560*3ac5e452SThomas Hebb int err; 561*3ac5e452SThomas Hebb 562*3ac5e452SThomas Hebb if (host->sg_count < 0) { 563*3ac5e452SThomas Hebb data->error = host->sg_count; 564*3ac5e452SThomas Hebb dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n", 565*3ac5e452SThomas Hebb __func__, host->sg_count); 566*3ac5e452SThomas Hebb return data->error; 567*3ac5e452SThomas Hebb } 568*3ac5e452SThomas Hebb 569*3ac5e452SThomas Hebb if (data->flags & MMC_DATA_READ) { 570*3ac5e452SThomas Hebb if (host->initial_mode) 571*3ac5e452SThomas Hebb sd_disable_initial_mode(host); 572*3ac5e452SThomas Hebb 573*3ac5e452SThomas Hebb err = sd_read_long_data(host, mrq); 574*3ac5e452SThomas Hebb 575*3ac5e452SThomas Hebb if (host->initial_mode) 576*3ac5e452SThomas Hebb sd_enable_initial_mode(host); 577*3ac5e452SThomas Hebb 578*3ac5e452SThomas Hebb return err; 579*3ac5e452SThomas Hebb } 580*3ac5e452SThomas Hebb 581*3ac5e452SThomas Hebb return sd_write_long_data(host, mrq); 582*3ac5e452SThomas Hebb } 583*3ac5e452SThomas Hebb 584ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 585ff984e57SWei WANG struct mmc_request *mrq) 586ff984e57SWei WANG { 587ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 588ff984e57SWei WANG struct mmc_data *data = mrq->data; 5891dcb3579SMicky Ching u8 *buf; 590ff984e57SWei WANG 591ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 592ff984e57SWei WANG if (!buf) { 593ff984e57SWei WANG cmd->error = -ENOMEM; 594ff984e57SWei WANG return; 595ff984e57SWei WANG } 596ff984e57SWei WANG 597ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 598ff984e57SWei WANG if (host->initial_mode) 599ff984e57SWei WANG sd_disable_initial_mode(host); 600ff984e57SWei WANG 6011dcb3579SMicky Ching cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf, 602ff984e57SWei WANG data->blksz, 200); 603ff984e57SWei WANG 604ff984e57SWei WANG if (host->initial_mode) 605ff984e57SWei WANG sd_enable_initial_mode(host); 606ff984e57SWei WANG 607ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 608ff984e57SWei WANG } else { 609ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 610ff984e57SWei WANG 6111dcb3579SMicky Ching cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf, 612ff984e57SWei WANG data->blksz, 200); 613ff984e57SWei WANG } 614ff984e57SWei WANG 615ff984e57SWei WANG kfree(buf); 616ff984e57SWei WANG } 617ff984e57SWei WANG 61884d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, 61984d72f9cSWei WANG u8 sample_point, bool rx) 620ff984e57SWei WANG { 621ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 6224686392cSRicky Wu u16 SD_VP_CTL = 0; 62384d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 62484d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point); 625ff984e57SWei WANG 626563be8b6Srui_feng rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 6274686392cSRicky Wu if (rx) { 6284686392cSRicky Wu SD_VP_CTL = SD_VPRX_CTL; 629563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_VPRX_CTL, 630563be8b6Srui_feng PHASE_SELECT_MASK, sample_point); 6314686392cSRicky Wu } else { 6324686392cSRicky Wu SD_VP_CTL = SD_VPTX_CTL; 633563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_VPTX_CTL, 634563be8b6Srui_feng PHASE_SELECT_MASK, sample_point); 6354686392cSRicky Wu } 6364686392cSRicky Wu rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0); 6374686392cSRicky Wu rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 638563be8b6Srui_feng PHASE_NOT_RESET); 639563be8b6Srui_feng rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0); 640563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 641ff984e57SWei WANG 642ff984e57SWei WANG return 0; 643ff984e57SWei WANG } 644ff984e57SWei WANG 645abcc6b29SMicky Ching static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 646abcc6b29SMicky Ching { 647abcc6b29SMicky Ching bit %= RTSX_PHASE_MAX; 648abcc6b29SMicky Ching return phase_map & (1 << bit); 649abcc6b29SMicky Ching } 650abcc6b29SMicky Ching 651abcc6b29SMicky Ching static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 652abcc6b29SMicky Ching { 653abcc6b29SMicky Ching int i; 654abcc6b29SMicky Ching 655abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 656abcc6b29SMicky Ching if (test_phase_bit(phase_map, start_bit + i) == 0) 657abcc6b29SMicky Ching return i; 658abcc6b29SMicky Ching } 659abcc6b29SMicky Ching return RTSX_PHASE_MAX; 660abcc6b29SMicky Ching } 661abcc6b29SMicky Ching 662ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 663ff984e57SWei WANG { 664abcc6b29SMicky Ching int start = 0, len = 0; 665abcc6b29SMicky Ching int start_final = 0, len_final = 0; 666ff984e57SWei WANG u8 final_phase = 0xFF; 667ff984e57SWei WANG 668abcc6b29SMicky Ching if (phase_map == 0) { 669abcc6b29SMicky Ching dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 670abcc6b29SMicky Ching return final_phase; 671ff984e57SWei WANG } 672ff984e57SWei WANG 673abcc6b29SMicky Ching while (start < RTSX_PHASE_MAX) { 674abcc6b29SMicky Ching len = sd_get_phase_len(phase_map, start); 675abcc6b29SMicky Ching if (len_final < len) { 676abcc6b29SMicky Ching start_final = start; 677abcc6b29SMicky Ching len_final = len; 678abcc6b29SMicky Ching } 679abcc6b29SMicky Ching start += len ? len : 1; 680ff984e57SWei WANG } 681ff984e57SWei WANG 682abcc6b29SMicky Ching final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 683abcc6b29SMicky Ching dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 684abcc6b29SMicky Ching phase_map, len_final, final_phase); 685ff984e57SWei WANG 686ff984e57SWei WANG return final_phase; 687ff984e57SWei WANG } 688ff984e57SWei WANG 689ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 690ff984e57SWei WANG { 691679209b3SLee Jones int i; 692ff984e57SWei WANG u8 val = 0; 693ff984e57SWei WANG 694ff984e57SWei WANG for (i = 0; i < 100; i++) { 695679209b3SLee Jones rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 696ff984e57SWei WANG if (val & SD_DATA_IDLE) 697ff984e57SWei WANG return; 698ff984e57SWei WANG 699ff984e57SWei WANG udelay(100); 700ff984e57SWei WANG } 701ff984e57SWei WANG } 702ff984e57SWei WANG 703ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 704ff984e57SWei WANG u8 opcode, u8 sample_point) 705ff984e57SWei WANG { 706ff984e57SWei WANG int err; 707c7836d15SMasahiro Yamada struct mmc_command cmd = {}; 708563be8b6Srui_feng struct rtsx_pcr *pcr = host->pcr; 709ff984e57SWei WANG 710563be8b6Srui_feng sd_change_phase(host, sample_point, true); 711563be8b6Srui_feng 712563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 713563be8b6Srui_feng SD_RSP_80CLK_TIMEOUT_EN); 714ff984e57SWei WANG 7151dcb3579SMicky Ching cmd.opcode = opcode; 7161dcb3579SMicky Ching err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100); 717ff984e57SWei WANG if (err < 0) { 718ff984e57SWei WANG /* Wait till SD DATA IDLE */ 719ff984e57SWei WANG sd_wait_data_idle(host); 720ff984e57SWei WANG sd_clear_error(host); 721563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3, 722563be8b6Srui_feng SD_RSP_80CLK_TIMEOUT_EN, 0); 723ff984e57SWei WANG return err; 724ff984e57SWei WANG } 725ff984e57SWei WANG 726563be8b6Srui_feng rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); 727ff984e57SWei WANG return 0; 728ff984e57SWei WANG } 729ff984e57SWei WANG 730ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 731ff984e57SWei WANG u8 opcode, u32 *phase_map) 732ff984e57SWei WANG { 733ff984e57SWei WANG int err, i; 734ff984e57SWei WANG u32 raw_phase_map = 0; 735ff984e57SWei WANG 736abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 737ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 738ff984e57SWei WANG if (err == 0) 739ff984e57SWei WANG raw_phase_map |= 1 << i; 740ff984e57SWei WANG } 741ff984e57SWei WANG 742ff984e57SWei WANG if (phase_map) 743ff984e57SWei WANG *phase_map = raw_phase_map; 744ff984e57SWei WANG 745ff984e57SWei WANG return 0; 746ff984e57SWei WANG } 747ff984e57SWei WANG 748ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 749ff984e57SWei WANG { 750ff984e57SWei WANG int err, i; 751ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 752ff984e57SWei WANG u8 final_phase; 753ff984e57SWei WANG 754ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 755ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 756ff984e57SWei WANG if (err < 0) 757ff984e57SWei WANG return err; 758ff984e57SWei WANG 759ff984e57SWei WANG if (raw_phase_map[i] == 0) 760ff984e57SWei WANG break; 761ff984e57SWei WANG } 762ff984e57SWei WANG 763ff984e57SWei WANG phase_map = 0xFFFFFFFF; 764ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 765ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 766ff984e57SWei WANG i, raw_phase_map[i]); 767ff984e57SWei WANG phase_map &= raw_phase_map[i]; 768ff984e57SWei WANG } 769ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 770ff984e57SWei WANG 771ff984e57SWei WANG if (phase_map) { 772ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 773ff984e57SWei WANG if (final_phase == 0xFF) 774ff984e57SWei WANG return -EINVAL; 775ff984e57SWei WANG 77684d72f9cSWei WANG err = sd_change_phase(host, final_phase, true); 777ff984e57SWei WANG if (err < 0) 778ff984e57SWei WANG return err; 779ff984e57SWei WANG } else { 780ff984e57SWei WANG return -EINVAL; 781ff984e57SWei WANG } 782ff984e57SWei WANG 783ff984e57SWei WANG return 0; 784ff984e57SWei WANG } 785ff984e57SWei WANG 7861dcb3579SMicky Ching static inline int sdio_extblock_cmd(struct mmc_command *cmd, 7871dcb3579SMicky Ching struct mmc_data *data) 7881dcb3579SMicky Ching { 7891dcb3579SMicky Ching return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512); 7901dcb3579SMicky Ching } 7911dcb3579SMicky Ching 7926291e715SMicky Ching static inline int sd_rw_cmd(struct mmc_command *cmd) 793ff984e57SWei WANG { 7946291e715SMicky Ching return mmc_op_multi(cmd->opcode) || 7956291e715SMicky Ching (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 7966291e715SMicky Ching (cmd->opcode == MMC_WRITE_BLOCK); 7976291e715SMicky Ching } 7986291e715SMicky Ching 7996291e715SMicky Ching static void sd_request(struct work_struct *work) 8006291e715SMicky Ching { 8016291e715SMicky Ching struct realtek_pci_sdmmc *host = container_of(work, 8026291e715SMicky Ching struct realtek_pci_sdmmc, work); 803ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 8046291e715SMicky Ching 8056291e715SMicky Ching struct mmc_host *mmc = host->mmc; 8066291e715SMicky Ching struct mmc_request *mrq = host->mrq; 807ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 808ff984e57SWei WANG struct mmc_data *data = mrq->data; 8096291e715SMicky Ching 810ff984e57SWei WANG unsigned int data_size = 0; 811c3481955SWei WANG int err; 812ff984e57SWei WANG 813b22217f9SMicky Ching if (host->eject || !sd_get_cd_int(host)) { 814ff984e57SWei WANG cmd->error = -ENOMEDIUM; 815ff984e57SWei WANG goto finish; 816ff984e57SWei WANG } 817ff984e57SWei WANG 818c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 819c3481955SWei WANG if (err) { 820c3481955SWei WANG cmd->error = err; 821c3481955SWei WANG goto finish; 822c3481955SWei WANG } 823c3481955SWei WANG 82498fcc576SMicky Ching mutex_lock(&pcr->pcr_mutex); 82598fcc576SMicky Ching 826ff984e57SWei WANG rtsx_pci_start_run(pcr); 827ff984e57SWei WANG 828ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 829ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 830ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 831ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 832ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 833ff984e57SWei WANG 83498fcc576SMicky Ching mutex_lock(&host->host_mutex); 83598fcc576SMicky Ching host->mrq = mrq; 83698fcc576SMicky Ching mutex_unlock(&host->host_mutex); 83798fcc576SMicky Ching 838ff984e57SWei WANG if (mrq->data) 839ff984e57SWei WANG data_size = data->blocks * data->blksz; 840ff984e57SWei WANG 8411dcb3579SMicky Ching if (!data_size) { 84298fcc576SMicky Ching sd_send_cmd_get_rsp(host, cmd); 8431dcb3579SMicky Ching } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) { 8441dcb3579SMicky Ching cmd->error = sd_rw_multi(host, mrq); 8456291e715SMicky Ching if (!host->using_cookie) 8466291e715SMicky Ching sdmmc_post_req(host->mmc, host->mrq, 0); 84798fcc576SMicky Ching 84898fcc576SMicky Ching if (mmc_op_multi(cmd->opcode) && mrq->stop) 84998fcc576SMicky Ching sd_send_cmd_get_rsp(host, mrq->stop); 85098fcc576SMicky Ching } else { 85198fcc576SMicky Ching sd_normal_rw(host, mrq); 85298fcc576SMicky Ching } 85398fcc576SMicky Ching 85498fcc576SMicky Ching if (mrq->data) { 85598fcc576SMicky Ching if (cmd->error || data->error) 85698fcc576SMicky Ching data->bytes_xfered = 0; 85798fcc576SMicky Ching else 85898fcc576SMicky Ching data->bytes_xfered = data->blocks * data->blksz; 85998fcc576SMicky Ching } 86098fcc576SMicky Ching 86198fcc576SMicky Ching mutex_unlock(&pcr->pcr_mutex); 862ff984e57SWei WANG 863ff984e57SWei WANG finish: 8641dcb3579SMicky Ching if (cmd->error) { 8651dcb3579SMicky Ching dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n", 8661dcb3579SMicky Ching cmd->opcode, cmd->arg, cmd->error); 8671dcb3579SMicky Ching } 86898fcc576SMicky Ching 86998fcc576SMicky Ching mutex_lock(&host->host_mutex); 87098fcc576SMicky Ching host->mrq = NULL; 87198fcc576SMicky Ching mutex_unlock(&host->host_mutex); 87298fcc576SMicky Ching 87398fcc576SMicky Ching mmc_request_done(mmc, mrq); 874ff984e57SWei WANG } 875ff984e57SWei WANG 8766291e715SMicky Ching static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 8776291e715SMicky Ching { 8786291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 8796291e715SMicky Ching struct mmc_data *data = mrq->data; 8806291e715SMicky Ching 8816291e715SMicky Ching mutex_lock(&host->host_mutex); 8826291e715SMicky Ching host->mrq = mrq; 8836291e715SMicky Ching mutex_unlock(&host->host_mutex); 8846291e715SMicky Ching 8851dcb3579SMicky Ching if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data)) 8866291e715SMicky Ching host->using_cookie = sd_pre_dma_transfer(host, data, false); 8876291e715SMicky Ching 8886ea62579SBhaktipriya Shridhar schedule_work(&host->work); 8896291e715SMicky Ching } 8906291e715SMicky Ching 891ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 892ff984e57SWei WANG unsigned char bus_width) 893ff984e57SWei WANG { 894ff984e57SWei WANG int err = 0; 895ff984e57SWei WANG u8 width[] = { 896ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 897ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 898ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 899ff984e57SWei WANG }; 900ff984e57SWei WANG 901ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 902ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 903ff984e57SWei WANG 0x03, width[bus_width]); 904ff984e57SWei WANG 905ff984e57SWei WANG return err; 906ff984e57SWei WANG } 907ff984e57SWei WANG 908ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 909ff984e57SWei WANG { 910ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 9119ff43c7bSRui Feng struct mmc_host *mmc = host->mmc; 912ff984e57SWei WANG int err; 9139ff43c7bSRui Feng u32 val; 9146b7b58f4SRui Feng u8 test_mode; 915ff984e57SWei WANG 916d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 917d88691beSWei WANG return 0; 918d88691beSWei WANG 91912b1c5edSRicky Wu msleep(100); 92012b1c5edSRicky Wu 921ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 922ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 923ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 924ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 925ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 926ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 927ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 928ff984e57SWei WANG if (err < 0) 929ff984e57SWei WANG return err; 930ff984e57SWei WANG 931ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 932ff984e57SWei WANG if (err < 0) 933ff984e57SWei WANG return err; 934ff984e57SWei WANG 935ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 936ff984e57SWei WANG if (err < 0) 937ff984e57SWei WANG return err; 938ff984e57SWei WANG 939ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 940ff984e57SWei WANG if (err < 0) 941ff984e57SWei WANG return err; 942ff984e57SWei WANG 9439ff43c7bSRui Feng if (PCI_PID(pcr) == PID_5261) { 9446b7b58f4SRui Feng /* 9456b7b58f4SRui Feng * If test mode is set switch to SD Express mandatorily, 9466b7b58f4SRui Feng * this is only for factory testing. 9476b7b58f4SRui Feng */ 9486b7b58f4SRui Feng rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode); 9496b7b58f4SRui Feng if (test_mode & RTS5261_FW_EXPRESS_TEST_MASK) { 9506b7b58f4SRui Feng sdmmc_init_sd_express(mmc, NULL); 9516b7b58f4SRui Feng return 0; 9526b7b58f4SRui Feng } 9539ff43c7bSRui Feng if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) 9549ff43c7bSRui Feng mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; 9559ff43c7bSRui Feng /* 9569ff43c7bSRui Feng * HW read wp status when resuming from S3/S4, 9579ff43c7bSRui Feng * and then picks SD legacy interface if it's set 9589ff43c7bSRui Feng * in read-only mode. 9599ff43c7bSRui Feng */ 9609ff43c7bSRui Feng val = rtsx_pci_readl(pcr, RTSX_BIPR); 9619ff43c7bSRui Feng if (val & SD_WRITE_PROTECT) { 9629ff43c7bSRui Feng pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS; 9639ff43c7bSRui Feng mmc->caps2 &= ~(MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V); 9649ff43c7bSRui Feng } 9659ff43c7bSRui Feng } 9669ff43c7bSRui Feng 967d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 968ff984e57SWei WANG return 0; 969ff984e57SWei WANG } 970ff984e57SWei WANG 971ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 972ff984e57SWei WANG { 973ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 974ff984e57SWei WANG int err; 975ff984e57SWei WANG 976d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 977d88691beSWei WANG 978ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 979ff984e57SWei WANG 980ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 981ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 982ff984e57SWei WANG 983ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 984ff984e57SWei WANG if (err < 0) 985ff984e57SWei WANG return err; 986ff984e57SWei WANG 987ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 988ff984e57SWei WANG if (err < 0) 989ff984e57SWei WANG return err; 990ff984e57SWei WANG 991ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 992ff984e57SWei WANG } 993ff984e57SWei WANG 994ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 995ff984e57SWei WANG unsigned char power_mode) 996ff984e57SWei WANG { 997ff984e57SWei WANG int err; 998ff984e57SWei WANG 999ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 1000ff984e57SWei WANG err = sd_power_off(host); 1001ff984e57SWei WANG else 1002ff984e57SWei WANG err = sd_power_on(host); 1003ff984e57SWei WANG 1004ff984e57SWei WANG return err; 1005ff984e57SWei WANG } 1006ff984e57SWei WANG 100784d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 1008ff984e57SWei WANG { 1009ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1010ff984e57SWei WANG int err = 0; 1011ff984e57SWei WANG 1012ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 1013ff984e57SWei WANG 1014ff984e57SWei WANG switch (timing) { 1015ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1016ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1017ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1018ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 1019ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 1020ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1021ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1022ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1023ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 1024ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1025ff984e57SWei WANG break; 1026ff984e57SWei WANG 10271a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 1028ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1029ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1030ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 1031ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 1032ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1033ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1034ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1035ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 1036ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1037ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1038ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 1039ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1040ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 1041ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 1042ff984e57SWei WANG break; 1043ff984e57SWei WANG 1044ff984e57SWei WANG case MMC_TIMING_MMC_HS: 1045ff984e57SWei WANG case MMC_TIMING_SD_HS: 1046ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1047ff984e57SWei WANG 0x0C, SD_20_MODE); 1048ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1049ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1050ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1051ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1052ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1053ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1054ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 1055ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1056ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 1057ff984e57SWei WANG break; 1058ff984e57SWei WANG 1059ff984e57SWei WANG default: 1060ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1061ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 1062ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1063ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 1064ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1065ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1066ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1067ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1068ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 1069ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1070ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 1071ff984e57SWei WANG break; 1072ff984e57SWei WANG } 1073ff984e57SWei WANG 1074ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 1075ff984e57SWei WANG 1076ff984e57SWei WANG return err; 1077ff984e57SWei WANG } 1078ff984e57SWei WANG 1079ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1080ff984e57SWei WANG { 1081ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1082ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1083ff984e57SWei WANG 1084ff984e57SWei WANG if (host->eject) 1085ff984e57SWei WANG return; 1086ff984e57SWei WANG 1087c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 1088c3481955SWei WANG return; 1089c3481955SWei WANG 1090ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1091ff984e57SWei WANG 1092ff984e57SWei WANG rtsx_pci_start_run(pcr); 1093ff984e57SWei WANG 1094ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 1095ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 109684d72f9cSWei WANG sd_set_timing(host, ios->timing); 1097ff984e57SWei WANG 1098ff984e57SWei WANG host->vpclk = false; 1099ff984e57SWei WANG host->double_clk = true; 1100ff984e57SWei WANG 1101ff984e57SWei WANG switch (ios->timing) { 1102ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1103ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1104ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 1105ff984e57SWei WANG host->vpclk = true; 1106ff984e57SWei WANG host->double_clk = false; 1107ff984e57SWei WANG break; 11081a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 1109ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1110ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 1111ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 1112ff984e57SWei WANG break; 1113ff984e57SWei WANG default: 1114ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 1115ff984e57SWei WANG break; 1116ff984e57SWei WANG } 1117ff984e57SWei WANG 1118ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 1119ff984e57SWei WANG 1120ff984e57SWei WANG host->clock = ios->clock; 1121ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 1122ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 1123ff984e57SWei WANG 1124ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1125ff984e57SWei WANG } 1126ff984e57SWei WANG 1127ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 1128ff984e57SWei WANG { 1129ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1130ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1131ff984e57SWei WANG int ro = 0; 1132ff984e57SWei WANG u32 val; 1133ff984e57SWei WANG 1134ff984e57SWei WANG if (host->eject) 1135ff984e57SWei WANG return -ENOMEDIUM; 1136ff984e57SWei WANG 1137ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1138ff984e57SWei WANG 1139ff984e57SWei WANG rtsx_pci_start_run(pcr); 1140ff984e57SWei WANG 1141ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 1142ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 1143ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1144ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 1145ff984e57SWei WANG ro = 1; 1146ff984e57SWei WANG 1147ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1148ff984e57SWei WANG 1149ff984e57SWei WANG return ro; 1150ff984e57SWei WANG } 1151ff984e57SWei WANG 1152ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 1153ff984e57SWei WANG { 1154ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1155ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1156ff984e57SWei WANG int cd = 0; 1157ff984e57SWei WANG u32 val; 1158ff984e57SWei WANG 1159ff984e57SWei WANG if (host->eject) 1160b22217f9SMicky Ching return cd; 1161ff984e57SWei WANG 1162ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1163ff984e57SWei WANG 1164ff984e57SWei WANG rtsx_pci_start_run(pcr); 1165ff984e57SWei WANG 1166ff984e57SWei WANG /* Check SD card detect */ 1167ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 1168ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1169ff984e57SWei WANG if (val & SD_EXIST) 1170ff984e57SWei WANG cd = 1; 1171ff984e57SWei WANG 1172ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1173ff984e57SWei WANG 1174ff984e57SWei WANG return cd; 1175ff984e57SWei WANG } 1176ff984e57SWei WANG 1177ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1178ff984e57SWei WANG { 1179ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1180ff984e57SWei WANG int err; 1181ff984e57SWei WANG u8 stat; 1182ff984e57SWei WANG 1183ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 1184ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 1185ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 1186ff984e57SWei WANG */ 1187ff984e57SWei WANG mdelay(1); 1188ff984e57SWei WANG 1189ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1190ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 1191ff984e57SWei WANG * abort the voltage switch sequence; 1192ff984e57SWei WANG */ 1193ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1194ff984e57SWei WANG if (err < 0) 1195ff984e57SWei WANG return err; 1196ff984e57SWei WANG 1197ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1198ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 1199ff984e57SWei WANG return -EINVAL; 1200ff984e57SWei WANG 1201ff984e57SWei WANG /* Stop toggle SD clock */ 1202ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1203ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 1204ff984e57SWei WANG if (err < 0) 1205ff984e57SWei WANG return err; 1206ff984e57SWei WANG 1207ff984e57SWei WANG return 0; 1208ff984e57SWei WANG } 1209ff984e57SWei WANG 1210ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1211ff984e57SWei WANG { 1212ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1213ff984e57SWei WANG int err; 1214ff984e57SWei WANG u8 stat, mask, val; 1215ff984e57SWei WANG 1216ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1217ff984e57SWei WANG msleep(50); 1218ff984e57SWei WANG 1219ff984e57SWei WANG /* Toggle SD clock again */ 1220ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1221ff984e57SWei WANG if (err < 0) 1222ff984e57SWei WANG return err; 1223ff984e57SWei WANG 1224ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1225ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1226ff984e57SWei WANG */ 1227ff984e57SWei WANG msleep(20); 1228ff984e57SWei WANG 1229ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1230ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1231ff984e57SWei WANG if (err < 0) 1232ff984e57SWei WANG return err; 1233ff984e57SWei WANG 1234ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1235ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1236ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1237ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1238ff984e57SWei WANG if ((stat & mask) != val) { 1239ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1240ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1241ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1242ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1243ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1244ff984e57SWei WANG return -EINVAL; 1245ff984e57SWei WANG } 1246ff984e57SWei WANG 1247ff984e57SWei WANG return 0; 1248ff984e57SWei WANG } 1249ff984e57SWei WANG 1250ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1251ff984e57SWei WANG { 1252ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1253ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1254ff984e57SWei WANG int err = 0; 1255ff984e57SWei WANG u8 voltage; 1256ff984e57SWei WANG 1257ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1258ff984e57SWei WANG __func__, ios->signal_voltage); 1259ff984e57SWei WANG 1260ff984e57SWei WANG if (host->eject) 1261ff984e57SWei WANG return -ENOMEDIUM; 1262ff984e57SWei WANG 1263c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1264c3481955SWei WANG if (err) 1265c3481955SWei WANG return err; 1266c3481955SWei WANG 1267ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1268ff984e57SWei WANG 1269ff984e57SWei WANG rtsx_pci_start_run(pcr); 1270ff984e57SWei WANG 1271ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1272ef85e736SWei WANG voltage = OUTPUT_3V3; 1273ff984e57SWei WANG else 1274ef85e736SWei WANG voltage = OUTPUT_1V8; 1275ff984e57SWei WANG 1276ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1277ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1278ff984e57SWei WANG if (err < 0) 1279ff984e57SWei WANG goto out; 1280ff984e57SWei WANG } 1281ff984e57SWei WANG 1282ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1283ff984e57SWei WANG if (err < 0) 1284ff984e57SWei WANG goto out; 1285ff984e57SWei WANG 1286ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1287ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1288ff984e57SWei WANG if (err < 0) 1289ff984e57SWei WANG goto out; 1290ff984e57SWei WANG } 1291ff984e57SWei WANG 12921b8055b4SWei WANG out: 1293ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1294ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1295ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1296ff984e57SWei WANG 1297ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1298ff984e57SWei WANG 1299ff984e57SWei WANG return err; 1300ff984e57SWei WANG } 1301ff984e57SWei WANG 1302ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1303ff984e57SWei WANG { 1304ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1305ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1306ff984e57SWei WANG int err = 0; 1307ff984e57SWei WANG 1308ff984e57SWei WANG if (host->eject) 1309ff984e57SWei WANG return -ENOMEDIUM; 1310ff984e57SWei WANG 1311c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1312c3481955SWei WANG if (err) 1313c3481955SWei WANG return err; 1314c3481955SWei WANG 1315ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1316ff984e57SWei WANG 1317ff984e57SWei WANG rtsx_pci_start_run(pcr); 1318ff984e57SWei WANG 131984d72f9cSWei WANG /* Set initial TX phase */ 132084d72f9cSWei WANG switch (mmc->ios.timing) { 132184d72f9cSWei WANG case MMC_TIMING_UHS_SDR104: 132284d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 132384d72f9cSWei WANG break; 1324ff984e57SWei WANG 132584d72f9cSWei WANG case MMC_TIMING_UHS_SDR50: 132684d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 132784d72f9cSWei WANG break; 132884d72f9cSWei WANG 132984d72f9cSWei WANG case MMC_TIMING_UHS_DDR50: 133084d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 133184d72f9cSWei WANG break; 133284d72f9cSWei WANG 133384d72f9cSWei WANG default: 133484d72f9cSWei WANG err = 0; 133584d72f9cSWei WANG } 133684d72f9cSWei WANG 133784d72f9cSWei WANG if (err) 133884d72f9cSWei WANG goto out; 133984d72f9cSWei WANG 134084d72f9cSWei WANG /* Tuning RX phase */ 134184d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 134284d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 134384d72f9cSWei WANG err = sd_tuning_rx(host, opcode); 134484d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 134584d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 134684d72f9cSWei WANG 134784d72f9cSWei WANG out: 1348ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1349ff984e57SWei WANG 1350ff984e57SWei WANG return err; 1351ff984e57SWei WANG } 1352ff984e57SWei WANG 13539ff43c7bSRui Feng static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) 13549ff43c7bSRui Feng { 13559ff43c7bSRui Feng u32 relink_time; 13569ff43c7bSRui Feng struct realtek_pci_sdmmc *host = mmc_priv(mmc); 13579ff43c7bSRui Feng struct rtsx_pcr *pcr = host->pcr; 13589ff43c7bSRui Feng 13599ff43c7bSRui Feng /* Set relink_time for changing to PCIe card */ 13609ff43c7bSRui Feng relink_time = 0x8FFF; 13619ff43c7bSRui Feng 13629ff43c7bSRui Feng rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time); 13639ff43c7bSRui Feng rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8); 13649ff43c7bSRui Feng rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16); 13659ff43c7bSRui Feng 13669ff43c7bSRui Feng rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80); 13679ff43c7bSRui Feng rtsx_pci_write_register(pcr, LDO_VCC_CFG0, 13689ff43c7bSRui Feng RTS5261_LDO1_OCP_THD_MASK, 13699ff43c7bSRui Feng pcr->option.sd_800mA_ocp_thd); 13709ff43c7bSRui Feng 13719ff43c7bSRui Feng if (pcr->ops->disable_auto_blink) 13729ff43c7bSRui Feng pcr->ops->disable_auto_blink(pcr); 13739ff43c7bSRui Feng 13749ff43c7bSRui Feng /* For PCIe/NVMe mode can't enter delink issue */ 13759ff43c7bSRui Feng pcr->hw_param.interrupt_en &= ~(SD_INT_EN); 13769ff43c7bSRui Feng rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en); 13779ff43c7bSRui Feng 13789ff43c7bSRui Feng rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4, 13799ff43c7bSRui Feng RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN); 13809ff43c7bSRui Feng rtsx_pci_write_register(pcr, RTS5261_FW_CFG0, 13819ff43c7bSRui Feng RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS); 13829ff43c7bSRui Feng rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, 13836b7b58f4SRui Feng RTS5261_MCU_CLOCK_GATING, RTS5261_MCU_CLOCK_GATING); 13846b7b58f4SRui Feng rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, 13859ff43c7bSRui Feng RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK 13866b7b58f4SRui Feng | RTS5261_DRIVER_ENABLE_FW, 13876b7b58f4SRui Feng RTS5261_MCU_CLOCK_SEL_16M | RTS5261_DRIVER_ENABLE_FW); 13889ff43c7bSRui Feng host->eject = true; 13899ff43c7bSRui Feng return 0; 13909ff43c7bSRui Feng } 13919ff43c7bSRui Feng 1392ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 13936291e715SMicky Ching .pre_req = sdmmc_pre_req, 13946291e715SMicky Ching .post_req = sdmmc_post_req, 1395ff984e57SWei WANG .request = sdmmc_request, 1396ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1397ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1398ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1399ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1400ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 14019ff43c7bSRui Feng .init_sd_express = sdmmc_init_sd_express, 1402ff984e57SWei WANG }; 1403ff984e57SWei WANG 1404ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1405ff984e57SWei WANG { 1406ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1407ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1408ff984e57SWei WANG 1409ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1410ff984e57SWei WANG 1411ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1412ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1413ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1414ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1415ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1416ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1417ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1418ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1419ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1420ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1421849a9366SRicky Wu if (pcr->extra_caps & EXTRA_CAPS_NO_MMC) 1422849a9366SRicky Wu mmc->caps2 |= MMC_CAP2_NO_MMC; 14239ff43c7bSRui Feng if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) 14249ff43c7bSRui Feng mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; 1425ff984e57SWei WANG } 1426ff984e57SWei WANG 1427ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1428ff984e57SWei WANG { 1429ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 14305b4258f6SRicky Wu struct rtsx_pcr *pcr = host->pcr; 1431ff984e57SWei WANG 1432ff984e57SWei WANG mmc->f_min = 250000; 1433ff984e57SWei WANG mmc->f_max = 208000000; 1434ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1435ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1436ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 14371be64c79SUlf Hansson MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 14385b4258f6SRicky Wu if (pcr->rtd3_en) 14395b4258f6SRicky Wu mmc->caps = mmc->caps | MMC_CAP_AGGRESSIVE_PM; 14408b280564SRicky Wu mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE | 14418b280564SRicky Wu MMC_CAP2_NO_SDIO; 1442ff984e57SWei WANG mmc->max_current_330 = 400; 1443ff984e57SWei WANG mmc->max_current_180 = 800; 1444ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1445ff984e57SWei WANG 1446ff984e57SWei WANG init_extra_caps(host); 1447ff984e57SWei WANG 1448ff984e57SWei WANG mmc->max_segs = 256; 1449ff984e57SWei WANG mmc->max_seg_size = 65536; 1450ff984e57SWei WANG mmc->max_blk_size = 512; 1451ff984e57SWei WANG mmc->max_blk_count = 65535; 1452ff984e57SWei WANG mmc->max_req_size = 524288; 1453ff984e57SWei WANG } 1454ff984e57SWei WANG 1455ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1456ff984e57SWei WANG { 1457ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1458ff984e57SWei WANG 14592057647fSMicky Ching host->cookie = -1; 1460ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1461ff984e57SWei WANG } 1462ff984e57SWei WANG 1463ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1464ff984e57SWei WANG { 1465ff984e57SWei WANG struct mmc_host *mmc; 1466ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1467ff984e57SWei WANG struct rtsx_pcr *pcr; 1468ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1469ff984e57SWei WANG 1470ff984e57SWei WANG if (!handle) 1471ff984e57SWei WANG return -ENXIO; 1472ff984e57SWei WANG 1473ff984e57SWei WANG pcr = handle->pcr; 1474ff984e57SWei WANG if (!pcr) 1475ff984e57SWei WANG return -ENXIO; 1476ff984e57SWei WANG 1477ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1478ff984e57SWei WANG 1479ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1480ff984e57SWei WANG if (!mmc) 1481ff984e57SWei WANG return -ENOMEM; 1482ff984e57SWei WANG 1483ff984e57SWei WANG host = mmc_priv(mmc); 1484ff984e57SWei WANG host->pcr = pcr; 1485ff984e57SWei WANG host->mmc = mmc; 1486ff984e57SWei WANG host->pdev = pdev; 14872057647fSMicky Ching host->cookie = -1; 1488d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 14896291e715SMicky Ching INIT_WORK(&host->work, sd_request); 1490ff984e57SWei WANG platform_set_drvdata(pdev, host); 1491ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1492ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1493ff984e57SWei WANG 149498fcc576SMicky Ching mutex_init(&host->host_mutex); 1495ff984e57SWei WANG 1496ff984e57SWei WANG realtek_init_host(host); 1497ff984e57SWei WANG 14985b4258f6SRicky Wu if (pcr->rtd3_en) { 14995b4258f6SRicky Wu pm_runtime_set_autosuspend_delay(&pdev->dev, 5000); 15005b4258f6SRicky Wu pm_runtime_use_autosuspend(&pdev->dev); 15015b4258f6SRicky Wu pm_runtime_enable(&pdev->dev); 15025b4258f6SRicky Wu } 15035b4258f6SRicky Wu 15045b4258f6SRicky Wu 1505ff984e57SWei WANG mmc_add_host(mmc); 1506ff984e57SWei WANG 1507ff984e57SWei WANG return 0; 1508ff984e57SWei WANG } 1509ff984e57SWei WANG 1510ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1511ff984e57SWei WANG { 1512ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1513ff984e57SWei WANG struct rtsx_pcr *pcr; 1514ff984e57SWei WANG struct mmc_host *mmc; 1515ff984e57SWei WANG 1516ff984e57SWei WANG if (!host) 1517ff984e57SWei WANG return 0; 1518ff984e57SWei WANG 1519ff984e57SWei WANG pcr = host->pcr; 1520ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1521ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1522ff984e57SWei WANG mmc = host->mmc; 1523ff984e57SWei WANG 15245b4258f6SRicky Wu if (pcr->rtd3_en) { 15255b4258f6SRicky Wu pm_runtime_dont_use_autosuspend(&pdev->dev); 15265b4258f6SRicky Wu pm_runtime_disable(&pdev->dev); 15275b4258f6SRicky Wu } 15285b4258f6SRicky Wu 15296291e715SMicky Ching cancel_work_sync(&host->work); 15306291e715SMicky Ching 153198fcc576SMicky Ching mutex_lock(&host->host_mutex); 1532ff984e57SWei WANG if (host->mrq) { 1533ff984e57SWei WANG dev_dbg(&(pdev->dev), 1534ff984e57SWei WANG "%s: Controller removed during transfer\n", 1535ff984e57SWei WANG mmc_hostname(mmc)); 1536ff984e57SWei WANG 153798fcc576SMicky Ching rtsx_pci_complete_unfinished_transfer(pcr); 1538ff984e57SWei WANG 153998fcc576SMicky Ching host->mrq->cmd->error = -ENOMEDIUM; 154098fcc576SMicky Ching if (host->mrq->stop) 154198fcc576SMicky Ching host->mrq->stop->error = -ENOMEDIUM; 154298fcc576SMicky Ching mmc_request_done(mmc, host->mrq); 1543ff984e57SWei WANG } 154498fcc576SMicky Ching mutex_unlock(&host->host_mutex); 1545ff984e57SWei WANG 1546ff984e57SWei WANG mmc_remove_host(mmc); 1547640e09bcSMicky Ching host->eject = true; 1548640e09bcSMicky Ching 15496ea62579SBhaktipriya Shridhar flush_work(&host->work); 15506291e715SMicky Ching 1551ff984e57SWei WANG mmc_free_host(mmc); 1552ff984e57SWei WANG 1553ff984e57SWei WANG dev_dbg(&(pdev->dev), 1554ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1555ff984e57SWei WANG 1556ff984e57SWei WANG return 0; 1557ff984e57SWei WANG } 1558ff984e57SWei WANG 1559f2483b0dSKrzysztof Kozlowski static const struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1560ff984e57SWei WANG { 1561ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1562ff984e57SWei WANG }, { 1563ff984e57SWei WANG /* sentinel */ 1564ff984e57SWei WANG } 1565ff984e57SWei WANG }; 1566ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1567ff984e57SWei WANG 1568ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1569ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1570ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1571ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1572ff984e57SWei WANG .driver = { 1573ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 157421b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1575ff984e57SWei WANG }, 1576ff984e57SWei WANG }; 1577ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1578ff984e57SWei WANG 1579ff984e57SWei WANG MODULE_LICENSE("GPL"); 1580ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1581ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1582