1ff984e57SWei WANG /* Realtek PCI-Express SD/MMC Card Interface driver 2ff984e57SWei WANG * 362282180SWei WANG * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4ff984e57SWei WANG * 5ff984e57SWei WANG * This program is free software; you can redistribute it and/or modify it 6ff984e57SWei WANG * under the terms of the GNU General Public License as published by the 7ff984e57SWei WANG * Free Software Foundation; either version 2, or (at your option) any 8ff984e57SWei WANG * later version. 9ff984e57SWei WANG * 10ff984e57SWei WANG * This program is distributed in the hope that it will be useful, but 11ff984e57SWei WANG * WITHOUT ANY WARRANTY; without even the implied warranty of 12ff984e57SWei WANG * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13ff984e57SWei WANG * General Public License for more details. 14ff984e57SWei WANG * 15ff984e57SWei WANG * You should have received a copy of the GNU General Public License along 16ff984e57SWei WANG * with this program; if not, see <http://www.gnu.org/licenses/>. 17ff984e57SWei WANG * 18ff984e57SWei WANG * Author: 19ff984e57SWei WANG * Wei WANG <wei_wang@realsil.com.cn> 20ff984e57SWei WANG */ 21ff984e57SWei WANG 22ff984e57SWei WANG #include <linux/module.h> 23433e075cSWei WANG #include <linux/slab.h> 24ff984e57SWei WANG #include <linux/highmem.h> 25ff984e57SWei WANG #include <linux/delay.h> 26ff984e57SWei WANG #include <linux/platform_device.h> 276291e715SMicky Ching #include <linux/workqueue.h> 28ff984e57SWei WANG #include <linux/mmc/host.h> 29ff984e57SWei WANG #include <linux/mmc/mmc.h> 30ff984e57SWei WANG #include <linux/mmc/sd.h> 31ff984e57SWei WANG #include <linux/mmc/card.h> 32ff984e57SWei WANG #include <linux/mfd/rtsx_pci.h> 33ff984e57SWei WANG #include <asm/unaligned.h> 34ff984e57SWei WANG 35ff984e57SWei WANG struct realtek_pci_sdmmc { 36ff984e57SWei WANG struct platform_device *pdev; 37ff984e57SWei WANG struct rtsx_pcr *pcr; 38ff984e57SWei WANG struct mmc_host *mmc; 39ff984e57SWei WANG struct mmc_request *mrq; 406291e715SMicky Ching struct workqueue_struct *workq; 416291e715SMicky Ching #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" 42ff984e57SWei WANG 436291e715SMicky Ching struct work_struct work; 4498fcc576SMicky Ching struct mutex host_mutex; 45ff984e57SWei WANG 46ff984e57SWei WANG u8 ssc_depth; 47ff984e57SWei WANG unsigned int clock; 48ff984e57SWei WANG bool vpclk; 49ff984e57SWei WANG bool double_clk; 50ff984e57SWei WANG bool eject; 51ff984e57SWei WANG bool initial_mode; 52d88691beSWei WANG int power_state; 53d88691beSWei WANG #define SDMMC_POWER_ON 1 54d88691beSWei WANG #define SDMMC_POWER_OFF 0 556291e715SMicky Ching 566291e715SMicky Ching unsigned int sg_count; 576291e715SMicky Ching s32 cookie; 586291e715SMicky Ching unsigned int cookie_sg_count; 596291e715SMicky Ching bool using_cookie; 60ff984e57SWei WANG }; 61ff984e57SWei WANG 62ff984e57SWei WANG static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 63ff984e57SWei WANG { 64ff984e57SWei WANG return &(host->pdev->dev); 65ff984e57SWei WANG } 66ff984e57SWei WANG 67ff984e57SWei WANG static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 68ff984e57SWei WANG { 69ff984e57SWei WANG rtsx_pci_write_register(host->pcr, CARD_STOP, 70ff984e57SWei WANG SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 71ff984e57SWei WANG } 72ff984e57SWei WANG 73ff984e57SWei WANG #ifdef DEBUG 74755987f9SMicky Ching static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end) 75755987f9SMicky Ching { 76755987f9SMicky Ching u16 len = end - start + 1; 77755987f9SMicky Ching int i; 78755987f9SMicky Ching u8 data[8]; 79755987f9SMicky Ching 80755987f9SMicky Ching for (i = 0; i < len; i += 8) { 81755987f9SMicky Ching int j; 82755987f9SMicky Ching int n = min(8, len - i); 83755987f9SMicky Ching 84755987f9SMicky Ching memset(&data, 0, sizeof(data)); 85755987f9SMicky Ching for (j = 0; j < n; j++) 86755987f9SMicky Ching rtsx_pci_read_register(host->pcr, start + i + j, 87755987f9SMicky Ching data + j); 88755987f9SMicky Ching dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n", 89755987f9SMicky Ching start + i, n, data); 90755987f9SMicky Ching } 91755987f9SMicky Ching } 92755987f9SMicky Ching 93ff984e57SWei WANG static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 94ff984e57SWei WANG { 95755987f9SMicky Ching dump_reg_range(host, 0xFDA0, 0xFDB3); 96755987f9SMicky Ching dump_reg_range(host, 0xFD52, 0xFD69); 97ff984e57SWei WANG } 98ff984e57SWei WANG #else 99ff984e57SWei WANG #define sd_print_debug_regs(host) 100ff984e57SWei WANG #endif /* DEBUG */ 101ff984e57SWei WANG 1022d48e5f1SMicky Ching static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd) 1032d48e5f1SMicky Ching { 1042d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 1052d48e5f1SMicky Ching SD_CMD_START | cmd->opcode); 1062d48e5f1SMicky Ching rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg); 1072d48e5f1SMicky Ching } 1082d48e5f1SMicky Ching 1092d48e5f1SMicky Ching static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz) 1102d48e5f1SMicky Ching { 1112d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); 1122d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); 1132d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); 1142d48e5f1SMicky Ching rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); 1152d48e5f1SMicky Ching } 1162d48e5f1SMicky Ching 1172d48e5f1SMicky Ching static int sd_response_type(struct mmc_command *cmd) 1182d48e5f1SMicky Ching { 1192d48e5f1SMicky Ching switch (mmc_resp_type(cmd)) { 1202d48e5f1SMicky Ching case MMC_RSP_NONE: 1212d48e5f1SMicky Ching return SD_RSP_TYPE_R0; 1222d48e5f1SMicky Ching case MMC_RSP_R1: 1232d48e5f1SMicky Ching return SD_RSP_TYPE_R1; 1242d48e5f1SMicky Ching case MMC_RSP_R1 & ~MMC_RSP_CRC: 1252d48e5f1SMicky Ching return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; 1262d48e5f1SMicky Ching case MMC_RSP_R1B: 1272d48e5f1SMicky Ching return SD_RSP_TYPE_R1b; 1282d48e5f1SMicky Ching case MMC_RSP_R2: 1292d48e5f1SMicky Ching return SD_RSP_TYPE_R2; 1302d48e5f1SMicky Ching case MMC_RSP_R3: 1312d48e5f1SMicky Ching return SD_RSP_TYPE_R3; 1322d48e5f1SMicky Ching default: 1332d48e5f1SMicky Ching return -EINVAL; 1342d48e5f1SMicky Ching } 1352d48e5f1SMicky Ching } 1362d48e5f1SMicky Ching 1372d48e5f1SMicky Ching static int sd_status_index(int resp_type) 1382d48e5f1SMicky Ching { 1392d48e5f1SMicky Ching if (resp_type == SD_RSP_TYPE_R0) 1402d48e5f1SMicky Ching return 0; 1412d48e5f1SMicky Ching else if (resp_type == SD_RSP_TYPE_R2) 1422d48e5f1SMicky Ching return 16; 1432d48e5f1SMicky Ching 1442d48e5f1SMicky Ching return 5; 1452d48e5f1SMicky Ching } 1466291e715SMicky Ching /* 1476291e715SMicky Ching * sd_pre_dma_transfer - do dma_map_sg() or using cookie 1486291e715SMicky Ching * 1496291e715SMicky Ching * @pre: if called in pre_req() 1506291e715SMicky Ching * return: 1516291e715SMicky Ching * 0 - do dma_map_sg() 1526291e715SMicky Ching * 1 - using cookie 1536291e715SMicky Ching */ 1546291e715SMicky Ching static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, 1556291e715SMicky Ching struct mmc_data *data, bool pre) 1566291e715SMicky Ching { 1576291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 1586291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 1596291e715SMicky Ching int count = 0; 1606291e715SMicky Ching int using_cookie = 0; 1616291e715SMicky Ching 1626291e715SMicky Ching if (!pre && data->host_cookie && data->host_cookie != host->cookie) { 1636291e715SMicky Ching dev_err(sdmmc_dev(host), 1646291e715SMicky Ching "error: data->host_cookie = %d, host->cookie = %d\n", 1656291e715SMicky Ching data->host_cookie, host->cookie); 1666291e715SMicky Ching data->host_cookie = 0; 1676291e715SMicky Ching } 1686291e715SMicky Ching 1696291e715SMicky Ching if (pre || data->host_cookie != host->cookie) { 1706291e715SMicky Ching count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); 1716291e715SMicky Ching } else { 1726291e715SMicky Ching count = host->cookie_sg_count; 1736291e715SMicky Ching using_cookie = 1; 1746291e715SMicky Ching } 1756291e715SMicky Ching 1766291e715SMicky Ching if (pre) { 1776291e715SMicky Ching host->cookie_sg_count = count; 1786291e715SMicky Ching if (++host->cookie < 0) 1796291e715SMicky Ching host->cookie = 1; 1806291e715SMicky Ching data->host_cookie = host->cookie; 1816291e715SMicky Ching } else { 1826291e715SMicky Ching host->sg_count = count; 1836291e715SMicky Ching } 1846291e715SMicky Ching 1856291e715SMicky Ching return using_cookie; 1866291e715SMicky Ching } 1876291e715SMicky Ching 1886291e715SMicky Ching static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 1896291e715SMicky Ching bool is_first_req) 1906291e715SMicky Ching { 1916291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1926291e715SMicky Ching struct mmc_data *data = mrq->data; 1936291e715SMicky Ching 1946291e715SMicky Ching if (data->host_cookie) { 1956291e715SMicky Ching dev_err(sdmmc_dev(host), 1966291e715SMicky Ching "error: reset data->host_cookie = %d\n", 1976291e715SMicky Ching data->host_cookie); 1986291e715SMicky Ching data->host_cookie = 0; 1996291e715SMicky Ching } 2006291e715SMicky Ching 2016291e715SMicky Ching sd_pre_dma_transfer(host, data, true); 2026291e715SMicky Ching dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); 2036291e715SMicky Ching } 2046291e715SMicky Ching 2056291e715SMicky Ching static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2066291e715SMicky Ching int err) 2076291e715SMicky Ching { 2086291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 2096291e715SMicky Ching struct rtsx_pcr *pcr = host->pcr; 2106291e715SMicky Ching struct mmc_data *data = mrq->data; 2116291e715SMicky Ching int read = data->flags & MMC_DATA_READ; 2126291e715SMicky Ching 2136291e715SMicky Ching rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); 2146291e715SMicky Ching data->host_cookie = 0; 2156291e715SMicky Ching } 2166291e715SMicky Ching 217ff984e57SWei WANG static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 218ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 219ff984e57SWei WANG { 220ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 221ff984e57SWei WANG int err, i; 222ff984e57SWei WANG u8 trans_mode; 223ff984e57SWei WANG 224ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40); 225ff984e57SWei WANG 226ff984e57SWei WANG if (!buf) 227ff984e57SWei WANG buf_len = 0; 228ff984e57SWei WANG 229ff984e57SWei WANG if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK) 230ff984e57SWei WANG trans_mode = SD_TM_AUTO_TUNING; 231ff984e57SWei WANG else 232ff984e57SWei WANG trans_mode = SD_TM_NORMAL_READ; 233ff984e57SWei WANG 234ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 235ff984e57SWei WANG 236ff984e57SWei WANG for (i = 0; i < 5; i++) 237ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]); 238ff984e57SWei WANG 239ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 240ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 241ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 242ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 243ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 244ff984e57SWei WANG 245ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 246ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 247ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 248ff984e57SWei WANG if (trans_mode != SD_TM_AUTO_TUNING) 249ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 250ff984e57SWei WANG CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 251ff984e57SWei WANG 252ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 253ff984e57SWei WANG 0xFF, trans_mode | SD_TRANSFER_START); 254ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 255ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 256ff984e57SWei WANG 257ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 258ff984e57SWei WANG if (err < 0) { 259ff984e57SWei WANG sd_print_debug_regs(host); 260ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 261ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 262ff984e57SWei WANG return err; 263ff984e57SWei WANG } 264ff984e57SWei WANG 265ff984e57SWei WANG if (buf && buf_len) { 266ff984e57SWei WANG err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 267ff984e57SWei WANG if (err < 0) { 268ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 269ff984e57SWei WANG "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 270ff984e57SWei WANG return err; 271ff984e57SWei WANG } 272ff984e57SWei WANG } 273ff984e57SWei WANG 274ff984e57SWei WANG return 0; 275ff984e57SWei WANG } 276ff984e57SWei WANG 277ff984e57SWei WANG static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, 278ff984e57SWei WANG u8 *buf, int buf_len, int timeout) 279ff984e57SWei WANG { 280ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 281ff984e57SWei WANG int err, i; 282ff984e57SWei WANG u8 trans_mode; 283ff984e57SWei WANG 284ff984e57SWei WANG if (!buf) 285ff984e57SWei WANG buf_len = 0; 286ff984e57SWei WANG 287ff984e57SWei WANG if (buf && buf_len) { 288ff984e57SWei WANG err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 289ff984e57SWei WANG if (err < 0) { 290ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 291ff984e57SWei WANG "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 292ff984e57SWei WANG return err; 293ff984e57SWei WANG } 294ff984e57SWei WANG } 295ff984e57SWei WANG 296ff984e57SWei WANG trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3; 297ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 298ff984e57SWei WANG 299ff984e57SWei WANG if (cmd) { 300ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__, 301ff984e57SWei WANG cmd[0] - 0x40); 302ff984e57SWei WANG 303ff984e57SWei WANG for (i = 0; i < 5; i++) 304ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 305ff984e57SWei WANG SD_CMD0 + i, 0xFF, cmd[i]); 306ff984e57SWei WANG } 307ff984e57SWei WANG 308ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); 309ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 310ff984e57SWei WANG 0xFF, (u8)(byte_cnt >> 8)); 311ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); 312ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); 313ff984e57SWei WANG 314ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 315ff984e57SWei WANG SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 316ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 317ff984e57SWei WANG 318ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 319ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 320ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 321ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 322ff984e57SWei WANG 323ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, timeout); 324ff984e57SWei WANG if (err < 0) { 325ff984e57SWei WANG sd_print_debug_regs(host); 326ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 327ff984e57SWei WANG "rtsx_pci_send_cmd fail (err = %d)\n", err); 328ff984e57SWei WANG return err; 329ff984e57SWei WANG } 330ff984e57SWei WANG 331ff984e57SWei WANG return 0; 332ff984e57SWei WANG } 333ff984e57SWei WANG 33498fcc576SMicky Ching static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 33598fcc576SMicky Ching struct mmc_command *cmd) 336ff984e57SWei WANG { 337ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 338ff984e57SWei WANG u8 cmd_idx = (u8)cmd->opcode; 339ff984e57SWei WANG u32 arg = cmd->arg; 340ff984e57SWei WANG int err = 0; 341ff984e57SWei WANG int timeout = 100; 342ff984e57SWei WANG int i; 34398fcc576SMicky Ching u8 *ptr; 3442d48e5f1SMicky Ching int rsp_type; 3452d48e5f1SMicky Ching int stat_idx; 34698fcc576SMicky Ching bool clock_toggled = false; 347ff984e57SWei WANG 348ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 349ff984e57SWei WANG __func__, cmd_idx, arg); 350ff984e57SWei WANG 3512d48e5f1SMicky Ching rsp_type = sd_response_type(cmd); 3522d48e5f1SMicky Ching if (rsp_type < 0) 353ff984e57SWei WANG goto out; 3542d48e5f1SMicky Ching 3552d48e5f1SMicky Ching stat_idx = sd_status_index(rsp_type); 356ff984e57SWei WANG 357ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R1b) 358ff984e57SWei WANG timeout = 3000; 359ff984e57SWei WANG 360ff984e57SWei WANG if (cmd->opcode == SD_SWITCH_VOLTAGE) { 361ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 362ff984e57SWei WANG 0xFF, SD_CLK_TOGGLE_EN); 363ff984e57SWei WANG if (err < 0) 364ff984e57SWei WANG goto out; 36598fcc576SMicky Ching 36698fcc576SMicky Ching clock_toggled = true; 367ff984e57SWei WANG } 368ff984e57SWei WANG 369ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 3702d48e5f1SMicky Ching sd_cmd_set_sd_cmd(pcr, cmd); 371ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 372ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 373ff984e57SWei WANG 0x01, PINGPONG_BUFFER); 374ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 375ff984e57SWei WANG 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 376ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 377ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE, 378ff984e57SWei WANG SD_TRANSFER_END | SD_STAT_IDLE); 379ff984e57SWei WANG 380ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 381ff984e57SWei WANG /* Read data from ping-pong buffer */ 382ff984e57SWei WANG for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 383ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 384ff984e57SWei WANG } else if (rsp_type != SD_RSP_TYPE_R0) { 385ff984e57SWei WANG /* Read data from SD_CMDx registers */ 386ff984e57SWei WANG for (i = SD_CMD0; i <= SD_CMD4; i++) 387ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 388ff984e57SWei WANG } 389ff984e57SWei WANG 390ff984e57SWei WANG rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 391ff984e57SWei WANG 39298fcc576SMicky Ching err = rtsx_pci_send_cmd(pcr, timeout); 39398fcc576SMicky Ching if (err < 0) { 39498fcc576SMicky Ching sd_print_debug_regs(host); 39598fcc576SMicky Ching sd_clear_error(host); 39698fcc576SMicky Ching dev_dbg(sdmmc_dev(host), 39798fcc576SMicky Ching "rtsx_pci_send_cmd error (err = %d)\n", err); 398ff984e57SWei WANG goto out; 399ff984e57SWei WANG } 400ff984e57SWei WANG 401ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R0) { 402ff984e57SWei WANG err = 0; 403ff984e57SWei WANG goto out; 404ff984e57SWei WANG } 405ff984e57SWei WANG 406ff984e57SWei WANG /* Eliminate returned value of CHECK_REG_CMD */ 407ff984e57SWei WANG ptr = rtsx_pci_get_cmd_data(pcr) + 1; 408ff984e57SWei WANG 409ff984e57SWei WANG /* Check (Start,Transmission) bit of Response */ 410ff984e57SWei WANG if ((ptr[0] & 0xC0) != 0) { 411ff984e57SWei WANG err = -EILSEQ; 412ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 413ff984e57SWei WANG goto out; 414ff984e57SWei WANG } 415ff984e57SWei WANG 416ff984e57SWei WANG /* Check CRC7 */ 417ff984e57SWei WANG if (!(rsp_type & SD_NO_CHECK_CRC7)) { 418ff984e57SWei WANG if (ptr[stat_idx] & SD_CRC7_ERR) { 419ff984e57SWei WANG err = -EILSEQ; 420ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 421ff984e57SWei WANG goto out; 422ff984e57SWei WANG } 423ff984e57SWei WANG } 424ff984e57SWei WANG 425ff984e57SWei WANG if (rsp_type == SD_RSP_TYPE_R2) { 426d1419d50SRoger Tseng /* 427d1419d50SRoger Tseng * The controller offloads the last byte {CRC-7, end bit 1'b1} 428d1419d50SRoger Tseng * of response type R2. Assign dummy CRC, 0, and end bit to the 429d1419d50SRoger Tseng * byte(ptr[16], goes into the LSB of resp[3] later). 430d1419d50SRoger Tseng */ 431d1419d50SRoger Tseng ptr[16] = 1; 432d1419d50SRoger Tseng 433ff984e57SWei WANG for (i = 0; i < 4; i++) { 434ff984e57SWei WANG cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 435ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 436ff984e57SWei WANG i, cmd->resp[i]); 437ff984e57SWei WANG } 438ff984e57SWei WANG } else { 439ff984e57SWei WANG cmd->resp[0] = get_unaligned_be32(ptr + 1); 440ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 441ff984e57SWei WANG cmd->resp[0]); 442ff984e57SWei WANG } 443ff984e57SWei WANG 444ff984e57SWei WANG out: 445ff984e57SWei WANG cmd->error = err; 4461b8055b4SWei WANG 44798fcc576SMicky Ching if (err && clock_toggled) 44898fcc576SMicky Ching rtsx_pci_write_register(pcr, SD_BUS_STAT, 44998fcc576SMicky Ching SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 450ff984e57SWei WANG } 451ff984e57SWei WANG 45298fcc576SMicky Ching static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 453ff984e57SWei WANG { 454ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 455ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 456ff984e57SWei WANG struct mmc_card *card = mmc->card; 457ff984e57SWei WANG struct mmc_data *data = mrq->data; 45871ef1ea4SJackey Shen int uhs = mmc_card_uhs(card); 45998fcc576SMicky Ching int read = (data->flags & MMC_DATA_READ) ? 1 : 0; 460ff984e57SWei WANG u8 cfg2, trans_mode; 461ff984e57SWei WANG int err; 462ff984e57SWei WANG size_t data_len = data->blksz * data->blocks; 463ff984e57SWei WANG 464ff984e57SWei WANG if (read) { 465ff984e57SWei WANG cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 466ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0; 467ff984e57SWei WANG trans_mode = SD_TM_AUTO_READ_3; 468ff984e57SWei WANG } else { 469ff984e57SWei WANG cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 470ff984e57SWei WANG SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 471ff984e57SWei WANG trans_mode = SD_TM_AUTO_WRITE_3; 472ff984e57SWei WANG } 473ff984e57SWei WANG 474ff984e57SWei WANG if (!uhs) 475ff984e57SWei WANG cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 476ff984e57SWei WANG 477ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 478ff984e57SWei WANG 479ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00); 480ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02); 481ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 482ff984e57SWei WANG 0xFF, (u8)data->blocks); 483ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 484ff984e57SWei WANG 0xFF, (u8)(data->blocks >> 8)); 485ff984e57SWei WANG 486ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 487ff984e57SWei WANG DMA_DONE_INT, DMA_DONE_INT); 488ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 489ff984e57SWei WANG 0xFF, (u8)(data_len >> 24)); 490ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 491ff984e57SWei WANG 0xFF, (u8)(data_len >> 16)); 492ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 493ff984e57SWei WANG 0xFF, (u8)(data_len >> 8)); 494ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 495ff984e57SWei WANG if (read) { 496ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 497ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 498ff984e57SWei WANG DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 499ff984e57SWei WANG } else { 500ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 501ff984e57SWei WANG 0x03 | DMA_PACK_SIZE_MASK, 502ff984e57SWei WANG DMA_DIR_TO_CARD | DMA_EN | DMA_512); 503ff984e57SWei WANG } 504ff984e57SWei WANG 505ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 506ff984e57SWei WANG 0x01, RING_BUFFER); 507ff984e57SWei WANG 50838d324dfSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 509ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 510ff984e57SWei WANG trans_mode | SD_TRANSFER_START); 511ff984e57SWei WANG rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 512ff984e57SWei WANG SD_TRANSFER_END, SD_TRANSFER_END); 513ff984e57SWei WANG 514ff984e57SWei WANG rtsx_pci_send_cmd_no_wait(pcr); 515ff984e57SWei WANG 5166291e715SMicky Ching err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, read, 10000); 517ff984e57SWei WANG if (err < 0) { 51898fcc576SMicky Ching sd_clear_error(host); 51998fcc576SMicky Ching return err; 520c42deffdSMicky Ching } 52198fcc576SMicky Ching 522c42deffdSMicky Ching return 0; 523ff984e57SWei WANG } 524ff984e57SWei WANG 525ff984e57SWei WANG static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 526ff984e57SWei WANG { 527ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 528ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 529ff984e57SWei WANG } 530ff984e57SWei WANG 531ff984e57SWei WANG static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 532ff984e57SWei WANG { 533ff984e57SWei WANG rtsx_pci_write_register(host->pcr, SD_CFG1, 534ff984e57SWei WANG SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 535ff984e57SWei WANG } 536ff984e57SWei WANG 537ff984e57SWei WANG static void sd_normal_rw(struct realtek_pci_sdmmc *host, 538ff984e57SWei WANG struct mmc_request *mrq) 539ff984e57SWei WANG { 540ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 541ff984e57SWei WANG struct mmc_data *data = mrq->data; 542ff984e57SWei WANG u8 _cmd[5], *buf; 543ff984e57SWei WANG 544ff984e57SWei WANG _cmd[0] = 0x40 | (u8)cmd->opcode; 545ff984e57SWei WANG put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1])); 546ff984e57SWei WANG 547ff984e57SWei WANG buf = kzalloc(data->blksz, GFP_NOIO); 548ff984e57SWei WANG if (!buf) { 549ff984e57SWei WANG cmd->error = -ENOMEM; 550ff984e57SWei WANG return; 551ff984e57SWei WANG } 552ff984e57SWei WANG 553ff984e57SWei WANG if (data->flags & MMC_DATA_READ) { 554ff984e57SWei WANG if (host->initial_mode) 555ff984e57SWei WANG sd_disable_initial_mode(host); 556ff984e57SWei WANG 557ff984e57SWei WANG cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf, 558ff984e57SWei WANG data->blksz, 200); 559ff984e57SWei WANG 560ff984e57SWei WANG if (host->initial_mode) 561ff984e57SWei WANG sd_enable_initial_mode(host); 562ff984e57SWei WANG 563ff984e57SWei WANG sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 564ff984e57SWei WANG } else { 565ff984e57SWei WANG sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 566ff984e57SWei WANG 567ff984e57SWei WANG cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf, 568ff984e57SWei WANG data->blksz, 200); 569ff984e57SWei WANG } 570ff984e57SWei WANG 571ff984e57SWei WANG kfree(buf); 572ff984e57SWei WANG } 573ff984e57SWei WANG 57484d72f9cSWei WANG static int sd_change_phase(struct realtek_pci_sdmmc *host, 57584d72f9cSWei WANG u8 sample_point, bool rx) 576ff984e57SWei WANG { 577ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 578ff984e57SWei WANG int err; 579ff984e57SWei WANG 58084d72f9cSWei WANG dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 58184d72f9cSWei WANG __func__, rx ? "RX" : "TX", sample_point); 582ff984e57SWei WANG 583ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 584ff984e57SWei WANG 585ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 58684d72f9cSWei WANG if (rx) 58784d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 58884d72f9cSWei WANG SD_VPRX_CTL, 0x1F, sample_point); 58984d72f9cSWei WANG else 59084d72f9cSWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 59184d72f9cSWei WANG SD_VPTX_CTL, 0x1F, sample_point); 592ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); 593ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 594ff984e57SWei WANG PHASE_NOT_RESET, PHASE_NOT_RESET); 595ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); 596ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 597ff984e57SWei WANG 598ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 599ff984e57SWei WANG if (err < 0) 600ff984e57SWei WANG return err; 601ff984e57SWei WANG 602ff984e57SWei WANG return 0; 603ff984e57SWei WANG } 604ff984e57SWei WANG 605abcc6b29SMicky Ching static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 606abcc6b29SMicky Ching { 607abcc6b29SMicky Ching bit %= RTSX_PHASE_MAX; 608abcc6b29SMicky Ching return phase_map & (1 << bit); 609abcc6b29SMicky Ching } 610abcc6b29SMicky Ching 611abcc6b29SMicky Ching static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 612abcc6b29SMicky Ching { 613abcc6b29SMicky Ching int i; 614abcc6b29SMicky Ching 615abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 616abcc6b29SMicky Ching if (test_phase_bit(phase_map, start_bit + i) == 0) 617abcc6b29SMicky Ching return i; 618abcc6b29SMicky Ching } 619abcc6b29SMicky Ching return RTSX_PHASE_MAX; 620abcc6b29SMicky Ching } 621abcc6b29SMicky Ching 622ff984e57SWei WANG static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 623ff984e57SWei WANG { 624abcc6b29SMicky Ching int start = 0, len = 0; 625abcc6b29SMicky Ching int start_final = 0, len_final = 0; 626ff984e57SWei WANG u8 final_phase = 0xFF; 627ff984e57SWei WANG 628abcc6b29SMicky Ching if (phase_map == 0) { 629abcc6b29SMicky Ching dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 630abcc6b29SMicky Ching return final_phase; 631ff984e57SWei WANG } 632ff984e57SWei WANG 633abcc6b29SMicky Ching while (start < RTSX_PHASE_MAX) { 634abcc6b29SMicky Ching len = sd_get_phase_len(phase_map, start); 635abcc6b29SMicky Ching if (len_final < len) { 636abcc6b29SMicky Ching start_final = start; 637abcc6b29SMicky Ching len_final = len; 638abcc6b29SMicky Ching } 639abcc6b29SMicky Ching start += len ? len : 1; 640ff984e57SWei WANG } 641ff984e57SWei WANG 642abcc6b29SMicky Ching final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 643abcc6b29SMicky Ching dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 644abcc6b29SMicky Ching phase_map, len_final, final_phase); 645ff984e57SWei WANG 646ff984e57SWei WANG return final_phase; 647ff984e57SWei WANG } 648ff984e57SWei WANG 649ff984e57SWei WANG static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 650ff984e57SWei WANG { 651ff984e57SWei WANG int err, i; 652ff984e57SWei WANG u8 val = 0; 653ff984e57SWei WANG 654ff984e57SWei WANG for (i = 0; i < 100; i++) { 655ff984e57SWei WANG err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 656ff984e57SWei WANG if (val & SD_DATA_IDLE) 657ff984e57SWei WANG return; 658ff984e57SWei WANG 659ff984e57SWei WANG udelay(100); 660ff984e57SWei WANG } 661ff984e57SWei WANG } 662ff984e57SWei WANG 663ff984e57SWei WANG static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 664ff984e57SWei WANG u8 opcode, u8 sample_point) 665ff984e57SWei WANG { 666ff984e57SWei WANG int err; 667ff984e57SWei WANG u8 cmd[5] = {0}; 668ff984e57SWei WANG 66984d72f9cSWei WANG err = sd_change_phase(host, sample_point, true); 670ff984e57SWei WANG if (err < 0) 671ff984e57SWei WANG return err; 672ff984e57SWei WANG 673ff984e57SWei WANG cmd[0] = 0x40 | opcode; 674ff984e57SWei WANG err = sd_read_data(host, cmd, 0x40, NULL, 0, 100); 675ff984e57SWei WANG if (err < 0) { 676ff984e57SWei WANG /* Wait till SD DATA IDLE */ 677ff984e57SWei WANG sd_wait_data_idle(host); 678ff984e57SWei WANG sd_clear_error(host); 679ff984e57SWei WANG return err; 680ff984e57SWei WANG } 681ff984e57SWei WANG 682ff984e57SWei WANG return 0; 683ff984e57SWei WANG } 684ff984e57SWei WANG 685ff984e57SWei WANG static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 686ff984e57SWei WANG u8 opcode, u32 *phase_map) 687ff984e57SWei WANG { 688ff984e57SWei WANG int err, i; 689ff984e57SWei WANG u32 raw_phase_map = 0; 690ff984e57SWei WANG 691abcc6b29SMicky Ching for (i = 0; i < RTSX_PHASE_MAX; i++) { 692ff984e57SWei WANG err = sd_tuning_rx_cmd(host, opcode, (u8)i); 693ff984e57SWei WANG if (err == 0) 694ff984e57SWei WANG raw_phase_map |= 1 << i; 695ff984e57SWei WANG } 696ff984e57SWei WANG 697ff984e57SWei WANG if (phase_map) 698ff984e57SWei WANG *phase_map = raw_phase_map; 699ff984e57SWei WANG 700ff984e57SWei WANG return 0; 701ff984e57SWei WANG } 702ff984e57SWei WANG 703ff984e57SWei WANG static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 704ff984e57SWei WANG { 705ff984e57SWei WANG int err, i; 706ff984e57SWei WANG u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 707ff984e57SWei WANG u8 final_phase; 708ff984e57SWei WANG 709ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 710ff984e57SWei WANG err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 711ff984e57SWei WANG if (err < 0) 712ff984e57SWei WANG return err; 713ff984e57SWei WANG 714ff984e57SWei WANG if (raw_phase_map[i] == 0) 715ff984e57SWei WANG break; 716ff984e57SWei WANG } 717ff984e57SWei WANG 718ff984e57SWei WANG phase_map = 0xFFFFFFFF; 719ff984e57SWei WANG for (i = 0; i < RX_TUNING_CNT; i++) { 720ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 721ff984e57SWei WANG i, raw_phase_map[i]); 722ff984e57SWei WANG phase_map &= raw_phase_map[i]; 723ff984e57SWei WANG } 724ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 725ff984e57SWei WANG 726ff984e57SWei WANG if (phase_map) { 727ff984e57SWei WANG final_phase = sd_search_final_phase(host, phase_map); 728ff984e57SWei WANG if (final_phase == 0xFF) 729ff984e57SWei WANG return -EINVAL; 730ff984e57SWei WANG 73184d72f9cSWei WANG err = sd_change_phase(host, final_phase, true); 732ff984e57SWei WANG if (err < 0) 733ff984e57SWei WANG return err; 734ff984e57SWei WANG } else { 735ff984e57SWei WANG return -EINVAL; 736ff984e57SWei WANG } 737ff984e57SWei WANG 738ff984e57SWei WANG return 0; 739ff984e57SWei WANG } 740ff984e57SWei WANG 7416291e715SMicky Ching static inline int sd_rw_cmd(struct mmc_command *cmd) 742ff984e57SWei WANG { 7436291e715SMicky Ching return mmc_op_multi(cmd->opcode) || 7446291e715SMicky Ching (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 7456291e715SMicky Ching (cmd->opcode == MMC_WRITE_BLOCK); 7466291e715SMicky Ching } 7476291e715SMicky Ching 7486291e715SMicky Ching static void sd_request(struct work_struct *work) 7496291e715SMicky Ching { 7506291e715SMicky Ching struct realtek_pci_sdmmc *host = container_of(work, 7516291e715SMicky Ching struct realtek_pci_sdmmc, work); 752ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 7536291e715SMicky Ching 7546291e715SMicky Ching struct mmc_host *mmc = host->mmc; 7556291e715SMicky Ching struct mmc_request *mrq = host->mrq; 756ff984e57SWei WANG struct mmc_command *cmd = mrq->cmd; 757ff984e57SWei WANG struct mmc_data *data = mrq->data; 7586291e715SMicky Ching 759ff984e57SWei WANG unsigned int data_size = 0; 760c3481955SWei WANG int err; 761ff984e57SWei WANG 762ff984e57SWei WANG if (host->eject) { 763ff984e57SWei WANG cmd->error = -ENOMEDIUM; 764ff984e57SWei WANG goto finish; 765ff984e57SWei WANG } 766ff984e57SWei WANG 767c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 768c3481955SWei WANG if (err) { 769c3481955SWei WANG cmd->error = err; 770c3481955SWei WANG goto finish; 771c3481955SWei WANG } 772c3481955SWei WANG 77398fcc576SMicky Ching mutex_lock(&pcr->pcr_mutex); 77498fcc576SMicky Ching 775ff984e57SWei WANG rtsx_pci_start_run(pcr); 776ff984e57SWei WANG 777ff984e57SWei WANG rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 778ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 779ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 780ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 781ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 782ff984e57SWei WANG 78398fcc576SMicky Ching mutex_lock(&host->host_mutex); 78498fcc576SMicky Ching host->mrq = mrq; 78598fcc576SMicky Ching mutex_unlock(&host->host_mutex); 78698fcc576SMicky Ching 787ff984e57SWei WANG if (mrq->data) 788ff984e57SWei WANG data_size = data->blocks * data->blksz; 789ff984e57SWei WANG 7906291e715SMicky Ching if (!data_size || sd_rw_cmd(cmd)) { 79198fcc576SMicky Ching sd_send_cmd_get_rsp(host, cmd); 792ff984e57SWei WANG 79398fcc576SMicky Ching if (!cmd->error && data_size) { 79498fcc576SMicky Ching sd_rw_multi(host, mrq); 7956291e715SMicky Ching if (!host->using_cookie) 7966291e715SMicky Ching sdmmc_post_req(host->mmc, host->mrq, 0); 79798fcc576SMicky Ching 79898fcc576SMicky Ching if (mmc_op_multi(cmd->opcode) && mrq->stop) 79998fcc576SMicky Ching sd_send_cmd_get_rsp(host, mrq->stop); 800ff984e57SWei WANG } 80198fcc576SMicky Ching } else { 80298fcc576SMicky Ching sd_normal_rw(host, mrq); 80398fcc576SMicky Ching } 80498fcc576SMicky Ching 80598fcc576SMicky Ching if (mrq->data) { 80698fcc576SMicky Ching if (cmd->error || data->error) 80798fcc576SMicky Ching data->bytes_xfered = 0; 80898fcc576SMicky Ching else 80998fcc576SMicky Ching data->bytes_xfered = data->blocks * data->blksz; 81098fcc576SMicky Ching } 81198fcc576SMicky Ching 81298fcc576SMicky Ching mutex_unlock(&pcr->pcr_mutex); 813ff984e57SWei WANG 814ff984e57SWei WANG finish: 81598fcc576SMicky Ching if (cmd->error) 81698fcc576SMicky Ching dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error); 81798fcc576SMicky Ching 81898fcc576SMicky Ching mutex_lock(&host->host_mutex); 81998fcc576SMicky Ching host->mrq = NULL; 82098fcc576SMicky Ching mutex_unlock(&host->host_mutex); 82198fcc576SMicky Ching 82298fcc576SMicky Ching mmc_request_done(mmc, mrq); 823ff984e57SWei WANG } 824ff984e57SWei WANG 8256291e715SMicky Ching static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 8266291e715SMicky Ching { 8276291e715SMicky Ching struct realtek_pci_sdmmc *host = mmc_priv(mmc); 8286291e715SMicky Ching struct mmc_data *data = mrq->data; 8296291e715SMicky Ching 8306291e715SMicky Ching mutex_lock(&host->host_mutex); 8316291e715SMicky Ching host->mrq = mrq; 8326291e715SMicky Ching mutex_unlock(&host->host_mutex); 8336291e715SMicky Ching 8346291e715SMicky Ching if (sd_rw_cmd(mrq->cmd)) 8356291e715SMicky Ching host->using_cookie = sd_pre_dma_transfer(host, data, false); 8366291e715SMicky Ching 8376291e715SMicky Ching queue_work(host->workq, &host->work); 8386291e715SMicky Ching } 8396291e715SMicky Ching 840ff984e57SWei WANG static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 841ff984e57SWei WANG unsigned char bus_width) 842ff984e57SWei WANG { 843ff984e57SWei WANG int err = 0; 844ff984e57SWei WANG u8 width[] = { 845ff984e57SWei WANG [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 846ff984e57SWei WANG [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 847ff984e57SWei WANG [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 848ff984e57SWei WANG }; 849ff984e57SWei WANG 850ff984e57SWei WANG if (bus_width <= MMC_BUS_WIDTH_8) 851ff984e57SWei WANG err = rtsx_pci_write_register(host->pcr, SD_CFG1, 852ff984e57SWei WANG 0x03, width[bus_width]); 853ff984e57SWei WANG 854ff984e57SWei WANG return err; 855ff984e57SWei WANG } 856ff984e57SWei WANG 857ff984e57SWei WANG static int sd_power_on(struct realtek_pci_sdmmc *host) 858ff984e57SWei WANG { 859ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 860ff984e57SWei WANG int err; 861ff984e57SWei WANG 862d88691beSWei WANG if (host->power_state == SDMMC_POWER_ON) 863d88691beSWei WANG return 0; 864d88691beSWei WANG 865ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 866ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 867ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 868ff984e57SWei WANG CARD_SHARE_MASK, CARD_SHARE_48_SD); 869ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 870ff984e57SWei WANG SD_CLK_EN, SD_CLK_EN); 871ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 872ff984e57SWei WANG if (err < 0) 873ff984e57SWei WANG return err; 874ff984e57SWei WANG 875ff984e57SWei WANG err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 876ff984e57SWei WANG if (err < 0) 877ff984e57SWei WANG return err; 878ff984e57SWei WANG 879ff984e57SWei WANG err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 880ff984e57SWei WANG if (err < 0) 881ff984e57SWei WANG return err; 882ff984e57SWei WANG 883ff984e57SWei WANG err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 884ff984e57SWei WANG if (err < 0) 885ff984e57SWei WANG return err; 886ff984e57SWei WANG 887d88691beSWei WANG host->power_state = SDMMC_POWER_ON; 888ff984e57SWei WANG return 0; 889ff984e57SWei WANG } 890ff984e57SWei WANG 891ff984e57SWei WANG static int sd_power_off(struct realtek_pci_sdmmc *host) 892ff984e57SWei WANG { 893ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 894ff984e57SWei WANG int err; 895ff984e57SWei WANG 896d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 897d88691beSWei WANG 898ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 899ff984e57SWei WANG 900ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 901ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 902ff984e57SWei WANG 903ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 904ff984e57SWei WANG if (err < 0) 905ff984e57SWei WANG return err; 906ff984e57SWei WANG 907ff984e57SWei WANG err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 908ff984e57SWei WANG if (err < 0) 909ff984e57SWei WANG return err; 910ff984e57SWei WANG 911ff984e57SWei WANG return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 912ff984e57SWei WANG } 913ff984e57SWei WANG 914ff984e57SWei WANG static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 915ff984e57SWei WANG unsigned char power_mode) 916ff984e57SWei WANG { 917ff984e57SWei WANG int err; 918ff984e57SWei WANG 919ff984e57SWei WANG if (power_mode == MMC_POWER_OFF) 920ff984e57SWei WANG err = sd_power_off(host); 921ff984e57SWei WANG else 922ff984e57SWei WANG err = sd_power_on(host); 923ff984e57SWei WANG 924ff984e57SWei WANG return err; 925ff984e57SWei WANG } 926ff984e57SWei WANG 92784d72f9cSWei WANG static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 928ff984e57SWei WANG { 929ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 930ff984e57SWei WANG int err = 0; 931ff984e57SWei WANG 932ff984e57SWei WANG rtsx_pci_init_cmd(pcr); 933ff984e57SWei WANG 934ff984e57SWei WANG switch (timing) { 935ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 936ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 937ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 938ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 939ff984e57SWei WANG SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 940ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 941ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 942ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 943ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 944ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 945ff984e57SWei WANG break; 946ff984e57SWei WANG 9471a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 948ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 949ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 950ff984e57SWei WANG 0x0C | SD_ASYNC_FIFO_NOT_RST, 951ff984e57SWei WANG SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 952ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 953ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 954ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 955ff984e57SWei WANG CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 956ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 957ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 958ff984e57SWei WANG DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 959ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 960ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 961ff984e57SWei WANG DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 962ff984e57SWei WANG break; 963ff984e57SWei WANG 964ff984e57SWei WANG case MMC_TIMING_MMC_HS: 965ff984e57SWei WANG case MMC_TIMING_SD_HS: 966ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 967ff984e57SWei WANG 0x0C, SD_20_MODE); 968ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 969ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 970ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 971ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 972ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 973ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 974ff984e57SWei WANG SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 975ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 976ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 977ff984e57SWei WANG break; 978ff984e57SWei WANG 979ff984e57SWei WANG default: 980ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 981ff984e57SWei WANG SD_CFG1, 0x0C, SD_20_MODE); 982ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 983ff984e57SWei WANG CLK_LOW_FREQ, CLK_LOW_FREQ); 984ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 985ff984e57SWei WANG CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 986ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 987ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 988ff984e57SWei WANG SD_PUSH_POINT_CTL, 0xFF, 0); 989ff984e57SWei WANG rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 990ff984e57SWei WANG SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 991ff984e57SWei WANG break; 992ff984e57SWei WANG } 993ff984e57SWei WANG 994ff984e57SWei WANG err = rtsx_pci_send_cmd(pcr, 100); 995ff984e57SWei WANG 996ff984e57SWei WANG return err; 997ff984e57SWei WANG } 998ff984e57SWei WANG 999ff984e57SWei WANG static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1000ff984e57SWei WANG { 1001ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1002ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1003ff984e57SWei WANG 1004ff984e57SWei WANG if (host->eject) 1005ff984e57SWei WANG return; 1006ff984e57SWei WANG 1007c3481955SWei WANG if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 1008c3481955SWei WANG return; 1009c3481955SWei WANG 1010ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1011ff984e57SWei WANG 1012ff984e57SWei WANG rtsx_pci_start_run(pcr); 1013ff984e57SWei WANG 1014ff984e57SWei WANG sd_set_bus_width(host, ios->bus_width); 1015ff984e57SWei WANG sd_set_power_mode(host, ios->power_mode); 101684d72f9cSWei WANG sd_set_timing(host, ios->timing); 1017ff984e57SWei WANG 1018ff984e57SWei WANG host->vpclk = false; 1019ff984e57SWei WANG host->double_clk = true; 1020ff984e57SWei WANG 1021ff984e57SWei WANG switch (ios->timing) { 1022ff984e57SWei WANG case MMC_TIMING_UHS_SDR104: 1023ff984e57SWei WANG case MMC_TIMING_UHS_SDR50: 1024ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_2M; 1025ff984e57SWei WANG host->vpclk = true; 1026ff984e57SWei WANG host->double_clk = false; 1027ff984e57SWei WANG break; 10281a0ae377SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 1029ff984e57SWei WANG case MMC_TIMING_UHS_DDR50: 1030ff984e57SWei WANG case MMC_TIMING_UHS_SDR25: 1031ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_1M; 1032ff984e57SWei WANG break; 1033ff984e57SWei WANG default: 1034ff984e57SWei WANG host->ssc_depth = RTSX_SSC_DEPTH_500K; 1035ff984e57SWei WANG break; 1036ff984e57SWei WANG } 1037ff984e57SWei WANG 1038ff984e57SWei WANG host->initial_mode = (ios->clock <= 1000000) ? true : false; 1039ff984e57SWei WANG 1040ff984e57SWei WANG host->clock = ios->clock; 1041ff984e57SWei WANG rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 1042ff984e57SWei WANG host->initial_mode, host->double_clk, host->vpclk); 1043ff984e57SWei WANG 1044ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1045ff984e57SWei WANG } 1046ff984e57SWei WANG 1047ff984e57SWei WANG static int sdmmc_get_ro(struct mmc_host *mmc) 1048ff984e57SWei WANG { 1049ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1050ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1051ff984e57SWei WANG int ro = 0; 1052ff984e57SWei WANG u32 val; 1053ff984e57SWei WANG 1054ff984e57SWei WANG if (host->eject) 1055ff984e57SWei WANG return -ENOMEDIUM; 1056ff984e57SWei WANG 1057ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1058ff984e57SWei WANG 1059ff984e57SWei WANG rtsx_pci_start_run(pcr); 1060ff984e57SWei WANG 1061ff984e57SWei WANG /* Check SD mechanical write-protect switch */ 1062ff984e57SWei WANG val = rtsx_pci_readl(pcr, RTSX_BIPR); 1063ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1064ff984e57SWei WANG if (val & SD_WRITE_PROTECT) 1065ff984e57SWei WANG ro = 1; 1066ff984e57SWei WANG 1067ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1068ff984e57SWei WANG 1069ff984e57SWei WANG return ro; 1070ff984e57SWei WANG } 1071ff984e57SWei WANG 1072ff984e57SWei WANG static int sdmmc_get_cd(struct mmc_host *mmc) 1073ff984e57SWei WANG { 1074ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1075ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1076ff984e57SWei WANG int cd = 0; 1077ff984e57SWei WANG u32 val; 1078ff984e57SWei WANG 1079ff984e57SWei WANG if (host->eject) 1080ff984e57SWei WANG return -ENOMEDIUM; 1081ff984e57SWei WANG 1082ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1083ff984e57SWei WANG 1084ff984e57SWei WANG rtsx_pci_start_run(pcr); 1085ff984e57SWei WANG 1086ff984e57SWei WANG /* Check SD card detect */ 1087ff984e57SWei WANG val = rtsx_pci_card_exist(pcr); 1088ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1089ff984e57SWei WANG if (val & SD_EXIST) 1090ff984e57SWei WANG cd = 1; 1091ff984e57SWei WANG 1092ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1093ff984e57SWei WANG 1094ff984e57SWei WANG return cd; 1095ff984e57SWei WANG } 1096ff984e57SWei WANG 1097ff984e57SWei WANG static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1098ff984e57SWei WANG { 1099ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1100ff984e57SWei WANG int err; 1101ff984e57SWei WANG u8 stat; 1102ff984e57SWei WANG 1103ff984e57SWei WANG /* Reference to Signal Voltage Switch Sequence in SD spec. 1104ff984e57SWei WANG * Wait for a period of time so that the card can drive SD_CMD and 1105ff984e57SWei WANG * SD_DAT[3:0] to low after sending back CMD11 response. 1106ff984e57SWei WANG */ 1107ff984e57SWei WANG mdelay(1); 1108ff984e57SWei WANG 1109ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1110ff984e57SWei WANG * If either one of SD_CMD,SD_DAT[3:0] is not low, 1111ff984e57SWei WANG * abort the voltage switch sequence; 1112ff984e57SWei WANG */ 1113ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1114ff984e57SWei WANG if (err < 0) 1115ff984e57SWei WANG return err; 1116ff984e57SWei WANG 1117ff984e57SWei WANG if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1118ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS)) 1119ff984e57SWei WANG return -EINVAL; 1120ff984e57SWei WANG 1121ff984e57SWei WANG /* Stop toggle SD clock */ 1122ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1123ff984e57SWei WANG 0xFF, SD_CLK_FORCE_STOP); 1124ff984e57SWei WANG if (err < 0) 1125ff984e57SWei WANG return err; 1126ff984e57SWei WANG 1127ff984e57SWei WANG return 0; 1128ff984e57SWei WANG } 1129ff984e57SWei WANG 1130ff984e57SWei WANG static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1131ff984e57SWei WANG { 1132ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1133ff984e57SWei WANG int err; 1134ff984e57SWei WANG u8 stat, mask, val; 1135ff984e57SWei WANG 1136ff984e57SWei WANG /* Wait 1.8V output of voltage regulator in card stable */ 1137ff984e57SWei WANG msleep(50); 1138ff984e57SWei WANG 1139ff984e57SWei WANG /* Toggle SD clock again */ 1140ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1141ff984e57SWei WANG if (err < 0) 1142ff984e57SWei WANG return err; 1143ff984e57SWei WANG 1144ff984e57SWei WANG /* Wait for a period of time so that the card can drive 1145ff984e57SWei WANG * SD_DAT[3:0] to high at 1.8V 1146ff984e57SWei WANG */ 1147ff984e57SWei WANG msleep(20); 1148ff984e57SWei WANG 1149ff984e57SWei WANG /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1150ff984e57SWei WANG err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1151ff984e57SWei WANG if (err < 0) 1152ff984e57SWei WANG return err; 1153ff984e57SWei WANG 1154ff984e57SWei WANG mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1155ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1156ff984e57SWei WANG val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1157ff984e57SWei WANG SD_DAT1_STATUS | SD_DAT0_STATUS; 1158ff984e57SWei WANG if ((stat & mask) != val) { 1159ff984e57SWei WANG dev_dbg(sdmmc_dev(host), 1160ff984e57SWei WANG "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1161ff984e57SWei WANG rtsx_pci_write_register(pcr, SD_BUS_STAT, 1162ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1163ff984e57SWei WANG rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1164ff984e57SWei WANG return -EINVAL; 1165ff984e57SWei WANG } 1166ff984e57SWei WANG 1167ff984e57SWei WANG return 0; 1168ff984e57SWei WANG } 1169ff984e57SWei WANG 1170ff984e57SWei WANG static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1171ff984e57SWei WANG { 1172ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1173ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1174ff984e57SWei WANG int err = 0; 1175ff984e57SWei WANG u8 voltage; 1176ff984e57SWei WANG 1177ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1178ff984e57SWei WANG __func__, ios->signal_voltage); 1179ff984e57SWei WANG 1180ff984e57SWei WANG if (host->eject) 1181ff984e57SWei WANG return -ENOMEDIUM; 1182ff984e57SWei WANG 1183c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1184c3481955SWei WANG if (err) 1185c3481955SWei WANG return err; 1186c3481955SWei WANG 1187ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1188ff984e57SWei WANG 1189ff984e57SWei WANG rtsx_pci_start_run(pcr); 1190ff984e57SWei WANG 1191ff984e57SWei WANG if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1192ef85e736SWei WANG voltage = OUTPUT_3V3; 1193ff984e57SWei WANG else 1194ef85e736SWei WANG voltage = OUTPUT_1V8; 1195ff984e57SWei WANG 1196ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1197ff984e57SWei WANG err = sd_wait_voltage_stable_1(host); 1198ff984e57SWei WANG if (err < 0) 1199ff984e57SWei WANG goto out; 1200ff984e57SWei WANG } 1201ff984e57SWei WANG 1202ef85e736SWei WANG err = rtsx_pci_switch_output_voltage(pcr, voltage); 1203ff984e57SWei WANG if (err < 0) 1204ff984e57SWei WANG goto out; 1205ff984e57SWei WANG 1206ef85e736SWei WANG if (voltage == OUTPUT_1V8) { 1207ff984e57SWei WANG err = sd_wait_voltage_stable_2(host); 1208ff984e57SWei WANG if (err < 0) 1209ff984e57SWei WANG goto out; 1210ff984e57SWei WANG } 1211ff984e57SWei WANG 12121b8055b4SWei WANG out: 1213ff984e57SWei WANG /* Stop toggle SD clock in idle */ 1214ff984e57SWei WANG err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1215ff984e57SWei WANG SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1216ff984e57SWei WANG 1217ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1218ff984e57SWei WANG 1219ff984e57SWei WANG return err; 1220ff984e57SWei WANG } 1221ff984e57SWei WANG 1222ff984e57SWei WANG static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1223ff984e57SWei WANG { 1224ff984e57SWei WANG struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1225ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1226ff984e57SWei WANG int err = 0; 1227ff984e57SWei WANG 1228ff984e57SWei WANG if (host->eject) 1229ff984e57SWei WANG return -ENOMEDIUM; 1230ff984e57SWei WANG 1231c3481955SWei WANG err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1232c3481955SWei WANG if (err) 1233c3481955SWei WANG return err; 1234c3481955SWei WANG 1235ff984e57SWei WANG mutex_lock(&pcr->pcr_mutex); 1236ff984e57SWei WANG 1237ff984e57SWei WANG rtsx_pci_start_run(pcr); 1238ff984e57SWei WANG 123984d72f9cSWei WANG /* Set initial TX phase */ 124084d72f9cSWei WANG switch (mmc->ios.timing) { 124184d72f9cSWei WANG case MMC_TIMING_UHS_SDR104: 124284d72f9cSWei WANG err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 124384d72f9cSWei WANG break; 1244ff984e57SWei WANG 124584d72f9cSWei WANG case MMC_TIMING_UHS_SDR50: 124684d72f9cSWei WANG err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 124784d72f9cSWei WANG break; 124884d72f9cSWei WANG 124984d72f9cSWei WANG case MMC_TIMING_UHS_DDR50: 125084d72f9cSWei WANG err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 125184d72f9cSWei WANG break; 125284d72f9cSWei WANG 125384d72f9cSWei WANG default: 125484d72f9cSWei WANG err = 0; 125584d72f9cSWei WANG } 125684d72f9cSWei WANG 125784d72f9cSWei WANG if (err) 125884d72f9cSWei WANG goto out; 125984d72f9cSWei WANG 126084d72f9cSWei WANG /* Tuning RX phase */ 126184d72f9cSWei WANG if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 126284d72f9cSWei WANG (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 126384d72f9cSWei WANG err = sd_tuning_rx(host, opcode); 126484d72f9cSWei WANG else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 126584d72f9cSWei WANG err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 126684d72f9cSWei WANG 126784d72f9cSWei WANG out: 1268ff984e57SWei WANG mutex_unlock(&pcr->pcr_mutex); 1269ff984e57SWei WANG 1270ff984e57SWei WANG return err; 1271ff984e57SWei WANG } 1272ff984e57SWei WANG 1273ff984e57SWei WANG static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 12746291e715SMicky Ching .pre_req = sdmmc_pre_req, 12756291e715SMicky Ching .post_req = sdmmc_post_req, 1276ff984e57SWei WANG .request = sdmmc_request, 1277ff984e57SWei WANG .set_ios = sdmmc_set_ios, 1278ff984e57SWei WANG .get_ro = sdmmc_get_ro, 1279ff984e57SWei WANG .get_cd = sdmmc_get_cd, 1280ff984e57SWei WANG .start_signal_voltage_switch = sdmmc_switch_voltage, 1281ff984e57SWei WANG .execute_tuning = sdmmc_execute_tuning, 1282ff984e57SWei WANG }; 1283ff984e57SWei WANG 1284ff984e57SWei WANG static void init_extra_caps(struct realtek_pci_sdmmc *host) 1285ff984e57SWei WANG { 1286ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1287ff984e57SWei WANG struct rtsx_pcr *pcr = host->pcr; 1288ff984e57SWei WANG 1289ff984e57SWei WANG dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1290ff984e57SWei WANG 1291ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1292ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR50; 1293ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1294ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_SDR104; 1295ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1296ff984e57SWei WANG mmc->caps |= MMC_CAP_UHS_DDR50; 1297ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1298ff984e57SWei WANG mmc->caps |= MMC_CAP_1_8V_DDR; 1299ff984e57SWei WANG if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1300ff984e57SWei WANG mmc->caps |= MMC_CAP_8_BIT_DATA; 1301ff984e57SWei WANG } 1302ff984e57SWei WANG 1303ff984e57SWei WANG static void realtek_init_host(struct realtek_pci_sdmmc *host) 1304ff984e57SWei WANG { 1305ff984e57SWei WANG struct mmc_host *mmc = host->mmc; 1306ff984e57SWei WANG 1307ff984e57SWei WANG mmc->f_min = 250000; 1308ff984e57SWei WANG mmc->f_max = 208000000; 1309ff984e57SWei WANG mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1310ff984e57SWei WANG mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1311ff984e57SWei WANG MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1312ff984e57SWei WANG MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1313517bf80fSRoger Tseng mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE; 1314ff984e57SWei WANG mmc->max_current_330 = 400; 1315ff984e57SWei WANG mmc->max_current_180 = 800; 1316ff984e57SWei WANG mmc->ops = &realtek_pci_sdmmc_ops; 1317ff984e57SWei WANG 1318ff984e57SWei WANG init_extra_caps(host); 1319ff984e57SWei WANG 1320ff984e57SWei WANG mmc->max_segs = 256; 1321ff984e57SWei WANG mmc->max_seg_size = 65536; 1322ff984e57SWei WANG mmc->max_blk_size = 512; 1323ff984e57SWei WANG mmc->max_blk_count = 65535; 1324ff984e57SWei WANG mmc->max_req_size = 524288; 1325ff984e57SWei WANG } 1326ff984e57SWei WANG 1327ff984e57SWei WANG static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1328ff984e57SWei WANG { 1329ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1330ff984e57SWei WANG 13312057647fSMicky Ching host->cookie = -1; 1332ff984e57SWei WANG mmc_detect_change(host->mmc, 0); 1333ff984e57SWei WANG } 1334ff984e57SWei WANG 1335ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1336ff984e57SWei WANG { 1337ff984e57SWei WANG struct mmc_host *mmc; 1338ff984e57SWei WANG struct realtek_pci_sdmmc *host; 1339ff984e57SWei WANG struct rtsx_pcr *pcr; 1340ff984e57SWei WANG struct pcr_handle *handle = pdev->dev.platform_data; 1341ff984e57SWei WANG 1342ff984e57SWei WANG if (!handle) 1343ff984e57SWei WANG return -ENXIO; 1344ff984e57SWei WANG 1345ff984e57SWei WANG pcr = handle->pcr; 1346ff984e57SWei WANG if (!pcr) 1347ff984e57SWei WANG return -ENXIO; 1348ff984e57SWei WANG 1349ff984e57SWei WANG dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1350ff984e57SWei WANG 1351ff984e57SWei WANG mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1352ff984e57SWei WANG if (!mmc) 1353ff984e57SWei WANG return -ENOMEM; 1354ff984e57SWei WANG 1355ff984e57SWei WANG host = mmc_priv(mmc); 13566291e715SMicky Ching host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME); 13576291e715SMicky Ching if (!host->workq) { 13586291e715SMicky Ching mmc_free_host(mmc); 13596291e715SMicky Ching return -ENOMEM; 13606291e715SMicky Ching } 1361ff984e57SWei WANG host->pcr = pcr; 1362ff984e57SWei WANG host->mmc = mmc; 1363ff984e57SWei WANG host->pdev = pdev; 13642057647fSMicky Ching host->cookie = -1; 1365d88691beSWei WANG host->power_state = SDMMC_POWER_OFF; 13666291e715SMicky Ching INIT_WORK(&host->work, sd_request); 1367ff984e57SWei WANG platform_set_drvdata(pdev, host); 1368ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1369ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1370ff984e57SWei WANG 137198fcc576SMicky Ching mutex_init(&host->host_mutex); 1372ff984e57SWei WANG 1373ff984e57SWei WANG realtek_init_host(host); 1374ff984e57SWei WANG 1375ff984e57SWei WANG mmc_add_host(mmc); 1376ff984e57SWei WANG 1377ff984e57SWei WANG return 0; 1378ff984e57SWei WANG } 1379ff984e57SWei WANG 1380ff984e57SWei WANG static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1381ff984e57SWei WANG { 1382ff984e57SWei WANG struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1383ff984e57SWei WANG struct rtsx_pcr *pcr; 1384ff984e57SWei WANG struct mmc_host *mmc; 1385ff984e57SWei WANG 1386ff984e57SWei WANG if (!host) 1387ff984e57SWei WANG return 0; 1388ff984e57SWei WANG 1389ff984e57SWei WANG pcr = host->pcr; 1390ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1391ff984e57SWei WANG pcr->slots[RTSX_SD_CARD].card_event = NULL; 1392ff984e57SWei WANG mmc = host->mmc; 1393ff984e57SWei WANG 13946291e715SMicky Ching cancel_work_sync(&host->work); 13956291e715SMicky Ching 139698fcc576SMicky Ching mutex_lock(&host->host_mutex); 1397ff984e57SWei WANG if (host->mrq) { 1398ff984e57SWei WANG dev_dbg(&(pdev->dev), 1399ff984e57SWei WANG "%s: Controller removed during transfer\n", 1400ff984e57SWei WANG mmc_hostname(mmc)); 1401ff984e57SWei WANG 140298fcc576SMicky Ching rtsx_pci_complete_unfinished_transfer(pcr); 1403ff984e57SWei WANG 140498fcc576SMicky Ching host->mrq->cmd->error = -ENOMEDIUM; 140598fcc576SMicky Ching if (host->mrq->stop) 140698fcc576SMicky Ching host->mrq->stop->error = -ENOMEDIUM; 140798fcc576SMicky Ching mmc_request_done(mmc, host->mrq); 1408ff984e57SWei WANG } 140998fcc576SMicky Ching mutex_unlock(&host->host_mutex); 1410ff984e57SWei WANG 1411ff984e57SWei WANG mmc_remove_host(mmc); 1412640e09bcSMicky Ching host->eject = true; 1413640e09bcSMicky Ching 14146291e715SMicky Ching flush_workqueue(host->workq); 14156291e715SMicky Ching destroy_workqueue(host->workq); 14166291e715SMicky Ching host->workq = NULL; 14176291e715SMicky Ching 1418ff984e57SWei WANG mmc_free_host(mmc); 1419ff984e57SWei WANG 1420ff984e57SWei WANG dev_dbg(&(pdev->dev), 1421ff984e57SWei WANG ": Realtek PCI-E SDMMC controller has been removed\n"); 1422ff984e57SWei WANG 1423ff984e57SWei WANG return 0; 1424ff984e57SWei WANG } 1425ff984e57SWei WANG 1426ff984e57SWei WANG static struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1427ff984e57SWei WANG { 1428ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1429ff984e57SWei WANG }, { 1430ff984e57SWei WANG /* sentinel */ 1431ff984e57SWei WANG } 1432ff984e57SWei WANG }; 1433ff984e57SWei WANG MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1434ff984e57SWei WANG 1435ff984e57SWei WANG static struct platform_driver rtsx_pci_sdmmc_driver = { 1436ff984e57SWei WANG .probe = rtsx_pci_sdmmc_drv_probe, 1437ff984e57SWei WANG .remove = rtsx_pci_sdmmc_drv_remove, 1438ff984e57SWei WANG .id_table = rtsx_pci_sdmmc_ids, 1439ff984e57SWei WANG .driver = { 1440ff984e57SWei WANG .name = DRV_NAME_RTSX_PCI_SDMMC, 1441ff984e57SWei WANG }, 1442ff984e57SWei WANG }; 1443ff984e57SWei WANG module_platform_driver(rtsx_pci_sdmmc_driver); 1444ff984e57SWei WANG 1445ff984e57SWei WANG MODULE_LICENSE("GPL"); 1446ff984e57SWei WANG MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1447ff984e57SWei WANG MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1448