1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DMA support for Internal DMAC with SDHI SD/SDIO controller 4 * 5 * Copyright (C) 2016-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/device.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/io-64-nonatomic-hi-lo.h> 14 #include <linux/mfd/tmio.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/pagemap.h> 20 #include <linux/scatterlist.h> 21 #include <linux/sys_soc.h> 22 23 #include "renesas_sdhi.h" 24 #include "tmio_mmc.h" 25 26 #define DM_CM_DTRAN_MODE 0x820 27 #define DM_CM_DTRAN_CTRL 0x828 28 #define DM_CM_RST 0x830 29 #define DM_CM_INFO1 0x840 30 #define DM_CM_INFO1_MASK 0x848 31 #define DM_CM_INFO2 0x850 32 #define DM_CM_INFO2_MASK 0x858 33 #define DM_DTRAN_ADDR 0x880 34 35 /* DM_CM_DTRAN_MODE */ 36 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 37 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 38 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 39 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */ 40 41 /* DM_CM_DTRAN_CTRL */ 42 #define DTRAN_CTRL_DM_START BIT(0) 43 44 /* DM_CM_RST */ 45 #define RST_DTRANRST1 BIT(9) 46 #define RST_DTRANRST0 BIT(8) 47 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 48 49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 50 #define INFO1_CLEAR 0 51 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 52 #define INFO1_DTRANEND1 BIT(20) 53 #define INFO1_DTRANEND1_OLD BIT(17) 54 #define INFO1_DTRANEND0 BIT(16) 55 56 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 57 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 58 #define INFO2_DTRANERR1 BIT(17) 59 #define INFO2_DTRANERR0 BIT(16) 60 61 enum renesas_sdhi_dma_cookie { 62 COOKIE_UNMAPPED, 63 COOKIE_PRE_MAPPED, 64 COOKIE_MAPPED, 65 }; 66 67 /* 68 * Specification of this driver: 69 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 70 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 71 * need a custom accessor. 72 */ 73 74 static unsigned long global_flags; 75 /* 76 * Workaround for avoiding to use RX DMAC by multiple channels. 77 * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use 78 * RX DMAC simultaneously, sometimes hundreds of bytes data are not 79 * stored into the system memory even if the DMAC interrupt happened. 80 * So, this driver then uses one RX DMAC channel only. 81 */ 82 #define SDHI_INTERNAL_DMAC_RX_IN_USE 0 83 84 /* Definitions for sampling clocks */ 85 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 86 { 87 .clk_rate = 0, 88 .tap = 0x00000300, 89 .tap_hs400_4tap = 0x00000100, 90 }, 91 }; 92 93 static const struct renesas_sdhi_of_data of_data_rza2 = { 94 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 95 TMIO_MMC_HAVE_CBSY, 96 .tmio_ocr_mask = MMC_VDD_32_33, 97 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 98 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 99 .bus_shift = 2, 100 .scc_offset = 0 - 0x1000, 101 .taps = rcar_gen3_scc_taps, 102 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 103 /* DMAC can handle 32bit blk count but only 1 segment */ 104 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 105 .max_segs = 1, 106 }; 107 108 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = { 109 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 110 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 111 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 112 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 113 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 114 .bus_shift = 2, 115 .scc_offset = 0x1000, 116 .taps = rcar_gen3_scc_taps, 117 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 118 /* DMAC can handle 32bit blk count but only 1 segment */ 119 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 120 .max_segs = 1, 121 .sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK, 122 }; 123 124 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = { 125 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 126 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 127 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 128 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 129 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 130 .bus_shift = 2, 131 .scc_offset = 0x1000, 132 .taps = rcar_gen3_scc_taps, 133 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 134 /* DMAC can handle 32bit blk count but only 1 segment */ 135 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 136 .max_segs = 1, 137 }; 138 139 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 140 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 141 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 142 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 143 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 144 }; 145 146 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 147 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 148 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 149 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 150 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 151 }; 152 153 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 154 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 155 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 156 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 157 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 158 }; 159 160 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 161 .hs400_disabled = true, 162 .hs400_4taps = true, 163 }; 164 165 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = { 166 .hs400_disabled = true, 167 .hs400_4taps = true, 168 .dma_one_rx_only = true, 169 .old_info1_layout = true, 170 }; 171 172 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 173 .hs400_4taps = true, 174 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 175 .manual_tap_correction = true, 176 }; 177 178 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 179 .hs400_disabled = true, 180 }; 181 182 static const struct renesas_sdhi_quirks sdhi_quirks_fixed_addr = { 183 .fixed_addr_mode = true, 184 }; 185 186 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 187 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 188 .manual_tap_correction = true, 189 }; 190 191 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 192 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 193 .manual_tap_correction = true, 194 }; 195 196 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 197 .hs400_4taps = true, 198 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 199 .hs400_calib_table = r8a7796_es13_calib_table, 200 .manual_tap_correction = true, 201 }; 202 203 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 204 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 205 .hs400_calib_table = r8a77965_calib_table, 206 .manual_tap_correction = true, 207 }; 208 209 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 210 .hs400_calib_table = r8a77990_calib_table, 211 .manual_tap_correction = true, 212 }; 213 214 /* 215 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 216 * So, we want to treat them equally and only have a match for ES1.2 to enforce 217 * this if there ever will be a way to distinguish ES1.2. 218 */ 219 static const struct soc_device_attribute sdhi_quirks_match[] = { 220 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 221 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400_one_rx }, 222 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 223 { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_4tap_nohs400_one_rx }, 224 { .soc_id = "r8a7796", .revision = "ES1.[12]", .data = &sdhi_quirks_4tap_nohs400 }, 225 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 226 { .soc_id = "r8a77980", .revision = "ES1.*", .data = &sdhi_quirks_nohs400 }, 227 { /* Sentinel. */ } 228 }; 229 230 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = { 231 .of_data = &of_data_rcar_gen3, 232 .quirks = &sdhi_quirks_bad_taps2367, 233 }; 234 235 static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = { 236 .of_data = &of_data_rcar_gen3, 237 .quirks = &sdhi_quirks_bad_taps1357, 238 }; 239 240 static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = { 241 .of_data = &of_data_rcar_gen3, 242 .quirks = &sdhi_quirks_r8a77965, 243 }; 244 245 static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = { 246 .of_data = &of_data_rcar_gen3_no_sdh_fallback, 247 .quirks = &sdhi_quirks_nohs400, 248 }; 249 250 static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = { 251 .of_data = &of_data_rcar_gen3, 252 .quirks = &sdhi_quirks_r8a77990, 253 }; 254 255 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = { 256 .of_data = &of_data_rcar_gen3, 257 }; 258 259 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_compatible = { 260 .of_data = &of_data_rcar_gen3, 261 .quirks = &sdhi_quirks_nohs400, 262 }; 263 264 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = { 265 .of_data = &of_data_rza2, 266 .quirks = &sdhi_quirks_fixed_addr, 267 }; 268 269 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 270 { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, }, 271 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, }, 272 { .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, }, 273 { .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, }, 274 { .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, }, 275 { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, }, 276 { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, 277 { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, }, 278 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 279 { .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, }, 280 {}, 281 }; 282 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 283 284 static void 285 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 286 { 287 struct renesas_sdhi *priv = host_to_priv(host); 288 289 if (!host->chan_tx || !host->chan_rx) 290 return; 291 292 if (!enable) 293 writel(INFO1_CLEAR, host->ctl + DM_CM_INFO1); 294 295 if (priv->dma_priv.enable) 296 priv->dma_priv.enable(host, enable); 297 } 298 299 static void 300 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) 301 { 302 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 303 304 renesas_sdhi_internal_dmac_enable_dma(host, false); 305 306 writel(RST_RESERVED_BITS & ~val, host->ctl + DM_CM_RST); 307 writel(RST_RESERVED_BITS | val, host->ctl + DM_CM_RST); 308 309 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 310 311 renesas_sdhi_internal_dmac_enable_dma(host, true); 312 } 313 314 static void 315 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) 316 { 317 struct renesas_sdhi *priv = host_to_priv(host); 318 319 tasklet_schedule(&priv->dma_priv.dma_complete); 320 } 321 322 /* 323 * renesas_sdhi_internal_dmac_map() will be called with two different 324 * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single 325 * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg 326 * pointer in a mmc_data instead of host->sg_ptr. 327 */ 328 static void 329 renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host, 330 struct mmc_data *data, 331 enum renesas_sdhi_dma_cookie cookie) 332 { 333 bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) : 334 (data->host_cookie == cookie); 335 336 if (unmap) { 337 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, 338 mmc_get_dma_dir(data)); 339 data->host_cookie = COOKIE_UNMAPPED; 340 } 341 } 342 343 static bool 344 renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host, 345 struct mmc_data *data, 346 enum renesas_sdhi_dma_cookie cookie) 347 { 348 if (data->host_cookie == COOKIE_PRE_MAPPED) 349 return true; 350 351 if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, 352 mmc_get_dma_dir(data))) 353 return false; 354 355 data->host_cookie = cookie; 356 357 /* This DMAC needs buffers to be 128-byte aligned */ 358 if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) { 359 renesas_sdhi_internal_dmac_unmap(host, data, cookie); 360 return false; 361 } 362 363 return true; 364 } 365 366 static void 367 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 368 struct mmc_data *data) 369 { 370 struct renesas_sdhi *priv = host_to_priv(host); 371 struct scatterlist *sg = host->sg_ptr; 372 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH; 373 374 if (!(priv->quirks && priv->quirks->fixed_addr_mode)) 375 dtran_mode |= DTRAN_MODE_ADDR_MODE; 376 377 if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED)) 378 goto force_pio; 379 380 if (data->flags & MMC_DATA_READ) { 381 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 382 if (priv->quirks && priv->quirks->dma_one_rx_only && 383 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 384 goto force_pio_with_unmap; 385 } else { 386 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 387 } 388 389 renesas_sdhi_internal_dmac_enable_dma(host, true); 390 391 /* set dma parameters */ 392 writel(dtran_mode, host->ctl + DM_CM_DTRAN_MODE); 393 writel(sg_dma_address(sg), host->ctl + DM_DTRAN_ADDR); 394 395 host->dma_on = true; 396 397 return; 398 399 force_pio_with_unmap: 400 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 401 402 force_pio: 403 renesas_sdhi_internal_dmac_enable_dma(host, false); 404 } 405 406 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 407 { 408 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 409 410 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 411 412 /* start the DMAC */ 413 writel(DTRAN_CTRL_DM_START, host->ctl + DM_CM_DTRAN_CTRL); 414 } 415 416 static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) 417 { 418 enum dma_data_direction dir; 419 420 if (!host->dma_on) 421 return false; 422 423 if (!host->data) 424 return false; 425 426 if (host->data->flags & MMC_DATA_READ) 427 dir = DMA_FROM_DEVICE; 428 else 429 dir = DMA_TO_DEVICE; 430 431 renesas_sdhi_internal_dmac_enable_dma(host, false); 432 renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED); 433 434 if (dir == DMA_FROM_DEVICE) 435 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 436 437 host->dma_on = false; 438 439 return true; 440 } 441 442 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 443 { 444 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 445 446 spin_lock_irq(&host->lock); 447 if (!renesas_sdhi_internal_dmac_complete(host)) 448 goto out; 449 450 tmio_mmc_do_data_irq(host); 451 out: 452 spin_unlock_irq(&host->lock); 453 } 454 455 static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host) 456 { 457 if (host->data) 458 renesas_sdhi_internal_dmac_complete(host); 459 } 460 461 static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc, 462 struct mmc_request *mrq, 463 int err) 464 { 465 struct tmio_mmc_host *host = mmc_priv(mmc); 466 struct mmc_data *data = mrq->data; 467 468 if (!data) 469 return; 470 471 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 472 } 473 474 static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc, 475 struct mmc_request *mrq) 476 { 477 struct tmio_mmc_host *host = mmc_priv(mmc); 478 struct mmc_data *data = mrq->data; 479 480 if (!data) 481 return; 482 483 data->host_cookie = COOKIE_UNMAPPED; 484 renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED); 485 } 486 487 static void 488 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 489 struct tmio_mmc_data *pdata) 490 { 491 struct renesas_sdhi *priv = host_to_priv(host); 492 493 /* Disable DMAC interrupts, we don't use them */ 494 writel(INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK); 495 writel(INFO2_MASK_CLEAR, host->ctl + DM_CM_INFO2_MASK); 496 497 /* Each value is set to non-zero to assume "enabling" each DMA */ 498 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 499 500 tasklet_init(&priv->dma_priv.dma_complete, 501 renesas_sdhi_internal_dmac_complete_tasklet_fn, 502 (unsigned long)host); 503 tasklet_init(&host->dma_issue, 504 renesas_sdhi_internal_dmac_issue_tasklet_fn, 505 (unsigned long)host); 506 507 /* Add pre_req and post_req */ 508 host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req; 509 host->ops.post_req = renesas_sdhi_internal_dmac_post_req; 510 } 511 512 static void 513 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 514 { 515 /* Each value is set to zero to assume "disabling" each DMA */ 516 host->chan_rx = host->chan_tx = NULL; 517 } 518 519 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 520 .start = renesas_sdhi_internal_dmac_start_dma, 521 .enable = renesas_sdhi_internal_dmac_enable_dma, 522 .request = renesas_sdhi_internal_dmac_request_dma, 523 .release = renesas_sdhi_internal_dmac_release_dma, 524 .abort = renesas_sdhi_internal_dmac_abort_dma, 525 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 526 .end = renesas_sdhi_internal_dmac_end_dma, 527 }; 528 529 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 530 { 531 const struct soc_device_attribute *attr; 532 const struct renesas_sdhi_of_data_with_quirks *of_data_quirks; 533 const struct renesas_sdhi_quirks *quirks; 534 struct device *dev = &pdev->dev; 535 536 of_data_quirks = of_device_get_match_data(&pdev->dev); 537 quirks = of_data_quirks->quirks; 538 539 attr = soc_device_match(sdhi_quirks_match); 540 if (attr) 541 quirks = attr->data; 542 543 /* value is max of SD_SECCNT. Confirmed by HW engineers */ 544 dma_set_max_seg_size(dev, 0xffffffff); 545 546 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops, 547 of_data_quirks->of_data, quirks); 548 } 549 550 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 551 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 552 pm_runtime_force_resume) 553 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 554 tmio_mmc_host_runtime_resume, 555 NULL) 556 }; 557 558 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 559 .driver = { 560 .name = "renesas_sdhi_internal_dmac", 561 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 562 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 563 .of_match_table = renesas_sdhi_internal_dmac_of_match, 564 }, 565 .probe = renesas_sdhi_internal_dmac_probe, 566 .remove = renesas_sdhi_remove, 567 }; 568 569 module_platform_driver(renesas_internal_dmac_sdhi_driver); 570 571 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 572 MODULE_AUTHOR("Yoshihiro Shimoda"); 573 MODULE_LICENSE("GPL v2"); 574