1 /* 2 * DMA support for Internal DMAC with SDHI SD/SDIO controller 3 * 4 * Copyright (C) 2016-17 Renesas Electronics Corporation 5 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/io-64-nonatomic-hi-lo.h> 15 #include <linux/mfd/tmio.h> 16 #include <linux/mmc/host.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/pagemap.h> 20 #include <linux/scatterlist.h> 21 #include <linux/sys_soc.h> 22 23 #include "renesas_sdhi.h" 24 #include "tmio_mmc.h" 25 26 #define DM_CM_DTRAN_MODE 0x820 27 #define DM_CM_DTRAN_CTRL 0x828 28 #define DM_CM_RST 0x830 29 #define DM_CM_INFO1 0x840 30 #define DM_CM_INFO1_MASK 0x848 31 #define DM_CM_INFO2 0x850 32 #define DM_CM_INFO2_MASK 0x858 33 #define DM_DTRAN_ADDR 0x880 34 35 /* DM_CM_DTRAN_MODE */ 36 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 37 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "uptream" = for read commands */ 38 #define DTRAN_MODE_BUS_WID_TH (BIT(5) | BIT(4)) 39 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address */ 40 41 /* DM_CM_DTRAN_CTRL */ 42 #define DTRAN_CTRL_DM_START BIT(0) 43 44 /* DM_CM_RST */ 45 #define RST_DTRANRST1 BIT(9) 46 #define RST_DTRANRST0 BIT(8) 47 #define RST_RESERVED_BITS GENMASK_ULL(32, 0) 48 49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 50 #define INFO1_CLEAR 0 51 #define INFO1_DTRANEND1 BIT(17) 52 #define INFO1_DTRANEND0 BIT(16) 53 54 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 55 #define INFO2_DTRANERR1 BIT(17) 56 #define INFO2_DTRANERR0 BIT(16) 57 58 /* 59 * Specification of this driver: 60 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 61 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 62 * need a custom accessor. 63 */ 64 65 /* Definitions for sampling clocks */ 66 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 67 { 68 .clk_rate = 0, 69 .tap = 0x00000300, 70 }, 71 }; 72 73 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = { 74 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 75 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 76 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 77 MMC_CAP_CMD23, 78 .bus_shift = 2, 79 .scc_offset = 0x1000, 80 .taps = rcar_gen3_scc_taps, 81 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 82 /* Gen3 SDHI DMAC can handle 0xffffffff blk count, but seg = 1 */ 83 .max_blk_count = 0xffffffff, 84 .max_segs = 1, 85 }; 86 87 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 88 { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, }, 89 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, 90 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 91 {}, 92 }; 93 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 94 95 static void 96 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 97 int addr, u64 val) 98 { 99 writeq(val, host->ctl + addr); 100 } 101 102 static void 103 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 104 { 105 struct renesas_sdhi *priv = host_to_priv(host); 106 107 if (!host->chan_tx || !host->chan_rx) 108 return; 109 110 if (!enable) 111 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 112 INFO1_CLEAR); 113 114 if (priv->dma_priv.enable) 115 priv->dma_priv.enable(host, enable); 116 } 117 118 static void 119 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) { 120 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 121 122 renesas_sdhi_internal_dmac_enable_dma(host, false); 123 124 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 125 RST_RESERVED_BITS & ~val); 126 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 127 RST_RESERVED_BITS | val); 128 129 renesas_sdhi_internal_dmac_enable_dma(host, true); 130 } 131 132 static void 133 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) { 134 struct renesas_sdhi *priv = host_to_priv(host); 135 136 tasklet_schedule(&priv->dma_priv.dma_complete); 137 } 138 139 static void 140 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 141 struct mmc_data *data) 142 { 143 struct scatterlist *sg = host->sg_ptr; 144 u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE; 145 enum dma_data_direction dir; 146 int ret; 147 148 /* This DMAC cannot handle if sg_len is not 1 */ 149 WARN_ON(host->sg_len > 1); 150 151 /* This DMAC cannot handle if buffer is not 8-bytes alignment */ 152 if (!IS_ALIGNED(sg->offset, 8)) 153 goto force_pio; 154 155 if (data->flags & MMC_DATA_READ) { 156 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 157 dir = DMA_FROM_DEVICE; 158 } else { 159 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 160 dir = DMA_TO_DEVICE; 161 } 162 163 ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir); 164 if (ret == 0) 165 goto force_pio; 166 167 renesas_sdhi_internal_dmac_enable_dma(host, true); 168 169 /* set dma parameters */ 170 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 171 dtran_mode); 172 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 173 sg->dma_address); 174 175 return; 176 177 force_pio: 178 host->force_pio = true; 179 renesas_sdhi_internal_dmac_enable_dma(host, false); 180 } 181 182 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 183 { 184 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 185 186 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 187 188 /* start the DMAC */ 189 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 190 DTRAN_CTRL_DM_START); 191 } 192 193 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 194 { 195 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 196 enum dma_data_direction dir; 197 198 spin_lock_irq(&host->lock); 199 200 if (!host->data) 201 goto out; 202 203 if (host->data->flags & MMC_DATA_READ) 204 dir = DMA_FROM_DEVICE; 205 else 206 dir = DMA_TO_DEVICE; 207 208 renesas_sdhi_internal_dmac_enable_dma(host, false); 209 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir); 210 211 tmio_mmc_do_data_irq(host); 212 out: 213 spin_unlock_irq(&host->lock); 214 } 215 216 static void 217 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 218 struct tmio_mmc_data *pdata) 219 { 220 struct renesas_sdhi *priv = host_to_priv(host); 221 222 /* Each value is set to non-zero to assume "enabling" each DMA */ 223 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 224 225 tasklet_init(&priv->dma_priv.dma_complete, 226 renesas_sdhi_internal_dmac_complete_tasklet_fn, 227 (unsigned long)host); 228 tasklet_init(&host->dma_issue, 229 renesas_sdhi_internal_dmac_issue_tasklet_fn, 230 (unsigned long)host); 231 } 232 233 static void 234 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 235 { 236 /* Each value is set to zero to assume "disabling" each DMA */ 237 host->chan_rx = host->chan_tx = NULL; 238 } 239 240 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 241 .start = renesas_sdhi_internal_dmac_start_dma, 242 .enable = renesas_sdhi_internal_dmac_enable_dma, 243 .request = renesas_sdhi_internal_dmac_request_dma, 244 .release = renesas_sdhi_internal_dmac_release_dma, 245 .abort = renesas_sdhi_internal_dmac_abort_dma, 246 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 247 }; 248 249 /* 250 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC 251 * implementation as others may use a different implementation. 252 */ 253 static const struct soc_device_attribute gen3_soc_whitelist[] = { 254 { .soc_id = "r8a7795", .revision = "ES1.*" }, 255 { .soc_id = "r8a7795", .revision = "ES2.0" }, 256 { .soc_id = "r8a7796", .revision = "ES1.0" }, 257 { .soc_id = "r8a77995", .revision = "ES1.0" }, 258 { /* sentinel */ } 259 }; 260 261 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 262 { 263 if (!soc_device_match(gen3_soc_whitelist)) 264 return -ENODEV; 265 266 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops); 267 } 268 269 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 270 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 271 pm_runtime_force_resume) 272 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 273 tmio_mmc_host_runtime_resume, 274 NULL) 275 }; 276 277 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 278 .driver = { 279 .name = "renesas_sdhi_internal_dmac", 280 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 281 .of_match_table = renesas_sdhi_internal_dmac_of_match, 282 }, 283 .probe = renesas_sdhi_internal_dmac_probe, 284 .remove = renesas_sdhi_remove, 285 }; 286 287 module_platform_driver(renesas_internal_dmac_sdhi_driver); 288 289 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 290 MODULE_AUTHOR("Yoshihiro Shimoda"); 291 MODULE_LICENSE("GPL v2"); 292