1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DMA support for Internal DMAC with SDHI SD/SDIO controller 4 * 5 * Copyright (C) 2016-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/device.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/io-64-nonatomic-hi-lo.h> 14 #include <linux/mfd/tmio.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/pagemap.h> 20 #include <linux/scatterlist.h> 21 #include <linux/sys_soc.h> 22 23 #include "renesas_sdhi.h" 24 #include "tmio_mmc.h" 25 26 #define DM_CM_DTRAN_MODE 0x820 27 #define DM_CM_DTRAN_CTRL 0x828 28 #define DM_CM_RST 0x830 29 #define DM_CM_INFO1 0x840 30 #define DM_CM_INFO1_MASK 0x848 31 #define DM_CM_INFO2 0x850 32 #define DM_CM_INFO2_MASK 0x858 33 #define DM_DTRAN_ADDR 0x880 34 35 /* DM_CM_DTRAN_MODE */ 36 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 37 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 38 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 39 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */ 40 41 /* DM_CM_DTRAN_CTRL */ 42 #define DTRAN_CTRL_DM_START BIT(0) 43 44 /* DM_CM_RST */ 45 #define RST_DTRANRST1 BIT(9) 46 #define RST_DTRANRST0 BIT(8) 47 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 48 49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 50 #define INFO1_CLEAR 0 51 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 52 #define INFO1_DTRANEND1 BIT(17) 53 #define INFO1_DTRANEND0 BIT(16) 54 55 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 56 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 57 #define INFO2_DTRANERR1 BIT(17) 58 #define INFO2_DTRANERR0 BIT(16) 59 60 enum renesas_sdhi_dma_cookie { 61 COOKIE_UNMAPPED, 62 COOKIE_PRE_MAPPED, 63 COOKIE_MAPPED, 64 }; 65 66 /* 67 * Specification of this driver: 68 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 69 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 70 * need a custom accessor. 71 */ 72 73 static unsigned long global_flags; 74 /* 75 * Workaround for avoiding to use RX DMAC by multiple channels. 76 * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use 77 * RX DMAC simultaneously, sometimes hundreds of bytes data are not 78 * stored into the system memory even if the DMAC interrupt happened. 79 * So, this driver then uses one RX DMAC channel only. 80 */ 81 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0 82 #define SDHI_INTERNAL_DMAC_RX_IN_USE 1 83 84 /* Definitions for sampling clocks */ 85 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 86 { 87 .clk_rate = 0, 88 .tap = 0x00000300, 89 .tap_hs400_4tap = 0x00000100, 90 }, 91 }; 92 93 static const struct renesas_sdhi_of_data of_data_rza2 = { 94 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 95 TMIO_MMC_HAVE_CBSY, 96 .tmio_ocr_mask = MMC_VDD_32_33, 97 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 98 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 99 .bus_shift = 2, 100 .scc_offset = 0 - 0x1000, 101 .taps = rcar_gen3_scc_taps, 102 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 103 /* DMAC can handle 32bit blk count but only 1 segment */ 104 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 105 .max_segs = 1, 106 }; 107 108 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = { 109 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 110 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 111 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 112 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 113 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 114 .bus_shift = 2, 115 .scc_offset = 0x1000, 116 .taps = rcar_gen3_scc_taps, 117 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 118 /* DMAC can handle 32bit blk count but only 1 segment */ 119 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 120 .max_segs = 1, 121 .sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK, 122 }; 123 124 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = { 125 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 126 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 127 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 128 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 129 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 130 .bus_shift = 2, 131 .scc_offset = 0x1000, 132 .taps = rcar_gen3_scc_taps, 133 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 134 /* DMAC can handle 32bit blk count but only 1 segment */ 135 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 136 .max_segs = 1, 137 }; 138 139 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 140 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 141 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 142 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 143 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 144 }; 145 146 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 147 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 148 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 149 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 150 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 151 }; 152 153 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 154 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 155 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 156 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 157 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 158 }; 159 160 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 161 .hs400_disabled = true, 162 .hs400_4taps = true, 163 }; 164 165 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 166 .hs400_4taps = true, 167 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 168 }; 169 170 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 171 .hs400_disabled = true, 172 }; 173 174 static const struct renesas_sdhi_quirks sdhi_quirks_fixed_addr = { 175 .fixed_addr_mode = true, 176 }; 177 178 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 179 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 180 }; 181 182 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 183 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 184 }; 185 186 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 187 .hs400_4taps = true, 188 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 189 .hs400_calib_table = r8a7796_es13_calib_table, 190 }; 191 192 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 193 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 194 .hs400_calib_table = r8a77965_calib_table, 195 }; 196 197 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 198 .hs400_calib_table = r8a77990_calib_table, 199 }; 200 201 /* 202 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 203 * So, we want to treat them equally and only have a match for ES1.2 to enforce 204 * this if there ever will be a way to distinguish ES1.2. 205 */ 206 static const struct soc_device_attribute sdhi_quirks_match[] = { 207 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 208 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 }, 209 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 210 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 211 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 212 { /* Sentinel. */ } 213 }; 214 215 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = { 216 .of_data = &of_data_rcar_gen3, 217 .quirks = &sdhi_quirks_bad_taps2367, 218 }; 219 220 static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = { 221 .of_data = &of_data_rcar_gen3, 222 .quirks = &sdhi_quirks_bad_taps1357, 223 }; 224 225 static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = { 226 .of_data = &of_data_rcar_gen3, 227 .quirks = &sdhi_quirks_r8a77965, 228 }; 229 230 static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = { 231 .of_data = &of_data_rcar_gen3_no_sdh_fallback, 232 }; 233 234 static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = { 235 .of_data = &of_data_rcar_gen3, 236 .quirks = &sdhi_quirks_r8a77990, 237 }; 238 239 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = { 240 .of_data = &of_data_rcar_gen3, 241 }; 242 243 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_compatible = { 244 .of_data = &of_data_rcar_gen3, 245 .quirks = &sdhi_quirks_nohs400, 246 }; 247 248 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = { 249 .of_data = &of_data_rza2, 250 .quirks = &sdhi_quirks_fixed_addr, 251 }; 252 253 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 254 { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, }, 255 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, }, 256 { .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, }, 257 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, 258 { .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, }, 259 { .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, }, 260 { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, }, 261 { .compatible = "renesas,sdhi-r8a77980", .data = &of_rcar_gen3_nohs400_compatible, }, 262 { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, 263 { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, }, 264 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 265 {}, 266 }; 267 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 268 269 static void 270 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 271 int addr, u64 val) 272 { 273 writeq(val, host->ctl + addr); 274 } 275 276 static void 277 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 278 { 279 struct renesas_sdhi *priv = host_to_priv(host); 280 281 if (!host->chan_tx || !host->chan_rx) 282 return; 283 284 if (!enable) 285 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 286 INFO1_CLEAR); 287 288 if (priv->dma_priv.enable) 289 priv->dma_priv.enable(host, enable); 290 } 291 292 static void 293 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) { 294 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 295 296 renesas_sdhi_internal_dmac_enable_dma(host, false); 297 298 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 299 RST_RESERVED_BITS & ~val); 300 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 301 RST_RESERVED_BITS | val); 302 303 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 304 305 renesas_sdhi_internal_dmac_enable_dma(host, true); 306 } 307 308 static void 309 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) { 310 struct renesas_sdhi *priv = host_to_priv(host); 311 312 tasklet_schedule(&priv->dma_priv.dma_complete); 313 } 314 315 /* 316 * renesas_sdhi_internal_dmac_map() will be called with two difference 317 * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single 318 * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg 319 * pointer in a mmc_data instead of host->sg_ptr. 320 */ 321 static void 322 renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host, 323 struct mmc_data *data, 324 enum renesas_sdhi_dma_cookie cookie) 325 { 326 bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) : 327 (data->host_cookie == cookie); 328 329 if (unmap) { 330 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, 331 mmc_get_dma_dir(data)); 332 data->host_cookie = COOKIE_UNMAPPED; 333 } 334 } 335 336 static bool 337 renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host, 338 struct mmc_data *data, 339 enum renesas_sdhi_dma_cookie cookie) 340 { 341 if (data->host_cookie == COOKIE_PRE_MAPPED) 342 return true; 343 344 if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, 345 mmc_get_dma_dir(data))) 346 return false; 347 348 data->host_cookie = cookie; 349 350 /* This DMAC cannot handle if buffer is not 128-bytes alignment */ 351 if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) { 352 renesas_sdhi_internal_dmac_unmap(host, data, cookie); 353 return false; 354 } 355 356 return true; 357 } 358 359 static void 360 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 361 struct mmc_data *data) 362 { 363 struct renesas_sdhi *priv = host_to_priv(host); 364 struct scatterlist *sg = host->sg_ptr; 365 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH; 366 367 if (!priv->quirks->fixed_addr_mode) 368 dtran_mode |= DTRAN_MODE_ADDR_MODE; 369 370 if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED)) 371 goto force_pio; 372 373 if (data->flags & MMC_DATA_READ) { 374 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 375 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) && 376 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 377 goto force_pio_with_unmap; 378 } else { 379 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 380 } 381 382 renesas_sdhi_internal_dmac_enable_dma(host, true); 383 384 /* set dma parameters */ 385 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 386 dtran_mode); 387 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 388 sg_dma_address(sg)); 389 390 host->dma_on = true; 391 392 return; 393 394 force_pio_with_unmap: 395 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 396 397 force_pio: 398 renesas_sdhi_internal_dmac_enable_dma(host, false); 399 } 400 401 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 402 { 403 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 404 405 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 406 407 /* start the DMAC */ 408 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 409 DTRAN_CTRL_DM_START); 410 } 411 412 static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) 413 { 414 enum dma_data_direction dir; 415 416 if (!host->dma_on) 417 return false; 418 419 if (!host->data) 420 return false; 421 422 if (host->data->flags & MMC_DATA_READ) 423 dir = DMA_FROM_DEVICE; 424 else 425 dir = DMA_TO_DEVICE; 426 427 renesas_sdhi_internal_dmac_enable_dma(host, false); 428 renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED); 429 430 if (dir == DMA_FROM_DEVICE) 431 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 432 433 host->dma_on = false; 434 435 return true; 436 } 437 438 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 439 { 440 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 441 442 spin_lock_irq(&host->lock); 443 if (!renesas_sdhi_internal_dmac_complete(host)) 444 goto out; 445 446 tmio_mmc_do_data_irq(host); 447 out: 448 spin_unlock_irq(&host->lock); 449 } 450 451 static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host) 452 { 453 if (host->data) 454 renesas_sdhi_internal_dmac_complete(host); 455 } 456 457 static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc, 458 struct mmc_request *mrq, 459 int err) 460 { 461 struct tmio_mmc_host *host = mmc_priv(mmc); 462 struct mmc_data *data = mrq->data; 463 464 if (!data) 465 return; 466 467 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 468 } 469 470 static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc, 471 struct mmc_request *mrq) 472 { 473 struct tmio_mmc_host *host = mmc_priv(mmc); 474 struct mmc_data *data = mrq->data; 475 476 if (!data) 477 return; 478 479 data->host_cookie = COOKIE_UNMAPPED; 480 renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED); 481 } 482 483 static void 484 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 485 struct tmio_mmc_data *pdata) 486 { 487 struct renesas_sdhi *priv = host_to_priv(host); 488 489 /* Disable DMAC interrupts, we don't use them */ 490 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK, 491 INFO1_MASK_CLEAR); 492 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK, 493 INFO2_MASK_CLEAR); 494 495 /* Each value is set to non-zero to assume "enabling" each DMA */ 496 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 497 498 tasklet_init(&priv->dma_priv.dma_complete, 499 renesas_sdhi_internal_dmac_complete_tasklet_fn, 500 (unsigned long)host); 501 tasklet_init(&host->dma_issue, 502 renesas_sdhi_internal_dmac_issue_tasklet_fn, 503 (unsigned long)host); 504 505 /* Add pre_req and post_req */ 506 host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req; 507 host->ops.post_req = renesas_sdhi_internal_dmac_post_req; 508 } 509 510 static void 511 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 512 { 513 /* Each value is set to zero to assume "disabling" each DMA */ 514 host->chan_rx = host->chan_tx = NULL; 515 } 516 517 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 518 .start = renesas_sdhi_internal_dmac_start_dma, 519 .enable = renesas_sdhi_internal_dmac_enable_dma, 520 .request = renesas_sdhi_internal_dmac_request_dma, 521 .release = renesas_sdhi_internal_dmac_release_dma, 522 .abort = renesas_sdhi_internal_dmac_abort_dma, 523 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 524 .end = renesas_sdhi_internal_dmac_end_dma, 525 }; 526 527 static const struct soc_device_attribute soc_dma_quirks[] = { 528 { .soc_id = "r8a7795", .revision = "ES1.*", 529 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 530 { .soc_id = "r8a7796", .revision = "ES1.0", 531 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 532 { /* sentinel */ } 533 }; 534 535 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 536 { 537 const struct soc_device_attribute *attr; 538 const struct renesas_sdhi_of_data_with_quirks *of_data_quirks; 539 const struct renesas_sdhi_quirks *quirks; 540 struct device *dev = &pdev->dev; 541 542 of_data_quirks = of_device_get_match_data(&pdev->dev); 543 quirks = of_data_quirks->quirks; 544 545 attr = soc_device_match(soc_dma_quirks); 546 if (attr) 547 global_flags |= (unsigned long)attr->data; 548 549 attr = soc_device_match(sdhi_quirks_match); 550 if (attr) 551 quirks = attr->data; 552 553 /* value is max of SD_SECCNT. Confirmed by HW engineers */ 554 dma_set_max_seg_size(dev, 0xffffffff); 555 556 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops, 557 of_data_quirks->of_data, quirks); 558 } 559 560 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 561 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 562 pm_runtime_force_resume) 563 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 564 tmio_mmc_host_runtime_resume, 565 NULL) 566 }; 567 568 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 569 .driver = { 570 .name = "renesas_sdhi_internal_dmac", 571 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 572 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 573 .of_match_table = renesas_sdhi_internal_dmac_of_match, 574 }, 575 .probe = renesas_sdhi_internal_dmac_probe, 576 .remove = renesas_sdhi_remove, 577 }; 578 579 module_platform_driver(renesas_internal_dmac_sdhi_driver); 580 581 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 582 MODULE_AUTHOR("Yoshihiro Shimoda"); 583 MODULE_LICENSE("GPL v2"); 584