1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DMA support for Internal DMAC with SDHI SD/SDIO controller 4 * 5 * Copyright (C) 2016-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/device.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/io-64-nonatomic-hi-lo.h> 14 #include <linux/mfd/tmio.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/pagemap.h> 20 #include <linux/scatterlist.h> 21 #include <linux/sys_soc.h> 22 23 #include "renesas_sdhi.h" 24 #include "tmio_mmc.h" 25 26 #define DM_CM_DTRAN_MODE 0x820 27 #define DM_CM_DTRAN_CTRL 0x828 28 #define DM_CM_RST 0x830 29 #define DM_CM_INFO1 0x840 30 #define DM_CM_INFO1_MASK 0x848 31 #define DM_CM_INFO2 0x850 32 #define DM_CM_INFO2_MASK 0x858 33 #define DM_DTRAN_ADDR 0x880 34 35 /* DM_CM_DTRAN_MODE */ 36 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 37 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 38 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 39 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */ 40 41 /* DM_CM_DTRAN_CTRL */ 42 #define DTRAN_CTRL_DM_START BIT(0) 43 44 /* DM_CM_RST */ 45 #define RST_DTRANRST1 BIT(9) 46 #define RST_DTRANRST0 BIT(8) 47 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 48 49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 50 #define INFO1_CLEAR 0 51 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 52 #define INFO1_DTRANEND1 BIT(17) 53 #define INFO1_DTRANEND0 BIT(16) 54 55 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 56 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 57 #define INFO2_DTRANERR1 BIT(17) 58 #define INFO2_DTRANERR0 BIT(16) 59 60 enum renesas_sdhi_dma_cookie { 61 COOKIE_UNMAPPED, 62 COOKIE_PRE_MAPPED, 63 COOKIE_MAPPED, 64 }; 65 66 /* 67 * Specification of this driver: 68 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 69 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 70 * need a custom accessor. 71 */ 72 73 static unsigned long global_flags; 74 /* 75 * Workaround for avoiding to use RX DMAC by multiple channels. 76 * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use 77 * RX DMAC simultaneously, sometimes hundreds of bytes data are not 78 * stored into the system memory even if the DMAC interrupt happened. 79 * So, this driver then uses one RX DMAC channel only. 80 */ 81 #define SDHI_INTERNAL_DMAC_RX_IN_USE 0 82 83 /* Definitions for sampling clocks */ 84 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 85 { 86 .clk_rate = 0, 87 .tap = 0x00000300, 88 .tap_hs400_4tap = 0x00000100, 89 }, 90 }; 91 92 static const struct renesas_sdhi_of_data of_data_rza2 = { 93 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 94 TMIO_MMC_HAVE_CBSY, 95 .tmio_ocr_mask = MMC_VDD_32_33, 96 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 97 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 98 .bus_shift = 2, 99 .scc_offset = 0 - 0x1000, 100 .taps = rcar_gen3_scc_taps, 101 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 102 /* DMAC can handle 32bit blk count but only 1 segment */ 103 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 104 .max_segs = 1, 105 }; 106 107 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = { 108 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 109 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 110 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 111 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 112 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 113 .bus_shift = 2, 114 .scc_offset = 0x1000, 115 .taps = rcar_gen3_scc_taps, 116 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 117 /* DMAC can handle 32bit blk count but only 1 segment */ 118 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 119 .max_segs = 1, 120 .sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK, 121 }; 122 123 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = { 124 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 125 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 126 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 127 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 128 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 129 .bus_shift = 2, 130 .scc_offset = 0x1000, 131 .taps = rcar_gen3_scc_taps, 132 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 133 /* DMAC can handle 32bit blk count but only 1 segment */ 134 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 135 .max_segs = 1, 136 }; 137 138 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 139 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 140 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 141 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 142 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 143 }; 144 145 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 146 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 147 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 148 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 149 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 150 }; 151 152 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 153 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 154 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 155 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 156 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 157 }; 158 159 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 160 .hs400_disabled = true, 161 .hs400_4taps = true, 162 }; 163 164 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = { 165 .hs400_disabled = true, 166 .hs400_4taps = true, 167 .dma_one_rx_only = true, 168 }; 169 170 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 171 .hs400_4taps = true, 172 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 173 .manual_tap_correction = true, 174 }; 175 176 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 177 .hs400_disabled = true, 178 }; 179 180 static const struct renesas_sdhi_quirks sdhi_quirks_fixed_addr = { 181 .fixed_addr_mode = true, 182 }; 183 184 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 185 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 186 .manual_tap_correction = true, 187 }; 188 189 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 190 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 191 .manual_tap_correction = true, 192 }; 193 194 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 195 .hs400_4taps = true, 196 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 197 .hs400_calib_table = r8a7796_es13_calib_table, 198 .manual_tap_correction = true, 199 }; 200 201 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 202 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 203 .hs400_calib_table = r8a77965_calib_table, 204 .manual_tap_correction = true, 205 }; 206 207 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 208 .hs400_calib_table = r8a77990_calib_table, 209 .manual_tap_correction = true, 210 }; 211 212 /* 213 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 214 * So, we want to treat them equally and only have a match for ES1.2 to enforce 215 * this if there ever will be a way to distinguish ES1.2. 216 */ 217 static const struct soc_device_attribute sdhi_quirks_match[] = { 218 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 219 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400_one_rx }, 220 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 221 { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_4tap_nohs400_one_rx }, 222 { .soc_id = "r8a7796", .revision = "ES1.[12]", .data = &sdhi_quirks_4tap_nohs400 }, 223 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 224 { .soc_id = "r8a77980", .revision = "ES1.*", .data = &sdhi_quirks_nohs400 }, 225 { /* Sentinel. */ } 226 }; 227 228 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = { 229 .of_data = &of_data_rcar_gen3, 230 .quirks = &sdhi_quirks_bad_taps2367, 231 }; 232 233 static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = { 234 .of_data = &of_data_rcar_gen3, 235 .quirks = &sdhi_quirks_bad_taps1357, 236 }; 237 238 static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = { 239 .of_data = &of_data_rcar_gen3, 240 .quirks = &sdhi_quirks_r8a77965, 241 }; 242 243 static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = { 244 .of_data = &of_data_rcar_gen3_no_sdh_fallback, 245 .quirks = &sdhi_quirks_nohs400, 246 }; 247 248 static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = { 249 .of_data = &of_data_rcar_gen3, 250 .quirks = &sdhi_quirks_r8a77990, 251 }; 252 253 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = { 254 .of_data = &of_data_rcar_gen3, 255 }; 256 257 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_compatible = { 258 .of_data = &of_data_rcar_gen3, 259 .quirks = &sdhi_quirks_nohs400, 260 }; 261 262 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = { 263 .of_data = &of_data_rza2, 264 .quirks = &sdhi_quirks_fixed_addr, 265 }; 266 267 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 268 { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, }, 269 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, }, 270 { .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, }, 271 { .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, }, 272 { .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, }, 273 { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, }, 274 { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, 275 { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, }, 276 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 277 { .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, }, 278 {}, 279 }; 280 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 281 282 static void 283 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 284 int addr, u64 val) 285 { 286 writeq(val, host->ctl + addr); 287 } 288 289 static void 290 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 291 { 292 struct renesas_sdhi *priv = host_to_priv(host); 293 294 if (!host->chan_tx || !host->chan_rx) 295 return; 296 297 if (!enable) 298 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 299 INFO1_CLEAR); 300 301 if (priv->dma_priv.enable) 302 priv->dma_priv.enable(host, enable); 303 } 304 305 static void 306 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) 307 { 308 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 309 310 renesas_sdhi_internal_dmac_enable_dma(host, false); 311 312 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 313 RST_RESERVED_BITS & ~val); 314 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 315 RST_RESERVED_BITS | val); 316 317 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 318 319 renesas_sdhi_internal_dmac_enable_dma(host, true); 320 } 321 322 static void 323 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) 324 { 325 struct renesas_sdhi *priv = host_to_priv(host); 326 327 tasklet_schedule(&priv->dma_priv.dma_complete); 328 } 329 330 /* 331 * renesas_sdhi_internal_dmac_map() will be called with two different 332 * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single 333 * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg 334 * pointer in a mmc_data instead of host->sg_ptr. 335 */ 336 static void 337 renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host, 338 struct mmc_data *data, 339 enum renesas_sdhi_dma_cookie cookie) 340 { 341 bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) : 342 (data->host_cookie == cookie); 343 344 if (unmap) { 345 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, 346 mmc_get_dma_dir(data)); 347 data->host_cookie = COOKIE_UNMAPPED; 348 } 349 } 350 351 static bool 352 renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host, 353 struct mmc_data *data, 354 enum renesas_sdhi_dma_cookie cookie) 355 { 356 if (data->host_cookie == COOKIE_PRE_MAPPED) 357 return true; 358 359 if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, 360 mmc_get_dma_dir(data))) 361 return false; 362 363 data->host_cookie = cookie; 364 365 /* This DMAC needs buffers to be 128-byte aligned */ 366 if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) { 367 renesas_sdhi_internal_dmac_unmap(host, data, cookie); 368 return false; 369 } 370 371 return true; 372 } 373 374 static void 375 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 376 struct mmc_data *data) 377 { 378 struct renesas_sdhi *priv = host_to_priv(host); 379 struct scatterlist *sg = host->sg_ptr; 380 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH; 381 382 if (!(priv->quirks && priv->quirks->fixed_addr_mode)) 383 dtran_mode |= DTRAN_MODE_ADDR_MODE; 384 385 if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED)) 386 goto force_pio; 387 388 if (data->flags & MMC_DATA_READ) { 389 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 390 if (priv->quirks && priv->quirks->dma_one_rx_only && 391 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 392 goto force_pio_with_unmap; 393 } else { 394 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 395 } 396 397 renesas_sdhi_internal_dmac_enable_dma(host, true); 398 399 /* set dma parameters */ 400 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 401 dtran_mode); 402 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 403 sg_dma_address(sg)); 404 405 host->dma_on = true; 406 407 return; 408 409 force_pio_with_unmap: 410 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 411 412 force_pio: 413 renesas_sdhi_internal_dmac_enable_dma(host, false); 414 } 415 416 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 417 { 418 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 419 420 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 421 422 /* start the DMAC */ 423 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 424 DTRAN_CTRL_DM_START); 425 } 426 427 static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) 428 { 429 enum dma_data_direction dir; 430 431 if (!host->dma_on) 432 return false; 433 434 if (!host->data) 435 return false; 436 437 if (host->data->flags & MMC_DATA_READ) 438 dir = DMA_FROM_DEVICE; 439 else 440 dir = DMA_TO_DEVICE; 441 442 renesas_sdhi_internal_dmac_enable_dma(host, false); 443 renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED); 444 445 if (dir == DMA_FROM_DEVICE) 446 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 447 448 host->dma_on = false; 449 450 return true; 451 } 452 453 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 454 { 455 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 456 457 spin_lock_irq(&host->lock); 458 if (!renesas_sdhi_internal_dmac_complete(host)) 459 goto out; 460 461 tmio_mmc_do_data_irq(host); 462 out: 463 spin_unlock_irq(&host->lock); 464 } 465 466 static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host) 467 { 468 if (host->data) 469 renesas_sdhi_internal_dmac_complete(host); 470 } 471 472 static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc, 473 struct mmc_request *mrq, 474 int err) 475 { 476 struct tmio_mmc_host *host = mmc_priv(mmc); 477 struct mmc_data *data = mrq->data; 478 479 if (!data) 480 return; 481 482 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 483 } 484 485 static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc, 486 struct mmc_request *mrq) 487 { 488 struct tmio_mmc_host *host = mmc_priv(mmc); 489 struct mmc_data *data = mrq->data; 490 491 if (!data) 492 return; 493 494 data->host_cookie = COOKIE_UNMAPPED; 495 renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED); 496 } 497 498 static void 499 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 500 struct tmio_mmc_data *pdata) 501 { 502 struct renesas_sdhi *priv = host_to_priv(host); 503 504 /* Disable DMAC interrupts, we don't use them */ 505 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK, 506 INFO1_MASK_CLEAR); 507 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK, 508 INFO2_MASK_CLEAR); 509 510 /* Each value is set to non-zero to assume "enabling" each DMA */ 511 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 512 513 tasklet_init(&priv->dma_priv.dma_complete, 514 renesas_sdhi_internal_dmac_complete_tasklet_fn, 515 (unsigned long)host); 516 tasklet_init(&host->dma_issue, 517 renesas_sdhi_internal_dmac_issue_tasklet_fn, 518 (unsigned long)host); 519 520 /* Add pre_req and post_req */ 521 host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req; 522 host->ops.post_req = renesas_sdhi_internal_dmac_post_req; 523 } 524 525 static void 526 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 527 { 528 /* Each value is set to zero to assume "disabling" each DMA */ 529 host->chan_rx = host->chan_tx = NULL; 530 } 531 532 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 533 .start = renesas_sdhi_internal_dmac_start_dma, 534 .enable = renesas_sdhi_internal_dmac_enable_dma, 535 .request = renesas_sdhi_internal_dmac_request_dma, 536 .release = renesas_sdhi_internal_dmac_release_dma, 537 .abort = renesas_sdhi_internal_dmac_abort_dma, 538 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 539 .end = renesas_sdhi_internal_dmac_end_dma, 540 }; 541 542 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 543 { 544 const struct soc_device_attribute *attr; 545 const struct renesas_sdhi_of_data_with_quirks *of_data_quirks; 546 const struct renesas_sdhi_quirks *quirks; 547 struct device *dev = &pdev->dev; 548 549 of_data_quirks = of_device_get_match_data(&pdev->dev); 550 quirks = of_data_quirks->quirks; 551 552 attr = soc_device_match(sdhi_quirks_match); 553 if (attr) 554 quirks = attr->data; 555 556 /* value is max of SD_SECCNT. Confirmed by HW engineers */ 557 dma_set_max_seg_size(dev, 0xffffffff); 558 559 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops, 560 of_data_quirks->of_data, quirks); 561 } 562 563 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 564 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 565 pm_runtime_force_resume) 566 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 567 tmio_mmc_host_runtime_resume, 568 NULL) 569 }; 570 571 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 572 .driver = { 573 .name = "renesas_sdhi_internal_dmac", 574 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 575 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 576 .of_match_table = renesas_sdhi_internal_dmac_of_match, 577 }, 578 .probe = renesas_sdhi_internal_dmac_probe, 579 .remove = renesas_sdhi_remove, 580 }; 581 582 module_platform_driver(renesas_internal_dmac_sdhi_driver); 583 584 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 585 MODULE_AUTHOR("Yoshihiro Shimoda"); 586 MODULE_LICENSE("GPL v2"); 587