1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DMA support for Internal DMAC with SDHI SD/SDIO controller 4 * 5 * Copyright (C) 2016-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/device.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/io-64-nonatomic-hi-lo.h> 14 #include <linux/mfd/tmio.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/pagemap.h> 20 #include <linux/scatterlist.h> 21 #include <linux/sys_soc.h> 22 23 #include "renesas_sdhi.h" 24 #include "tmio_mmc.h" 25 26 #define DM_CM_DTRAN_MODE 0x820 27 #define DM_CM_DTRAN_CTRL 0x828 28 #define DM_CM_RST 0x830 29 #define DM_CM_INFO1 0x840 30 #define DM_CM_INFO1_MASK 0x848 31 #define DM_CM_INFO2 0x850 32 #define DM_CM_INFO2_MASK 0x858 33 #define DM_DTRAN_ADDR 0x880 34 35 /* DM_CM_DTRAN_MODE */ 36 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 37 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 38 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 39 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */ 40 41 /* DM_CM_DTRAN_CTRL */ 42 #define DTRAN_CTRL_DM_START BIT(0) 43 44 /* DM_CM_RST */ 45 #define RST_DTRANRST1 BIT(9) 46 #define RST_DTRANRST0 BIT(8) 47 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 48 49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 50 #define INFO1_CLEAR 0 51 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 52 #define INFO1_DTRANEND1 BIT(17) 53 #define INFO1_DTRANEND0 BIT(16) 54 55 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 56 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 57 #define INFO2_DTRANERR1 BIT(17) 58 #define INFO2_DTRANERR0 BIT(16) 59 60 enum renesas_sdhi_dma_cookie { 61 COOKIE_UNMAPPED, 62 COOKIE_PRE_MAPPED, 63 COOKIE_MAPPED, 64 }; 65 66 /* 67 * Specification of this driver: 68 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 69 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 70 * need a custom accessor. 71 */ 72 73 static unsigned long global_flags; 74 /* 75 * Workaround for avoiding to use RX DMAC by multiple channels. 76 * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use 77 * RX DMAC simultaneously, sometimes hundreds of bytes data are not 78 * stored into the system memory even if the DMAC interrupt happened. 79 * So, this driver then uses one RX DMAC channel only. 80 */ 81 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0 82 #define SDHI_INTERNAL_DMAC_RX_IN_USE 1 83 84 /* RZ/A2 does not have the ADRR_MODE bit */ 85 #define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2 86 87 /* Definitions for sampling clocks */ 88 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 89 { 90 .clk_rate = 0, 91 .tap = 0x00000300, 92 .tap_hs400_4tap = 0x00000100, 93 }, 94 }; 95 96 static const struct renesas_sdhi_of_data of_data_rza2 = { 97 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 98 TMIO_MMC_HAVE_CBSY, 99 .tmio_ocr_mask = MMC_VDD_32_33, 100 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 101 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 102 .bus_shift = 2, 103 .scc_offset = 0 - 0x1000, 104 .taps = rcar_gen3_scc_taps, 105 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 106 /* DMAC can handle 32bit blk count but only 1 segment */ 107 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 108 .max_segs = 1, 109 }; 110 111 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = { 112 .of_data = &of_data_rza2, 113 }; 114 115 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = { 116 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 117 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 118 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 119 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 120 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 121 .bus_shift = 2, 122 .scc_offset = 0x1000, 123 .taps = rcar_gen3_scc_taps, 124 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 125 /* DMAC can handle 32bit blk count but only 1 segment */ 126 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 127 .max_segs = 1, 128 .sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK, 129 }; 130 131 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = { 132 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 133 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 134 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 135 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 136 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 137 .bus_shift = 2, 138 .scc_offset = 0x1000, 139 .taps = rcar_gen3_scc_taps, 140 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 141 /* DMAC can handle 32bit blk count but only 1 segment */ 142 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 143 .max_segs = 1, 144 }; 145 146 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 147 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 148 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 149 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 150 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 151 }; 152 153 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 154 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 155 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 156 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 157 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 158 }; 159 160 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 161 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 162 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 163 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 164 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 165 }; 166 167 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 168 .hs400_disabled = true, 169 .hs400_4taps = true, 170 }; 171 172 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 173 .hs400_4taps = true, 174 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 175 }; 176 177 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 178 .hs400_disabled = true, 179 }; 180 181 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 182 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 183 }; 184 185 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 186 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 187 }; 188 189 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 190 .hs400_4taps = true, 191 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 192 .hs400_calib_table = r8a7796_es13_calib_table, 193 }; 194 195 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 196 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 197 .hs400_calib_table = r8a77965_calib_table, 198 }; 199 200 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 201 .hs400_calib_table = r8a77990_calib_table, 202 }; 203 204 /* 205 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 206 * So, we want to treat them equally and only have a match for ES1.2 to enforce 207 * this if there ever will be a way to distinguish ES1.2. 208 */ 209 static const struct soc_device_attribute sdhi_quirks_match[] = { 210 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 211 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 }, 212 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 213 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 214 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 215 { /* Sentinel. */ } 216 }; 217 218 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = { 219 .of_data = &of_data_rcar_gen3, 220 .quirks = &sdhi_quirks_bad_taps2367, 221 }; 222 223 static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = { 224 .of_data = &of_data_rcar_gen3, 225 .quirks = &sdhi_quirks_bad_taps1357, 226 }; 227 228 static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = { 229 .of_data = &of_data_rcar_gen3, 230 .quirks = &sdhi_quirks_r8a77965, 231 }; 232 233 static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = { 234 .of_data = &of_data_rcar_gen3_no_sdh_fallback, 235 }; 236 237 static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = { 238 .of_data = &of_data_rcar_gen3, 239 .quirks = &sdhi_quirks_r8a77990, 240 }; 241 242 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = { 243 .of_data = &of_data_rcar_gen3, 244 }; 245 246 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_compatible = { 247 .of_data = &of_data_rcar_gen3, 248 .quirks = &sdhi_quirks_nohs400, 249 }; 250 251 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 252 { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, }, 253 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, }, 254 { .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, }, 255 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, 256 { .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, }, 257 { .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, }, 258 { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, }, 259 { .compatible = "renesas,sdhi-r8a77980", .data = &of_rcar_gen3_nohs400_compatible, }, 260 { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, 261 { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, }, 262 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 263 {}, 264 }; 265 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 266 267 static void 268 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 269 int addr, u64 val) 270 { 271 writeq(val, host->ctl + addr); 272 } 273 274 static void 275 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 276 { 277 struct renesas_sdhi *priv = host_to_priv(host); 278 279 if (!host->chan_tx || !host->chan_rx) 280 return; 281 282 if (!enable) 283 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 284 INFO1_CLEAR); 285 286 if (priv->dma_priv.enable) 287 priv->dma_priv.enable(host, enable); 288 } 289 290 static void 291 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) { 292 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 293 294 renesas_sdhi_internal_dmac_enable_dma(host, false); 295 296 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 297 RST_RESERVED_BITS & ~val); 298 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 299 RST_RESERVED_BITS | val); 300 301 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 302 303 renesas_sdhi_internal_dmac_enable_dma(host, true); 304 } 305 306 static void 307 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) { 308 struct renesas_sdhi *priv = host_to_priv(host); 309 310 tasklet_schedule(&priv->dma_priv.dma_complete); 311 } 312 313 /* 314 * renesas_sdhi_internal_dmac_map() will be called with two difference 315 * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single 316 * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg 317 * pointer in a mmc_data instead of host->sg_ptr. 318 */ 319 static void 320 renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host, 321 struct mmc_data *data, 322 enum renesas_sdhi_dma_cookie cookie) 323 { 324 bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) : 325 (data->host_cookie == cookie); 326 327 if (unmap) { 328 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, 329 mmc_get_dma_dir(data)); 330 data->host_cookie = COOKIE_UNMAPPED; 331 } 332 } 333 334 static bool 335 renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host, 336 struct mmc_data *data, 337 enum renesas_sdhi_dma_cookie cookie) 338 { 339 if (data->host_cookie == COOKIE_PRE_MAPPED) 340 return true; 341 342 if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, 343 mmc_get_dma_dir(data))) 344 return false; 345 346 data->host_cookie = cookie; 347 348 /* This DMAC cannot handle if buffer is not 128-bytes alignment */ 349 if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) { 350 renesas_sdhi_internal_dmac_unmap(host, data, cookie); 351 return false; 352 } 353 354 return true; 355 } 356 357 static void 358 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 359 struct mmc_data *data) 360 { 361 struct scatterlist *sg = host->sg_ptr; 362 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH; 363 364 if (!test_bit(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY, &global_flags)) 365 dtran_mode |= DTRAN_MODE_ADDR_MODE; 366 367 if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED)) 368 goto force_pio; 369 370 if (data->flags & MMC_DATA_READ) { 371 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 372 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) && 373 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 374 goto force_pio_with_unmap; 375 } else { 376 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 377 } 378 379 renesas_sdhi_internal_dmac_enable_dma(host, true); 380 381 /* set dma parameters */ 382 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 383 dtran_mode); 384 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 385 sg_dma_address(sg)); 386 387 host->dma_on = true; 388 389 return; 390 391 force_pio_with_unmap: 392 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 393 394 force_pio: 395 renesas_sdhi_internal_dmac_enable_dma(host, false); 396 } 397 398 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 399 { 400 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 401 402 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 403 404 /* start the DMAC */ 405 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 406 DTRAN_CTRL_DM_START); 407 } 408 409 static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) 410 { 411 enum dma_data_direction dir; 412 413 if (!host->dma_on) 414 return false; 415 416 if (!host->data) 417 return false; 418 419 if (host->data->flags & MMC_DATA_READ) 420 dir = DMA_FROM_DEVICE; 421 else 422 dir = DMA_TO_DEVICE; 423 424 renesas_sdhi_internal_dmac_enable_dma(host, false); 425 renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED); 426 427 if (dir == DMA_FROM_DEVICE) 428 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 429 430 host->dma_on = false; 431 432 return true; 433 } 434 435 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 436 { 437 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 438 439 spin_lock_irq(&host->lock); 440 if (!renesas_sdhi_internal_dmac_complete(host)) 441 goto out; 442 443 tmio_mmc_do_data_irq(host); 444 out: 445 spin_unlock_irq(&host->lock); 446 } 447 448 static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host) 449 { 450 if (host->data) 451 renesas_sdhi_internal_dmac_complete(host); 452 } 453 454 static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc, 455 struct mmc_request *mrq, 456 int err) 457 { 458 struct tmio_mmc_host *host = mmc_priv(mmc); 459 struct mmc_data *data = mrq->data; 460 461 if (!data) 462 return; 463 464 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 465 } 466 467 static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc, 468 struct mmc_request *mrq) 469 { 470 struct tmio_mmc_host *host = mmc_priv(mmc); 471 struct mmc_data *data = mrq->data; 472 473 if (!data) 474 return; 475 476 data->host_cookie = COOKIE_UNMAPPED; 477 renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED); 478 } 479 480 static void 481 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 482 struct tmio_mmc_data *pdata) 483 { 484 struct renesas_sdhi *priv = host_to_priv(host); 485 486 /* Disable DMAC interrupts, we don't use them */ 487 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK, 488 INFO1_MASK_CLEAR); 489 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK, 490 INFO2_MASK_CLEAR); 491 492 /* Each value is set to non-zero to assume "enabling" each DMA */ 493 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 494 495 tasklet_init(&priv->dma_priv.dma_complete, 496 renesas_sdhi_internal_dmac_complete_tasklet_fn, 497 (unsigned long)host); 498 tasklet_init(&host->dma_issue, 499 renesas_sdhi_internal_dmac_issue_tasklet_fn, 500 (unsigned long)host); 501 502 /* Add pre_req and post_req */ 503 host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req; 504 host->ops.post_req = renesas_sdhi_internal_dmac_post_req; 505 } 506 507 static void 508 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 509 { 510 /* Each value is set to zero to assume "disabling" each DMA */ 511 host->chan_rx = host->chan_tx = NULL; 512 } 513 514 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 515 .start = renesas_sdhi_internal_dmac_start_dma, 516 .enable = renesas_sdhi_internal_dmac_enable_dma, 517 .request = renesas_sdhi_internal_dmac_request_dma, 518 .release = renesas_sdhi_internal_dmac_release_dma, 519 .abort = renesas_sdhi_internal_dmac_abort_dma, 520 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 521 .end = renesas_sdhi_internal_dmac_end_dma, 522 }; 523 524 /* 525 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC 526 * implementation as others may use a different implementation. 527 */ 528 static const struct soc_device_attribute soc_dma_quirks[] = { 529 { .soc_id = "r7s9210", 530 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) }, 531 { .soc_id = "r8a7795", .revision = "ES1.*", 532 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 533 { .soc_id = "r8a7796", .revision = "ES1.0", 534 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 535 { /* sentinel */ } 536 }; 537 538 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 539 { 540 const struct soc_device_attribute *attr; 541 const struct renesas_sdhi_of_data_with_quirks *of_data_quirks; 542 const struct renesas_sdhi_quirks *quirks; 543 struct device *dev = &pdev->dev; 544 545 of_data_quirks = of_device_get_match_data(&pdev->dev); 546 quirks = of_data_quirks->quirks; 547 548 attr = soc_device_match(soc_dma_quirks); 549 if (attr) 550 global_flags |= (unsigned long)attr->data; 551 552 attr = soc_device_match(sdhi_quirks_match); 553 if (attr) 554 quirks = attr->data; 555 556 /* value is max of SD_SECCNT. Confirmed by HW engineers */ 557 dma_set_max_seg_size(dev, 0xffffffff); 558 559 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops, 560 of_data_quirks->of_data, quirks); 561 } 562 563 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 564 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 565 pm_runtime_force_resume) 566 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 567 tmio_mmc_host_runtime_resume, 568 NULL) 569 }; 570 571 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 572 .driver = { 573 .name = "renesas_sdhi_internal_dmac", 574 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 575 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 576 .of_match_table = renesas_sdhi_internal_dmac_of_match, 577 }, 578 .probe = renesas_sdhi_internal_dmac_probe, 579 .remove = renesas_sdhi_remove, 580 }; 581 582 module_platform_driver(renesas_internal_dmac_sdhi_driver); 583 584 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 585 MODULE_AUTHOR("Yoshihiro Shimoda"); 586 MODULE_LICENSE("GPL v2"); 587