1 /* 2 * DMA support for Internal DMAC with SDHI SD/SDIO controller 3 * 4 * Copyright (C) 2016-17 Renesas Electronics Corporation 5 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/io-64-nonatomic-hi-lo.h> 15 #include <linux/mfd/tmio.h> 16 #include <linux/mmc/host.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/pagemap.h> 20 #include <linux/scatterlist.h> 21 #include <linux/sys_soc.h> 22 23 #include "renesas_sdhi.h" 24 #include "tmio_mmc.h" 25 26 #define DM_CM_DTRAN_MODE 0x820 27 #define DM_CM_DTRAN_CTRL 0x828 28 #define DM_CM_RST 0x830 29 #define DM_CM_INFO1 0x840 30 #define DM_CM_INFO1_MASK 0x848 31 #define DM_CM_INFO2 0x850 32 #define DM_CM_INFO2_MASK 0x858 33 #define DM_DTRAN_ADDR 0x880 34 35 /* DM_CM_DTRAN_MODE */ 36 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 37 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "uptream" = for read commands */ 38 #define DTRAN_MODE_BUS_WID_TH (BIT(5) | BIT(4)) 39 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address */ 40 41 /* DM_CM_DTRAN_CTRL */ 42 #define DTRAN_CTRL_DM_START BIT(0) 43 44 /* DM_CM_RST */ 45 #define RST_DTRANRST1 BIT(9) 46 #define RST_DTRANRST0 BIT(8) 47 #define RST_RESERVED_BITS GENMASK_ULL(32, 0) 48 49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 50 #define INFO1_CLEAR 0 51 #define INFO1_DTRANEND1 BIT(17) 52 #define INFO1_DTRANEND0 BIT(16) 53 54 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 55 #define INFO2_DTRANERR1 BIT(17) 56 #define INFO2_DTRANERR0 BIT(16) 57 58 /* 59 * Specification of this driver: 60 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 61 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 62 * need a custom accessor. 63 */ 64 65 /* Definitions for sampling clocks */ 66 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 67 { 68 .clk_rate = 0, 69 .tap = 0x00000300, 70 }, 71 }; 72 73 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = { 74 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE | 75 TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2, 76 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 77 MMC_CAP_CMD23, 78 .bus_shift = 2, 79 .scc_offset = 0x1000, 80 .taps = rcar_gen3_scc_taps, 81 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 82 /* Gen3 SDHI DMAC can handle 0xffffffff blk count, but seg = 1 */ 83 .max_blk_count = 0xffffffff, 84 .max_segs = 1, 85 }; 86 87 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 88 { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, }, 89 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, 90 {}, 91 }; 92 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 93 94 static void 95 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 96 int addr, u64 val) 97 { 98 writeq(val, host->ctl + addr); 99 } 100 101 static void 102 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 103 { 104 if (!host->chan_tx || !host->chan_rx) 105 return; 106 107 if (!enable) 108 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 109 INFO1_CLEAR); 110 111 if (host->dma->enable) 112 host->dma->enable(host, enable); 113 } 114 115 static void 116 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) { 117 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 118 119 renesas_sdhi_internal_dmac_enable_dma(host, false); 120 121 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 122 RST_RESERVED_BITS & ~val); 123 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 124 RST_RESERVED_BITS | val); 125 126 renesas_sdhi_internal_dmac_enable_dma(host, true); 127 } 128 129 static void 130 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) { 131 tasklet_schedule(&host->dma_complete); 132 } 133 134 static void 135 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 136 struct mmc_data *data) 137 { 138 struct scatterlist *sg = host->sg_ptr; 139 u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE; 140 enum dma_data_direction dir; 141 int ret; 142 u32 irq_mask; 143 144 /* This DMAC cannot handle if sg_len is not 1 */ 145 WARN_ON(host->sg_len > 1); 146 147 /* This DMAC cannot handle if buffer is not 8-bytes alignment */ 148 if (!IS_ALIGNED(sg->offset, 8)) { 149 host->force_pio = true; 150 renesas_sdhi_internal_dmac_enable_dma(host, false); 151 return; 152 } 153 154 if (data->flags & MMC_DATA_READ) { 155 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 156 dir = DMA_FROM_DEVICE; 157 irq_mask = TMIO_STAT_RXRDY; 158 } else { 159 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 160 dir = DMA_TO_DEVICE; 161 irq_mask = TMIO_STAT_TXRQ; 162 } 163 164 ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir); 165 if (ret < 0) 166 return; 167 168 renesas_sdhi_internal_dmac_enable_dma(host, true); 169 170 /* disable PIO irqs to avoid "PIO IRQ in DMA mode!" */ 171 tmio_mmc_disable_mmc_irqs(host, irq_mask); 172 173 /* set dma parameters */ 174 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 175 dtran_mode); 176 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 177 sg->dma_address); 178 } 179 180 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 181 { 182 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 183 184 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 185 186 /* start the DMAC */ 187 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 188 DTRAN_CTRL_DM_START); 189 } 190 191 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 192 { 193 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 194 enum dma_data_direction dir; 195 196 spin_lock_irq(&host->lock); 197 198 if (!host->data) 199 goto out; 200 201 if (host->data->flags & MMC_DATA_READ) 202 dir = DMA_FROM_DEVICE; 203 else 204 dir = DMA_TO_DEVICE; 205 206 renesas_sdhi_internal_dmac_enable_dma(host, false); 207 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir); 208 209 tmio_mmc_do_data_irq(host); 210 out: 211 spin_unlock_irq(&host->lock); 212 } 213 214 static void 215 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 216 struct tmio_mmc_data *pdata) 217 { 218 /* Each value is set to non-zero to assume "enabling" each DMA */ 219 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 220 221 tasklet_init(&host->dma_complete, 222 renesas_sdhi_internal_dmac_complete_tasklet_fn, 223 (unsigned long)host); 224 tasklet_init(&host->dma_issue, 225 renesas_sdhi_internal_dmac_issue_tasklet_fn, 226 (unsigned long)host); 227 } 228 229 static void 230 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 231 { 232 /* Each value is set to zero to assume "disabling" each DMA */ 233 host->chan_rx = host->chan_tx = NULL; 234 } 235 236 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 237 .start = renesas_sdhi_internal_dmac_start_dma, 238 .enable = renesas_sdhi_internal_dmac_enable_dma, 239 .request = renesas_sdhi_internal_dmac_request_dma, 240 .release = renesas_sdhi_internal_dmac_release_dma, 241 .abort = renesas_sdhi_internal_dmac_abort_dma, 242 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 243 }; 244 245 /* 246 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC 247 * implementation as others may use a different implementation. 248 */ 249 static const struct soc_device_attribute gen3_soc_whitelist[] = { 250 { .soc_id = "r8a7795", .revision = "ES1.*" }, 251 { .soc_id = "r8a7795", .revision = "ES2.0" }, 252 { .soc_id = "r8a7796", .revision = "ES1.0" }, 253 { /* sentinel */ } 254 }; 255 256 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 257 { 258 if (!soc_device_match(gen3_soc_whitelist)) 259 return -ENODEV; 260 261 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops); 262 } 263 264 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 265 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 266 pm_runtime_force_resume) 267 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 268 tmio_mmc_host_runtime_resume, 269 NULL) 270 }; 271 272 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 273 .driver = { 274 .name = "renesas_sdhi_internal_dmac", 275 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 276 .of_match_table = renesas_sdhi_internal_dmac_of_match, 277 }, 278 .probe = renesas_sdhi_internal_dmac_probe, 279 .remove = renesas_sdhi_remove, 280 }; 281 282 module_platform_driver(renesas_internal_dmac_sdhi_driver); 283 284 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 285 MODULE_AUTHOR("Yoshihiro Shimoda"); 286 MODULE_LICENSE("GPL v2"); 287