1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/iopoll.h> 24 #include <linux/kernel.h> 25 #include <linux/mfd/tmio.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/mmc.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/module.h> 30 #include <linux/of_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pinctrl/pinctrl-state.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_domain.h> 35 #include <linux/regulator/consumer.h> 36 #include <linux/reset.h> 37 #include <linux/sh_dma.h> 38 #include <linux/slab.h> 39 #include <linux/sys_soc.h> 40 41 #include "renesas_sdhi.h" 42 #include "tmio_mmc.h" 43 44 #define CTL_HOST_MODE 0xe4 45 #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 46 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 47 #define HOST_MODE_GEN3_WMODE BIT(0) 48 #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 49 50 #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 51 #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 52 #define HOST_MODE_GEN3_64BIT 0 53 54 #define CTL_SDIF_MODE 0xe6 55 #define SDIF_MODE_HS400 BIT(0) 56 57 #define SDHI_VER_GEN2_SDR50 0x490c 58 #define SDHI_VER_RZ_A1 0x820b 59 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 60 #define SDHI_VER_GEN2_SDR104 0xcb0d 61 #define SDHI_VER_GEN3_SD 0xcc10 62 #define SDHI_VER_GEN3_SDMMC 0xcd10 63 64 #define SDHI_GEN3_MMC0_ADDR 0xee140000 65 66 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 67 { 68 u32 val; 69 70 /* 71 * see also 72 * renesas_sdhi_of_data :: dma_buswidth 73 */ 74 switch (sd_ctrl_read16(host, CTL_VERSION)) { 75 case SDHI_VER_GEN2_SDR50: 76 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 77 break; 78 case SDHI_VER_GEN2_SDR104: 79 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 80 break; 81 case SDHI_VER_GEN3_SD: 82 case SDHI_VER_GEN3_SDMMC: 83 if (width == 64) 84 val = HOST_MODE_GEN3_64BIT; 85 else if (width == 32) 86 val = HOST_MODE_GEN3_32BIT; 87 else 88 val = HOST_MODE_GEN3_16BIT; 89 break; 90 default: 91 /* nothing to do */ 92 return; 93 } 94 95 sd_ctrl_write16(host, CTL_HOST_MODE, val); 96 } 97 98 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 99 { 100 struct mmc_host *mmc = host->mmc; 101 struct renesas_sdhi *priv = host_to_priv(host); 102 int ret; 103 104 ret = clk_prepare_enable(priv->clk_cd); 105 if (ret < 0) 106 return ret; 107 108 /* 109 * The clock driver may not know what maximum frequency 110 * actually works, so it should be set with the max-frequency 111 * property which will already have been read to f_max. If it 112 * was missing, assume the current frequency is the maximum. 113 */ 114 if (!mmc->f_max) 115 mmc->f_max = clk_get_rate(priv->clk); 116 117 /* 118 * Minimum frequency is the minimum input clock frequency 119 * divided by our maximum divider. 120 */ 121 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 122 123 /* enable 16bit data access on SDBUF as default */ 124 renesas_sdhi_sdbuf_width(host, 16); 125 126 return 0; 127 } 128 129 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 130 unsigned int new_clock) 131 { 132 struct renesas_sdhi *priv = host_to_priv(host); 133 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 134 int i; 135 136 /* 137 * We simply return the current rate if a) we are not on a R-Car Gen2+ 138 * SoC (may work for others, but untested) or b) if the SCC needs its 139 * clock during tuning, so we don't change the external clock setup. 140 */ 141 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 142 return clk_get_rate(priv->clk); 143 144 /* 145 * We want the bus clock to be as close as possible to, but no 146 * greater than, new_clock. As we can divide by 1 << i for 147 * any i in [0, 9] we want the input clock to be as close as 148 * possible, but no greater than, new_clock << i. 149 */ 150 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 151 freq = clk_round_rate(priv->clk, new_clock << i); 152 if (freq > (new_clock << i)) { 153 /* Too fast; look for a slightly slower option */ 154 freq = clk_round_rate(priv->clk, 155 (new_clock << i) / 4 * 3); 156 if (freq > (new_clock << i)) 157 continue; 158 } 159 160 diff = new_clock - (freq >> i); 161 if (diff <= diff_min) { 162 best_freq = freq; 163 diff_min = diff; 164 } 165 } 166 167 clk_set_rate(priv->clk, best_freq); 168 169 return clk_get_rate(priv->clk); 170 } 171 172 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 173 unsigned int new_clock) 174 { 175 u32 clk = 0, clock; 176 177 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 178 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 179 180 if (new_clock == 0) { 181 host->mmc->actual_clock = 0; 182 goto out; 183 } 184 185 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 186 clock = host->mmc->actual_clock / 512; 187 188 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 189 clock <<= 1; 190 191 /* 1/1 clock is option */ 192 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 193 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 194 clk |= 0xff; 195 else 196 clk &= ~0xff; 197 } 198 199 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 200 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 201 usleep_range(10000, 11000); 202 203 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 204 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 205 206 out: 207 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 208 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 209 usleep_range(10000, 11000); 210 } 211 212 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 213 { 214 struct renesas_sdhi *priv = host_to_priv(host); 215 216 clk_disable_unprepare(priv->clk_cd); 217 } 218 219 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 220 { 221 struct tmio_mmc_host *host = mmc_priv(mmc); 222 223 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 224 TMIO_STAT_DAT0); 225 } 226 227 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 228 struct mmc_ios *ios) 229 { 230 struct tmio_mmc_host *host = mmc_priv(mmc); 231 struct renesas_sdhi *priv = host_to_priv(host); 232 struct pinctrl_state *pin_state; 233 int ret; 234 235 switch (ios->signal_voltage) { 236 case MMC_SIGNAL_VOLTAGE_330: 237 pin_state = priv->pins_default; 238 break; 239 case MMC_SIGNAL_VOLTAGE_180: 240 pin_state = priv->pins_uhs; 241 break; 242 default: 243 return -EINVAL; 244 } 245 246 /* 247 * If anything is missing, assume signal voltage is fixed at 248 * 3.3V and succeed/fail accordingly. 249 */ 250 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 251 return ios->signal_voltage == 252 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 253 254 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 255 if (ret < 0) 256 return ret; 257 258 return pinctrl_select_state(priv->pinctrl, pin_state); 259 } 260 261 /* SCC registers */ 262 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 263 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 264 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 265 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 266 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 267 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 268 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 269 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 270 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 271 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 272 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 273 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 274 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 275 276 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 277 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 278 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 279 280 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 281 282 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 283 284 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 285 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 286 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 287 288 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 289 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 290 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 291 292 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 293 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 294 295 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 296 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 297 298 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 299 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 300 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 301 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 302 303 /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 304 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 305 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 306 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 307 308 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 309 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 310 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 311 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 312 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 313 }; 314 315 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 316 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 317 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 318 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 319 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 320 }; 321 322 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 323 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 324 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 325 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 326 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 327 }; 328 329 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 330 struct renesas_sdhi *priv, int addr) 331 { 332 return readl(priv->scc_ctl + (addr << host->bus_shift)); 333 } 334 335 static inline void sd_scc_write32(struct tmio_mmc_host *host, 336 struct renesas_sdhi *priv, 337 int addr, u32 val) 338 { 339 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 340 } 341 342 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 343 { 344 struct renesas_sdhi *priv; 345 346 priv = host_to_priv(host); 347 348 /* Initialize SCC */ 349 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 350 351 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 352 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 353 354 /* set sampling clock selection range */ 355 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 356 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 357 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 358 359 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 360 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 361 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 362 363 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 364 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 365 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 366 367 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 368 369 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 370 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 371 372 /* Read TAPNUM */ 373 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 374 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 375 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 376 } 377 378 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 379 { 380 struct tmio_mmc_host *host = mmc_priv(mmc); 381 struct renesas_sdhi *priv = host_to_priv(host); 382 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 383 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 384 385 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 386 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 387 388 /* Set HS400 mode */ 389 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 390 sd_ctrl_read16(host, CTL_SDIF_MODE)); 391 392 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 393 priv->scc_tappos_hs400); 394 395 /* Gen3 can't do automatic tap correction with HS400, so disable it */ 396 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) 397 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 398 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 399 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 400 401 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 402 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 403 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 404 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 405 406 /* Set the sampling clock selection range of HS400 mode */ 407 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 408 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 409 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 410 411 /* Avoid bad TAP */ 412 if (bad_taps & BIT(priv->tap_set)) { 413 u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 414 415 if (bad_taps & BIT(new_tap)) 416 new_tap = (priv->tap_set - 1) % priv->tap_num; 417 418 if (bad_taps & BIT(new_tap)) { 419 new_tap = priv->tap_set; 420 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 421 } 422 423 priv->tap_set = new_tap; 424 } 425 426 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 427 priv->tap_set / (use_4tap ? 2 : 1)); 428 429 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 430 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 431 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 432 433 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 434 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 435 436 if (priv->adjust_hs400_calib_table) 437 priv->needs_adjust_hs400 = true; 438 } 439 440 static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 441 { 442 struct tmio_mmc_host *host = mmc_priv(mmc); 443 struct renesas_sdhi *priv = host_to_priv(host); 444 445 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 446 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 447 448 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 449 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 450 sd_scc_read32(host, priv, 451 SH_MOBILE_SDHI_SCC_CKSEL)); 452 453 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 454 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 455 sd_scc_read32(host, priv, 456 SH_MOBILE_SDHI_SCC_DTCNTL)); 457 458 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 459 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 460 } 461 462 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 463 struct renesas_sdhi *priv, u32 addr) 464 { 465 /* read mode */ 466 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 467 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 468 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 469 470 /* access start and stop */ 471 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 472 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 473 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 474 475 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 476 } 477 478 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 479 struct renesas_sdhi *priv, u32 addr, u32 val) 480 { 481 /* write mode */ 482 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 483 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 484 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 485 486 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 487 488 /* access start and stop */ 489 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 490 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 491 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 492 } 493 494 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 495 { 496 struct renesas_sdhi *priv = host_to_priv(host); 497 u32 calib_code; 498 499 /* disable write protect */ 500 sd_scc_tmpport_write32(host, priv, 0x00, 501 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 502 /* read calibration code and adjust */ 503 calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 504 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 505 506 sd_scc_tmpport_write32(host, priv, 0x22, 507 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 508 priv->adjust_hs400_calib_table[calib_code]); 509 510 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 511 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 512 513 /* adjustment done, clear flag */ 514 priv->needs_adjust_hs400 = false; 515 } 516 517 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 518 { 519 struct renesas_sdhi *priv = host_to_priv(host); 520 521 /* disable write protect */ 522 sd_scc_tmpport_write32(host, priv, 0x00, 523 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 524 /* disable manual calibration */ 525 sd_scc_tmpport_write32(host, priv, 0x22, 0); 526 /* clear offset value of TMPPORT3 */ 527 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 528 } 529 530 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 531 struct renesas_sdhi *priv) 532 { 533 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 534 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 535 536 /* Reset HS400 mode */ 537 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 538 sd_ctrl_read16(host, CTL_SDIF_MODE)); 539 540 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 541 542 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 543 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 544 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 545 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 546 547 if (priv->adjust_hs400_calib_table) 548 renesas_sdhi_adjust_hs400_mode_disable(host); 549 550 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 551 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 552 } 553 554 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 555 { 556 struct tmio_mmc_host *host = mmc_priv(mmc); 557 558 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 559 return 0; 560 } 561 562 static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) 563 { 564 renesas_sdhi_disable_scc(host->mmc); 565 renesas_sdhi_reset_hs400_mode(host, priv); 566 priv->needs_adjust_hs400 = false; 567 568 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 569 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 570 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 571 } 572 573 /* only populated for TMIO_MMC_MIN_RCAR2 */ 574 static void renesas_sdhi_reset(struct tmio_mmc_host *host) 575 { 576 struct renesas_sdhi *priv = host_to_priv(host); 577 int ret; 578 u16 val; 579 580 if (priv->rstc) { 581 reset_control_reset(priv->rstc); 582 /* Unknown why but without polling reset status, it will hang */ 583 read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, 584 false, priv->rstc); 585 priv->needs_adjust_hs400 = false; 586 renesas_sdhi_set_clock(host, host->clk_cache); 587 } else if (priv->scc_ctl) { 588 renesas_sdhi_scc_reset(host, priv); 589 } 590 591 if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { 592 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 593 val |= CARD_OPT_EXTOP; 594 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); 595 } 596 } 597 598 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) 599 { 600 u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 601 602 num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; 603 return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); 604 605 } 606 607 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 608 609 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 610 { 611 struct renesas_sdhi *priv = host_to_priv(host); 612 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 613 unsigned int taps_size = priv->tap_num * 2, min_tap_row; 614 unsigned long *bitmap; 615 616 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 617 618 /* 619 * When tuning CMD19 is issued twice for each tap, merge the 620 * result requiring the tap to be good in both runs before 621 * considering it for tuning selection. 622 */ 623 for (i = 0; i < taps_size; i++) { 624 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 625 626 if (!test_bit(i, priv->taps)) 627 clear_bit(i + offset, priv->taps); 628 629 if (!test_bit(i, priv->smpcmp)) 630 clear_bit(i + offset, priv->smpcmp); 631 } 632 633 /* 634 * If all TAP are OK, the sampling clock position is selected by 635 * identifying the change point of data. 636 */ 637 if (bitmap_full(priv->taps, taps_size)) { 638 bitmap = priv->smpcmp; 639 min_tap_row = 1; 640 } else { 641 bitmap = priv->taps; 642 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 643 } 644 645 /* 646 * Find the longest consecutive run of successful probes. If that 647 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 648 * center index as the tap, otherwise bail out. 649 */ 650 bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) { 651 if (re - rs > tap_cnt) { 652 tap_end = re; 653 tap_start = rs; 654 tap_cnt = tap_end - tap_start; 655 } 656 } 657 658 if (tap_cnt >= min_tap_row) 659 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 660 else 661 return -EIO; 662 663 /* Set SCC */ 664 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 665 666 /* Enable auto re-tuning */ 667 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 668 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 669 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 670 671 return 0; 672 } 673 674 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 675 { 676 struct tmio_mmc_host *host = mmc_priv(mmc); 677 struct renesas_sdhi *priv = host_to_priv(host); 678 int i, ret; 679 680 priv->tap_num = renesas_sdhi_init_tuning(host); 681 if (!priv->tap_num) 682 return 0; /* Tuning is not supported */ 683 684 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 685 dev_err(&host->pdev->dev, 686 "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 687 return -EINVAL; 688 } 689 690 bitmap_zero(priv->taps, priv->tap_num * 2); 691 bitmap_zero(priv->smpcmp, priv->tap_num * 2); 692 693 /* Issue CMD19 twice for each tap */ 694 for (i = 0; i < 2 * priv->tap_num; i++) { 695 /* Set sampling clock position */ 696 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 697 698 if (mmc_send_tuning(mmc, opcode, NULL) == 0) 699 set_bit(i, priv->taps); 700 701 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 702 set_bit(i, priv->smpcmp); 703 } 704 705 ret = renesas_sdhi_select_tuning(host); 706 if (ret < 0) 707 renesas_sdhi_scc_reset(host, priv); 708 return ret; 709 } 710 711 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 712 { 713 struct renesas_sdhi *priv = host_to_priv(host); 714 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 715 u32 val; 716 717 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 718 if (!val) 719 return false; 720 721 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 722 723 /* Change TAP position according to correction status */ 724 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && 725 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 726 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 727 /* 728 * With HS400, the DAT signal is based on DS, not CLK. 729 * Therefore, use only CMD status. 730 */ 731 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 732 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 733 if (!smpcmp) { 734 return false; /* no error in CMD signal */ 735 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 736 new_tap++; 737 error_tap--; 738 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 739 new_tap--; 740 error_tap++; 741 } else { 742 return true; /* need retune */ 743 } 744 745 /* 746 * When new_tap is a bad tap, we cannot change. Then, we compare 747 * with the HS200 tuning result. When smpcmp[error_tap] is OK, 748 * we can at least retune. 749 */ 750 if (bad_taps & BIT(new_tap % priv->tap_num)) 751 return test_bit(error_tap % priv->tap_num, priv->smpcmp); 752 } else { 753 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 754 return true; /* need retune */ 755 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 756 new_tap++; 757 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 758 new_tap--; 759 else 760 return false; 761 } 762 763 priv->tap_set = (new_tap % priv->tap_num); 764 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 765 priv->tap_set / (use_4tap ? 2 : 1)); 766 767 return false; 768 } 769 770 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 771 { 772 struct renesas_sdhi *priv = host_to_priv(host); 773 774 /* Check SCC error */ 775 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 776 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 777 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 778 return true; 779 } 780 781 return false; 782 } 783 784 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, 785 struct mmc_request *mrq) 786 { 787 struct renesas_sdhi *priv = host_to_priv(host); 788 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 789 bool ret = false; 790 791 /* 792 * Skip checking SCC errors when running on 4 taps in HS400 mode as 793 * any retuning would still result in the same 4 taps being used. 794 */ 795 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 796 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 797 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 798 return false; 799 800 if (mmc_doing_tune(host->mmc)) 801 return false; 802 803 if (((mrq->cmd->error == -ETIMEDOUT) || 804 (mrq->data && mrq->data->error == -ETIMEDOUT)) && 805 ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 806 (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 807 ret |= true; 808 809 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 810 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 811 ret |= renesas_sdhi_auto_correction(host); 812 else 813 ret |= renesas_sdhi_manual_correction(host, use_4tap); 814 815 return ret; 816 } 817 818 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 819 { 820 int timeout = 1000; 821 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 822 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 823 824 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 825 & bit) == wait_state) 826 udelay(1); 827 828 if (!timeout) { 829 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 830 return -EBUSY; 831 } 832 833 return 0; 834 } 835 836 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 837 { 838 u32 bit = TMIO_STAT_SCLKDIVEN; 839 840 switch (addr) { 841 case CTL_SD_CMD: 842 case CTL_STOP_INTERNAL_ACTION: 843 case CTL_XFER_BLK_COUNT: 844 case CTL_SD_XFER_LEN: 845 case CTL_SD_MEM_CARD_OPT: 846 case CTL_TRANSACTION_CTL: 847 case CTL_DMA_ENABLE: 848 case CTL_HOST_MODE: 849 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 850 bit = TMIO_STAT_CMD_BUSY; 851 fallthrough; 852 case CTL_SD_CARD_CLK_CTL: 853 return renesas_sdhi_wait_idle(host, bit); 854 } 855 856 return 0; 857 } 858 859 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 860 unsigned int direction, int blk_size) 861 { 862 /* 863 * In Renesas controllers, when performing a 864 * multiple block read of one or two blocks, 865 * depending on the timing with which the 866 * response register is read, the response 867 * value may not be read properly. 868 * Use single block read for this HW bug 869 */ 870 if ((direction == MMC_DATA_READ) && 871 blk_size == 2) 872 return 1; 873 874 return blk_size; 875 } 876 877 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 878 { 879 struct renesas_sdhi *priv = host_to_priv(host); 880 881 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 882 renesas_sdhi_adjust_hs400_mode_enable(host); 883 } 884 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 885 { 886 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 887 int width = (host->bus_shift == 2) ? 64 : 32; 888 889 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 890 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 891 } 892 893 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 894 .hs400_disabled = true, 895 .hs400_4taps = true, 896 }; 897 898 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 899 .hs400_4taps = true, 900 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 901 }; 902 903 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 904 .hs400_disabled = true, 905 }; 906 907 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 908 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 909 }; 910 911 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 912 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 913 }; 914 915 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 916 .hs400_4taps = true, 917 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 918 .hs400_calib_table = r8a7796_es13_calib_table, 919 }; 920 921 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 922 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 923 .hs400_calib_table = r8a77965_calib_table, 924 }; 925 926 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 927 .hs400_calib_table = r8a77990_calib_table, 928 }; 929 930 /* 931 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 932 * So, we want to treat them equally and only have a match for ES1.2 to enforce 933 * this if there ever will be a way to distinguish ES1.2. 934 */ 935 static const struct soc_device_attribute sdhi_quirks_match[] = { 936 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 937 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 }, 938 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 939 { .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 }, 940 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 941 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 942 { .soc_id = "r8a7796", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps1357 }, 943 { .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 }, 944 { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 }, 945 { .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 }, 946 { /* Sentinel. */ }, 947 }; 948 949 int renesas_sdhi_probe(struct platform_device *pdev, 950 const struct tmio_mmc_dma_ops *dma_ops) 951 { 952 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 953 const struct renesas_sdhi_quirks *quirks = NULL; 954 const struct renesas_sdhi_of_data *of_data; 955 const struct soc_device_attribute *attr; 956 struct tmio_mmc_data *mmc_data; 957 struct tmio_mmc_dma *dma_priv; 958 struct tmio_mmc_host *host; 959 struct renesas_sdhi *priv; 960 int num_irqs, irq, ret, i; 961 struct resource *res; 962 u16 ver; 963 964 of_data = of_device_get_match_data(&pdev->dev); 965 966 attr = soc_device_match(sdhi_quirks_match); 967 if (attr) 968 quirks = attr->data; 969 970 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 971 if (!res) 972 return -EINVAL; 973 974 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 975 GFP_KERNEL); 976 if (!priv) 977 return -ENOMEM; 978 979 priv->quirks = quirks; 980 mmc_data = &priv->mmc_data; 981 dma_priv = &priv->dma_priv; 982 983 priv->clk = devm_clk_get(&pdev->dev, NULL); 984 if (IS_ERR(priv->clk)) { 985 ret = PTR_ERR(priv->clk); 986 dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 987 return ret; 988 } 989 990 /* 991 * Some controllers provide a 2nd clock just to run the internal card 992 * detection logic. Unfortunately, the existing driver architecture does 993 * not support a separation of clocks for runtime PM usage. When 994 * native hotplug is used, the tmio driver assumes that the core 995 * must continue to run for card detect to stay active, so we cannot 996 * disable it. 997 * Additionally, it is prohibited to supply a clock to the core but not 998 * to the card detect circuit. That leaves us with if separate clocks 999 * are presented, we must treat them both as virtually 1 clock. 1000 */ 1001 priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 1002 if (IS_ERR(priv->clk_cd)) 1003 priv->clk_cd = NULL; 1004 1005 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 1006 if (!IS_ERR(priv->pinctrl)) { 1007 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 1008 PINCTRL_STATE_DEFAULT); 1009 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 1010 "state_uhs"); 1011 } 1012 1013 host = tmio_mmc_host_alloc(pdev, mmc_data); 1014 if (IS_ERR(host)) 1015 return PTR_ERR(host); 1016 1017 if (of_data) { 1018 mmc_data->flags |= of_data->tmio_flags; 1019 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 1020 mmc_data->capabilities |= of_data->capabilities; 1021 mmc_data->capabilities2 |= of_data->capabilities2; 1022 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 1023 mmc_data->max_blk_count = of_data->max_blk_count; 1024 mmc_data->max_segs = of_data->max_segs; 1025 dma_priv->dma_buswidth = of_data->dma_buswidth; 1026 host->bus_shift = of_data->bus_shift; 1027 } 1028 1029 host->write16_hook = renesas_sdhi_write16_hook; 1030 host->clk_enable = renesas_sdhi_clk_enable; 1031 host->clk_disable = renesas_sdhi_clk_disable; 1032 host->set_clock = renesas_sdhi_set_clock; 1033 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 1034 host->dma_ops = dma_ops; 1035 1036 if (quirks && quirks->hs400_disabled) 1037 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 1038 1039 /* For some SoC, we disable internal WP. GPIO may override this */ 1040 if (mmc_can_gpio_ro(host->mmc)) 1041 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 1042 1043 /* SDR speeds are only available on Gen2+ */ 1044 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 1045 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 1046 host->ops.card_busy = renesas_sdhi_card_busy; 1047 host->ops.start_signal_voltage_switch = 1048 renesas_sdhi_start_signal_voltage_switch; 1049 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 1050 host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; 1051 host->reset = renesas_sdhi_reset; 1052 } 1053 1054 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 1055 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 1056 host->bus_shift = 1; 1057 1058 if (mmd) 1059 *mmc_data = *mmd; 1060 1061 dma_priv->filter = shdma_chan_filter; 1062 dma_priv->enable = renesas_sdhi_enable_dma; 1063 1064 mmc_data->alignment_shift = 1; /* 2-byte alignment */ 1065 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1066 1067 /* 1068 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1069 * bus width mode. 1070 */ 1071 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1072 1073 /* 1074 * All SDHI blocks support SDIO IRQ signalling. 1075 */ 1076 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1077 1078 /* All SDHI have CMD12 control bit */ 1079 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1080 1081 /* All SDHI have SDIO status bits which must be 1 */ 1082 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1083 1084 /* All SDHI support HW busy detection */ 1085 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 1086 1087 dev_pm_domain_start(&pdev->dev); 1088 1089 ret = renesas_sdhi_clk_enable(host); 1090 if (ret) 1091 goto efree; 1092 1093 priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1094 if (IS_ERR(priv->rstc)) 1095 return PTR_ERR(priv->rstc); 1096 1097 ver = sd_ctrl_read16(host, CTL_VERSION); 1098 /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1099 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1100 mmc_data->max_blk_count = U16_MAX; 1101 1102 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1103 if (ver == SDHI_VER_GEN2_SDR50) 1104 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 1105 1106 if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1107 host->fixup_request = renesas_sdhi_fixup_request; 1108 priv->adjust_hs400_calib_table = *( 1109 res->start == SDHI_GEN3_MMC0_ADDR ? 1110 quirks->hs400_calib_table : 1111 quirks->hs400_calib_table + 1); 1112 } 1113 1114 /* these have an EXTOP bit */ 1115 if (ver >= SDHI_VER_GEN3_SD) 1116 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1117 1118 /* Enable tuning iff we have an SCC and a supported mode */ 1119 if (of_data && of_data->scc_offset && 1120 (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1121 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 1122 MMC_CAP2_HS400_1_8V))) { 1123 const struct renesas_sdhi_scc *taps = of_data->taps; 1124 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 1125 bool hit = false; 1126 1127 for (i = 0; i < of_data->taps_num; i++) { 1128 if (taps[i].clk_rate == 0 || 1129 taps[i].clk_rate == host->mmc->f_max) { 1130 priv->scc_tappos = taps->tap; 1131 priv->scc_tappos_hs400 = use_4tap ? 1132 taps->tap_hs400_4tap : 1133 taps->tap; 1134 hit = true; 1135 break; 1136 } 1137 } 1138 1139 if (!hit) 1140 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1141 1142 priv->scc_ctl = host->ctl + of_data->scc_offset; 1143 host->check_retune = renesas_sdhi_check_scc_error; 1144 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1145 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1146 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1147 host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1148 } 1149 1150 ret = tmio_mmc_host_probe(host); 1151 if (ret < 0) 1152 goto edisclk; 1153 1154 num_irqs = platform_irq_count(pdev); 1155 if (num_irqs < 0) { 1156 ret = num_irqs; 1157 goto eirq; 1158 } 1159 1160 /* There must be at least one IRQ source */ 1161 if (!num_irqs) { 1162 ret = -ENXIO; 1163 goto eirq; 1164 } 1165 1166 for (i = 0; i < num_irqs; i++) { 1167 irq = platform_get_irq(pdev, i); 1168 if (irq < 0) { 1169 ret = irq; 1170 goto eirq; 1171 } 1172 1173 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1174 dev_name(&pdev->dev), host); 1175 if (ret) 1176 goto eirq; 1177 } 1178 1179 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1180 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1181 1182 return ret; 1183 1184 eirq: 1185 tmio_mmc_host_remove(host); 1186 edisclk: 1187 renesas_sdhi_clk_disable(host); 1188 efree: 1189 tmio_mmc_host_free(host); 1190 1191 return ret; 1192 } 1193 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1194 1195 int renesas_sdhi_remove(struct platform_device *pdev) 1196 { 1197 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1198 1199 tmio_mmc_host_remove(host); 1200 renesas_sdhi_clk_disable(host); 1201 tmio_mmc_host_free(host); 1202 1203 return 0; 1204 } 1205 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1206 1207 MODULE_LICENSE("GPL v2"); 1208