1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas SDHI
4  *
5  * Copyright (C) 2015-19 Renesas Electronics Corporation
6  * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8  * Copyright (C) 2009 Magnus Damm
9  *
10  * Based on "Compaq ASIC3 support":
11  *
12  * Copyright 2001 Compaq Computer Corporation.
13  * Copyright 2004-2005 Phil Blundell
14  * Copyright 2007-2008 OpenedHand Ltd.
15  *
16  * Authors: Phil Blundell <pb@handhelds.org>,
17  *	    Samuel Ortiz <sameo@openedhand.com>
18  *
19  */
20 
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/iopoll.h>
24 #include <linux/kernel.h>
25 #include <linux/mfd/tmio.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/mmc.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/module.h>
30 #include <linux/of_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pinctrl/pinctrl-state.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_domain.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/reset.h>
37 #include <linux/sh_dma.h>
38 #include <linux/slab.h>
39 #include <linux/sys_soc.h>
40 
41 #include "renesas_sdhi.h"
42 #include "tmio_mmc.h"
43 
44 #define CTL_HOST_MODE	0xe4
45 #define HOST_MODE_GEN2_SDR50_WMODE	BIT(0)
46 #define HOST_MODE_GEN2_SDR104_WMODE	BIT(0)
47 #define HOST_MODE_GEN3_WMODE		BIT(0)
48 #define HOST_MODE_GEN3_BUSWIDTH		BIT(8)
49 
50 #define HOST_MODE_GEN3_16BIT	HOST_MODE_GEN3_WMODE
51 #define HOST_MODE_GEN3_32BIT	(HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH)
52 #define HOST_MODE_GEN3_64BIT	0
53 
54 #define CTL_SDIF_MODE	0xe6
55 #define SDIF_MODE_HS400		BIT(0)
56 
57 #define SDHI_VER_GEN2_SDR50	0x490c
58 #define SDHI_VER_RZ_A1		0x820b
59 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
60 #define SDHI_VER_GEN2_SDR104	0xcb0d
61 #define SDHI_VER_GEN3_SD	0xcc10
62 #define SDHI_VER_GEN3_SDMMC	0xcd10
63 
64 #define SDHI_GEN3_MMC0_ADDR	0xee140000
65 
66 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
67 {
68 	u32 val;
69 
70 	/*
71 	 * see also
72 	 *	renesas_sdhi_of_data :: dma_buswidth
73 	 */
74 	switch (sd_ctrl_read16(host, CTL_VERSION)) {
75 	case SDHI_VER_GEN2_SDR50:
76 		val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0;
77 		break;
78 	case SDHI_VER_GEN2_SDR104:
79 		val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE;
80 		break;
81 	case SDHI_VER_GEN3_SD:
82 	case SDHI_VER_GEN3_SDMMC:
83 		if (width == 64)
84 			val = HOST_MODE_GEN3_64BIT;
85 		else if (width == 32)
86 			val = HOST_MODE_GEN3_32BIT;
87 		else
88 			val = HOST_MODE_GEN3_16BIT;
89 		break;
90 	default:
91 		/* nothing to do */
92 		return;
93 	}
94 
95 	sd_ctrl_write16(host, CTL_HOST_MODE, val);
96 }
97 
98 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
99 {
100 	struct mmc_host *mmc = host->mmc;
101 	struct renesas_sdhi *priv = host_to_priv(host);
102 	int ret;
103 
104 	ret = clk_prepare_enable(priv->clk_cd);
105 	if (ret < 0)
106 		return ret;
107 
108 	/*
109 	 * The clock driver may not know what maximum frequency
110 	 * actually works, so it should be set with the max-frequency
111 	 * property which will already have been read to f_max.  If it
112 	 * was missing, assume the current frequency is the maximum.
113 	 */
114 	if (!mmc->f_max)
115 		mmc->f_max = clk_get_rate(priv->clk);
116 
117 	/*
118 	 * Minimum frequency is the minimum input clock frequency
119 	 * divided by our maximum divider.
120 	 */
121 	mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
122 
123 	/* enable 16bit data access on SDBUF as default */
124 	renesas_sdhi_sdbuf_width(host, 16);
125 
126 	return 0;
127 }
128 
129 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
130 					    unsigned int new_clock)
131 {
132 	struct renesas_sdhi *priv = host_to_priv(host);
133 	unsigned int freq, diff, best_freq = 0, diff_min = ~0;
134 	int i;
135 
136 	/*
137 	 * We simply return the current rate if a) we are not on a R-Car Gen2+
138 	 * SoC (may work for others, but untested) or b) if the SCC needs its
139 	 * clock during tuning, so we don't change the external clock setup.
140 	 */
141 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
142 		return clk_get_rate(priv->clk);
143 
144 	/*
145 	 * We want the bus clock to be as close as possible to, but no
146 	 * greater than, new_clock.  As we can divide by 1 << i for
147 	 * any i in [0, 9] we want the input clock to be as close as
148 	 * possible, but no greater than, new_clock << i.
149 	 */
150 	for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
151 		freq = clk_round_rate(priv->clk, new_clock << i);
152 		if (freq > (new_clock << i)) {
153 			/* Too fast; look for a slightly slower option */
154 			freq = clk_round_rate(priv->clk,
155 					      (new_clock << i) / 4 * 3);
156 			if (freq > (new_clock << i))
157 				continue;
158 		}
159 
160 		diff = new_clock - (freq >> i);
161 		if (diff <= diff_min) {
162 			best_freq = freq;
163 			diff_min = diff;
164 		}
165 	}
166 
167 	clk_set_rate(priv->clk, best_freq);
168 
169 	return clk_get_rate(priv->clk);
170 }
171 
172 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
173 				   unsigned int new_clock)
174 {
175 	u32 clk = 0, clock;
176 
177 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
178 		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
179 
180 	if (new_clock == 0) {
181 		host->mmc->actual_clock = 0;
182 		goto out;
183 	}
184 
185 	host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
186 	clock = host->mmc->actual_clock / 512;
187 
188 	for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
189 		clock <<= 1;
190 
191 	/* 1/1 clock is option */
192 	if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
193 		if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
194 			clk |= 0xff;
195 		else
196 			clk &= ~0xff;
197 	}
198 
199 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
200 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
201 		usleep_range(10000, 11000);
202 
203 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
204 		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
205 
206 out:
207 	/* HW engineers overrode docs: no sleep needed on R-Car2+ */
208 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
209 		usleep_range(10000, 11000);
210 }
211 
212 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
213 {
214 	struct renesas_sdhi *priv = host_to_priv(host);
215 
216 	clk_disable_unprepare(priv->clk_cd);
217 }
218 
219 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
220 {
221 	struct tmio_mmc_host *host = mmc_priv(mmc);
222 
223 	return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
224 		 TMIO_STAT_DAT0);
225 }
226 
227 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
228 						    struct mmc_ios *ios)
229 {
230 	struct tmio_mmc_host *host = mmc_priv(mmc);
231 	struct renesas_sdhi *priv = host_to_priv(host);
232 	struct pinctrl_state *pin_state;
233 	int ret;
234 
235 	switch (ios->signal_voltage) {
236 	case MMC_SIGNAL_VOLTAGE_330:
237 		pin_state = priv->pins_default;
238 		break;
239 	case MMC_SIGNAL_VOLTAGE_180:
240 		pin_state = priv->pins_uhs;
241 		break;
242 	default:
243 		return -EINVAL;
244 	}
245 
246 	/*
247 	 * If anything is missing, assume signal voltage is fixed at
248 	 * 3.3V and succeed/fail accordingly.
249 	 */
250 	if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
251 		return ios->signal_voltage ==
252 			MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
253 
254 	ret = mmc_regulator_set_vqmmc(host->mmc, ios);
255 	if (ret < 0)
256 		return ret;
257 
258 	return pinctrl_select_state(priv->pinctrl, pin_state);
259 }
260 
261 /* SCC registers */
262 #define SH_MOBILE_SDHI_SCC_DTCNTL	0x000
263 #define SH_MOBILE_SDHI_SCC_TAPSET	0x002
264 #define SH_MOBILE_SDHI_SCC_DT2FF	0x004
265 #define SH_MOBILE_SDHI_SCC_CKSEL	0x006
266 #define SH_MOBILE_SDHI_SCC_RVSCNTL	0x008
267 #define SH_MOBILE_SDHI_SCC_RVSREQ	0x00A
268 #define SH_MOBILE_SDHI_SCC_SMPCMP       0x00C
269 #define SH_MOBILE_SDHI_SCC_TMPPORT2	0x00E
270 #define SH_MOBILE_SDHI_SCC_TMPPORT3	0x014
271 #define SH_MOBILE_SDHI_SCC_TMPPORT4	0x016
272 #define SH_MOBILE_SDHI_SCC_TMPPORT5	0x018
273 #define SH_MOBILE_SDHI_SCC_TMPPORT6	0x01A
274 #define SH_MOBILE_SDHI_SCC_TMPPORT7	0x01C
275 
276 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN		BIT(0)
277 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT	16
278 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK	0xff
279 
280 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL		BIT(0)
281 
282 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN	BIT(0)
283 
284 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN	BIT(0)
285 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP	BIT(1)
286 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR	BIT(2)
287 
288 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN	BIT(8)
289 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP	BIT(24)
290 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR	(BIT(8) | BIT(24))
291 
292 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL	BIT(4)
293 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN	BIT(31)
294 
295 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
296 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START	BIT(0)
297 
298 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
299 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R	BIT(8)
300 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W	(0 << 8)
301 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK	0x3F
302 
303 /* Definitions for values the SH_MOBILE_SDHI_SCC register */
304 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE	0xa5000000
305 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK	0x1f
306 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE		BIT(7)
307 
308 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
309 				struct renesas_sdhi *priv, int addr)
310 {
311 	return readl(priv->scc_ctl + (addr << host->bus_shift));
312 }
313 
314 static inline void sd_scc_write32(struct tmio_mmc_host *host,
315 				  struct renesas_sdhi *priv,
316 				  int addr, u32 val)
317 {
318 	writel(val, priv->scc_ctl + (addr << host->bus_shift));
319 }
320 
321 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
322 {
323 	struct renesas_sdhi *priv;
324 
325 	priv = host_to_priv(host);
326 
327 	/* Initialize SCC */
328 	sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
329 
330 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
331 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
332 
333 	/* set sampling clock selection range */
334 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
335 		       SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
336 		       0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
337 
338 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
339 		       SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
340 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
341 
342 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
343 		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
344 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
345 
346 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
347 
348 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
349 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
350 
351 	/* Read TAPNUM */
352 	return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
353 		SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
354 		SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
355 }
356 
357 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
358 {
359 	struct tmio_mmc_host *host = mmc_priv(mmc);
360 	struct renesas_sdhi *priv = host_to_priv(host);
361 	u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
362 	bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
363 
364 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
365 		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
366 
367 	/* Set HS400 mode */
368 	sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 |
369 			sd_ctrl_read16(host, CTL_SDIF_MODE));
370 
371 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
372 		       priv->scc_tappos_hs400);
373 
374 	/* Gen3 can't do automatic tap correction with HS400, so disable it */
375 	if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
376 		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
377 			       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
378 			       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
379 
380 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
381 		       (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
382 			SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
383 			sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
384 
385 	/* Set the sampling clock selection range of HS400 mode */
386 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
387 		       SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
388 		       0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
389 
390 	/* Avoid bad TAP */
391 	if (bad_taps & BIT(priv->tap_set)) {
392 		u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
393 
394 		if (bad_taps & BIT(new_tap))
395 			new_tap = (priv->tap_set - 1) % priv->tap_num;
396 
397 		if (bad_taps & BIT(new_tap)) {
398 			new_tap = priv->tap_set;
399 			dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
400 		}
401 
402 		priv->tap_set = new_tap;
403 	}
404 
405 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
406 		       priv->tap_set / (use_4tap ? 2 : 1));
407 
408 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
409 		       SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
410 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
411 
412 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
413 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
414 
415 	if (priv->adjust_hs400_calib_table)
416 		priv->needs_adjust_hs400 = true;
417 }
418 
419 static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
420 {
421 	struct tmio_mmc_host *host = mmc_priv(mmc);
422 	struct renesas_sdhi *priv = host_to_priv(host);
423 
424 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
425 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
426 
427 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
428 		       ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
429 		       sd_scc_read32(host, priv,
430 				     SH_MOBILE_SDHI_SCC_CKSEL));
431 
432 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
433 		       ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
434 		       sd_scc_read32(host, priv,
435 				     SH_MOBILE_SDHI_SCC_DTCNTL));
436 
437 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
438 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
439 }
440 
441 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
442 				 struct renesas_sdhi *priv, u32 addr)
443 {
444 	/* read mode */
445 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
446 		       SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
447 		       (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
448 
449 	/* access start and stop */
450 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
451 		       SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
452 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
453 
454 	return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
455 }
456 
457 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
458 				   struct renesas_sdhi *priv, u32 addr, u32 val)
459 {
460 	/* write mode */
461 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
462 		       SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
463 		       (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
464 
465 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
466 
467 	/* access start and stop */
468 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
469 		       SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
470 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
471 }
472 
473 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
474 {
475 	struct renesas_sdhi *priv = host_to_priv(host);
476 	u32 calib_code;
477 
478 	/* disable write protect */
479 	sd_scc_tmpport_write32(host, priv, 0x00,
480 			       SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
481 	/* read calibration code and adjust */
482 	calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
483 	calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
484 
485 	sd_scc_tmpport_write32(host, priv, 0x22,
486 			       SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
487 			       priv->adjust_hs400_calib_table[calib_code]);
488 
489 	/* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
490 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
491 
492 	/* adjustment done, clear flag */
493 	priv->needs_adjust_hs400 = false;
494 }
495 
496 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
497 {
498 	struct renesas_sdhi *priv = host_to_priv(host);
499 
500 	/* disable write protect */
501 	sd_scc_tmpport_write32(host, priv, 0x00,
502 			       SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
503 	/* disable manual calibration */
504 	sd_scc_tmpport_write32(host, priv, 0x22, 0);
505 	/* clear offset value of TMPPORT3 */
506 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
507 }
508 
509 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
510 					  struct renesas_sdhi *priv)
511 {
512 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
513 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
514 
515 	/* Reset HS400 mode */
516 	sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 &
517 			sd_ctrl_read16(host, CTL_SDIF_MODE));
518 
519 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
520 
521 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
522 		       ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
523 			 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
524 			sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
525 
526 	if (priv->adjust_hs400_calib_table)
527 		renesas_sdhi_adjust_hs400_mode_disable(host);
528 
529 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
530 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
531 }
532 
533 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
534 {
535 	struct tmio_mmc_host *host = mmc_priv(mmc);
536 
537 	renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
538 	return 0;
539 }
540 
541 static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv)
542 {
543 	renesas_sdhi_disable_scc(host->mmc);
544 	renesas_sdhi_reset_hs400_mode(host, priv);
545 	priv->needs_adjust_hs400 = false;
546 
547 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
548 		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
549 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
550 }
551 
552 /* only populated for TMIO_MMC_MIN_RCAR2 */
553 static void renesas_sdhi_reset(struct tmio_mmc_host *host)
554 {
555 	struct renesas_sdhi *priv = host_to_priv(host);
556 	int ret;
557 	u16 val;
558 
559 	if (priv->rstc) {
560 		reset_control_reset(priv->rstc);
561 		/* Unknown why but without polling reset status, it will hang */
562 		read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100,
563 				  false, priv->rstc);
564 		/* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */
565 		sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
566 		priv->needs_adjust_hs400 = false;
567 		renesas_sdhi_set_clock(host, host->clk_cache);
568 	} else if (priv->scc_ctl) {
569 		renesas_sdhi_scc_reset(host, priv);
570 	}
571 
572 	if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) {
573 		val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
574 		val |= CARD_OPT_EXTOP;
575 		sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val);
576 	}
577 }
578 
579 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host)
580 {
581 	u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
582 
583 	num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT;
584 	return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num);
585 
586 }
587 
588 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3
589 
590 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
591 {
592 	struct renesas_sdhi *priv = host_to_priv(host);
593 	unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
594 	unsigned int taps_size = priv->tap_num * 2, min_tap_row;
595 	unsigned long *bitmap;
596 
597 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
598 
599 	/*
600 	 * When tuning CMD19 is issued twice for each tap, merge the
601 	 * result requiring the tap to be good in both runs before
602 	 * considering it for tuning selection.
603 	 */
604 	for (i = 0; i < taps_size; i++) {
605 		int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
606 
607 		if (!test_bit(i, priv->taps))
608 			clear_bit(i + offset, priv->taps);
609 
610 		if (!test_bit(i, priv->smpcmp))
611 			clear_bit(i + offset, priv->smpcmp);
612 	}
613 
614 	/*
615 	 * If all TAP are OK, the sampling clock position is selected by
616 	 * identifying the change point of data.
617 	 */
618 	if (bitmap_full(priv->taps, taps_size)) {
619 		bitmap = priv->smpcmp;
620 		min_tap_row = 1;
621 	} else {
622 		bitmap = priv->taps;
623 		min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
624 	}
625 
626 	/*
627 	 * Find the longest consecutive run of successful probes. If that
628 	 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
629 	 * center index as the tap, otherwise bail out.
630 	 */
631 	bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) {
632 		if (re - rs > tap_cnt) {
633 			tap_end = re;
634 			tap_start = rs;
635 			tap_cnt = tap_end - tap_start;
636 		}
637 	}
638 
639 	if (tap_cnt >= min_tap_row)
640 		priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
641 	else
642 		return -EIO;
643 
644 	/* Set SCC */
645 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
646 
647 	/* Enable auto re-tuning */
648 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
649 		       SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
650 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
651 
652 	return 0;
653 }
654 
655 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
656 {
657 	struct tmio_mmc_host *host = mmc_priv(mmc);
658 	struct renesas_sdhi *priv = host_to_priv(host);
659 	int i, ret;
660 
661 	priv->tap_num = renesas_sdhi_init_tuning(host);
662 	if (!priv->tap_num)
663 		return 0; /* Tuning is not supported */
664 
665 	if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
666 		dev_err(&host->pdev->dev,
667 			"Too many taps, please update 'taps' in tmio_mmc_host!\n");
668 		return -EINVAL;
669 	}
670 
671 	bitmap_zero(priv->taps, priv->tap_num * 2);
672 	bitmap_zero(priv->smpcmp, priv->tap_num * 2);
673 
674 	/* Issue CMD19 twice for each tap */
675 	for (i = 0; i < 2 * priv->tap_num; i++) {
676 		int cmd_error = 0;
677 
678 		/* Set sampling clock position */
679 		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
680 
681 		if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
682 			set_bit(i, priv->taps);
683 
684 		if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
685 			set_bit(i, priv->smpcmp);
686 
687 		if (cmd_error)
688 			mmc_send_abort_tuning(mmc, opcode);
689 	}
690 
691 	ret = renesas_sdhi_select_tuning(host);
692 	if (ret < 0)
693 		renesas_sdhi_scc_reset(host, priv);
694 	return ret;
695 }
696 
697 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
698 {
699 	struct renesas_sdhi *priv = host_to_priv(host);
700 	unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
701 	u32 val;
702 
703 	val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
704 	if (!val)
705 		return false;
706 
707 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
708 
709 	/* Change TAP position according to correction status */
710 	if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
711 	    host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
712 		u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
713 		/*
714 		 * With HS400, the DAT signal is based on DS, not CLK.
715 		 * Therefore, use only CMD status.
716 		 */
717 		u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
718 					   SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
719 		if (!smpcmp) {
720 			return false;	/* no error in CMD signal */
721 		} else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
722 			new_tap++;
723 			error_tap--;
724 		} else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
725 			new_tap--;
726 			error_tap++;
727 		} else {
728 			return true;	/* need retune */
729 		}
730 
731 		/*
732 		 * When new_tap is a bad tap, we cannot change. Then, we compare
733 		 * with the HS200 tuning result. When smpcmp[error_tap] is OK,
734 		 * we can at least retune.
735 		 */
736 		if (bad_taps & BIT(new_tap % priv->tap_num))
737 			return test_bit(error_tap % priv->tap_num, priv->smpcmp);
738 	} else {
739 		if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
740 			return true;    /* need retune */
741 		else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
742 			new_tap++;
743 		else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
744 			new_tap--;
745 		else
746 			return false;
747 	}
748 
749 	priv->tap_set = (new_tap % priv->tap_num);
750 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
751 		       priv->tap_set / (use_4tap ? 2 : 1));
752 
753 	return false;
754 }
755 
756 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
757 {
758 	struct renesas_sdhi *priv = host_to_priv(host);
759 
760 	/* Check SCC error */
761 	if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
762 	    SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
763 		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
764 		return true;
765 	}
766 
767 	return false;
768 }
769 
770 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host,
771 					 struct mmc_request *mrq)
772 {
773 	struct renesas_sdhi *priv = host_to_priv(host);
774 	bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
775 	bool ret = false;
776 
777 	/*
778 	 * Skip checking SCC errors when running on 4 taps in HS400 mode as
779 	 * any retuning would still result in the same 4 taps being used.
780 	 */
781 	if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
782 	    !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
783 	    !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
784 		return false;
785 
786 	if (mmc_doing_tune(host->mmc))
787 		return false;
788 
789 	if (((mrq->cmd->error == -ETIMEDOUT) ||
790 	     (mrq->data && mrq->data->error == -ETIMEDOUT)) &&
791 	    ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
792 	     (host->ops.get_cd && host->ops.get_cd(host->mmc))))
793 		ret |= true;
794 
795 	if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
796 	    SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
797 		ret |= renesas_sdhi_auto_correction(host);
798 	else
799 		ret |= renesas_sdhi_manual_correction(host, use_4tap);
800 
801 	return ret;
802 }
803 
804 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
805 {
806 	int timeout = 1000;
807 	/* CBSY is set when busy, SCLKDIVEN is cleared when busy */
808 	u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
809 
810 	while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
811 			      & bit) == wait_state)
812 		udelay(1);
813 
814 	if (!timeout) {
815 		dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
816 		return -EBUSY;
817 	}
818 
819 	return 0;
820 }
821 
822 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
823 {
824 	u32 bit = TMIO_STAT_SCLKDIVEN;
825 
826 	switch (addr) {
827 	case CTL_SD_CMD:
828 	case CTL_STOP_INTERNAL_ACTION:
829 	case CTL_XFER_BLK_COUNT:
830 	case CTL_SD_XFER_LEN:
831 	case CTL_SD_MEM_CARD_OPT:
832 	case CTL_TRANSACTION_CTL:
833 	case CTL_DMA_ENABLE:
834 	case CTL_HOST_MODE:
835 		if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
836 			bit = TMIO_STAT_CMD_BUSY;
837 		fallthrough;
838 	case CTL_SD_CARD_CLK_CTL:
839 		return renesas_sdhi_wait_idle(host, bit);
840 	}
841 
842 	return 0;
843 }
844 
845 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
846 				       unsigned int direction, int blk_size)
847 {
848 	/*
849 	 * In Renesas controllers, when performing a
850 	 * multiple block read of one or two blocks,
851 	 * depending on the timing with which the
852 	 * response register is read, the response
853 	 * value may not be read properly.
854 	 * Use single block read for this HW bug
855 	 */
856 	if ((direction == MMC_DATA_READ) &&
857 	    blk_size == 2)
858 		return 1;
859 
860 	return blk_size;
861 }
862 
863 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
864 {
865 	struct renesas_sdhi *priv = host_to_priv(host);
866 
867 	if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
868 		renesas_sdhi_adjust_hs400_mode_enable(host);
869 }
870 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
871 {
872 	/* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
873 	int width = (host->bus_shift == 2) ? 64 : 32;
874 
875 	sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
876 	renesas_sdhi_sdbuf_width(host, enable ? width : 16);
877 }
878 
879 int renesas_sdhi_probe(struct platform_device *pdev,
880 		       const struct tmio_mmc_dma_ops *dma_ops,
881 		       const struct renesas_sdhi_of_data *of_data,
882 		       const struct renesas_sdhi_quirks *quirks)
883 {
884 	struct tmio_mmc_data *mmd = pdev->dev.platform_data;
885 	struct tmio_mmc_data *mmc_data;
886 	struct tmio_mmc_dma *dma_priv;
887 	struct tmio_mmc_host *host;
888 	struct renesas_sdhi *priv;
889 	int num_irqs, irq, ret, i;
890 	struct resource *res;
891 	u16 ver;
892 
893 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
894 	if (!res)
895 		return -EINVAL;
896 
897 	priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
898 			    GFP_KERNEL);
899 	if (!priv)
900 		return -ENOMEM;
901 
902 	priv->quirks = quirks;
903 	mmc_data = &priv->mmc_data;
904 	dma_priv = &priv->dma_priv;
905 
906 	priv->clk = devm_clk_get(&pdev->dev, NULL);
907 	if (IS_ERR(priv->clk)) {
908 		ret = PTR_ERR(priv->clk);
909 		dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
910 		return ret;
911 	}
912 
913 	/*
914 	 * Some controllers provide a 2nd clock just to run the internal card
915 	 * detection logic. Unfortunately, the existing driver architecture does
916 	 * not support a separation of clocks for runtime PM usage. When
917 	 * native hotplug is used, the tmio driver assumes that the core
918 	 * must continue to run for card detect to stay active, so we cannot
919 	 * disable it.
920 	 * Additionally, it is prohibited to supply a clock to the core but not
921 	 * to the card detect circuit. That leaves us with if separate clocks
922 	 * are presented, we must treat them both as virtually 1 clock.
923 	 */
924 	priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
925 	if (IS_ERR(priv->clk_cd))
926 		priv->clk_cd = NULL;
927 
928 	priv->pinctrl = devm_pinctrl_get(&pdev->dev);
929 	if (!IS_ERR(priv->pinctrl)) {
930 		priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
931 						PINCTRL_STATE_DEFAULT);
932 		priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
933 						"state_uhs");
934 	}
935 
936 	host = tmio_mmc_host_alloc(pdev, mmc_data);
937 	if (IS_ERR(host))
938 		return PTR_ERR(host);
939 
940 	if (of_data) {
941 		mmc_data->flags |= of_data->tmio_flags;
942 		mmc_data->ocr_mask = of_data->tmio_ocr_mask;
943 		mmc_data->capabilities |= of_data->capabilities;
944 		mmc_data->capabilities2 |= of_data->capabilities2;
945 		mmc_data->dma_rx_offset = of_data->dma_rx_offset;
946 		mmc_data->max_blk_count = of_data->max_blk_count;
947 		mmc_data->max_segs = of_data->max_segs;
948 		dma_priv->dma_buswidth = of_data->dma_buswidth;
949 		host->bus_shift = of_data->bus_shift;
950 	}
951 
952 	host->write16_hook	= renesas_sdhi_write16_hook;
953 	host->clk_enable	= renesas_sdhi_clk_enable;
954 	host->clk_disable	= renesas_sdhi_clk_disable;
955 	host->set_clock		= renesas_sdhi_set_clock;
956 	host->multi_io_quirk	= renesas_sdhi_multi_io_quirk;
957 	host->dma_ops		= dma_ops;
958 
959 	if (quirks && quirks->hs400_disabled)
960 		host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
961 
962 	/* For some SoC, we disable internal WP. GPIO may override this */
963 	if (mmc_can_gpio_ro(host->mmc))
964 		mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
965 
966 	/* SDR speeds are only available on Gen2+ */
967 	if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
968 		/* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
969 		host->ops.card_busy = renesas_sdhi_card_busy;
970 		host->ops.start_signal_voltage_switch =
971 			renesas_sdhi_start_signal_voltage_switch;
972 		host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
973 		host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2;
974 		host->reset = renesas_sdhi_reset;
975 	}
976 
977 	/* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
978 	if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
979 		host->bus_shift = 1;
980 
981 	if (mmd)
982 		*mmc_data = *mmd;
983 
984 	dma_priv->filter = shdma_chan_filter;
985 	dma_priv->enable = renesas_sdhi_enable_dma;
986 
987 	mmc_data->alignment_shift = 1; /* 2-byte alignment */
988 	mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
989 
990 	/*
991 	 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
992 	 * bus width mode.
993 	 */
994 	mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
995 
996 	/*
997 	 * All SDHI blocks support SDIO IRQ signalling.
998 	 */
999 	mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1000 
1001 	/* All SDHI have CMD12 control bit */
1002 	mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1003 
1004 	/* All SDHI have SDIO status bits which must be 1 */
1005 	mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1006 
1007 	/* All SDHI support HW busy detection */
1008 	mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
1009 
1010 	dev_pm_domain_start(&pdev->dev);
1011 
1012 	ret = renesas_sdhi_clk_enable(host);
1013 	if (ret)
1014 		goto efree;
1015 
1016 	priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1017 	if (IS_ERR(priv->rstc))
1018 		return PTR_ERR(priv->rstc);
1019 
1020 	ver = sd_ctrl_read16(host, CTL_VERSION);
1021 	/* GEN2_SDR104 is first known SDHI to use 32bit block count */
1022 	if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1023 		mmc_data->max_blk_count = U16_MAX;
1024 
1025 	/* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1026 	if (ver == SDHI_VER_GEN2_SDR50)
1027 		mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
1028 
1029 	if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) {
1030 		host->fixup_request = renesas_sdhi_fixup_request;
1031 		priv->adjust_hs400_calib_table = *(
1032 			res->start == SDHI_GEN3_MMC0_ADDR ?
1033 			quirks->hs400_calib_table :
1034 			quirks->hs400_calib_table + 1);
1035 	}
1036 
1037 	/* these have an EXTOP bit */
1038 	if (ver >= SDHI_VER_GEN3_SD)
1039 		host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles;
1040 
1041 	/* Enable tuning iff we have an SCC and a supported mode */
1042 	if (of_data && of_data->scc_offset &&
1043 	    (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1044 	     host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
1045 				 MMC_CAP2_HS400_1_8V))) {
1046 		const struct renesas_sdhi_scc *taps = of_data->taps;
1047 		bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
1048 		bool hit = false;
1049 
1050 		for (i = 0; i < of_data->taps_num; i++) {
1051 			if (taps[i].clk_rate == 0 ||
1052 			    taps[i].clk_rate == host->mmc->f_max) {
1053 				priv->scc_tappos = taps->tap;
1054 				priv->scc_tappos_hs400 = use_4tap ?
1055 							 taps->tap_hs400_4tap :
1056 							 taps->tap;
1057 				hit = true;
1058 				break;
1059 			}
1060 		}
1061 
1062 		if (!hit)
1063 			dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1064 
1065 		priv->scc_ctl = host->ctl + of_data->scc_offset;
1066 		host->check_retune = renesas_sdhi_check_scc_error;
1067 		host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1068 		host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1069 		host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1070 		host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1071 	}
1072 
1073 	ret = tmio_mmc_host_probe(host);
1074 	if (ret < 0)
1075 		goto edisclk;
1076 
1077 	num_irqs = platform_irq_count(pdev);
1078 	if (num_irqs < 0) {
1079 		ret = num_irqs;
1080 		goto eirq;
1081 	}
1082 
1083 	/* There must be at least one IRQ source */
1084 	if (!num_irqs) {
1085 		ret = -ENXIO;
1086 		goto eirq;
1087 	}
1088 
1089 	for (i = 0; i < num_irqs; i++) {
1090 		irq = platform_get_irq(pdev, i);
1091 		if (irq < 0) {
1092 			ret = irq;
1093 			goto eirq;
1094 		}
1095 
1096 		ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1097 				       dev_name(&pdev->dev), host);
1098 		if (ret)
1099 			goto eirq;
1100 	}
1101 
1102 	dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1103 		 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1104 
1105 	return ret;
1106 
1107 eirq:
1108 	tmio_mmc_host_remove(host);
1109 edisclk:
1110 	renesas_sdhi_clk_disable(host);
1111 efree:
1112 	tmio_mmc_host_free(host);
1113 
1114 	return ret;
1115 }
1116 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1117 
1118 int renesas_sdhi_remove(struct platform_device *pdev)
1119 {
1120 	struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1121 
1122 	tmio_mmc_host_remove(host);
1123 	renesas_sdhi_clk_disable(host);
1124 	tmio_mmc_host_free(host);
1125 
1126 	return 0;
1127 }
1128 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1129 
1130 MODULE_LICENSE("GPL v2");
1131