1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/iopoll.h> 24 #include <linux/kernel.h> 25 #include <linux/mfd/tmio.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/mmc.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/module.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/pinctrl-state.h> 32 #include <linux/platform_device.h> 33 #include <linux/pm_domain.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/reset.h> 36 #include <linux/sh_dma.h> 37 #include <linux/slab.h> 38 39 #include "renesas_sdhi.h" 40 #include "tmio_mmc.h" 41 42 #define CTL_HOST_MODE 0xe4 43 #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 44 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 45 #define HOST_MODE_GEN3_WMODE BIT(0) 46 #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 47 48 #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 49 #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 50 #define HOST_MODE_GEN3_64BIT 0 51 52 #define SDHI_VER_GEN2_SDR50 0x490c 53 #define SDHI_VER_RZ_A1 0x820b 54 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 55 #define SDHI_VER_GEN2_SDR104 0xcb0d 56 #define SDHI_VER_GEN3_SD 0xcc10 57 #define SDHI_VER_GEN3_SDMMC 0xcd10 58 59 #define SDHI_GEN3_MMC0_ADDR 0xee140000 60 61 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 62 { 63 u32 val; 64 65 /* 66 * see also 67 * renesas_sdhi_of_data :: dma_buswidth 68 */ 69 switch (sd_ctrl_read16(host, CTL_VERSION)) { 70 case SDHI_VER_GEN2_SDR50: 71 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 72 break; 73 case SDHI_VER_GEN2_SDR104: 74 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 75 break; 76 case SDHI_VER_GEN3_SD: 77 case SDHI_VER_GEN3_SDMMC: 78 if (width == 64) 79 val = HOST_MODE_GEN3_64BIT; 80 else if (width == 32) 81 val = HOST_MODE_GEN3_32BIT; 82 else 83 val = HOST_MODE_GEN3_16BIT; 84 break; 85 default: 86 /* nothing to do */ 87 return; 88 } 89 90 sd_ctrl_write16(host, CTL_HOST_MODE, val); 91 } 92 93 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 94 { 95 struct mmc_host *mmc = host->mmc; 96 struct renesas_sdhi *priv = host_to_priv(host); 97 int ret; 98 99 ret = clk_prepare_enable(priv->clk_cd); 100 if (ret < 0) 101 return ret; 102 103 /* 104 * The clock driver may not know what maximum frequency 105 * actually works, so it should be set with the max-frequency 106 * property which will already have been read to f_max. If it 107 * was missing, assume the current frequency is the maximum. 108 */ 109 if (!mmc->f_max) 110 mmc->f_max = clk_get_rate(priv->clk); 111 112 /* 113 * Minimum frequency is the minimum input clock frequency 114 * divided by our maximum divider. 115 */ 116 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 117 118 /* enable 16bit data access on SDBUF as default */ 119 renesas_sdhi_sdbuf_width(host, 16); 120 121 return 0; 122 } 123 124 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 125 unsigned int wanted_clock) 126 { 127 struct renesas_sdhi *priv = host_to_priv(host); 128 struct clk *ref_clk = priv->clk; 129 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 130 unsigned int new_clock, clkh_shift = 0; 131 int i; 132 133 /* 134 * We simply return the current rate if a) we are not on a R-Car Gen2+ 135 * SoC (may work for others, but untested) or b) if the SCC needs its 136 * clock during tuning, so we don't change the external clock setup. 137 */ 138 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 139 return clk_get_rate(priv->clk); 140 141 if (priv->clkh) { 142 /* HS400 with 4TAP needs different clock settings */ 143 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 144 bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; 145 clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; 146 ref_clk = priv->clkh; 147 } 148 149 new_clock = wanted_clock << clkh_shift; 150 151 /* 152 * We want the bus clock to be as close as possible to, but no 153 * greater than, new_clock. As we can divide by 1 << i for 154 * any i in [0, 9] we want the input clock to be as close as 155 * possible, but no greater than, new_clock << i. 156 */ 157 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 158 freq = clk_round_rate(ref_clk, new_clock << i); 159 if (freq > (new_clock << i)) { 160 /* Too fast; look for a slightly slower option */ 161 freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3); 162 if (freq > (new_clock << i)) 163 continue; 164 } 165 166 diff = new_clock - (freq >> i); 167 if (diff <= diff_min) { 168 best_freq = freq; 169 diff_min = diff; 170 } 171 } 172 173 clk_set_rate(ref_clk, best_freq); 174 175 if (priv->clkh) 176 clk_set_rate(priv->clk, best_freq >> clkh_shift); 177 178 return clk_get_rate(priv->clk); 179 } 180 181 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 182 unsigned int new_clock) 183 { 184 u32 clk = 0, clock; 185 186 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 187 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 188 189 if (new_clock == 0) { 190 host->mmc->actual_clock = 0; 191 goto out; 192 } 193 194 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 195 clock = host->mmc->actual_clock / 512; 196 197 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 198 clock <<= 1; 199 200 /* 1/1 clock is option */ 201 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 202 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 203 clk |= 0xff; 204 else 205 clk &= ~0xff; 206 } 207 208 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 209 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 210 usleep_range(10000, 11000); 211 212 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 213 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 214 215 out: 216 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 217 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 218 usleep_range(10000, 11000); 219 } 220 221 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 222 { 223 struct renesas_sdhi *priv = host_to_priv(host); 224 225 clk_disable_unprepare(priv->clk_cd); 226 } 227 228 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 229 { 230 struct tmio_mmc_host *host = mmc_priv(mmc); 231 232 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 233 TMIO_STAT_DAT0); 234 } 235 236 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 237 struct mmc_ios *ios) 238 { 239 struct tmio_mmc_host *host = mmc_priv(mmc); 240 struct renesas_sdhi *priv = host_to_priv(host); 241 struct pinctrl_state *pin_state; 242 int ret; 243 244 switch (ios->signal_voltage) { 245 case MMC_SIGNAL_VOLTAGE_330: 246 pin_state = priv->pins_default; 247 break; 248 case MMC_SIGNAL_VOLTAGE_180: 249 pin_state = priv->pins_uhs; 250 break; 251 default: 252 return -EINVAL; 253 } 254 255 /* 256 * If anything is missing, assume signal voltage is fixed at 257 * 3.3V and succeed/fail accordingly. 258 */ 259 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 260 return ios->signal_voltage == 261 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 262 263 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 264 if (ret < 0) 265 return ret; 266 267 return pinctrl_select_state(priv->pinctrl, pin_state); 268 } 269 270 /* SCC registers */ 271 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 272 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 273 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 274 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 275 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 276 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 277 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 278 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 279 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 280 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 281 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 282 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 283 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 284 285 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 286 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 287 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 288 289 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 290 291 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 292 293 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 294 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 295 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 296 297 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 298 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 299 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 300 301 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 302 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 303 304 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 305 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 306 307 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 308 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 309 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 310 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 311 312 /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 313 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 314 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 315 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 316 317 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 318 struct renesas_sdhi *priv, int addr) 319 { 320 return readl(priv->scc_ctl + (addr << host->bus_shift)); 321 } 322 323 static inline void sd_scc_write32(struct tmio_mmc_host *host, 324 struct renesas_sdhi *priv, 325 int addr, u32 val) 326 { 327 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 328 } 329 330 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 331 { 332 struct renesas_sdhi *priv; 333 334 priv = host_to_priv(host); 335 336 /* Initialize SCC */ 337 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 338 339 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 340 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 341 342 /* set sampling clock selection range */ 343 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 344 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 345 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 346 347 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 348 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 349 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 350 351 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 352 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 353 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 354 355 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 356 357 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 358 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 359 360 /* Read TAPNUM */ 361 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 362 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 363 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 364 } 365 366 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 367 { 368 struct tmio_mmc_host *host = mmc_priv(mmc); 369 struct renesas_sdhi *priv = host_to_priv(host); 370 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 371 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 372 373 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 374 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 375 376 /* Set HS400 mode */ 377 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 378 sd_ctrl_read16(host, CTL_SDIF_MODE)); 379 380 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 381 priv->scc_tappos_hs400); 382 383 if (priv->quirks && priv->quirks->manual_tap_correction) 384 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 385 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 386 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 387 388 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 389 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 390 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 391 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 392 393 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 394 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 395 sd_scc_read32(host, priv, 396 SH_MOBILE_SDHI_SCC_DTCNTL)); 397 398 /* Avoid bad TAP */ 399 if (bad_taps & BIT(priv->tap_set)) { 400 u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 401 402 if (bad_taps & BIT(new_tap)) 403 new_tap = (priv->tap_set - 1) % priv->tap_num; 404 405 if (bad_taps & BIT(new_tap)) { 406 new_tap = priv->tap_set; 407 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 408 } 409 410 priv->tap_set = new_tap; 411 } 412 413 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 414 priv->tap_set / (use_4tap ? 2 : 1)); 415 416 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 417 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 418 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 419 420 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 421 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 422 423 if (priv->adjust_hs400_calib_table) 424 priv->needs_adjust_hs400 = true; 425 } 426 427 static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 428 { 429 struct tmio_mmc_host *host = mmc_priv(mmc); 430 struct renesas_sdhi *priv = host_to_priv(host); 431 432 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 433 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 434 435 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 436 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 437 sd_scc_read32(host, priv, 438 SH_MOBILE_SDHI_SCC_CKSEL)); 439 440 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 441 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 442 sd_scc_read32(host, priv, 443 SH_MOBILE_SDHI_SCC_DTCNTL)); 444 445 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 446 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 447 } 448 449 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 450 struct renesas_sdhi *priv, u32 addr) 451 { 452 /* read mode */ 453 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 454 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 455 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 456 457 /* access start and stop */ 458 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 459 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 460 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 461 462 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 463 } 464 465 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 466 struct renesas_sdhi *priv, u32 addr, u32 val) 467 { 468 /* write mode */ 469 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 470 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 471 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 472 473 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 474 475 /* access start and stop */ 476 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 477 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 478 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 479 } 480 481 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 482 { 483 struct renesas_sdhi *priv = host_to_priv(host); 484 u32 calib_code; 485 486 /* disable write protect */ 487 sd_scc_tmpport_write32(host, priv, 0x00, 488 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 489 /* read calibration code and adjust */ 490 calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 491 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 492 493 sd_scc_tmpport_write32(host, priv, 0x22, 494 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 495 priv->adjust_hs400_calib_table[calib_code]); 496 497 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 498 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 499 500 /* adjustment done, clear flag */ 501 priv->needs_adjust_hs400 = false; 502 } 503 504 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 505 { 506 struct renesas_sdhi *priv = host_to_priv(host); 507 508 /* disable write protect */ 509 sd_scc_tmpport_write32(host, priv, 0x00, 510 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 511 /* disable manual calibration */ 512 sd_scc_tmpport_write32(host, priv, 0x22, 0); 513 /* clear offset value of TMPPORT3 */ 514 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 515 } 516 517 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 518 struct renesas_sdhi *priv) 519 { 520 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 521 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 522 523 /* Reset HS400 mode */ 524 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 525 sd_ctrl_read16(host, CTL_SDIF_MODE)); 526 527 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 528 529 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 530 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 531 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 532 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 533 534 if (priv->adjust_hs400_calib_table) 535 renesas_sdhi_adjust_hs400_mode_disable(host); 536 537 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 538 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 539 } 540 541 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 542 { 543 struct tmio_mmc_host *host = mmc_priv(mmc); 544 545 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 546 return 0; 547 } 548 549 static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) 550 { 551 renesas_sdhi_disable_scc(host->mmc); 552 renesas_sdhi_reset_hs400_mode(host, priv); 553 priv->needs_adjust_hs400 = false; 554 555 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 556 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 557 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 558 } 559 560 /* only populated for TMIO_MMC_MIN_RCAR2 */ 561 static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve) 562 { 563 struct renesas_sdhi *priv = host_to_priv(host); 564 int ret; 565 u16 val; 566 567 if (!preserve) { 568 if (priv->rstc) { 569 reset_control_reset(priv->rstc); 570 /* Unknown why but without polling reset status, it will hang */ 571 read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, 572 false, priv->rstc); 573 /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ 574 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); 575 priv->needs_adjust_hs400 = false; 576 renesas_sdhi_set_clock(host, host->clk_cache); 577 } else if (priv->scc_ctl) { 578 renesas_sdhi_scc_reset(host, priv); 579 } 580 } 581 582 if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { 583 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 584 val |= CARD_OPT_EXTOP; 585 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); 586 } 587 } 588 589 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) 590 { 591 u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 592 593 num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; 594 return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); 595 596 } 597 598 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 599 600 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 601 { 602 struct renesas_sdhi *priv = host_to_priv(host); 603 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 604 unsigned int taps_size = priv->tap_num * 2, min_tap_row; 605 unsigned long *bitmap; 606 607 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 608 609 /* 610 * When tuning CMD19 is issued twice for each tap, merge the 611 * result requiring the tap to be good in both runs before 612 * considering it for tuning selection. 613 */ 614 for (i = 0; i < taps_size; i++) { 615 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 616 617 if (!test_bit(i, priv->taps)) 618 clear_bit(i + offset, priv->taps); 619 620 if (!test_bit(i, priv->smpcmp)) 621 clear_bit(i + offset, priv->smpcmp); 622 } 623 624 /* 625 * If all TAP are OK, the sampling clock position is selected by 626 * identifying the change point of data. 627 */ 628 if (bitmap_full(priv->taps, taps_size)) { 629 bitmap = priv->smpcmp; 630 min_tap_row = 1; 631 } else { 632 bitmap = priv->taps; 633 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 634 } 635 636 /* 637 * Find the longest consecutive run of successful probes. If that 638 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 639 * center index as the tap, otherwise bail out. 640 */ 641 for_each_set_bitrange(rs, re, bitmap, taps_size) { 642 if (re - rs > tap_cnt) { 643 tap_end = re; 644 tap_start = rs; 645 tap_cnt = tap_end - tap_start; 646 } 647 } 648 649 if (tap_cnt >= min_tap_row) 650 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 651 else 652 return -EIO; 653 654 /* Set SCC */ 655 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 656 657 /* Enable auto re-tuning */ 658 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 659 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 660 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 661 662 return 0; 663 } 664 665 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 666 { 667 struct tmio_mmc_host *host = mmc_priv(mmc); 668 struct renesas_sdhi *priv = host_to_priv(host); 669 int i, ret; 670 671 priv->tap_num = renesas_sdhi_init_tuning(host); 672 if (!priv->tap_num) 673 return 0; /* Tuning is not supported */ 674 675 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 676 dev_err(&host->pdev->dev, 677 "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 678 return -EINVAL; 679 } 680 681 bitmap_zero(priv->taps, priv->tap_num * 2); 682 bitmap_zero(priv->smpcmp, priv->tap_num * 2); 683 684 /* Issue CMD19 twice for each tap */ 685 for (i = 0; i < 2 * priv->tap_num; i++) { 686 int cmd_error = 0; 687 688 /* Set sampling clock position */ 689 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 690 691 if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) 692 set_bit(i, priv->taps); 693 694 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 695 set_bit(i, priv->smpcmp); 696 697 if (cmd_error) 698 mmc_send_abort_tuning(mmc, opcode); 699 } 700 701 ret = renesas_sdhi_select_tuning(host); 702 if (ret < 0) 703 renesas_sdhi_scc_reset(host, priv); 704 return ret; 705 } 706 707 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 708 { 709 struct renesas_sdhi *priv = host_to_priv(host); 710 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 711 u32 val; 712 713 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 714 if (!val) 715 return false; 716 717 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 718 719 /* Change TAP position according to correction status */ 720 if (priv->quirks && priv->quirks->manual_tap_correction && 721 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 722 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 723 /* 724 * With HS400, the DAT signal is based on DS, not CLK. 725 * Therefore, use only CMD status. 726 */ 727 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 728 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 729 if (!smpcmp) { 730 return false; /* no error in CMD signal */ 731 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 732 new_tap++; 733 error_tap--; 734 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 735 new_tap--; 736 error_tap++; 737 } else { 738 return true; /* need retune */ 739 } 740 741 /* 742 * When new_tap is a bad tap, we cannot change. Then, we compare 743 * with the HS200 tuning result. When smpcmp[error_tap] is OK, 744 * we can at least retune. 745 */ 746 if (bad_taps & BIT(new_tap % priv->tap_num)) 747 return test_bit(error_tap % priv->tap_num, priv->smpcmp); 748 } else { 749 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 750 return true; /* need retune */ 751 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 752 new_tap++; 753 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 754 new_tap--; 755 else 756 return false; 757 } 758 759 priv->tap_set = (new_tap % priv->tap_num); 760 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 761 priv->tap_set / (use_4tap ? 2 : 1)); 762 763 return false; 764 } 765 766 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 767 { 768 struct renesas_sdhi *priv = host_to_priv(host); 769 770 /* Check SCC error */ 771 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 772 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 773 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 774 return true; 775 } 776 777 return false; 778 } 779 780 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, 781 struct mmc_request *mrq) 782 { 783 struct renesas_sdhi *priv = host_to_priv(host); 784 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 785 bool ret = false; 786 787 /* 788 * Skip checking SCC errors when running on 4 taps in HS400 mode as 789 * any retuning would still result in the same 4 taps being used. 790 */ 791 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 792 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 793 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 794 return false; 795 796 if (mmc_doing_tune(host->mmc)) 797 return false; 798 799 if (((mrq->cmd->error == -ETIMEDOUT) || 800 (mrq->data && mrq->data->error == -ETIMEDOUT)) && 801 ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 802 (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 803 ret |= true; 804 805 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 806 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 807 ret |= renesas_sdhi_auto_correction(host); 808 else 809 ret |= renesas_sdhi_manual_correction(host, use_4tap); 810 811 return ret; 812 } 813 814 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 815 { 816 int timeout = 1000; 817 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 818 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 819 820 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 821 & bit) == wait_state) 822 udelay(1); 823 824 if (!timeout) { 825 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 826 return -EBUSY; 827 } 828 829 return 0; 830 } 831 832 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 833 { 834 u32 bit = TMIO_STAT_SCLKDIVEN; 835 836 switch (addr) { 837 case CTL_SD_CMD: 838 case CTL_STOP_INTERNAL_ACTION: 839 case CTL_XFER_BLK_COUNT: 840 case CTL_SD_XFER_LEN: 841 case CTL_SD_MEM_CARD_OPT: 842 case CTL_TRANSACTION_CTL: 843 case CTL_DMA_ENABLE: 844 case CTL_HOST_MODE: 845 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 846 bit = TMIO_STAT_CMD_BUSY; 847 fallthrough; 848 case CTL_SD_CARD_CLK_CTL: 849 return renesas_sdhi_wait_idle(host, bit); 850 } 851 852 return 0; 853 } 854 855 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 856 unsigned int direction, int blk_size) 857 { 858 /* 859 * In Renesas controllers, when performing a 860 * multiple block read of one or two blocks, 861 * depending on the timing with which the 862 * response register is read, the response 863 * value may not be read properly. 864 * Use single block read for this HW bug 865 */ 866 if ((direction == MMC_DATA_READ) && 867 blk_size == 2) 868 return 1; 869 870 return blk_size; 871 } 872 873 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 874 { 875 struct renesas_sdhi *priv = host_to_priv(host); 876 877 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 878 renesas_sdhi_adjust_hs400_mode_enable(host); 879 } 880 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 881 { 882 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 883 int width = (host->bus_shift == 2) ? 64 : 32; 884 885 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 886 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 887 } 888 889 int renesas_sdhi_probe(struct platform_device *pdev, 890 const struct tmio_mmc_dma_ops *dma_ops, 891 const struct renesas_sdhi_of_data *of_data, 892 const struct renesas_sdhi_quirks *quirks) 893 { 894 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 895 struct tmio_mmc_data *mmc_data; 896 struct tmio_mmc_dma *dma_priv; 897 struct tmio_mmc_host *host; 898 struct renesas_sdhi *priv; 899 int num_irqs, irq, ret, i; 900 struct resource *res; 901 u16 ver; 902 903 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 904 if (!res) 905 return -EINVAL; 906 907 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 908 GFP_KERNEL); 909 if (!priv) 910 return -ENOMEM; 911 912 priv->quirks = quirks; 913 mmc_data = &priv->mmc_data; 914 dma_priv = &priv->dma_priv; 915 916 priv->clk = devm_clk_get(&pdev->dev, NULL); 917 if (IS_ERR(priv->clk)) 918 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock"); 919 920 priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh"); 921 if (IS_ERR(priv->clkh)) 922 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh"); 923 924 /* 925 * Some controllers provide a 2nd clock just to run the internal card 926 * detection logic. Unfortunately, the existing driver architecture does 927 * not support a separation of clocks for runtime PM usage. When 928 * native hotplug is used, the tmio driver assumes that the core 929 * must continue to run for card detect to stay active, so we cannot 930 * disable it. 931 * Additionally, it is prohibited to supply a clock to the core but not 932 * to the card detect circuit. That leaves us with if separate clocks 933 * are presented, we must treat them both as virtually 1 clock. 934 */ 935 priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd"); 936 if (IS_ERR(priv->clk_cd)) 937 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock"); 938 939 priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 940 if (IS_ERR(priv->rstc)) 941 return PTR_ERR(priv->rstc); 942 943 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 944 if (!IS_ERR(priv->pinctrl)) { 945 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 946 PINCTRL_STATE_DEFAULT); 947 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 948 "state_uhs"); 949 } 950 951 host = tmio_mmc_host_alloc(pdev, mmc_data); 952 if (IS_ERR(host)) 953 return PTR_ERR(host); 954 955 if (of_data) { 956 mmc_data->flags |= of_data->tmio_flags; 957 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 958 mmc_data->capabilities |= of_data->capabilities; 959 mmc_data->capabilities2 |= of_data->capabilities2; 960 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 961 mmc_data->max_blk_count = of_data->max_blk_count; 962 mmc_data->max_segs = of_data->max_segs; 963 dma_priv->dma_buswidth = of_data->dma_buswidth; 964 host->bus_shift = of_data->bus_shift; 965 /* Fallback for old DTs */ 966 if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) 967 priv->clkh = clk_get_parent(clk_get_parent(priv->clk)); 968 969 } 970 971 host->write16_hook = renesas_sdhi_write16_hook; 972 host->clk_enable = renesas_sdhi_clk_enable; 973 host->clk_disable = renesas_sdhi_clk_disable; 974 host->set_clock = renesas_sdhi_set_clock; 975 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 976 host->dma_ops = dma_ops; 977 978 if (quirks && quirks->hs400_disabled) 979 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 980 981 /* For some SoC, we disable internal WP. GPIO may override this */ 982 if (mmc_can_gpio_ro(host->mmc)) 983 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 984 985 /* SDR speeds are only available on Gen2+ */ 986 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 987 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 988 host->ops.card_busy = renesas_sdhi_card_busy; 989 host->ops.start_signal_voltage_switch = 990 renesas_sdhi_start_signal_voltage_switch; 991 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 992 host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; 993 host->reset = renesas_sdhi_reset; 994 } 995 996 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 997 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 998 host->bus_shift = 1; 999 1000 if (mmd) 1001 *mmc_data = *mmd; 1002 1003 dma_priv->filter = shdma_chan_filter; 1004 dma_priv->enable = renesas_sdhi_enable_dma; 1005 1006 mmc_data->alignment_shift = 1; /* 2-byte alignment */ 1007 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1008 1009 /* 1010 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1011 * bus width mode. 1012 */ 1013 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1014 1015 /* 1016 * All SDHI blocks support SDIO IRQ signalling. 1017 */ 1018 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1019 1020 /* All SDHI have CMD12 control bit */ 1021 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1022 1023 /* All SDHI have SDIO status bits which must be 1 */ 1024 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1025 1026 /* All SDHI support HW busy detection */ 1027 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 1028 1029 dev_pm_domain_start(&pdev->dev); 1030 1031 ret = renesas_sdhi_clk_enable(host); 1032 if (ret) 1033 goto efree; 1034 1035 ver = sd_ctrl_read16(host, CTL_VERSION); 1036 /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1037 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1038 mmc_data->max_blk_count = U16_MAX; 1039 1040 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1041 if (ver == SDHI_VER_GEN2_SDR50) 1042 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 1043 1044 if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1045 host->fixup_request = renesas_sdhi_fixup_request; 1046 priv->adjust_hs400_calib_table = *( 1047 res->start == SDHI_GEN3_MMC0_ADDR ? 1048 quirks->hs400_calib_table : 1049 quirks->hs400_calib_table + 1); 1050 } 1051 1052 /* these have an EXTOP bit */ 1053 if (ver >= SDHI_VER_GEN3_SD) 1054 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1055 1056 /* Enable tuning iff we have an SCC and a supported mode */ 1057 if (of_data && of_data->scc_offset && 1058 (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1059 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 1060 MMC_CAP2_HS400_1_8V))) { 1061 const struct renesas_sdhi_scc *taps = of_data->taps; 1062 bool use_4tap = quirks && quirks->hs400_4taps; 1063 bool hit = false; 1064 1065 for (i = 0; i < of_data->taps_num; i++) { 1066 if (taps[i].clk_rate == 0 || 1067 taps[i].clk_rate == host->mmc->f_max) { 1068 priv->scc_tappos = taps->tap; 1069 priv->scc_tappos_hs400 = use_4tap ? 1070 taps->tap_hs400_4tap : 1071 taps->tap; 1072 hit = true; 1073 break; 1074 } 1075 } 1076 1077 if (!hit) 1078 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1079 1080 priv->scc_ctl = host->ctl + of_data->scc_offset; 1081 host->check_retune = renesas_sdhi_check_scc_error; 1082 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1083 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1084 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1085 host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1086 } 1087 1088 ret = tmio_mmc_host_probe(host); 1089 if (ret < 0) 1090 goto edisclk; 1091 1092 num_irqs = platform_irq_count(pdev); 1093 if (num_irqs < 0) { 1094 ret = num_irqs; 1095 goto eirq; 1096 } 1097 1098 /* There must be at least one IRQ source */ 1099 if (!num_irqs) { 1100 ret = -ENXIO; 1101 goto eirq; 1102 } 1103 1104 for (i = 0; i < num_irqs; i++) { 1105 irq = platform_get_irq(pdev, i); 1106 if (irq < 0) { 1107 ret = irq; 1108 goto eirq; 1109 } 1110 1111 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1112 dev_name(&pdev->dev), host); 1113 if (ret) 1114 goto eirq; 1115 } 1116 1117 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1118 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1119 1120 return ret; 1121 1122 eirq: 1123 tmio_mmc_host_remove(host); 1124 edisclk: 1125 renesas_sdhi_clk_disable(host); 1126 efree: 1127 tmio_mmc_host_free(host); 1128 1129 return ret; 1130 } 1131 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1132 1133 int renesas_sdhi_remove(struct platform_device *pdev) 1134 { 1135 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1136 1137 tmio_mmc_host_remove(host); 1138 renesas_sdhi_clk_disable(host); 1139 tmio_mmc_host_free(host); 1140 1141 return 0; 1142 } 1143 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1144 1145 MODULE_LICENSE("GPL v2"); 1146