1 /* 2 * Renesas SDHI 3 * 4 * Copyright (C) 2015-17 Renesas Electronics Corporation 5 * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 * Copyright (C) 2009 Magnus Damm 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Based on "Compaq ASIC3 support": 14 * 15 * Copyright 2001 Compaq Computer Corporation. 16 * Copyright 2004-2005 Phil Blundell 17 * Copyright 2007-2008 OpenedHand Ltd. 18 * 19 * Authors: Phil Blundell <pb@handhelds.org>, 20 * Samuel Ortiz <sameo@openedhand.com> 21 * 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/clk.h> 26 #include <linux/slab.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mfd/tmio.h> 31 #include <linux/sh_dma.h> 32 #include <linux/delay.h> 33 #include <linux/pinctrl/consumer.h> 34 #include <linux/pinctrl/pinctrl-state.h> 35 #include <linux/regulator/consumer.h> 36 37 #include "renesas_sdhi.h" 38 #include "tmio_mmc.h" 39 40 #define EXT_ACC 0xe4 41 42 #define SDHI_VER_GEN2_SDR50 0x490c 43 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 44 #define SDHI_VER_GEN2_SDR104 0xcb0d 45 #define SDHI_VER_GEN3_SD 0xcc10 46 #define SDHI_VER_GEN3_SDMMC 0xcd10 47 48 #define host_to_priv(host) \ 49 container_of((host)->pdata, struct renesas_sdhi, mmc_data) 50 51 struct renesas_sdhi { 52 struct clk *clk; 53 struct clk *clk_cd; 54 struct tmio_mmc_data mmc_data; 55 struct tmio_mmc_dma dma_priv; 56 struct pinctrl *pinctrl; 57 struct pinctrl_state *pins_default, *pins_uhs; 58 void __iomem *scc_ctl; 59 }; 60 61 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 62 { 63 u32 val; 64 65 /* 66 * see also 67 * renesas_sdhi_of_data :: dma_buswidth 68 */ 69 switch (sd_ctrl_read16(host, CTL_VERSION)) { 70 case SDHI_VER_GEN2_SDR50: 71 val = (width == 32) ? 0x0001 : 0x0000; 72 break; 73 case SDHI_VER_GEN2_SDR104: 74 val = (width == 32) ? 0x0000 : 0x0001; 75 break; 76 case SDHI_VER_GEN3_SD: 77 case SDHI_VER_GEN3_SDMMC: 78 if (width == 64) 79 val = 0x0000; 80 else if (width == 32) 81 val = 0x0101; 82 else 83 val = 0x0001; 84 break; 85 default: 86 /* nothing to do */ 87 return; 88 } 89 90 sd_ctrl_write16(host, EXT_ACC, val); 91 } 92 93 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 94 { 95 struct mmc_host *mmc = host->mmc; 96 struct renesas_sdhi *priv = host_to_priv(host); 97 int ret = clk_prepare_enable(priv->clk); 98 99 if (ret < 0) 100 return ret; 101 102 ret = clk_prepare_enable(priv->clk_cd); 103 if (ret < 0) { 104 clk_disable_unprepare(priv->clk); 105 return ret; 106 } 107 108 /* 109 * The clock driver may not know what maximum frequency 110 * actually works, so it should be set with the max-frequency 111 * property which will already have been read to f_max. If it 112 * was missing, assume the current frequency is the maximum. 113 */ 114 if (!mmc->f_max) 115 mmc->f_max = clk_get_rate(priv->clk); 116 117 /* 118 * Minimum frequency is the minimum input clock frequency 119 * divided by our maximum divider. 120 */ 121 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 122 123 /* enable 16bit data access on SDBUF as default */ 124 renesas_sdhi_sdbuf_width(host, 16); 125 126 return 0; 127 } 128 129 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 130 unsigned int new_clock) 131 { 132 struct renesas_sdhi *priv = host_to_priv(host); 133 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 134 int i, ret; 135 136 /* tested only on R-Car Gen2+ currently; may work for others */ 137 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 138 return clk_get_rate(priv->clk); 139 140 /* 141 * We want the bus clock to be as close as possible to, but no 142 * greater than, new_clock. As we can divide by 1 << i for 143 * any i in [0, 9] we want the input clock to be as close as 144 * possible, but no greater than, new_clock << i. 145 */ 146 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 147 freq = clk_round_rate(priv->clk, new_clock << i); 148 if (freq > (new_clock << i)) { 149 /* Too fast; look for a slightly slower option */ 150 freq = clk_round_rate(priv->clk, 151 (new_clock << i) / 4 * 3); 152 if (freq > (new_clock << i)) 153 continue; 154 } 155 156 diff = new_clock - (freq >> i); 157 if (diff <= diff_min) { 158 best_freq = freq; 159 diff_min = diff; 160 } 161 } 162 163 ret = clk_set_rate(priv->clk, best_freq); 164 165 return ret == 0 ? best_freq : clk_get_rate(priv->clk); 166 } 167 168 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 169 { 170 struct renesas_sdhi *priv = host_to_priv(host); 171 172 clk_disable_unprepare(priv->clk); 173 clk_disable_unprepare(priv->clk_cd); 174 } 175 176 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 177 { 178 struct tmio_mmc_host *host = mmc_priv(mmc); 179 180 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 181 TMIO_STAT_DAT0); 182 } 183 184 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 185 struct mmc_ios *ios) 186 { 187 struct tmio_mmc_host *host = mmc_priv(mmc); 188 struct renesas_sdhi *priv = host_to_priv(host); 189 struct pinctrl_state *pin_state; 190 int ret; 191 192 switch (ios->signal_voltage) { 193 case MMC_SIGNAL_VOLTAGE_330: 194 pin_state = priv->pins_default; 195 break; 196 case MMC_SIGNAL_VOLTAGE_180: 197 pin_state = priv->pins_uhs; 198 break; 199 default: 200 return -EINVAL; 201 } 202 203 /* 204 * If anything is missing, assume signal voltage is fixed at 205 * 3.3V and succeed/fail accordingly. 206 */ 207 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 208 return ios->signal_voltage == 209 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 210 211 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 212 if (ret) 213 return ret; 214 215 return pinctrl_select_state(priv->pinctrl, pin_state); 216 } 217 218 /* SCC registers */ 219 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 220 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 221 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 222 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 223 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 224 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 225 226 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */ 227 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 228 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 229 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 230 231 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */ 232 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 233 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */ 234 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 235 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */ 236 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 237 238 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 239 struct renesas_sdhi *priv, int addr) 240 { 241 return readl(priv->scc_ctl + (addr << host->bus_shift)); 242 } 243 244 static inline void sd_scc_write32(struct tmio_mmc_host *host, 245 struct renesas_sdhi *priv, 246 int addr, u32 val) 247 { 248 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 249 } 250 251 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 252 { 253 struct renesas_sdhi *priv; 254 255 priv = host_to_priv(host); 256 257 /* set sampling clock selection range */ 258 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 259 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 260 261 /* Initialize SCC */ 262 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 263 264 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 265 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 266 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL)); 267 268 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 269 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 270 271 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 272 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 273 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 274 275 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 276 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 277 278 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 279 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 280 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 281 282 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos); 283 284 /* Read TAPNUM */ 285 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 286 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 287 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 288 } 289 290 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host, 291 unsigned long tap) 292 { 293 struct renesas_sdhi *priv = host_to_priv(host); 294 295 /* Set sampling clock position */ 296 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap); 297 } 298 299 #define SH_MOBILE_SDHI_MAX_TAP 3 300 301 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 302 { 303 struct renesas_sdhi *priv = host_to_priv(host); 304 unsigned long tap_cnt; /* counter of tuning success */ 305 unsigned long tap_set; /* tap position */ 306 unsigned long tap_start;/* start position of tuning success */ 307 unsigned long tap_end; /* end position of tuning success */ 308 unsigned long ntap; /* temporary counter of tuning success */ 309 unsigned long i; 310 311 /* Clear SCC_RVSREQ */ 312 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 313 314 /* 315 * Find the longest consecutive run of successful probes. If that 316 * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the 317 * center index as the tap. 318 */ 319 tap_cnt = 0; 320 ntap = 0; 321 tap_start = 0; 322 tap_end = 0; 323 for (i = 0; i < host->tap_num * 2; i++) { 324 if (test_bit(i, host->taps)) { 325 ntap++; 326 } else { 327 if (ntap > tap_cnt) { 328 tap_start = i - ntap; 329 tap_end = i - 1; 330 tap_cnt = ntap; 331 } 332 ntap = 0; 333 } 334 } 335 336 if (ntap > tap_cnt) { 337 tap_start = i - ntap; 338 tap_end = i - 1; 339 tap_cnt = ntap; 340 } 341 342 if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP) 343 tap_set = (tap_start + tap_end) / 2 % host->tap_num; 344 else 345 return -EIO; 346 347 /* Set SCC */ 348 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set); 349 350 /* Enable auto re-tuning */ 351 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 352 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 353 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 354 355 return 0; 356 } 357 358 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 359 { 360 struct renesas_sdhi *priv = host_to_priv(host); 361 362 /* Check SCC error */ 363 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 364 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN && 365 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 366 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 367 /* Clear SCC error */ 368 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 369 return true; 370 } 371 372 return false; 373 } 374 375 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host) 376 { 377 struct renesas_sdhi *priv; 378 379 priv = host_to_priv(host); 380 381 /* Reset SCC */ 382 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 383 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 384 385 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 386 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 387 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 388 389 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 390 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 391 392 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 393 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 394 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 395 396 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 397 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 398 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 399 } 400 401 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host) 402 { 403 int timeout = 1000; 404 405 while (--timeout && !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 406 & TMIO_STAT_SCLKDIVEN)) 407 udelay(1); 408 409 if (!timeout) { 410 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 411 return -EBUSY; 412 } 413 414 return 0; 415 } 416 417 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 418 { 419 switch (addr) { 420 case CTL_SD_CMD: 421 case CTL_STOP_INTERNAL_ACTION: 422 case CTL_XFER_BLK_COUNT: 423 case CTL_SD_CARD_CLK_CTL: 424 case CTL_SD_XFER_LEN: 425 case CTL_SD_MEM_CARD_OPT: 426 case CTL_TRANSACTION_CTL: 427 case CTL_DMA_ENABLE: 428 case EXT_ACC: 429 return renesas_sdhi_wait_idle(host); 430 } 431 432 return 0; 433 } 434 435 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 436 unsigned int direction, int blk_size) 437 { 438 /* 439 * In Renesas controllers, when performing a 440 * multiple block read of one or two blocks, 441 * depending on the timing with which the 442 * response register is read, the response 443 * value may not be read properly. 444 * Use single block read for this HW bug 445 */ 446 if ((direction == MMC_DATA_READ) && 447 blk_size == 2) 448 return 1; 449 450 return blk_size; 451 } 452 453 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 454 { 455 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? 2 : 0); 456 457 /* enable 32bit access if DMA mode if possibile */ 458 renesas_sdhi_sdbuf_width(host, enable ? 32 : 16); 459 } 460 461 int renesas_sdhi_probe(struct platform_device *pdev, 462 const struct tmio_mmc_dma_ops *dma_ops) 463 { 464 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 465 const struct renesas_sdhi_of_data *of_data; 466 struct tmio_mmc_data *mmc_data; 467 struct tmio_mmc_dma *dma_priv; 468 struct tmio_mmc_host *host; 469 struct renesas_sdhi *priv; 470 struct resource *res; 471 int irq, ret, i; 472 473 of_data = of_device_get_match_data(&pdev->dev); 474 475 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 476 if (!res) 477 return -EINVAL; 478 479 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 480 GFP_KERNEL); 481 if (!priv) 482 return -ENOMEM; 483 484 mmc_data = &priv->mmc_data; 485 dma_priv = &priv->dma_priv; 486 487 priv->clk = devm_clk_get(&pdev->dev, NULL); 488 if (IS_ERR(priv->clk)) { 489 ret = PTR_ERR(priv->clk); 490 dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 491 goto eprobe; 492 } 493 494 /* 495 * Some controllers provide a 2nd clock just to run the internal card 496 * detection logic. Unfortunately, the existing driver architecture does 497 * not support a separation of clocks for runtime PM usage. When 498 * native hotplug is used, the tmio driver assumes that the core 499 * must continue to run for card detect to stay active, so we cannot 500 * disable it. 501 * Additionally, it is prohibited to supply a clock to the core but not 502 * to the card detect circuit. That leaves us with if separate clocks 503 * are presented, we must treat them both as virtually 1 clock. 504 */ 505 priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 506 if (IS_ERR(priv->clk_cd)) 507 priv->clk_cd = NULL; 508 509 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 510 if (!IS_ERR(priv->pinctrl)) { 511 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 512 PINCTRL_STATE_DEFAULT); 513 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 514 "state_uhs"); 515 } 516 517 host = tmio_mmc_host_alloc(pdev); 518 if (!host) { 519 ret = -ENOMEM; 520 goto eprobe; 521 } 522 523 if (of_data) { 524 mmc_data->flags |= of_data->tmio_flags; 525 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 526 mmc_data->capabilities |= of_data->capabilities; 527 mmc_data->capabilities2 |= of_data->capabilities2; 528 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 529 dma_priv->dma_buswidth = of_data->dma_buswidth; 530 host->bus_shift = of_data->bus_shift; 531 } 532 533 host->dma = dma_priv; 534 host->write16_hook = renesas_sdhi_write16_hook; 535 host->clk_enable = renesas_sdhi_clk_enable; 536 host->clk_update = renesas_sdhi_clk_update; 537 host->clk_disable = renesas_sdhi_clk_disable; 538 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 539 540 /* SDR speeds are only available on Gen2+ */ 541 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 542 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 543 host->card_busy = renesas_sdhi_card_busy; 544 host->start_signal_voltage_switch = 545 renesas_sdhi_start_signal_voltage_switch; 546 } 547 548 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 549 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 550 host->bus_shift = 1; 551 552 if (mmd) 553 *mmc_data = *mmd; 554 555 dma_priv->filter = shdma_chan_filter; 556 dma_priv->enable = renesas_sdhi_enable_dma; 557 558 mmc_data->alignment_shift = 1; /* 2-byte alignment */ 559 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 560 561 /* 562 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 563 * bus width mode. 564 */ 565 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 566 567 /* 568 * All SDHI blocks support SDIO IRQ signalling. 569 */ 570 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 571 572 /* All SDHI have CMD12 control bit */ 573 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 574 575 /* All SDHI have SDIO status bits which must be 1 */ 576 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 577 578 ret = tmio_mmc_host_probe(host, mmc_data, dma_ops); 579 if (ret < 0) 580 goto efree; 581 582 /* Enable tuning iff we have an SCC and a supported mode */ 583 if (of_data && of_data->scc_offset && 584 (host->mmc->caps & MMC_CAP_UHS_SDR104 || 585 host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) { 586 const struct renesas_sdhi_scc *taps = of_data->taps; 587 bool hit = false; 588 589 host->mmc->caps |= MMC_CAP_HW_RESET; 590 591 for (i = 0; i < of_data->taps_num; i++) { 592 if (taps[i].clk_rate == 0 || 593 taps[i].clk_rate == host->mmc->f_max) { 594 host->scc_tappos = taps->tap; 595 hit = true; 596 break; 597 } 598 } 599 600 if (!hit) 601 dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); 602 603 priv->scc_ctl = host->ctl + of_data->scc_offset; 604 host->init_tuning = renesas_sdhi_init_tuning; 605 host->prepare_tuning = renesas_sdhi_prepare_tuning; 606 host->select_tuning = renesas_sdhi_select_tuning; 607 host->check_scc_error = renesas_sdhi_check_scc_error; 608 host->hw_reset = renesas_sdhi_hw_reset; 609 } 610 611 i = 0; 612 while (1) { 613 irq = platform_get_irq(pdev, i); 614 if (irq < 0) 615 break; 616 i++; 617 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 618 dev_name(&pdev->dev), host); 619 if (ret) 620 goto eirq; 621 } 622 623 /* There must be at least one IRQ source */ 624 if (!i) { 625 ret = irq; 626 goto eirq; 627 } 628 629 dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n", 630 mmc_hostname(host->mmc), (unsigned long) 631 (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start), 632 host->mmc->f_max / 1000000); 633 634 return ret; 635 636 eirq: 637 tmio_mmc_host_remove(host); 638 efree: 639 tmio_mmc_host_free(host); 640 eprobe: 641 return ret; 642 } 643 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 644 645 int renesas_sdhi_remove(struct platform_device *pdev) 646 { 647 struct mmc_host *mmc = platform_get_drvdata(pdev); 648 struct tmio_mmc_host *host = mmc_priv(mmc); 649 650 tmio_mmc_host_remove(host); 651 652 return 0; 653 } 654 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 655