1 /* 2 * Renesas SDHI 3 * 4 * Copyright (C) 2015-17 Renesas Electronics Corporation 5 * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 * Copyright (C) 2009 Magnus Damm 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Based on "Compaq ASIC3 support": 14 * 15 * Copyright 2001 Compaq Computer Corporation. 16 * Copyright 2004-2005 Phil Blundell 17 * Copyright 2007-2008 OpenedHand Ltd. 18 * 19 * Authors: Phil Blundell <pb@handhelds.org>, 20 * Samuel Ortiz <sameo@openedhand.com> 21 * 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/clk.h> 26 #include <linux/slab.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/platform_device.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/mfd/tmio.h> 33 #include <linux/sh_dma.h> 34 #include <linux/delay.h> 35 #include <linux/pinctrl/consumer.h> 36 #include <linux/pinctrl/pinctrl-state.h> 37 #include <linux/regulator/consumer.h> 38 39 #include "renesas_sdhi.h" 40 #include "tmio_mmc.h" 41 42 #define HOST_MODE 0xe4 43 44 #define SDHI_VER_GEN2_SDR50 0x490c 45 #define SDHI_VER_RZ_A1 0x820b 46 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 47 #define SDHI_VER_GEN2_SDR104 0xcb0d 48 #define SDHI_VER_GEN3_SD 0xcc10 49 #define SDHI_VER_GEN3_SDMMC 0xcd10 50 51 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 52 { 53 u32 val; 54 55 /* 56 * see also 57 * renesas_sdhi_of_data :: dma_buswidth 58 */ 59 switch (sd_ctrl_read16(host, CTL_VERSION)) { 60 case SDHI_VER_GEN2_SDR50: 61 val = (width == 32) ? 0x0001 : 0x0000; 62 break; 63 case SDHI_VER_GEN2_SDR104: 64 val = (width == 32) ? 0x0000 : 0x0001; 65 break; 66 case SDHI_VER_GEN3_SD: 67 case SDHI_VER_GEN3_SDMMC: 68 if (width == 64) 69 val = 0x0000; 70 else if (width == 32) 71 val = 0x0101; 72 else 73 val = 0x0001; 74 break; 75 default: 76 /* nothing to do */ 77 return; 78 } 79 80 sd_ctrl_write16(host, HOST_MODE, val); 81 } 82 83 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 84 { 85 struct mmc_host *mmc = host->mmc; 86 struct renesas_sdhi *priv = host_to_priv(host); 87 int ret = clk_prepare_enable(priv->clk); 88 89 if (ret < 0) 90 return ret; 91 92 ret = clk_prepare_enable(priv->clk_cd); 93 if (ret < 0) { 94 clk_disable_unprepare(priv->clk); 95 return ret; 96 } 97 98 /* 99 * The clock driver may not know what maximum frequency 100 * actually works, so it should be set with the max-frequency 101 * property which will already have been read to f_max. If it 102 * was missing, assume the current frequency is the maximum. 103 */ 104 if (!mmc->f_max) 105 mmc->f_max = clk_get_rate(priv->clk); 106 107 /* 108 * Minimum frequency is the minimum input clock frequency 109 * divided by our maximum divider. 110 */ 111 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 112 113 /* enable 16bit data access on SDBUF as default */ 114 renesas_sdhi_sdbuf_width(host, 16); 115 116 return 0; 117 } 118 119 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 120 unsigned int new_clock) 121 { 122 struct renesas_sdhi *priv = host_to_priv(host); 123 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 124 int i, ret; 125 126 /* tested only on R-Car Gen2+ currently; may work for others */ 127 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 128 return clk_get_rate(priv->clk); 129 130 /* 131 * We want the bus clock to be as close as possible to, but no 132 * greater than, new_clock. As we can divide by 1 << i for 133 * any i in [0, 9] we want the input clock to be as close as 134 * possible, but no greater than, new_clock << i. 135 */ 136 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 137 freq = clk_round_rate(priv->clk, new_clock << i); 138 if (freq > (new_clock << i)) { 139 /* Too fast; look for a slightly slower option */ 140 freq = clk_round_rate(priv->clk, 141 (new_clock << i) / 4 * 3); 142 if (freq > (new_clock << i)) 143 continue; 144 } 145 146 diff = new_clock - (freq >> i); 147 if (diff <= diff_min) { 148 best_freq = freq; 149 diff_min = diff; 150 } 151 } 152 153 ret = clk_set_rate(priv->clk, best_freq); 154 155 return ret == 0 ? best_freq : clk_get_rate(priv->clk); 156 } 157 158 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 159 { 160 struct renesas_sdhi *priv = host_to_priv(host); 161 162 clk_disable_unprepare(priv->clk); 163 clk_disable_unprepare(priv->clk_cd); 164 } 165 166 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 167 { 168 struct tmio_mmc_host *host = mmc_priv(mmc); 169 170 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 171 TMIO_STAT_DAT0); 172 } 173 174 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 175 struct mmc_ios *ios) 176 { 177 struct tmio_mmc_host *host = mmc_priv(mmc); 178 struct renesas_sdhi *priv = host_to_priv(host); 179 struct pinctrl_state *pin_state; 180 int ret; 181 182 switch (ios->signal_voltage) { 183 case MMC_SIGNAL_VOLTAGE_330: 184 pin_state = priv->pins_default; 185 break; 186 case MMC_SIGNAL_VOLTAGE_180: 187 pin_state = priv->pins_uhs; 188 break; 189 default: 190 return -EINVAL; 191 } 192 193 /* 194 * If anything is missing, assume signal voltage is fixed at 195 * 3.3V and succeed/fail accordingly. 196 */ 197 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 198 return ios->signal_voltage == 199 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 200 201 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 202 if (ret) 203 return ret; 204 205 return pinctrl_select_state(priv->pinctrl, pin_state); 206 } 207 208 /* SCC registers */ 209 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 210 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 211 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 212 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 213 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 214 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 215 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 216 217 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */ 218 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 219 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 220 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 221 222 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */ 223 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 224 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */ 225 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 226 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */ 227 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 228 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */ 229 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 230 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 231 232 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 233 struct renesas_sdhi *priv, int addr) 234 { 235 return readl(priv->scc_ctl + (addr << host->bus_shift)); 236 } 237 238 static inline void sd_scc_write32(struct tmio_mmc_host *host, 239 struct renesas_sdhi *priv, 240 int addr, u32 val) 241 { 242 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 243 } 244 245 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 246 { 247 struct renesas_sdhi *priv; 248 249 priv = host_to_priv(host); 250 251 /* Initialize SCC */ 252 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 253 254 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 255 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 256 257 /* set sampling clock selection range */ 258 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 259 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 260 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 261 262 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 263 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 264 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 265 266 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 267 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 268 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 269 270 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 271 272 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 273 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 274 275 /* Read TAPNUM */ 276 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 277 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 278 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 279 } 280 281 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host, 282 unsigned long tap) 283 { 284 struct renesas_sdhi *priv = host_to_priv(host); 285 286 /* Set sampling clock position */ 287 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap); 288 } 289 290 static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host) 291 { 292 struct renesas_sdhi *priv = host_to_priv(host); 293 294 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 295 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 296 297 /* Set HS400 mode */ 298 sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 | 299 sd_ctrl_read16(host, CTL_SDIF_MODE)); 300 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 301 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 302 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 303 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 304 305 /* Set the sampling clock selection range of HS400 mode */ 306 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 307 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 308 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 309 310 311 if (host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400) 312 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 313 host->tap_set / 2); 314 315 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 316 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 317 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 318 319 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 320 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 321 } 322 323 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host, 324 struct renesas_sdhi *priv) 325 { 326 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 327 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 328 329 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 330 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 331 sd_scc_read32(host, priv, 332 SH_MOBILE_SDHI_SCC_CKSEL)); 333 } 334 335 static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host) 336 { 337 struct renesas_sdhi *priv = host_to_priv(host); 338 339 renesas_sdhi_reset_scc(host, priv); 340 341 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 342 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 343 sd_scc_read32(host, priv, 344 SH_MOBILE_SDHI_SCC_DTCNTL)); 345 346 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 347 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 348 } 349 350 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 351 struct renesas_sdhi *priv) 352 { 353 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 354 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 355 356 /* Reset HS400 mode */ 357 sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 & 358 sd_ctrl_read16(host, CTL_SDIF_MODE)); 359 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 360 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 361 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 362 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 363 364 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 365 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 366 } 367 368 static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host) 369 { 370 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 371 } 372 373 #define SH_MOBILE_SDHI_MAX_TAP 3 374 375 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 376 { 377 struct renesas_sdhi *priv = host_to_priv(host); 378 unsigned long tap_cnt; /* counter of tuning success */ 379 unsigned long tap_start;/* start position of tuning success */ 380 unsigned long tap_end; /* end position of tuning success */ 381 unsigned long ntap; /* temporary counter of tuning success */ 382 unsigned long i; 383 384 /* Clear SCC_RVSREQ */ 385 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 386 387 /* 388 * When tuning CMD19 is issued twice for each tap, merge the 389 * result requiring the tap to be good in both runs before 390 * considering it for tuning selection. 391 */ 392 for (i = 0; i < host->tap_num * 2; i++) { 393 int offset = host->tap_num * (i < host->tap_num ? 1 : -1); 394 395 if (!test_bit(i, host->taps)) 396 clear_bit(i + offset, host->taps); 397 } 398 399 /* 400 * Find the longest consecutive run of successful probes. If that 401 * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the 402 * center index as the tap. 403 */ 404 tap_cnt = 0; 405 ntap = 0; 406 tap_start = 0; 407 tap_end = 0; 408 for (i = 0; i < host->tap_num * 2; i++) { 409 if (test_bit(i, host->taps)) { 410 ntap++; 411 } else { 412 if (ntap > tap_cnt) { 413 tap_start = i - ntap; 414 tap_end = i - 1; 415 tap_cnt = ntap; 416 } 417 ntap = 0; 418 } 419 } 420 421 if (ntap > tap_cnt) { 422 tap_start = i - ntap; 423 tap_end = i - 1; 424 tap_cnt = ntap; 425 } 426 427 if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP) 428 host->tap_set = (tap_start + tap_end) / 2 % host->tap_num; 429 else 430 return -EIO; 431 432 /* Set SCC */ 433 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, host->tap_set); 434 435 /* Enable auto re-tuning */ 436 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 437 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 438 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 439 440 return 0; 441 } 442 443 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 444 { 445 struct renesas_sdhi *priv = host_to_priv(host); 446 447 /* Check SCC error */ 448 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 449 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN && 450 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 451 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 452 /* Clear SCC error */ 453 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 454 return true; 455 } 456 457 return false; 458 } 459 460 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host) 461 { 462 struct renesas_sdhi *priv; 463 464 priv = host_to_priv(host); 465 466 renesas_sdhi_reset_scc(host, priv); 467 renesas_sdhi_reset_hs400_mode(host, priv); 468 469 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 470 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 471 472 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 473 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 474 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 475 476 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 477 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 478 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 479 } 480 481 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 482 { 483 int timeout = 1000; 484 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 485 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 486 487 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 488 & bit) == wait_state) 489 udelay(1); 490 491 if (!timeout) { 492 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 493 return -EBUSY; 494 } 495 496 return 0; 497 } 498 499 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 500 { 501 u32 bit = TMIO_STAT_SCLKDIVEN; 502 503 switch (addr) { 504 case CTL_SD_CMD: 505 case CTL_STOP_INTERNAL_ACTION: 506 case CTL_XFER_BLK_COUNT: 507 case CTL_SD_XFER_LEN: 508 case CTL_SD_MEM_CARD_OPT: 509 case CTL_TRANSACTION_CTL: 510 case CTL_DMA_ENABLE: 511 case HOST_MODE: 512 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 513 bit = TMIO_STAT_CMD_BUSY; 514 /* fallthrough */ 515 case CTL_SD_CARD_CLK_CTL: 516 return renesas_sdhi_wait_idle(host, bit); 517 } 518 519 return 0; 520 } 521 522 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 523 unsigned int direction, int blk_size) 524 { 525 /* 526 * In Renesas controllers, when performing a 527 * multiple block read of one or two blocks, 528 * depending on the timing with which the 529 * response register is read, the response 530 * value may not be read properly. 531 * Use single block read for this HW bug 532 */ 533 if ((direction == MMC_DATA_READ) && 534 blk_size == 2) 535 return 1; 536 537 return blk_size; 538 } 539 540 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 541 { 542 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 543 int width = (host->bus_shift == 2) ? 64 : 32; 544 545 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 546 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 547 } 548 549 int renesas_sdhi_probe(struct platform_device *pdev, 550 const struct tmio_mmc_dma_ops *dma_ops) 551 { 552 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 553 const struct renesas_sdhi_of_data *of_data; 554 struct tmio_mmc_data *mmc_data; 555 struct tmio_mmc_dma *dma_priv; 556 struct tmio_mmc_host *host; 557 struct renesas_sdhi *priv; 558 struct resource *res; 559 int irq, ret, i; 560 561 of_data = of_device_get_match_data(&pdev->dev); 562 563 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 564 if (!res) 565 return -EINVAL; 566 567 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 568 GFP_KERNEL); 569 if (!priv) 570 return -ENOMEM; 571 572 mmc_data = &priv->mmc_data; 573 dma_priv = &priv->dma_priv; 574 575 priv->clk = devm_clk_get(&pdev->dev, NULL); 576 if (IS_ERR(priv->clk)) { 577 ret = PTR_ERR(priv->clk); 578 dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 579 return ret; 580 } 581 582 /* 583 * Some controllers provide a 2nd clock just to run the internal card 584 * detection logic. Unfortunately, the existing driver architecture does 585 * not support a separation of clocks for runtime PM usage. When 586 * native hotplug is used, the tmio driver assumes that the core 587 * must continue to run for card detect to stay active, so we cannot 588 * disable it. 589 * Additionally, it is prohibited to supply a clock to the core but not 590 * to the card detect circuit. That leaves us with if separate clocks 591 * are presented, we must treat them both as virtually 1 clock. 592 */ 593 priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 594 if (IS_ERR(priv->clk_cd)) 595 priv->clk_cd = NULL; 596 597 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 598 if (!IS_ERR(priv->pinctrl)) { 599 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 600 PINCTRL_STATE_DEFAULT); 601 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 602 "state_uhs"); 603 } 604 605 host = tmio_mmc_host_alloc(pdev, mmc_data); 606 if (IS_ERR(host)) 607 return PTR_ERR(host); 608 609 if (of_data) { 610 mmc_data->flags |= of_data->tmio_flags; 611 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 612 mmc_data->capabilities |= of_data->capabilities; 613 mmc_data->capabilities2 |= of_data->capabilities2; 614 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 615 mmc_data->max_blk_count = of_data->max_blk_count; 616 mmc_data->max_segs = of_data->max_segs; 617 dma_priv->dma_buswidth = of_data->dma_buswidth; 618 host->bus_shift = of_data->bus_shift; 619 } 620 621 host->write16_hook = renesas_sdhi_write16_hook; 622 host->clk_enable = renesas_sdhi_clk_enable; 623 host->clk_update = renesas_sdhi_clk_update; 624 host->clk_disable = renesas_sdhi_clk_disable; 625 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 626 host->dma_ops = dma_ops; 627 628 /* For some SoC, we disable internal WP. GPIO may override this */ 629 if (mmc_can_gpio_ro(host->mmc)) 630 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 631 632 /* SDR speeds are only available on Gen2+ */ 633 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 634 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 635 host->ops.card_busy = renesas_sdhi_card_busy; 636 host->ops.start_signal_voltage_switch = 637 renesas_sdhi_start_signal_voltage_switch; 638 } 639 640 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 641 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 642 host->bus_shift = 1; 643 644 if (mmd) 645 *mmc_data = *mmd; 646 647 dma_priv->filter = shdma_chan_filter; 648 dma_priv->enable = renesas_sdhi_enable_dma; 649 650 mmc_data->alignment_shift = 1; /* 2-byte alignment */ 651 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 652 653 /* 654 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 655 * bus width mode. 656 */ 657 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 658 659 /* 660 * All SDHI blocks support SDIO IRQ signalling. 661 */ 662 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 663 664 /* All SDHI have CMD12 control bit */ 665 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 666 667 /* All SDHI have SDIO status bits which must be 1 */ 668 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 669 670 ret = renesas_sdhi_clk_enable(host); 671 if (ret) 672 goto efree; 673 674 ret = tmio_mmc_host_probe(host); 675 if (ret < 0) 676 goto edisclk; 677 678 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 679 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50) 680 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 681 682 /* Enable tuning iff we have an SCC and a supported mode */ 683 if (of_data && of_data->scc_offset && 684 (host->mmc->caps & MMC_CAP_UHS_SDR104 || 685 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 686 MMC_CAP2_HS400_1_8V))) { 687 const struct renesas_sdhi_scc *taps = of_data->taps; 688 bool hit = false; 689 690 host->mmc->caps |= MMC_CAP_HW_RESET; 691 692 for (i = 0; i < of_data->taps_num; i++) { 693 if (taps[i].clk_rate == 0 || 694 taps[i].clk_rate == host->mmc->f_max) { 695 priv->scc_tappos = taps->tap; 696 hit = true; 697 break; 698 } 699 } 700 701 if (!hit) 702 dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); 703 704 priv->scc_ctl = host->ctl + of_data->scc_offset; 705 host->init_tuning = renesas_sdhi_init_tuning; 706 host->prepare_tuning = renesas_sdhi_prepare_tuning; 707 host->select_tuning = renesas_sdhi_select_tuning; 708 host->check_scc_error = renesas_sdhi_check_scc_error; 709 host->hw_reset = renesas_sdhi_hw_reset; 710 host->prepare_hs400_tuning = 711 renesas_sdhi_prepare_hs400_tuning; 712 host->hs400_downgrade = renesas_sdhi_disable_scc; 713 host->hs400_complete = renesas_sdhi_hs400_complete; 714 } 715 716 i = 0; 717 while (1) { 718 irq = platform_get_irq(pdev, i); 719 if (irq < 0) 720 break; 721 i++; 722 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 723 dev_name(&pdev->dev), host); 724 if (ret) 725 goto eirq; 726 } 727 728 /* There must be at least one IRQ source */ 729 if (!i) { 730 ret = irq; 731 goto eirq; 732 } 733 734 dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n", 735 mmc_hostname(host->mmc), (unsigned long) 736 (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start), 737 host->mmc->f_max / 1000000); 738 739 return ret; 740 741 eirq: 742 tmio_mmc_host_remove(host); 743 edisclk: 744 renesas_sdhi_clk_disable(host); 745 efree: 746 tmio_mmc_host_free(host); 747 748 return ret; 749 } 750 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 751 752 int renesas_sdhi_remove(struct platform_device *pdev) 753 { 754 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 755 756 tmio_mmc_host_remove(host); 757 renesas_sdhi_clk_disable(host); 758 759 return 0; 760 } 761 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 762 763 MODULE_LICENSE("GPL v2"); 764